TW202020538A - Shift register and gate driver circuit - Google Patents

Abstract

A shift register and a gate driver circuit are provided. The shift register includes an input unit, an output unit, a reset unit, and an electrostatic discharge unit. The input unit provides an input signal. The output unit is coupled to the input unit and the gate output terminal. The output unit outputs an output signal via the gate output according to the input signal. The electrostatic discharge unit is coupled to the output unit. After the gate output terminal outputs the output signal, the electrostatic discharge unit pulls down a voltage of the gate output terminal according to an low gate voltage. The reset unit is coupled to the input unit and the output unit. After the electrostatic discharge unit pulls down the voltage of the gate output terminal, the reset unit resets a voltage of a bootstrap node.

Description

Shift register and gate drive circuit

The present invention relates to a register design, and in particular to a shift register and its gate driving circuit suitable for a gate driver on array (GOA).

Generally speaking, in the field of display driving technology, liquid crystal displays (LCD) and electrophoretic displays (EPD) usually use driving signals and scanning signals provided by the source driving circuit and the gate driving circuit To drive the display panel. In addition, in order to save the manufacturing cost of the display, the technology of gate driver on array (GOA) is currently developed. In other words, the gate driving circuit can be directly fabricated on the glass substrate, instead of the driving chip made of the external silicon chip. However, since the gate driving circuit is directly fabricated on the glass substrate, the gate driving circuit will occupy the area of the display panel, which in turn leads to a reduction in the display area of the display panel. Therefore, how to improve and increase the display area of the display panel of the gate drive circuit on the array is one of the important topics in the art. In view of this, several solutions will be proposed below.

The invention provides a shift register suitable for a gate driver on array (GOA) and its gate driving circuit, which can effectively increase the area of the display area of the display panel.

A shift register of the present invention includes an input unit, an output unit, an electrostatic discharge unit, and a reset unit. The input unit provides an input signal. The output unit is coupled to the input unit and the gate output terminal. The output unit outputs an output signal through the gate output terminal according to the input signal. The electrostatic discharge unit is coupled to the output unit. After the gate output terminal outputs the output signal, the ESD unit pulls down the voltage at the gate output terminal according to the gate low voltage. The reset unit is coupled to the input unit and the output unit. After the electrostatic discharge unit pulls down the voltage at the output terminal of the gate, the reset unit resets the voltage at the bootstrap node.

A gate drive circuit of the present invention includes a plurality of shift registers as described above. In a driving cycle, the output units of the plurality of shift registers pull up the voltage of the gate output terminal by the first clock signal according to the input signal, so that the gate output terminal outputs the voltage The output signal, and then the electrostatic discharge unit pulls down the voltage at the gate output terminal. After the electrostatic discharge unit pulls down the voltage at the output terminal of the gate, the reset unit of the plurality of shift registers resets the bootstrapping node by the gate low voltage according to the second clock signal Voltage. The clock phase of the first clock signal differs from the second clock signal by two gate line on-times.

Based on the above, the shift register and the gate driving circuit of the present invention can replace the pull-down transistor or reduce the layout area of the pull-down transistor on the display panel by the electrostatic discharge unit, so as to effectively increase the area of the display area of the display panel.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

In order to make the content of the present invention easier to understand, the following specific embodiments are taken as examples on which the present invention can indeed be implemented. In addition, wherever possible, elements/components/steps using the same reference numbers in the drawings and embodiments represent the same or similar components.

FIG. 1 is a schematic diagram of a shift register according to an embodiment of the invention. Referring to FIG. 1, the shift register 100 of the present invention includes an input unit 110, an output unit 120, a reset unit 130 and an electrostatic discharge unit 140. In this embodiment, the input unit 110 is coupled to the output unit 120 to provide an input signal to the output unit 120. The output unit 120 outputs the output signal via the gate output terminal according to the input signal. The reset unit 130 is coupled to the input unit 110 and the output unit 120. The electrostatic discharge unit 140 is coupled to the output unit 120. In this embodiment, after the output unit 120 outputs an output signal through the gate output terminal, the ESD unit 140 pulls down the voltage at the gate output terminal according to the gate low voltage. Moreover, after the electrostatic discharge unit 140 pulls down the voltage at the gate output terminal, the reset unit 130 resets the voltage of the bootstrap node.

In this embodiment, the shift register 100 is adapted to a gate driver on array (GOA) in the display panel, and is coupled to the gate line of the display panel through the gate output terminal . The shift register 100 provides an output signal to the gate line of the display panel through the output circuit 120 as a scanning signal. In this embodiment, the output circuit 120 provides a high voltage level signal to the gate output terminal, and when the output circuit 120 stops providing the high voltage level signal to the gate output terminal, the ESD unit 140 discharges the gate The voltage at the output. In other words, the ESD unit 140 of this embodiment is used to provide the function of pulling down the voltage. Next, after the electrostatic discharge unit 140 discharges the voltage at the gate output terminal, the reset unit 130 resets the voltage of the bootstrap node in the circuit of the shift register 100 to complete the output of one scan signal. In addition, the electrostatic discharge unit 140 of the present embodiment can not only serve as a pull-down circuit, but also provide an electrostatic protection function suitable for the shift register 100 and the display panel.

In addition, in this embodiment, the above-mentioned display panel may refer to a display panel disposed in a liquid crystal display (LCD), an organic light emitting display (OLED) or an electrophoretic display (EPD), for example, and The display panel may be, for example, a thin film transistor (TFT) panel made of glass or plastic.

2 is a circuit diagram of a shift register according to an embodiment of the invention. Referring to FIG. 2, the shift register 200 includes an input unit 210, an output unit 220, a reset unit 230 and an electrostatic discharge unit 240. In this embodiment, the input unit 210 includes a first transistor 211 and a second transistor 212. The control terminal of the first transistor 211 receives the first control signal CS1, and the first terminal of the first transistor 211 receives the first input signal IS1. The control terminal of the second transistor 212 receives the second control signal CS2. The first end of the second transistor 212 is coupled to the second end of the first transistor 211, and the second end of the second transistor 212 receives the second input signal IS2. The second end of the first transistor 211 and the first end of the second transistor 212 are coupled to the output unit 220. The first transistor 211 and the second transistor 212 are used to periodically (or selectively) provide input signals to the output unit 120, respectively. In this embodiment, the first input signal IS1 may be one of the forward input signal and the reverse input signal, and the second input signal IS2 may be the other of the forward input signal and the reverse input signal. The signal types of the first input signal IS1 and the second input signal IS2 can be determined according to different driving states, and the invention is not limited thereto.

In this embodiment, the output unit 220 includes a third transistor 221. The control terminal of the third transistor 221 is coupled to the second terminal of the first transistor 211 and the first terminal of the second transistor 212, wherein the first terminal of the third transistor 221 receives the first clock signal CLK1, and the third The second terminal of the transistor 221 is coupled to the gate output terminal Gout. In this embodiment, the third transistor 221 is used to determine whether to output the first clock signal CLK1 as the output signal to the gate output terminal Gout according to the input signal provided by the input unit 210. In other words, the output unit 220 can be regarded as a pull-up circuit and uses the voltage of the gate output terminal Gout. In this embodiment, a capacitor C1 is included between the control terminal of the third transistor 221 and the gate output terminal Gout and the second terminal of the third transistor 221. The capacitor C1 is used to achieve the purpose of bootstrap and to stabilize the characteristics of the cut-off voltage level of the output signal of the gate output terminal Gout to protect the display panel.

In the present embodiment, the reset unit 230 includes the fourth transistor 231. The control terminal of the fourth transistor 231 receives the second clock signal CLK2. The first end of the fourth transistor 231 is coupled to the bootstrap node P of the signal line between the input unit 210 and the output unit 220. The second terminal of the fourth transistor 231 receives the gate low voltage VGL. In this embodiment, the fourth transistor 231 is used to periodically reset the voltage of the bootstrap node P to the gate low voltage VGL according to the second clock signal CLK2 to stabilize the shift register 200.

In this embodiment, the electrostatic discharge unit 240 includes a fifth transistor 241 and a sixth transistor 242. The first terminal of the fifth transistor 241 is coupled to the gate output terminal Gout. The control terminal of the fifth transistor 241 is coupled to the second terminal of the fifth transistor 241, and the second terminal of the fifth transistor 241 receives the gate low voltage VGL. The first terminal of the sixth transistor 242 receives the gate low voltage VGL. The control terminal of the sixth transistor 242 is coupled to the second terminal of the sixth transistor 242, and the second terminal of the sixth transistor 242 is coupled to the gate output terminal Gout. The first end of the fifth transistor 241 is coupled to the second end of the sixth transistor 242, and the second end of the fifth transistor 241 is coupled to the first end of the sixth transistor 242. In this embodiment, when the voltage at the gate output terminal Gout and the gate low voltage VGL have a voltage difference, the fifth transistor 241 and the sixth transistor 242 are used to discharge the voltage at the gate output terminal Gout. In other words, the electrostatic discharge unit 240 can be regarded as a pull-down circuit and used to pull down the voltage of the gate output terminal Gout.

However, in an embodiment, the shift register 200 may additionally include pull-down transistors. The first end of the pull-down transistor is coupled to the gate output terminal Gout, and the second end of the pull-down transistor receives the gate low voltage VGL. The pull-down transistor may pull the voltage of the gate output terminal Gout corresponding to the third transistor 221. That is to say, in one embodiment, the electrostatic discharge unit 240 can combine the pull-down transistor to pull down the voltage of the gate output terminal Gout at the same time. Therefore, since the electrostatic discharge unit 240 and the pull-down transistor discharge the gate output terminal Gout at the same time, the area of the pull-down transistor can be effectively reduced.

In this embodiment, the shift register 200 is used for bidirectional driving. The first control signal CS1 and the second control signal CS2 received by the control terminals of the first transistor 211 and the second transistor 212 of the input unit 210 are used to Receive the output signal of the shift register of the previous stage or the subsequent stage to periodically (or selectively) provide a positive input signal with a high gate voltage or a reverse input signal with a low gate voltage to the output unit 220 . In this embodiment, when the output unit 220 receives the input voltage provided by the input unit 210, the output unit 220 outputs an output signal to the gate output terminal Gout. And, when the output unit 220 stops receiving the input voltage provided by the input unit 210, the electrostatic discharge circuit 240 discharges the voltage of the gate output terminal Gout. That is, the output unit 220 pulls up the voltage at the gate output terminal Gout, and the electrostatic discharge circuit 240 pulls down the voltage at the gate output terminal Gout. The output unit 220 and the electrostatic discharge circuit 240 can make the output signal of the gate output terminal Gout output to the gate line of the display panel be a scanning signal that periodically changes. Finally, after the electrostatic discharge circuit 240 finishes pulling down the voltage of the gate output terminal Gout, the reset unit 230 will then reset the voltage of the bootstrap node P. Therefore, the circuit architecture of the shift register 200 of this embodiment does not require a large-area pull-down circuit design. The shift register 200 of this embodiment can effectively discharge the voltage of the gate output terminal Gout through the electrostatic discharge circuit 240 between the shift register 200 and the display panel.

In addition, in this embodiment, each of the above transistors may be, for example, a thin film transistor (Thin Film Transistor, TFT), a metal oxide thin film transistor (Metal Oxide Thin Film Transistor, MOTFT), or a metal oxide half field effect transistor ( Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or Junction Field Effect Transistor (JFET) etc.

3 is a schematic diagram of a gate driving circuit according to an embodiment of the invention. FIG. 4 is a driving timing diagram of the gate driving circuit according to the embodiment of FIG. 3. 3 and 4, the gate driving circuit 300 is a gate driving circuit on an array. In this embodiment, the gate driving circuit 300 includes a plurality of shift registers 310-340, wherein the number of shift registers is not limited to that shown in FIG. 3, and the shift registers 310-340 may be, for example, the above-described FIG. 1 and FIG. 2 The shift register described in the embodiment. Therefore, the relevant circuit features and implementation details of the shift registers 310-340 of this embodiment can be combined with the descriptions of the above-mentioned embodiments of FIG. 1 and FIG. 2 to obtain sufficient teachings, suggestions, and implementation descriptions, and thus will not be described in detail.

In this embodiment, the gate driving circuit 300 can increase the discharge time of the electrostatic discharge circuits of the shift registers 310 to 340 through timing control, so as to effectively reduce the electrostatic discharge of the shift registers 310 to 340. The layout area of the circuit on the display panel. In detail, the gate driving circuit 300 can drive the shift registers 310 to 340 by four reference clock signals CK1 to CK4, and the clock phases of the four reference clock signals CK1 to CK4 are sequentially different by one gate line on-time (As shown in Figure 4). In this embodiment, the first clock signal of each shift register 310~340 is the first or second of the four reference clock signals CK1~CK4, and the second clock of each shift register 310~340 The signal is the third or fourth of the four reference clock signals CK1~CK4. Moreover, the first control signal received by each shift register 310-340 is the output signal of the shift register of the previous stage, and the second control signal of each shift register 310-340 is the shift register of the subsequent stage, respectively. Output signal.

In detail, as shown in FIG. 3, the shift registers 310, 330 receive the reference clock signal CK1 as the first clock signal received by the output unit, and the shift registers 310, 330 receive the reference clock signal CK3 as the reset unit. The received second clock signal. The shift registers 320, 340 receive the reference clock signal CK2 as the first clock signal received by the output unit, and the shift registers 320, 340 receive the reference clock signal CK4 as the second clock signal received by the reset unit. After the shift register 310 receives the start signal STV, the shift register 310 outputs the output signal Gout1 according to the forward input signal FW and the reverse input signal BW. As shown in FIG. 3, the first control signals received by the shift registers 320 to 340 are the output signals Gout1 to Gout3 of the previous stage of the shift registers 310 to 340, and the second control signals of the shift registers 310 to 330 are respectively It is the output signals Gout2~Gout4 of the shift registers 320~340 of the latter stage. By analogy, the shift registers 310 to 340 can sequentially output the output signals Gout1 to Gout4 in the forward input signal FW and the reverse input signal BW.

That is to say, since the clock phase of the first clock signal received by the output unit of each of the shift registers 310 to 340 in FIG. 3 differs from the second clock signal received by the reset unit by two gate-line on-times, each The electrostatic discharge unit of a shift register 310~340 has sufficient discharge time before the reset unit resets the voltage of the bootstrap node. In other words, the electrostatic discharge units of the shift registers 310-340 of this embodiment do not require a large-area transistor design, so the layout area occupied by the shift registers 310-340 on the display panel can be effectively reduced.

5 is a schematic diagram of a gate driving circuit according to another embodiment of the invention. 6 is a driving timing diagram of the gate driving circuit according to the embodiment of FIG. 5. 5 and 6, the gate driving circuit 500 is a gate driving circuit on an array. In this embodiment, the gate driving circuit 500 includes a plurality of shift registers 510-540, wherein the number of shift registers is not limited to that shown in FIG. 5, and the shift registers 510-540 may be, for example, the above-mentioned FIG. 1 and FIG. 2 The shift register described in the embodiment. Therefore, the relevant circuit features and implementation details of the shift registers 510-540 of this embodiment can be combined with the descriptions of the above-mentioned embodiments of FIG. 1 and FIG. 2 to obtain sufficient teachings, suggestions, and implementation descriptions, and thus will not be repeated.

In this embodiment, the gate driving circuit 500 can increase the discharge time of each of the electrostatic discharge circuits of the shift registers 510-540 through timing control, so as to effectively reduce the electrostatic discharge of each of the shift registers 510-540 The layout area of the circuit on the display panel. In detail, the gate driving circuit 500 can drive the shift registers 510-540 by eight reference clock signals CK1'~CK8', and the clock phases of the eight reference clock signals CK1'~CK8' differ by two in sequence One gate line conduction time (as shown in Figure 6). In this embodiment, the shift registers 510-540 are divided into odd-numbered groups and even-numbered groups, wherein the odd-numbered groups of shift registers 510, 530 and the even-numbered groups of shift registers 520-540 are separately arranged on both sides of the display panel to The display panel of this embodiment can have the characteristics of a narrow bezel.

In this embodiment, the first clock signal of each shift register 510, 530 of the odd-numbered group is the first or third of the eight reference clock signals CK1'~CK8'. The first clock signal of each shift register 520, 540 of the even group is the second or fourth of the eight reference clock signals CK1'~CK8'. The second clock signal of each shift register 510, 530 of the odd group is the fifth or seventh of the eight reference clock signals CK1'~CK8'. The second clock signal of each shift register 520, 540 of the even group is the sixth or eighth of the eight reference clock signals CK1' to CK8'. In this embodiment, the first control signal received by each shift register 510-540 is the output signal of the shift register of the first two stages, respectively, and the second control signal of each shift register 510-540 is the rear The output signal of the second-level shift register.

In detail, as shown in FIG. 5, the shift registers 510 and 530 receive the reference clock signals CK1 ′ and CK3 ′ as the first clock signals received by the output unit, and the shift registers 510 and 530 receive the reference clock signal CK5 ′ , CK7' as the second clock signal received by the reset unit. The shift registers 520, 540 receive the reference clock signals CK2', CK4' as the first clock signal received by the output unit, and the shift registers 520, 540 receive the reference clock signals CK6', CK8' as the received by the reset unit The second clock signal. After the shift register 510 receives the start signal STV, the shift register 510 outputs the output signal Gout1 according to the forward input signal FW and the reverse input signal BW. As shown in FIG. 5, the first control signals received by the shift registers 530, 540 are the output signals Gout1', Gout2' of the shift registers 510, 520 of the first two stages, respectively, and the second of the shift registers 510, 520 The control signals are the output signals Gout3'~Gout4' of the shift registers 530, 540 of the second stage, respectively. By analogy, the shift registers 510-540 can sequentially output the output signals Gout1'~Gout4' according to the forward input signal FW and the reverse input signal BW.

That is to say, since the clock phase of the first clock signal received by the output unit of each shift register 510 to 540 in FIG. 5 is different from the second clock signal received by the reset unit by two gate-line on-times, each The ESD cells of a shift register 510-540 have sufficient discharge time before the reset unit resets the voltage of the bootstrap node. In other words, the electrostatic discharge units of the shift registers 510-540 of this embodiment do not require a large-area transistor design, so the layout area occupied by the shift registers 510-540 on the display panel can be effectively reduced. Moreover, the shift registers 510 to 540 of this embodiment are separately arranged on both sides of the display panel, so that the display panel of this embodiment also has the characteristics of a narrow bezel.

7 is a schematic diagram of a gate driving circuit according to yet another embodiment of the present invention. FIG. 8 is a driving timing diagram of the gate driving circuit according to the embodiment of FIG. 7. 7 and 8, the gate driving circuit 700 is a gate driving circuit on an array. In this embodiment, the gate driving circuit 700 includes a plurality of shift registers 710-780, wherein the number of shift registers is not limited to that shown in FIG. 7, and the shift registers 710-780 may be, for example, the above-mentioned FIG. 1 and FIG. 2 Examples of shift register 200. Therefore, the relevant circuit features and implementation details of the shift registers 710-780 of this embodiment can be combined with the descriptions of the above-mentioned embodiments of FIG. 1 and FIG. 2 to obtain sufficient teachings, suggestions, and implementation descriptions, and thus will not be repeated.

In this embodiment, the gate driving circuit 700 can increase the discharge time of each of the electrostatic discharge circuits of the shift registers 710-780 through timing control, so as to effectively reduce the electrostatic discharge of each of the shift registers 710-780. The layout area of the circuit on the display panel. For example, the gate driving circuit 700 can drive the shift registers 710~780 by seven reference clock signals CK1"~CK7", and the clock phases of the seven reference clock signals CK1"~CK7" are sequentially different by two One of the gate line conduction time (as shown in Figure 8). In this embodiment, the first clock signal of each shift register 710~780 is sequentially selected from one of the seven reference clock signals CK1"~CK7", and the first The two clock signals are sequentially selected from one of the seven reference clock signals CK1"~CK7". It is worth noting that the first clock signal and the second clock signal of each shift register 710-780 differ by two gate-line on-times. Moreover, the first control signal received by each shift register 710~780 is the output signal of the shift register 710~780 of the previous stage, and the second control signal of each shift register 710~780 is the latter stage of the The output signal of the shift register.

In detail, as shown in FIG. 7, the shift register 710 receives the reference clock signal CK1″ as the first clock signal received by the output unit, and the shift register 710 receives the reference clock signal CK4″ as the received clock signal by the reset unit The second clock signal. Therefore, the first clock signal and the second clock signal received by the shift register 710 differ by two gate line on-times. The shift register 720 receives the reference clock signal CK2" as the first clock signal received by the output unit, and the shift register 720 receives the reference clock signal CK5" as the second clock signal received by the reset unit. Therefore, the first clock signal and the second clock signal received by the shift register 720 differ by two gate line on-times. By analogy, the shift registers 730-780 sequentially select two reference clock signals that differ by two gate line on-times as the first clock signal and the second clock signal, respectively.

In more detail, after the shift register 710 receives the start signal STV, the shift register 710 outputs the output signal Gout1" according to the forward input signal FW and the reverse input signal BW. As shown in FIG. 7, the shift register 720~ The first control signals received by 780 are the output signals Gout1"~Gout7" of the shift registers 710~770 of the previous stage, and the second control signals of the shift registers 710~770 are the shift registers 720~ of the latter stage, respectively. The output signals Gout2"~Gout8" of 780. By analogy, the shift registers 710~780 can sequentially output the output signals Gout1"~Gout8" according to the forward input signal FW and the reverse input signal BW.

That is to say, since the clock phase of the first clock signal received by the output unit of each shift register 710 to 780 in FIG. 7 is different from the second clock signal received by the reset unit by two gate-line on-times, each The electrostatic discharge unit of a shift register 710~780 has sufficient discharge time before the reset unit resets the voltage of the bootstrap node. In other words, the ESD cells of the shift registers 710-740 of this embodiment do not require a large-area transistor design, so the layout area occupied by the shift registers 710-740 on the display panel can be effectively reduced.

However, in an embodiment, the number of reference clock signals of the gate driving circuit 700 may not be limited to that shown in FIG. 7, and the manner of selecting the first clock signal and the second clock signal is not limited to that shown in FIG. 7. For example, if the first clock signal and the second clock signal received by each of the shift registers 710-780 of the gate driving circuit 700 want to differ by M gate-on times, the number N of reference clock signals may be at least The design is 3M+1 (N=3M+1), where N and M are positive integers greater than zero. Moreover, the first control signals received by the shift registers 720-780 are output signals of the previous stage, respectively, and the second control signals of the shift registers 710-770 are output signals of the latter stage, respectively.

In summary, the shift register and the gate driving circuit of the present invention can use an electrostatic discharge unit as a pull-down circuit to effectively pull down the voltage at the output end of the gate. Therefore, the shift register and the gate driving circuit of the present invention can effectively reduce the area occupied by the pull-down transistor on the display panel, or directly replace the pull-down transistor with an electrostatic discharge unit. In addition, the shift register and the gate driving circuit of the present invention can also increase the discharge time of the ESD unit through the design of the clock signal, which can further effectively reduce the transistor area of the ESD unit.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100, 200: shift register 110, 210: input unit 120, 220: output unit 130, 230: reset unit 140, 240: electrostatic discharge unit 211, 212, 221, 231, 241, 242: transistor 300, 500, 700: gate drive circuit 310~340, 510~540, 710~780: shift register C1: capacitor P: bootstrap node CS1, CS2: control signal BW, FW: input signal CLK1, CLK2: clock signal VGL: gate Very low voltage Gout: gate output STV: start signal CK1~CK4, CK1'~CK8', CK1"~CK7": reference clock signal Gout1~Gout4, Gout1'~Gout4', Gout1"~Gout8": output signal

FIG. 1 is a schematic diagram of a shift register according to an embodiment of the invention. 2 is a circuit diagram of a shift register according to an embodiment of the invention. 3 is a schematic diagram of a gate driving circuit according to an embodiment of the invention. FIG. 4 is a driving timing diagram of the gate driving circuit according to the embodiment of FIG. 3. 5 is a schematic diagram of a gate driving circuit according to another embodiment of the invention. 6 is a driving timing diagram of the gate driving circuit according to the embodiment of FIG. 5. 7 is a schematic diagram of a gate driving circuit according to yet another embodiment of the present invention. FIG. 8 is a driving timing diagram of the gate driving circuit according to the embodiment of FIG. 7.

100: shift register

110: input unit

120: output unit

130: reset unit

140: Electrostatic discharge unit

Claims (10)

A shift register includes: an input unit providing an input signal; an output unit coupled to the input unit and a gate output terminal, the output unit passing the gate output terminal according to the input signal Output an output signal; an electrostatic discharge unit, coupled to the output unit, when the gate output terminal outputs the output signal, the electrostatic discharge unit pulls down the voltage at the gate output terminal according to a gate low voltage And a reset unit, coupled to the input unit and the output unit, when the electrostatic discharge unit pulls down the voltage at the output terminal of the gate, the reset unit resets the voltage of a bootstrap node. The shift register according to item 1 of the patent application scope, wherein the input unit includes: a first transistor, wherein a control terminal of the first transistor receives a first control signal, and the first A first terminal of the transistor receives a first input signal; and a second transistor, wherein a control terminal of the second transistor receives a second control signal, wherein a first of the second transistor Is coupled to a second end of the first transistor, and a second end of the second transistor receives a second input signal, wherein the second end of the first transistor and the second The first end of the second transistor is coupled to the output unit. The shift register according to item 2 of the patent application scope, wherein the output unit includes: a third transistor, wherein a control terminal of the third transistor is coupled to the first transistor Two ends and the first end of the second transistor, wherein a first end of the third transistor receives a first clock signal, and a second end of the third transistor is coupled to the Describe the gate output. The shift register of claim 3, wherein the reset unit includes: a fourth transistor, wherein a control terminal of the fourth transistor receives a second clock signal, wherein the fourth A first end of the transistor is coupled to the bootstrap node, and a second end of the fourth transistor receives the gate low voltage. The shift register according to item 4 of the patent application scope, wherein a clock phase of the first clock signal differs from the second clock signal by two gate-line on-times, and the first input signal is the previous stage Or an output signal provided by the shift register of the previous stage, and the second input signal is an output signal provided by the shift register of the latter stage or the second stage. The shift register according to item 1 of the patent application scope, wherein the electrostatic discharge unit includes: a fifth transistor, wherein a first end of the fifth transistor is coupled to the gate output terminal, wherein A control terminal of the fifth transistor is coupled to a second terminal of the fifth transistor, and the second terminal of the fifth transistor receives the gate low voltage; and a sixth circuit A crystal, wherein a first terminal of the sixth transistor receives the gate low voltage, wherein a control terminal of the sixth transistor is coupled to a second terminal of the sixth transistor, and the The second terminal of the sixth transistor is coupled to the gate output terminal, wherein the first terminal of the fifth transistor is coupled to the second terminal of the sixth transistor, and the The second end of the fifth transistor is coupled to the first end of the sixth transistor. A gate drive circuit, including: a plurality of shift registers as described in item 1 of the patent application range, wherein, in a drive cycle, the output units of the plurality of shift registers are based on the input signal The voltage at the gate output terminal is pulled up by a first clock signal, so that the gate output terminal outputs the output signal, and then the electrostatic discharge unit pulls down the voltage at the gate output terminal, where After the electrostatic discharge unit pulls down the voltage at the output terminal of the gate, the reset unit of the plurality of shift registers resets the voltage of the bootstrap node by the low voltage of the gate according to a second clock signal, Wherein, a clock phase of the first clock signal differs from the second clock signal by two gate line on-times. The gate drive circuit according to item 7 of the patent application range, wherein the gate drive circuit drives the plurality of shift registers with four reference clock signals, and the clock phases of the four reference clock signals A gate line conduction time differs in sequence, wherein the first clock signals of the multiple shift registers are the first or second of the four reference clock signals, and the multiple shift registers have The second clock signal is the third or fourth of the four reference clock signals, wherein a first control signal of the plurality of shift registers is an output signal of the shift register of the previous stage, and A second control signal of the plurality of shift registers is an output signal of the shift register of the subsequent stage. The gate drive circuit as described in item 7 of the patent application range, wherein the gate drive circuit drives the plurality of shift registers with eight reference clock signals, and the clock phases of the eight reference clock signals The gate-on time differs by half in sequence, wherein the multiple shift registers are divided into an odd group and an even group, wherein the first clocks of the multiple shift registers of the odd group The signal is the first or third of the eight reference clock signals, and the first clock signal of the multiple shift registers of the even group is the second of the multiple reference clock signals Or a fourth, wherein the second clock signal of the multiple shift registers of the odd group is the fifth or seventh of the multiple reference clock signals, and the The second clock signals of the multiple shift registers are the sixth or eighth of the multiple reference clock signals, wherein a first control signal of the multiple shift registers is the shift of the first two stages An output signal of the register, and a second control signal of the plurality of shift registers is an output signal of the shift register of the second stage. The gate drive circuit according to item 7 of the patent application range, wherein the gate drive circuit drives the plurality of shift registers by a plurality of reference clock signals, and the clock phases of the plurality of reference clock signals The gate line conduction time differs by half in sequence, wherein the respective first clock signals of the plurality of shift registers are sequentially selected from one of the multiple reference clock signals, and the multiple The second clock signals of each shift register are sequentially selected from the other of the multiple reference clock signals, wherein one of the multiple reference clock signals and the multiple reference clock signals The other of the two differs by the conduction time of the two gate lines, where a first control signal of the plurality of shift registers is an output signal of the shift register of the previous stage, and the A second control signal is an output signal of the shift register of the subsequent stage.

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