TW202018925A - Optical sensor structure and method for forming the same - Google Patents

Optical sensor structure and method for forming the same Download PDF

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TW202018925A
TW202018925A TW107138601A TW107138601A TW202018925A TW 202018925 A TW202018925 A TW 202018925A TW 107138601 A TW107138601 A TW 107138601A TW 107138601 A TW107138601 A TW 107138601A TW 202018925 A TW202018925 A TW 202018925A
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light
substrate
item
optical sensing
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TWI686940B (en
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李新輝
曾漢良
林學榮
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世界先進積體電路股份有限公司
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Abstract

An optical sensor structure is provided. The optical sensor structure includes a sensor pixel array in a substrate, and the sensor pixel array having a plurality of sensor pixels, a collimating layer on the substrate, and at least a through-substrate via. The at least a through-substrate via extends from a first surface to an opposite second surface of the substrate, and the at least a through-substrate via is in the sensor pixel array and does not vertically overlap with the plurality of sensor pixels.

Description

光學感測結構及其形成方法 Optical sensing structure and its forming method

本發明係關於一種感測結構,特別是有關於一種光學感測結構及其形成方法。 The present invention relates to a sensing structure, in particular to an optical sensing structure and its forming method.

現今的行動電子裝置(例如手機、平板電腦、筆記型電腦等)通常配備有使用者辨識系統,用以保護個人資料安全。由於每個人的指紋皆不同,因此指紋感測器是一種常見並可靠的使用者辨識系統。 Today's mobile electronic devices (such as mobile phones, tablet computers, notebook computers, etc.) are usually equipped with user identification systems to protect personal data. Since each person's fingerprint is different, the fingerprint sensor is a common and reliable user identification system.

市面上的指紋感測器常使用光學技術以感測使用者的指紋,這種基於光學技術的指紋感測器之光學元件可包括光準直器(light collimator)、分束器、聚焦鏡以及線性感測器等,其中使用準直器(collimator)來使入射到感測器的光線平行前進,以減少因光發散所導致之能量損失。 The fingerprint sensors on the market often use optical technology to sense a user's fingerprint. The optical elements of such a fingerprint sensor based on optical technology may include a light collimator, a beam splitter, a focusing lens, and Linear sensors, etc., where a collimator is used to advance light incident on the sensor in parallel to reduce energy loss due to light divergence.

傳統上,必須在平面上拉長金屬導線,經過許多不同的結構層才能將指紋感測器連接至其他裝置,導致體積增加、訊號衰減、以及成本的提高。 Traditionally, metal wires must be elongated on a flat surface and pass through many different structural layers to connect the fingerprint sensor to other devices, resulting in increased volume, signal attenuation, and increased cost.

雖然現有的光學指紋感測器大致符合需求,但並非各方面皆令人滿意,特別是提升高光學指紋感應器的光準直器與其他裝置的連接技術仍需進一步改善。 Although the existing optical fingerprint sensors generally meet the requirements, they are not satisfactory in all aspects. In particular, the improvement of the connection technology between the optical collimator of the high optical fingerprint sensor and other devices needs further improvement.

本發明實施例提供一種光學感測結構,上述光學感測結構包括位於基板中的感測畫素陣列,其中上述感測畫素陣列包括複數個感測畫素、位於基板之上的光準直層、以及至少一導通孔,上述至少一導通孔由上述基板的第一表面延伸至相對的第二表面,其中上述至少一導通孔位於上述感測畫素陣列中,且不與上述感測畫素垂直重疊。 An embodiment of the present invention provides an optical sensing structure. The optical sensing structure includes a sensing pixel array in a substrate, wherein the sensing pixel array includes a plurality of sensing pixels, and light collimation on the substrate Layer and at least one via hole, the at least one via hole extends from the first surface of the substrate to the opposite second surface, wherein the at least one via hole is located in the sensing pixel array and is not in contact with the sensing picture The elements overlap vertically.

本發明實施例另提供一種光學感測結構的形成方法,此方法包括在基板中形成至少一導通孔、在上述基板中形成感測畫素陣列,其中上述感測畫素陣列包括複數個感測畫素,且其中上述至少一導通孔位於上述感測畫素陣列中,且不與上述感測畫素垂直重疊、以及在上述基板之上形成光準直層。 An embodiment of the present invention further provides a method for forming an optical sensing structure. The method includes forming at least one via hole in a substrate, and forming a sensing pixel array in the substrate, wherein the sensing pixel array includes a plurality of sensing elements Pixels, and wherein the at least one via hole is located in the sensing pixel array and does not vertically overlap the sensing pixel, and a light collimating layer is formed on the substrate.

本發明實施例的光學感測結構可應用於多種類型的光學指紋辨識系統,為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉數個實施例,並配合所附圖式,作詳細說明如下。 The optical sensing structure of the embodiments of the present invention can be applied to various types of optical fingerprint recognition systems. In order to make the above objects, features and advantages of the present invention more obvious and understandable, a few embodiments are given below in conjunction with the accompanying drawings The formula is described in detail below.

10‧‧‧光學感測結構 10‧‧‧Optical sensing structure

90‧‧‧導電部件 90‧‧‧Conductive parts

100‧‧‧基板 100‧‧‧ substrate

100A‧‧‧頂表面 100A‧‧‧Top surface

100B、102B‧‧‧底表面 100B, 102B‧‧‧Bottom surface

100B'‧‧‧第二表面 100B'‧‧‧Second surface

102‧‧‧孔洞 102‧‧‧hole

102’‧‧‧貫孔 102’‧‧‧through hole

102S‧‧‧側壁 102S‧‧‧Side wall

104‧‧‧晶種層 104‧‧‧Seed layer

106‧‧‧導電層 106‧‧‧conductive layer

108‧‧‧導孔 108‧‧‧Guide hole

110‧‧‧導通孔 110‧‧‧via

200‧‧‧感測畫素陣列 200‧‧‧sensor pixel array

202‧‧‧感測畫素 202‧‧‧sensing pixels

300‧‧‧透光柱 300‧‧‧Transparent column

400‧‧‧遮光層 400‧‧‧shading layer

500‧‧‧遮光蓋 500‧‧‧Blackout

600‧‧‧光準直層 600‧‧‧Light collimation layer

以下將配合所附圖式詳述本揭露之實施例。應注意的是,依據在業界的標準做法,各種特徵並未按照比例繪製且僅用以說明例示。事實上,可能任意地放大或縮小元件的尺寸,以清楚地表現出本揭露的特徵。 The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that according to standard practices in the industry, various features are not drawn to scale and are used for illustration only. In fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

第1-7、8A、8B、9、10圖係根據本發明的一些實施例,繪示出光學感測結構之製造方法的剖面示意圖。 Figures 1-7, 8A, 8B, 9, and 10 are schematic cross-sectional views illustrating a method of manufacturing an optical sensing structure according to some embodiments of the present invention.

以下的揭示內容提供許多不同的實施例或範例,以展示本揭露的不同部件。以下將揭示本說明書各部件及其排列方式之特定範例,用以簡化本揭露敘述。當然,這些特定範例並非用於限定本揭露。例如,若是本說明書以下的發明內容敘述了將形成第一部件於第二部件之上或上方,即表示其包括了所形成之第一及第二部件是直接接觸的實施例,亦包括了尚可將附加的部件形成於上述第一及第二部件之間,則第一及第二部件為未直接接觸的實施例。此外,本揭露說明中的各式範例可能使用重複的參照符號及/或用字。這些重複符號或用字的目的在於簡化與清晰,並非用以限定各式實施例及/或所述配置之間的關係。 The following disclosure provides many different embodiments or examples to show the different components of the present disclosure. The following will disclose specific examples of components and arrangements in this specification to simplify the disclosure. Of course, these specific examples are not intended to limit this disclosure. For example, if the following summary of the description of this specification describes the formation of the first component on or above the second component, it means that it includes an embodiment where the formed first and second components are in direct contact, and also includes Additional components can be formed between the first and second components, and the first and second components are embodiments that are not in direct contact. In addition, various examples in this disclosure description may use repeated reference symbols and/or words. The purpose of these repeated symbols or words is to simplify and clarify, not to limit the relationship between the various embodiments and/or the configurations.

再者,為了方便描述圖式中一元件或部件與另一(些)元件或部件的關係,可使用空間相對用語,例如「在...之下」、「下方」、「下部」、「上方」、「上部」及諸如此類用語。除了圖式所繪示之方位外,空間相對用語亦涵蓋使用或操作中之裝置的不同方位。當裝置被轉向不同方位時(例如,旋轉90度或者其他方位),則其中所使用的空間相對形容詞亦將依轉向後的方位來解釋。 Furthermore, in order to conveniently describe the relationship between one element or component and another element(s) in the drawing, relative terms in space may be used, such as "below", "below", "lower", "" "Above", "upper" and the like. In addition to the orientation shown in the drawings, the relative spatial terms also cover different orientations of the device in use or operation. When the device is turned to different orientations (for example, rotated 90 degrees or other orientations), the relative adjectives used in space will also be interpreted according to the turned orientation.

在此,「約」、「大約」、「大抵」之用語通常表示在一給定值或範圍的20%之內,較佳是10%之內,且更佳是5%之內,或3%之內,或2%之內,或1%之內,或0.5%之內。應注意的是,說明書中所提供的數量為大約的數量,亦即在沒有特定說明「約」、「大約」、「大抵」的情況下,仍可隱含 「約」、「大約」、「大抵」之含義。 Here, the terms “about”, “approximately” and “approximately” generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the description is an approximate quantity, that is, if there is no specific description of "about", "approximate", "approximately", it can still be implied The meanings of "approximately", "approximately" and "approximately".

以下說明本發明實施例之光學感測裝置及其形成方法。然而,應理解的是,以下的實施例僅用於說明以特定方法製作及使用本發明實施例,並非用以侷限本發明的範圍。本領域具有通常知識者將可容易理解在其他實施例的範圍內可做各種的修改。再者,雖然下述的方法實施例是以特定順序進行說明,但其他方法實施例可以另一合乎邏輯的順序進行,且可包括少於或多於此處討論的步驟。 The optical sensing device and the forming method thereof according to the embodiments of the present invention are described below. However, it should be understood that the following embodiments are only used to illustrate that the embodiments of the present invention are made and used by a specific method, and are not intended to limit the scope of the present invention. Those of ordinary skill in the art will readily understand that various modifications can be made within the scope of other embodiments. Furthermore, although the method embodiments described below are described in a specific order, other method embodiments may be performed in another logical order, and may include fewer or more steps than discussed herein.

本發明實施例提供一種光學感測結構及其形成方法,特別是一種包括光準直層的光學感測結構,其利用位於光準直層下方的導通孔(through-substrate via,TSV)垂直導通堆疊的裝置,使訊號傳遞的方式由水平改成垂直傳輸。如此一來,可以增加裝置堆疊密度、縮小體積、以及提升電性能。此外,由於無須額外形成用於封裝的金屬導線、模製化合物(molding compound)、及封裝基板,可進一步縮減結構厚度,以及降低因熱膨脹係數不匹配所導致的缺陷。 Embodiments of the present invention provide an optical sensing structure and a method for forming the same, in particular, an optical sensing structure including a light collimating layer, which utilizes a through-substrate via (TSV) under the light collimating layer for vertical conduction The stacked device changes the signal transmission method from horizontal to vertical transmission. In this way, the stacking density of the device can be increased, the volume can be reduced, and the electrical performance can be improved. In addition, since there is no need to additionally form metal wires, molding compounds, and packaging substrates for packaging, the thickness of the structure can be further reduced, and defects caused by mismatched thermal expansion coefficients can be reduced.

此外,本發明實施例更進一步利用感測畫素陣列中未設置感測畫素的區域,將導通孔設置在感測畫素陣列中。有別於將導通孔設置在感測畫素陣列的外圍區域,將導通孔設置在感測畫素陣列中能更進一步縮小光學感測結構的體積,並提高基板利用率。 In addition, the embodiment of the present invention further utilizes the area in the sensing pixel array where no sensing pixel is provided, and sets the via hole in the sensing pixel array. Different from disposing the via hole in the peripheral area of the sensing pixel array, disposing the via hole in the sensing pixel array can further reduce the volume of the optical sensing structure and improve substrate utilization.

第1-7、8A、8B、9、10圖是根據本發明的一些實施例,繪示出用於形成第10圖之光學感測結構10的製程中之各個不同階段的製程剖面示意圖。 FIGS. 1-7, 8A, 8B, 9, and 10 are schematic cross-sectional views of various stages in the process for forming the optical sensing structure 10 of FIG. 10 according to some embodiments of the present invention.

首先請參考第1圖,在一些實施例中,提供一基板100,其具有孔洞102。在一實施例中,上述基板100可為矽基板、矽鍺(silicon germanium,SiGe)基板、化合物半導體(compound semiconductor)基板、塊體半導體(bulk semiconductor)基板、絕緣體上覆半導體(semiconductor-on-insulator,SOI)基板或類似基板,其可為摻雜(例如,使用p-型或n-型摻質(dopant))或未摻雜的。一般而言,絕緣體上覆半導體基板包括形成於絕緣體上的半導體材料的膜層。舉例來說,此絕緣層可為,埋藏氧化物(buried oxide,BOX)層、氧化矽(silicon oxide)層、或類似層。提供上述絕緣層於基板上,通常是矽(silicon)或玻璃(glass)基板。亦可使用其他基板,例如多層(multi-layered)或梯度(gradient)基板。在一些實施例中,半導體基板之半導體材料可包括含矽(silicon,Si)或鍺(germanium,Ge)的元素半導體;包括碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)或銻化銦(indium antimonide)的化合物(compound)半導體;包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、或GaInAsP的合金半導體;或上述之組合。 First, please refer to FIG. 1. In some embodiments, a substrate 100 is provided with holes 102. In an embodiment, the substrate 100 may be a silicon substrate, a silicon germanium (SiGe) substrate, a compound semiconductor substrate, a bulk semiconductor substrate, or a semiconductor-on-insulator Insulator (SOI) substrate or similar substrate, which may be doped (for example, using p-type or n-type dopant) or undoped. In general, the semiconductor-on-insulator substrate includes a film layer of semiconductor material formed on the insulator. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The above-mentioned insulating layer is provided on the substrate, usually a silicon or glass substrate. Other substrates may also be used, such as multi-layered or gradient substrates. In some embodiments, the semiconductor material of the semiconductor substrate may include elemental semiconductors containing silicon (silicon, Si) or germanium (Ge); including silicon carbide (silicon carbide), gallium arsenic (gallium arsenic), and gallium phosphide (gallium phosphide), indium phosphide, indium arsenide, or indium antimonide compound semiconductors; including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP Alloy semiconductor; or a combination of the above.

在一些實施例中,基板100可包含各種隔離部件(未繪示),用以定義主動區,並電性隔離基板100之中/之上的主動區元件。在一些實施例中,隔離部件包含淺溝槽隔離(shallow trench isolation,STI)部件、局部矽氧化(local oxidation of silicon,LOCOS)部件、其他合適的隔離部件、或上述之組合。 In some embodiments, the substrate 100 may include various isolation components (not shown) to define active regions and electrically isolate the active region elements in/on the substrate 100. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination of the foregoing.

繼續參考第1圖,上述孔洞102位於將於後形成的感測畫素陣列200(請參考第5圖)的預定區,且將在後續製程中成為導通孔110(請參考第9圖),以將光學感測裝置10與其他裝置連接。上述孔洞102自基板100之頂表面100A朝向基板100之底表面100B延伸,但並未延伸至底表面100B。雖然在所繪示的實施例中,基板100具有三個孔洞102,但本發明實施例不限於此,上述基板100可以依實際設計需求而具有更多或更少數量的孔洞102,例如1個孔洞102。在一些實施例中,孔洞102之側壁102S可以與孔洞102之底表面102B夾一角度θ,上述角度θ在約90度至130度的範圍。舉例來說,上述角度θ可以為90度(即,孔洞102具有垂直的側壁)、或可以為92度(即,孔洞102具有傾斜的側壁)。在一些實施例中,孔洞102的深度在約25微米至約300微米,例如約100微米。在一些實施例中,孔洞102的直徑在約10微米至約150微米,舉例來說,為約50微米。在一些實施例中,孔洞102的深寬比(aspect ratio)在約1至20的範圍。可藉由適當的製程形成上述孔洞102,例如微影和蝕刻製程。 Continuing to refer to FIG. 1, the above-mentioned hole 102 is located in a predetermined area of the sensing pixel array 200 (refer to FIG. 5) to be formed later, and will become a via hole 110 (refer to FIG. 9) in the subsequent manufacturing process, In order to connect the optical sensing device 10 with other devices. The hole 102 extends from the top surface 100A of the substrate 100 toward the bottom surface 100B of the substrate 100, but does not extend to the bottom surface 100B. Although in the illustrated embodiment, the substrate 100 has three holes 102, the embodiments of the present invention are not limited thereto. The above-mentioned substrate 100 may have more or less number of holes 102 according to actual design requirements, such as one Hole 102. In some embodiments, the side wall 102S of the hole 102 may form an angle θ with the bottom surface 102B of the hole 102, and the above-mentioned angle θ ranges from about 90 degrees to 130 degrees. For example, the above-mentioned angle θ may be 90 degrees (that is, the hole 102 has a vertical side wall), or may be 92 degrees (that is, the hole 102 has an inclined side wall). In some embodiments, the depth of the hole 102 is from about 25 microns to about 300 microns, such as about 100 microns. In some embodiments, the diameter of the hole 102 is about 10 microns to about 150 microns, for example, about 50 microns. In some embodiments, the aspect ratio of the hole 102 ranges from about 1 to 20. The above-mentioned holes 102 can be formed by suitable processes, such as lithography and etching processes.

請參考第2圖,根據一些實施例,可在孔洞102的側壁102S和底表面102B上,以及在基板100之頂表面100A上順應地形成晶種層104。上述晶種層104可用於在後續製程(例如,電鍍(electrode plating)製程)中形成導電層106(如第3圖所示)。在一些實施例中,上述晶種層104之材料可以是導電材料,例如銅、鎢、鋁、類似材料、或上述之組合,且可以藉由化學氣相沉積(chemical vapor deposition,CVD)製程、原子層 沉積(atomic layer deposition,ALD)製程、物理沉積(physical vapor deposition,PVD)製程、其他合適的製程、或前述之組合來形成上述晶種層104。在一些實施例中,藉由上述方法所形成之晶種層104之厚度在約0.1微米至3微米。 Referring to FIG. 2, according to some embodiments, a seed layer 104 may be conformally formed on the sidewall 102S and bottom surface 102B of the hole 102 and on the top surface 100A of the substrate 100. The seed layer 104 can be used to form the conductive layer 106 (as shown in FIG. 3) in a subsequent process (for example, an electrode plating process). In some embodiments, the material of the seed layer 104 may be a conductive material, such as copper, tungsten, aluminum, similar materials, or a combination thereof, and may be formed by a chemical vapor deposition (CVD) process, Atomic layer The seed layer 104 is formed by an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or a combination of the foregoing. In some embodiments, the thickness of the seed layer 104 formed by the above method is about 0.1 μm to 3 μm.

請參考第3圖,根據一些實施例,在形成上述晶種層104之後,可以藉由電鍍製程在孔洞102內和基板100之頂表面100A上形成導電層106。在後續製程中,上述孔洞102、晶種層104、以及導電層106將共同構成導孔108(如第4圖所示)。在一些實施例中,上述導電層106可以包含金屬或其他合適的導電材料,例如:鎢、銅、鎳、鋁、多晶矽或前述之組合。 Referring to FIG. 3, according to some embodiments, after forming the seed layer 104, a conductive layer 106 may be formed in the hole 102 and the top surface 100A of the substrate 100 by an electroplating process. In the subsequent manufacturing process, the hole 102, the seed layer 104, and the conductive layer 106 will collectively form a via 108 (as shown in FIG. 4). In some embodiments, the conductive layer 106 may include metal or other suitable conductive materials, such as tungsten, copper, nickel, aluminum, polysilicon, or a combination of the foregoing.

第4圖繪示出上述導孔108的形成。在一些實施例中,對基板100的頂表面100A進行第一平坦化製程,以去除孔洞102外過量的晶種層104和導電層106,並暴露基板100的頂表面100A。在一些實施例中,第一平坦化製程可以包括化學機械研磨(chemical mechanical polishing,CMP)製程、研磨(grinding)製程、蝕刻製程、其他合適的製程、或前述之組合。 FIG. 4 illustrates the formation of the above-mentioned via hole 108. In some embodiments, a first planarization process is performed on the top surface 100A of the substrate 100 to remove excess seed layer 104 and conductive layer 106 outside the holes 102 and expose the top surface 100A of the substrate 100. In some embodiments, the first planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, other suitable processes, or a combination of the foregoing.

請參考第5圖,在一些實施例中,在基板100中形成感測畫素陣列200,且上述感測畫素陣列200具有複數個感測畫素202。在一些實施例中,基板100可包含各種裝置元件。此些裝置元件並未繪示以求簡化及清晰。這些裝置元件可以包括電晶體、二極體、其他合適元件或上述之組合。舉例來說,電晶體可為金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)、互補式金屬氧化物半導體(complementary metal oxide semiconductor,CMOS) 電晶體、雙極性接面電晶體(bipolar junction transistors,BJT)、高壓電晶體、高頻電晶體、p-通道及/或n-通道場效電晶體(PFETs/NFETs)等等。 Please refer to FIG. 5. In some embodiments, a sensing pixel array 200 is formed in the substrate 100, and the sensing pixel array 200 has a plurality of sensing pixels 202. In some embodiments, the substrate 100 may include various device elements. These device components are not shown for simplicity and clarity. These device elements may include transistors, diodes, other suitable elements, or combinations thereof. For example, the transistor may be a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) Transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.

在一些實施例中,上述基板100可以包括各種導電元件(例如:導線或導孔)(未繪示)。舉例來說,上述導電元件可由鋁(Aluminum)、銅(Copper)、鎢(Tungsten)、其他適當之導電材料、上述之合金、或上述之組合所形成。 In some embodiments, the above substrate 100 may include various conductive elements (eg, wires or vias) (not shown). For example, the conductive element may be formed of aluminum, copper, tungsten, other suitable conductive materials, the above alloy, or a combination of the above.

繼續參考第5圖,上述導孔108位於感測畫素陣列200中,但不與上述感測畫素202垂直重疊。在一些實施例中,上述感測畫素202可與訊號處理電路(signal process circuitry)(未繪示)連接。在一些實施例中,感測畫素陣列200所具有之感測畫素202的數量取決於光學感測區的面積大小。每個感測畫素202可包含一或多個光偵測器(photodetector)。在一些實施例中,光偵測器可包含光電二極體,其中光電二極體可包含P型半導體層、本質層(intrinsic layer)、以及N型半導體層之三層結構的光電材料(photoelectric material),本質層吸收光以產生出激子(exciton),並且激子會在P型半導體層及N型半導體層的接面分成電子與電洞,進而產生電流訊號。在其他實施例中,光偵測器可也包含電荷耦合元件(charged coupling device,CCD)感測器、互補式金屬氧化物半導體(complimentary metal-oxide-semiconductor,CMOS)影像感測器、主動感測器、被動感測器、其他適合的感測器、或上述之組合。在一些實施例中,感測畫素202可藉由光偵測器將接收到的光訊號轉換成電子訊號,並透過訊號處理電路處理上述電子訊號。 With continued reference to FIG. 5, the via hole 108 is located in the sensing pixel array 200, but does not vertically overlap with the sensing pixel 202. In some embodiments, the sensing pixel 202 may be connected to signal process circuitry (not shown). In some embodiments, the number of sensing pixels 202 in the sensing pixel array 200 depends on the area of the optical sensing area. Each sensing pixel 202 may include one or more photodetectors. In some embodiments, the photodetector may include a photodiode, wherein the photodiode may include a P-type semiconductor layer, an intrinsic layer, and an N-type semiconductor layer. material), the intrinsic layer absorbs light to generate excitons, and the excitons are divided into electrons and holes at the junction of the P-type semiconductor layer and the N-type semiconductor layer, thereby generating a current signal. In other embodiments, the photodetector may also include a charged coupled device (CCD) sensor, a complementary metal-oxide-semiconductor (CMOS) image sensor, and an active sensor Sensors, passive sensors, other suitable sensors, or a combination of the above. In some embodiments, the sensing pixel 202 can convert the received optical signal into an electronic signal by a light detector, and process the electronic signal through a signal processing circuit.

在一些實施例中,如第5圖所示,在剖面示意圖中,感測畫素陣列200中的感測畫素202位於基板100的頂表面100A,且與上述導孔108錯開設置。值得注意的是,在第5圖所繪示之感測畫素陣列200的數量與排列方式僅為例示性的,本發明實施例並不以此為限,感測畫素202可為任何行列數目之陣列或其他的排列方式。 In some embodiments, as shown in FIG. 5, in the schematic cross-sectional view, the sensing pixels 202 in the sensing pixel array 200 are located on the top surface 100A of the substrate 100 and are offset from the above-mentioned via holes 108. It is worth noting that the number and arrangement of the sensing pixel array 200 shown in FIG. 5 are only exemplary, and the embodiment of the present invention is not limited to this. The sensing pixel 202 can be any row and column The number of arrays or other arrangements.

這種將導孔108與感測畫素202錯開且不垂直重疊的設置方式,可以充分利用感測畫素陣列中未設置感測畫素的區域,使將於後續製程中形成的導通孔設置在感測畫素陣列中。有別於將導通孔設置在感測畫素陣列的外圍區域,將導通孔設置在感測畫素陣列中能更進一步縮小光學感測結構的體積,並提高基板利用率。 This arrangement method in which the via hole 108 and the sensing pixel 202 are staggered and do not overlap vertically can make full use of the area of the sensing pixel array where the sensing pixel is not provided, so that the via hole to be formed in the subsequent process is set In the sensing pixel array. Different from disposing the via hole in the peripheral area of the sensing pixel array, disposing the via hole in the sensing pixel array can further reduce the volume of the optical sensing structure and improve substrate utilization.

請參考第6圖,形成設置於感測畫素陣列200之上並對應感測畫素202的複數個透光柱300。在一些實施例中,可先於基板100上毯覆性地形成透光材料層(未繪示),以覆蓋感測畫素陣列200。在一些實施例中,上述透光材料層可以包含透光材料,其對於在300奈米至1200奈米波長範圍下的光穿透率大於90%,從而允許部分入射光線穿過透光材料層而抵達感測畫素202。 Please refer to FIG. 6 to form a plurality of light-transmitting pillars 300 disposed on the sensing pixel array 200 and corresponding to the sensing pixels 202. In some embodiments, a light-transmitting material layer (not shown) may be blanket formed on the substrate 100 to cover the sensing pixel array 200. In some embodiments, the above light-transmitting material layer may include a light-transmitting material, which has a light transmittance greater than 90% in the wavelength range of 300 nm to 1200 nm, thereby allowing part of incident light to pass through the light-transmitting material layer And arrived at the sensing pixel 202.

在一些實施例中,上述透光材料層可以包含光固化材料(UV-curable material)、熱固化材料(thermosetting material)、或上述之組合。舉例來說,透光材料可包含例如聚甲基丙烯酸甲酯(poly(methyl methacrylate,PMMA)、聚對苯二甲酸乙二酯(polyethylene terephthalate,PET)、聚萘二甲酸乙 二醇酯(polyethylene naphthalate,PEN)聚碳酸酯(Polycarbonate,PC)、全氟環丁基(perfluorocyclobutyl,PFCB)聚合物、聚亞醯胺(Polyimide,PI)、壓克力樹酯、環氧樹脂(Epoxy resins)、聚丙烯(Polypropylene,PP)、聚乙烯(polyethylene,PE)、聚苯乙烯(Polystyrene,PS)、聚氯乙烯(Polyvinyl chloride,PVC)、其他適當之材料、或上述之組合。可以使用旋轉塗佈法(spin-coating)、鑄模(casting)、棒狀塗佈(bar coating)、刮刀塗佈(blade coating)、滾筒塗佈(roller coating)、線棒塗佈(wire bar coating)、浸漬塗佈(dip coating)、化學氣相沉積法(CVD)、其他適合之方法、或上述之組合,以於基板100上沉積上述透光材料層。在一些實施例中,藉由上述方法所形成之透光材料層之厚度在約10至約300微米的範圍,例如可為100微米。在其他實施例中,透光材料層之厚度在約100至約500微米的範圍,例如可為300微米。 In some embodiments, the light-transmitting material layer may include a UV-curable material, a thermosetting material, or a combination thereof. For example, the light-transmitting material may include, for example, poly (methyl methacrylate (PMMA), polyethylene terephthalate (PET), polyethylene naphthalate Polyethylene naphthalate (PEN) polycarbonate (Polycarbonate, PC), perfluorocyclobutyl (PFCB) polymer, polyimide (Polyimide, PI), acrylic resin, epoxy resin (Epoxy resins), polypropylene (Polypropylene, PP), polyethylene (PE), polystyrene (Polystyrene, PS), polyvinyl chloride (Polyvinyl chloride, PVC), other suitable materials, or a combination of the above. Spin-coating, casting, bar coating, blade coating, roller coating, wire bar coating can be used ), dip coating, chemical vapor deposition (CVD), other suitable methods, or a combination of the above, to deposit the above-mentioned light-transmitting material layer on the substrate 100. In some embodiments, the thickness of the light-transmitting material layer formed by the above method is in the range of about 10 to about 300 microns, for example, 100 microns. In other embodiments, the thickness of the light-transmitting material layer is in the range of about 100 to about 500 microns, for example, 300 microns.

接著,選擇性移除形成於基板100上的透光材料層,如第6圖所示。在一些實施例中,由於上述透光柱300對應設置於感測畫素202之上,故而在剖面示意圖中,上述透光柱300及上述導孔108亦為不垂直重疊的,換句話說,上述透光柱300及上述導孔108為錯開設置的。在一些實施例中,對應設置於感測畫素202之上的透光柱300可保護感測畫素202,並減少或避免感測畫素202於製程中受到污染及/或損害,進而影響光學感測結構10的靈敏度。在一些實施例中,每一個透光柱300對應地設置於每一個感測畫素202之上,如第6圖所示。在其他實施例中,至少一個透光柱300覆蓋兩個以上之感測畫素 202(未繪示)。在一些實施例中,在上視圖中,上述透光柱300可以為圓形、矩形、多邊形、任何形狀、或前述之組合,並且排列成陣列(未繪示)。 Next, the light-transmitting material layer formed on the substrate 100 is selectively removed, as shown in FIG. 6. In some embodiments, since the light-transmitting pillar 300 is correspondingly disposed on the sensing pixel 202, in the schematic cross-sectional view, the light-transmitting pillar 300 and the guide hole 108 are not vertically overlapped, in other words, The light transmission column 300 and the guide hole 108 are staggered. In some embodiments, the light-transmitting column 300 corresponding to the sensing pixel 202 can protect the sensing pixel 202 and reduce or prevent the sensing pixel 202 from being contaminated and/or damaged during the manufacturing process, thereby affecting The sensitivity of the optical sensing structure 10. In some embodiments, each light-transmitting pillar 300 is correspondingly disposed on each sensing pixel 202, as shown in FIG. 6. In other embodiments, at least one light-transmitting column 300 covers more than two sensing pixels 202 (not shown). In some embodiments, in the upper view, the light-transmitting pillar 300 may be circular, rectangular, polygonal, any shape, or a combination of the foregoing, and arranged in an array (not shown).

在一些實施例中,可使用圖案化製程以選擇性去除上述透光材料層,以形成上述透光柱300。在其中上述透光材料層為非光阻材料的一些實施例中,圖案化製程可包含微影製程與蝕刻製程。微影製程可包含例如:光阻塗佈(例如旋轉塗佈)、軟烤、曝光圖案、曝光後烘烤、光阻顯影、清洗及乾燥(例如硬烤)、其他適當的製程、或上述之組合。蝕刻製程可包含例如:濕式蝕刻製程、乾式蝕刻製程(例如,反應離子蝕刻(reactive ion etching,RIE)、電漿蝕刻、離子研磨)、其他適合的製程、或上述之組合。 In some embodiments, a patterning process may be used to selectively remove the light-transmitting material layer to form the light-transmitting pillar 300. In some embodiments in which the light-transmitting material layer is a non-photoresist material, the patterning process may include a lithography process and an etching process. The lithography process may include, for example: photoresist coating (such as spin coating), soft baking, exposure pattern, post-exposure baking, photoresist development, cleaning and drying (such as hard baking), other suitable processes, or the above combination. The etching process may include, for example, a wet etching process, a dry etching process (eg, reactive ion etching (RIE), plasma etching, ion milling), other suitable processes, or a combination thereof.

在其他實施例中,上述透光材料層可以是光阻材料,在此情況下,可藉由微影製程來圖案化上述透光材料層,以直接形成圖案化的透光柱300,而不需要額外經過蝕刻製程。上述微影製程類似於上述所提及的微影製程,故於此不再贅述。 In other embodiments, the light-transmitting material layer may be a photoresist material. In this case, the light-transmitting material layer may be patterned by a lithography process to directly form a patterned light-transmitting pillar 300 without An additional etching process is required. The aforementioned lithography process is similar to the aforementioned lithography process, so it will not be repeated here.

在一些實施例中,藉由上述方法所形成之透光柱300之厚度在約10至約300微米的範圍,例如可為100微米。在其他實施例中,透光柱300之厚度在約100至約500微米的範圍,例如可為300微米。 In some embodiments, the thickness of the light-transmitting pillar 300 formed by the above method is in the range of about 10 to about 300 microns, for example, 100 microns. In other embodiments, the thickness of the light-transmitting pillar 300 is in the range of about 100 to about 500 microns, for example, 300 microns.

接著,請參照第7圖,形成遮光層400於基板100上,並且填充於上述的複數個透光柱300之間。在一些實施例中,遮光層400可以包括光阻(例如:黑光阻或其他適當之非透明 的光阻)、油墨(例如:黑色油墨或其他適當之非透明的油墨)、模製化合物(molding compound,例如:黑色模製化合物或其他適當之非透明的模製化合物)、防焊材料(solder mask,例如:黑色防焊材料或其他適當之非透明的防焊材料)、其他合適的材料或上述之組合。 Next, referring to FIG. 7, a light-shielding layer 400 is formed on the substrate 100 and filled between the plurality of light-transmitting pillars 300 described above. In some embodiments, the light-shielding layer 400 may include a photoresist (eg, black photoresist or other suitable non-transparent Photoresist), ink (for example: black ink or other suitable non-transparent ink), molding compound (for example: black molding compound or other suitable non-transparent molding compound), solder mask ( solder mask, for example: black solder resist material or other suitable non-transparent solder resist material), other suitable materials or a combination of the above.

在一些實施例中,遮光層400可以是光固化材料、熱固化材料或上述之組合。在上述實施例中,可將遮光材料(未繪示)設置於基板100之上,且填充於複數個透光柱300之間,接著進行固化製程以固化上述遮光材料,以形成遮光層400。舉例而言,上述固化製程可為光固化製程、熱固化製程或上述組合。 In some embodiments, the light-shielding layer 400 may be a photo-curable material, a thermo-curable material, or a combination thereof. In the above embodiment, a light-shielding material (not shown) may be disposed on the substrate 100 and filled between the plurality of light-transmitting pillars 300, and then a curing process is performed to cure the light-shielding material to form the light-shielding layer 400. For example, the above curing process may be a photo curing process, a thermal curing process, or a combination of the above.

在另一些實施例中,上述遮光層400可以包括金屬材料。在上述遮光層400包括金屬材料的一些實施例中,可藉由在形成上述透光柱300之前,先在基板100上沉積包含金屬材料的晶種層(未繪示),接著將上述晶種層圖案化,以露出基板100上的感測畫素202,同時保留位於導孔108上的晶種層。在上視圖中,上述圖案化晶種層與感測畫素202的形狀為互補(未繪示)。在形成上述透光柱300之後,進行電鍍製程,以形成填充於複數個透光柱300之間的遮光層400,如第7圖所示。在一些實施例中,藉由電鍍製程或其他適合的製程所產生的遮光層400之厚度可以高於、相等於、或低於上述透光柱300。在一些實施例中,遮光層400可包含銅(Copper)、鎳(Nickel)、其他適合的金屬材料、或前述之組合。 In other embodiments, the light shielding layer 400 may include a metal material. In some embodiments where the light-shielding layer 400 includes a metal material, a seed layer (not shown) containing a metal material may be deposited on the substrate 100 before forming the light-transmitting pillar 300, and then the seed crystal The layer is patterned to expose the sensing pixels 202 on the substrate 100 while retaining the seed layer on the via hole 108. In the top view, the shape of the patterned seed layer and the sensing pixel 202 are complementary (not shown). After forming the light-transmitting pillars 300, an electroplating process is performed to form a light-shielding layer 400 filled between the plurality of light-transmitting pillars 300, as shown in FIG. In some embodiments, the thickness of the light-shielding layer 400 generated by the electroplating process or other suitable processes may be higher than, equal to, or lower than that of the light-transmitting pillar 300 described above. In some embodiments, the light shielding layer 400 may include copper, nickel, other suitable metal materials, or a combination of the foregoing.

此外,在上述遮光層400包括金屬材料的一些實施 例中,可以額外形成遮光蓋500於遮光層400之上。在這類實施例中,上述遮光蓋500例如可包含樹脂遮光材料,其對於在300奈米至1200奈米波長範圍下的光穿透率小於1%。遮光材料可以包含光固化材料、熱固化材料、或上述之組合。在一些實施例中,於遮光層400上所形成的遮光蓋500可避免感測畫素202接收到不需要的光線,並可防止入射光學感測結構10之光線所產生之串音(crosstalk),進而提升光學感測結構10的效能。 In addition, some implementations of the above-mentioned light-shielding layer 400 including metallic materials For example, a light-shielding cover 500 may be additionally formed on the light-shielding layer 400. In such an embodiment, the above-mentioned light-shielding cover 500 may include, for example, a resin light-shielding material, which has a light transmittance of less than 1% for a wavelength range of 300 nm to 1200 nm. The light-shielding material may include a photo-curable material, a thermo-curable material, or a combination of the foregoing. In some embodiments, the light-shielding cover 500 formed on the light-shielding layer 400 can prevent the sensing pixels 202 from receiving unnecessary light, and can prevent crosstalk caused by light incident on the optical sensing structure 10 , Thereby improving the performance of the optical sensing structure 10.

在一些實施例中,可藉由旋轉塗佈法(spin-coating)、化學氣相沉積法(CVD)、其他適當之方法、或上述之組合將遮光蓋的材料形成於遮光層400上,並進行固化製程(例如,光固化製程、熱固化製程或上述組合),以固化遮光材料,接著可以進行圖案化製程,以形成在遮光層400之上的遮光蓋500。上述經過圖案化製程之遮光蓋500僅覆蓋於遮光層400之上,而不會覆蓋透光柱300。在一些實施例中,藉由上述方法所形成之遮光蓋500之厚度在約0奈米至約500奈米的範圍,例如可為100奈米。在其他實施例中,遮光蓋500之厚度在約10奈米至約500奈米的範圍,例如可為200奈米。 In some embodiments, the material of the light-shielding cover may be formed on the light-shielding layer 400 by spin-coating, chemical vapor deposition (CVD), other suitable methods, or a combination thereof, and A curing process (for example, a light curing process, a thermal curing process, or a combination thereof) is performed to cure the light-shielding material, and then a patterning process may be performed to form the light-shielding cover 500 above the light-shielding layer 400. The light-shielding cover 500 after the patterning process only covers the light-shielding layer 400 and does not cover the light-transmitting pillar 300. In some embodiments, the thickness of the light shielding cover 500 formed by the above method is in the range of about 0 nanometers to about 500 nanometers, for example, 100 nanometers. In other embodiments, the thickness of the light shielding cover 500 is in the range of about 10 nanometers to about 500 nanometers, for example, 200 nanometers.

在一些實施例中,上述遮光蓋的材料可以包含非透明的碳黑、油墨、模製化合物、防焊材料、其他適當之材料、或上述之組合。在此情況下,上述的圖案化製程可包含微影製程與蝕刻製程。此處的微影製程與蝕刻製程可類似於前述關於第6圖中使用為非光阻材料來形成透光柱的實施例,故於此不再贅述。 In some embodiments, the material of the light-shielding cover may include non-transparent carbon black, ink, molding compound, solder resist material, other suitable materials, or a combination thereof. In this case, the above-mentioned patterning process may include a lithography process and an etching process. The photolithography process and the etching process here may be similar to the foregoing embodiments regarding the use of non-photoresist materials in FIG. 6 to form the light-transmitting pillars, so they will not be repeated here.

在其他實施例中,上述遮光蓋的材料可以包含非 透明的光阻材料。在此情況下,類似於先前關於第6圖中使用光阻材料來形成透光柱的實施例,可以直接圖案化上述遮光蓋的材料以在遮光層400上形成遮光蓋500,而不需要額外經過蝕刻製程。 In other embodiments, the material of the shading cover may include non- Transparent photoresist material. In this case, similar to the previous embodiment regarding the use of photoresist materials to form the light-transmitting pillars in FIG. 6, the material of the light-shielding cover can be directly patterned to form the light-shielding cover 500 on the light-shielding layer 400 without additional After the etching process.

在一些實施例中,在形成遮光蓋500於遮光層400之上之前,可執行平坦化製程(例如化學機械研磨(CMP)製程)以平坦化遮光層400,使得遮光層400與透光柱300之頂面齊平。接著,於上述實施例中,形成於經過平坦化製程之遮光層400之上的遮光蓋500之頂面將會略高於透光柱300之頂面,即如第8A圖所繪示。舉例來說,遮光層400之上的遮光蓋500之頂面將會略高於透光柱300之頂面約10奈米。 In some embodiments, before forming the light-shielding cover 500 over the light-shielding layer 400, a planarization process (such as a chemical mechanical polishing (CMP) process) may be performed to planarize the light-shielding layer 400, so that the light-shielding layer 400 and the light-transmitting pillar 300 The top surface is flush. Next, in the above embodiment, the top surface of the light-shielding cover 500 formed on the light-shielding layer 400 after the planarization process will be slightly higher than the top surface of the light-transmitting pillar 300, as shown in FIG. 8A. For example, the top surface of the light-shielding cover 500 above the light-shielding layer 400 will be slightly higher than the top surface of the light-transmitting pillar 300 by about 10 nm.

在其他實施例中,可藉由控制電鍍製程的時間,使得形成於圖案化晶種層之上的遮光層400之頂面略低於透光柱300之頂面(例如遮光層400之頂面略低於透光柱300之頂面約10奈米至約10微米),並且形成遮光蓋500於此遮光層400與透光柱300之頂面之上,使得此遮光蓋500之頂面略高於透光柱300之頂面(例如遮光蓋500之頂面略高於透光柱300之頂面約為10奈米),接著可執行平坦化製程(例如化學機械研磨(CMP)製程)以平坦化遮光蓋500,使得遮光蓋500與透光柱300之頂面齊平,即如第8B圖所繪示。 In other embodiments, the top surface of the light-shielding layer 400 formed on the patterned seed layer may be slightly lower than the top surface of the light-transmitting pillar 300 (for example, the top surface of the light-shielding layer 400) by controlling the time of the electroplating process (Slightly lower than the top surface of the light-transmitting pillar 300 by about 10 nm to about 10 microns) Higher than the top surface of the transparent pillar 300 (for example, the top surface of the light-shielding cover 500 is slightly higher than the top surface of the transparent pillar 300 by about 10 nanometers), and then a planarization process (for example, chemical mechanical polishing (CMP) process) can be performed The light-shielding cover 500 is planarized so that the light-shielding cover 500 is flush with the top surface of the light-transmitting pillar 300, as shown in FIG. 8B.

根據本發明之一些實施例中,設置於上述感測畫素202上的透光柱300、填充在上述透光柱之間的遮光層400、以及對應設置於遮光層400上的遮光蓋500(如果有的話)之組合共同構成一光準直層600。此光準直層的功能在於準直 (collimate)光線,以減少因光發散所導致之能量損失。在一些實施例中,光準直層上方可包含其他光學元件,例如:彩色濾光片(color filter)、玻璃、透鏡等(未繪示)。在一些實施例中,入射的光線透過光準直層600上方的光學元件經過光準直層600導入至感測畫素202。其中,透光柱300的深寬比(aspect ratio)在2至30的範圍,例如可為5、10、15、或20。若透光柱700太高(即深寬比太大),則透光柱300容易變形或倒塌,而導致製程難度提高,相對地也將提高製程成本。若透光柱300太寬(即深寬比太小),則容易接收到不必要的入射光,難以達到準直效果,因而降低光學感測結構10的靈敏度。 According to some embodiments of the present invention, the light-transmitting pillar 300 disposed on the sensing pixel 202, the light-shielding layer 400 filled between the light-transmitting pillars, and the light-shielding cover 500 correspondingly disposed on the light-shielding layer 400 ( If any, the combination of them together constitutes a light collimating layer 600. The function of this optical collimation layer is to collimate (collimate) Light to reduce the energy loss caused by light divergence. In some embodiments, the optical collimating layer may include other optical elements, such as color filters, glass, lenses, etc. (not shown). In some embodiments, the incident light is introduced into the sensing pixel 202 through the optical element above the light collimating layer 600 through the light collimating layer 600. The aspect ratio of the light-transmitting pillar 300 is in the range of 2 to 30, for example, 5, 10, 15, or 20. If the light-transmitting column 700 is too high (that is, the aspect ratio is too large), the light-transmitting column 300 is easily deformed or collapsed, resulting in an increase in the difficulty of the manufacturing process and a relatively high manufacturing cost. If the light transmission column 300 is too wide (that is, the aspect ratio is too small), it is easy to receive unnecessary incident light, and it is difficult to achieve the collimating effect, thus reducing the sensitivity of the optical sensing structure 10.

在一些實施例中,光準直層上方可包含設置於光準直層之上的蓋板層(未繪示)。蓋板層可為硬質透光材料,例如:鋁矽酸鹽玻璃(calcium aluminosilicate glass)、鈉鈣玻璃(soda lime glass)、藍寶石(sapphire)、透明聚合物、或其他適合的材料,使得至少部分的入射光線能夠穿透而到達感測畫素202,並且此硬質蓋板能夠保護在其之下的光學感測結構10及其他元件。 In some embodiments, a cover layer (not shown) disposed above the light collimating layer may be included above the light collimating layer. The cover plate layer may be a hard light-transmitting material, such as: calcium aluminosilicate glass, soda lime glass, sapphire, transparent polymer, or other suitable materials, so that at least part of The incident light can penetrate and reach the sensing pixel 202, and the hard cover can protect the optical sensing structure 10 and other components under it.

後續以第8B圖之結構來繼續用於形成光學感測結構10的製程的說明,但應可理解,亦可以使用第7圖或第8A圖之結構來形成光學感測結構10。接下來請參考第9圖,在一些實施例中,對基板100的底表面100B進行背面薄化(backside thinning)製程,以形成貫穿基板100的導通孔110。上述導通孔110具有從基板100的第一表面100A(亦稱為頂表面100A)延伸至基板100之相對的第二表面100B’的貫孔102’。此外,晶種層 104位於貫孔102’內,且介於基板100及填充在貫孔102’中的導電層106之間。在一些實施例中,進行上述背面薄化製程直到露出上述導電層106,以去除位於導電層106下方的一部份之晶種層104,如第9圖所示。在另一些實施例中,進行背面薄化製程直到露出上述晶種層104,因此一部分之晶種層104位於導電層106下方(未繪示)。上述貫孔102’、晶種層104、以及導電層106之組合共同構成導通孔110。上述導通孔110之底表面與基板100之第二表面100B’齊平。 The description of the process for forming the optical sensing structure 10 is continued with the structure of FIG. 8B, but it should be understood that the structure of FIG. 7 or FIG. 8A can also be used to form the optical sensing structure 10. Next, referring to FIG. 9, in some embodiments, a backside thinning process is performed on the bottom surface 100B of the substrate 100 to form a via 110 through the substrate 100. The via hole 110 has a through hole 102' extending from the first surface 100A (also referred to as the top surface 100A) of the substrate 100 to the opposite second surface 100B' of the substrate 100. In addition, the seed layer 104 is located in the through hole 102' and interposed between the substrate 100 and the conductive layer 106 filled in the through hole 102'. In some embodiments, the backside thinning process is performed until the conductive layer 106 is exposed to remove a part of the seed layer 104 under the conductive layer 106, as shown in FIG. 9. In other embodiments, the backside thinning process is performed until the seed layer 104 is exposed, so a part of the seed layer 104 is located under the conductive layer 106 (not shown). The combination of the through hole 102', the seed layer 104, and the conductive layer 106 together constitute the via hole 110. The bottom surface of the via hole 110 is flush with the second surface 100B' of the substrate 100.

請參考第10圖,在一些實施例中,在進行上述第二平坦化製程之後,可以在基板100的第二表面100B’上形成導電部件90,上述導電部件90與相應導通孔110連接,以形成光學感測結構10。可藉由導通孔110透過上述導電部件90將光學感測結構10與其他裝置電連接。上述導電部件90可以包括導電墊、導電凸塊、導電柱、或上述之組合,且可以由鋁(Al)、銅(Cu)、鎢(W)、其他適當之導電材料、上述之合金、或上述之組合所形成。 Please refer to FIG. 10, in some embodiments, after performing the above second planarization process, a conductive member 90 may be formed on the second surface 100B′ of the substrate 100, and the conductive member 90 is connected to the corresponding via hole 110 to The optical sensing structure 10 is formed. The optical sensing structure 10 can be electrically connected to other devices through the via 110 through the conductive member 90. The conductive member 90 may include conductive pads, conductive bumps, conductive pillars, or a combination of the foregoing, and may be made of aluminum (Al), copper (Cu), tungsten (W), other suitable conductive materials, the above alloys, or The combination of the above.

在第10圖所示的實施例中,光學感測結構10包括位於基板100中的感測畫素陣列200、位於基板之上的光準直層600、以及由基板100之第一表面100A延伸至相對的第二表面100B’的導通孔110。上述感測畫素陣列200包括複數個感測畫素202。上述導通孔110位於上述感測畫素陣列200中,且不與上述感測畫素202垂直重疊。此種將導通孔110設置在感測畫素陣列200中而非感測畫素陣列200外圍的配置,能更進一步縮小光學感測結構10的體積,並提高基板利用率。此外,雖然第10 圖中將導通孔110及感測畫素202繪示為彼此鄰接,但本發明實施例並不限於此。舉例來說,導通孔110及感測畫素202可以是沒有彼此鄰接的,例如導通孔110的寬度可以小於相鄰感測畫素202之間的間距。 In the embodiment shown in FIG. 10, the optical sensing structure 10 includes a sensing pixel array 200 in the substrate 100, a light collimating layer 600 on the substrate, and a first surface 100A extending from the substrate 100 The via 110 to the opposite second surface 100B'. The sensing pixel array 200 includes a plurality of sensing pixels 202. The via 110 is located in the sensing pixel array 200 and does not overlap the sensing pixel 202 vertically. Such a configuration in which the via hole 110 is disposed in the sensing pixel array 200 instead of the periphery of the sensing pixel array 200 can further reduce the volume of the optical sensing structure 10 and improve substrate utilization. In addition, although the 10th In the figure, the via hole 110 and the sensing pixel 202 are shown adjacent to each other, but the embodiment of the present invention is not limited thereto. For example, the via hole 110 and the sensing pixel 202 may not be adjacent to each other, for example, the width of the via hole 110 may be smaller than the spacing between adjacent sensing pixels 202.

在本實施例中,上述光學感測結構10更包括導電部件90。上述導電部件90位於基板100的第二表面100B’上,且相應地連接至上述導通孔110。上述導電部件90包括導電墊、導電凸塊、導電柱、或上述之組合。 In this embodiment, the above-mentioned optical sensing structure 10 further includes a conductive member 90. The above-mentioned conductive member 90 is located on the second surface 100B' of the substrate 100 and is connected to the above-mentioned via 110 accordingly. The conductive member 90 includes conductive pads, conductive bumps, conductive pillars, or a combination thereof.

在本發明實施例中,上述導通孔110包括貫孔102’、填充於上述貫孔102’內的導電層106、以及設置在上述貫孔102’內,且介於上述導電層106及基板100之間的晶種層104。 In the embodiment of the present invention, the via 110 includes a through hole 102 ′, a conductive layer 106 filled in the through hole 102 ′, and is disposed in the through hole 102 ′ and interposed between the conductive layer 106 and the substrate 100 Between the seed layer 104.

在本發明實施例中,上述光準直層600包括對應設置於感測畫素202之上的複數個透光柱300、以及位於基板100之尚且填充於上述透光柱300之間的遮光層400。上述透光柱300可保護感測畫素202,並減少或避免感測畫素202於製程中受到污染及/或損害,進而影響光學感測結構10的靈敏度。上述透光柱300由透明材料所形成,且上述透明材料在300奈米至1200奈米波長範圍下的光穿透率大於90%。 In the embodiment of the present invention, the light collimating layer 600 includes a plurality of light-transmitting pillars 300 corresponding to the light-sensing pixels 202, and a light-shielding layer located on the substrate 100 and filling the light-transmitting pillars 300. 400. The light-transmitting column 300 can protect the sensing pixel 202 and reduce or avoid the contamination and/or damage of the sensing pixel 202 during the manufacturing process, thereby affecting the sensitivity of the optical sensing structure 10. The light-transmitting pillar 300 is formed of a transparent material, and the light transmittance of the transparent material in the wavelength range of 300 nm to 1200 nm is greater than 90%.

根據上述實施例,在形成具有光準直層的光學感測結構時,可以利用位於光準直層下方的導通孔(through-substrate via,TSV)垂直導通堆疊的裝置,使訊號傳遞的方式由水平改成垂直傳輸。有別於傳統上在平面上拉長金屬導線,經過許多不同的結構層才能將指紋感測器連接至其他裝置的方式,使用導通孔來垂直導通堆疊的裝置可以增加裝置堆 疊密度、縮小體積、以及縮短傳導路徑,以進一步提升電性能。此外,由於無須額外形成用於封裝的金屬導線、模製化合物(molding compound)、及封裝基板,可進一步縮減結構厚度,以及降低因熱膨脹係數不匹配所導致的缺陷。 According to the above embodiments, when forming an optical sensing structure with a light collimating layer, a through-substrate via (TSV) device that vertically underlies the light collimating layer can be used to vertically stack the stacked device, so that the signal transmission mode is Horizontal to vertical transmission. Unlike the traditional way of elongated metal wires on a flat surface, the fingerprint sensor can be connected to other devices through many different structural layers. Using via holes to vertically conduct stacked devices can increase the device stack Stack density, reduce volume, and shorten conduction paths to further improve electrical performance. In addition, since there is no need to additionally form metal wires, molding compounds, and packaging substrates for packaging, the thickness of the structure can be further reduced, and defects caused by mismatched thermal expansion coefficients can be reduced.

此外,本發明實施例更進一步利用感測畫素陣列中未設置感測畫素的區域,將導通孔設置在感測畫素陣列中。有別於將導通孔設置在感測畫素陣列的外圍區域,將導通孔設置在感測畫素陣列中能更進一步縮小光學感測結構的體積,並提高基板利用率。 In addition, the embodiment of the present invention further utilizes the area in the sensing pixel array where no sensing pixel is provided, and sets the via hole in the sensing pixel array. Different from disposing the via hole in the peripheral area of the sensing pixel array, disposing the via hole in the sensing pixel array can further reduce the volume of the optical sensing structure and improve substrate utilization.

值得注意的是,雖然此處所討論的範例所揭露的例示性實施方式係有關於指紋感測裝置,但本發明所提供之技術也可應用至其他型態的感測器,而不僅止於應用在偵測指紋的感測器裝置。舉例來說,亦可應用至生物感測器(biosensor)、醫學相關以及輻射研究等領域(例如,心跳、血氧等)的感測裝置中,並不侷限於上述實施例所揭露的範圍。 It is worth noting that although the exemplary embodiments disclosed in the examples discussed herein are related to fingerprint sensing devices, the technology provided by the present invention can also be applied to other types of sensors, not just applications Sensor device that detects fingerprints. For example, it can also be applied to sensing devices in biosensor, medical-related, and radiation research fields (for example, heartbeat, blood oxygen, etc.), and is not limited to the scope disclosed in the foregoing embodiments.

以上概略說明了本揭露數個實施例的特徵,使所屬技術領域內具有通常知識者對於本揭露可更為容易理解。任何所屬技術領域內具有通常知識者應瞭解到本說明書可輕易作為其他結構或製程的變更或設計基礎,以進行相同於本揭露實施例的目的及/或獲得相同的優點。任何所屬技術領域內具有通常知識者亦可理解與上述等同的結構或製程並未脫離本揭露之精神及保護範圍內,且可在不脫離本揭露之精神及範圍內,當可作更動、替代與潤飾。 The above outlines the features of several embodiments of the present disclosure, so that those with ordinary knowledge in the art can more easily understand the present disclosure. Anyone with ordinary knowledge in the technical field should understand that this specification can be easily used as a basis for changes or design of other structures or processes to perform the same purposes and/or obtain the same advantages as the embodiments of the present disclosure. Any person with ordinary knowledge in the technical field can also understand that the structure or process equivalent to the above does not deviate from the spirit and scope of the disclosure, and can be changed or replaced without departing from the spirit and scope of the disclosure With retouch.

10‧‧‧光學感測結構 10‧‧‧Optical sensing structure

90‧‧‧導電部件 90‧‧‧Conductive parts

100‧‧‧基板 100‧‧‧ substrate

100A‧‧‧頂表面(又稱為第一表面) 100A‧‧‧Top surface (also called the first surface)

100B'‧‧‧第二表面 100B'‧‧‧Second surface

102’‧‧‧貫孔 102’‧‧‧through hole

104‧‧‧晶種層 104‧‧‧Seed layer

106‧‧‧導電層 106‧‧‧conductive layer

110‧‧‧導通孔 110‧‧‧via

200‧‧‧感測畫素陣列 200‧‧‧sensor pixel array

202‧‧‧感測畫素 202‧‧‧sensing pixels

300‧‧‧透光柱 300‧‧‧Transparent column

400‧‧‧遮光層 400‧‧‧shading layer

500‧‧‧遮光蓋 500‧‧‧Blackout

600‧‧‧光準直層 600‧‧‧Light collimation layer

Claims (20)

一種光學感測結構,包括:一感測畫素陣列,位於一基板中,其中該感測畫素陣列包括複數個感測畫素;一光準直層,位於該基板之上;以及至少一導通孔,由該基板的一第一表面延伸至相對的一第二表面,其中該至少一導通孔位於該感測畫素陣列中,且不與該些感測畫素垂直重疊。 An optical sensing structure includes: a sensing pixel array located in a substrate, wherein the sensing pixel array includes a plurality of sensing pixels; a light collimating layer on the substrate; and at least one The via hole extends from a first surface of the substrate to an opposite second surface, wherein the at least one via hole is located in the sensing pixel array and does not vertically overlap the sensing pixels. 如申請專利範圍第1項所述之光學感測結構,更包括至少一導電部件,位於該第二表面上且相應地連接於該至少一導通孔。 The optical sensing structure as described in item 1 of the patent application scope further includes at least one conductive member located on the second surface and correspondingly connected to the at least one via hole. 如申請專利範圍第2項所述之光學感測結構,其中該至少一導電部件包括導電墊、導電凸塊、導電柱、或上述之組合。 The optical sensing structure as described in item 2 of the patent application scope, wherein the at least one conductive component comprises a conductive pad, a conductive bump, a conductive pillar, or a combination thereof. 如申請專利範圍第1項所述之光學感測結構,其中該至少一導通孔包括:一貫孔;一導電層,填充於該貫孔內;以及一晶種層,設置於該貫孔內,且介於該導電層與該基板之間。 The optical sensing structure as described in item 1 of the patent application scope, wherein the at least one via hole includes: a through hole; a conductive layer filled in the through hole; and a seed layer provided in the through hole, And between the conductive layer and the substrate. 如申請專利範圍第1項所述之光學感測結構,其中該光準直層包括:複數個透光柱,對應設置於該感測畫素陣列之該些感測畫素之上;以及 一遮光層,位於該基板之上且填充於該些透光柱之間。 The optical sensing structure as described in item 1 of the patent application scope, wherein the light collimating layer includes: a plurality of light-transmitting pillars correspondingly disposed on the sensing pixels of the sensing pixel array; and A light-shielding layer is located on the substrate and filled between the light-transmitting pillars. 如申請專利範圍第5項所述之光學感測結構,其中該些透光柱由一透明材料所形成,並且該透明材料在300奈米至1200奈米波長範圍下的光穿透率大於90%。 The optical sensing structure as described in item 5 of the patent application scope, wherein the light-transmitting pillars are formed of a transparent material, and the light transmittance of the transparent material in the wavelength range of 300 nm to 1200 nm is greater than 90 %. 如申請專利範圍第5項所述之光學感測結構,其中該些遮光層由光阻、油墨、模製化合物、防焊材料或上述之組合所形成。 The optical sensing structure as described in item 5 of the patent application scope, wherein the light-shielding layers are formed of photoresist, ink, molding compound, solder mask, or a combination thereof. 如申請專利範圍第5項所述之光學感測結構,其中該些遮光層包括金屬材料。 The optical sensing structure as described in item 5 of the patent application scope, wherein the light-shielding layers include metal materials. 如申請專利範圍第5項所述之光學感測結構,其中該光準直層更包括一遮光蓋,位於該遮光層之上。 The optical sensing structure as described in item 5 of the patent application scope, wherein the light collimating layer further includes a light-shielding cover located above the light-shielding layer. 如申請專利範圍第9項所述之光學感測結構,其中該遮光蓋為一樹脂遮光蓋,並且該樹脂遮光蓋在300奈米至1200奈米波長範圍下的光穿透率小於1%。 The optical sensing structure as described in item 9 of the patent application range, wherein the light-shielding cover is a resin light-shielding cover, and the light transmittance of the resin light-shielding cover in the wavelength range of 300 nm to 1200 nm is less than 1%. 一種光學感測結構的形成方法,包括:在一基板中形成至少一導通孔;在該基板中形成一感測畫素陣列,其中該感測畫素陣列包括複數個感測畫素,且其中該至少一導通孔位於該感測畫素陣列中,且不與該些感測畫素垂直重疊;以及在該基板之上形成一光準直層。 A method for forming an optical sensing structure includes: forming at least one via hole in a substrate; forming a sensing pixel array in the substrate, wherein the sensing pixel array includes a plurality of sensing pixels, and wherein The at least one via hole is located in the sensing pixel array and does not vertically overlap with the sensing pixels; and a light collimating layer is formed on the substrate. 如申請專利範圍第11項所述之光學感測結構的形成方法,更包括形成至少一導電部件,且該至少一導電部件與相應該至少一導通孔電性連接。 The method for forming an optical sensing structure as described in item 11 of the patent application scope further includes forming at least one conductive component, and the at least one conductive component is electrically connected to the corresponding at least one via hole. 如申請專利範圍第12項所述之光學感測結構的形成方 法,其中該至少一導電部件包括導電墊、導電凸塊、導電柱、或上述之組合。 The formation method of the optical sensing structure as described in item 12 of the patent application scope Method, wherein the at least one conductive component includes a conductive pad, a conductive bump, a conductive post, or a combination thereof. 如申請專利範圍第11項所述之光學感測結構的形成方法,其中該至少一導通孔包括:一貫孔;一導電層,填充於該貫孔內;以及一晶種層,設置於該貫孔內,且介於該導電層與該基板之間。 The method for forming an optical sensing structure as described in item 11 of the patent application range, wherein the at least one via hole includes: a through hole; a conductive layer filled in the through hole; and a seed layer provided in the through hole Inside the hole and between the conductive layer and the substrate. 如申請專利範圍第11項所述之光學感測結構的形成方法,其中形成該至少一導通孔的步驟包括,對該基板之底表面實施一平坦化製程,去除一部分該基板,以露出該至少一導通孔之底表面。 The method for forming an optical sensing structure as described in item 11 of the patent application scope, wherein the step of forming the at least one via hole includes performing a planarization process on the bottom surface of the substrate to remove a portion of the substrate to expose the at least one The bottom surface of a via hole. 如申請專利範圍第11項所述之光學感測結構的形成方法,其中該光準直層包括:複數個透光柱,對應設置於該感測畫素陣列之該些感測畫素之上;以及一遮光層,位於該基板之上且填充於該些透光柱之間。 The method for forming an optical sensing structure as described in item 11 of the patent application range, wherein the light collimating layer includes: a plurality of light-transmitting pillars corresponding to the sensing pixels of the sensing pixel array ; And a light-shielding layer, located on the substrate and filled between the light-transmitting columns. 如申請專利範圍第16項所述之光學感測結構的形成方法,其中該些透光柱由一透明材料所形成,並且該透明材料在300奈米至1200奈米波長範圍下的光穿透率大於90%。 The method for forming an optical sensing structure as described in item 16 of the patent application range, wherein the transparent columns are formed of a transparent material, and the transparent material transmits light in the wavelength range of 300 nm to 1200 nm The rate is greater than 90%. 如申請專利範圍第16項所述之光學感測結構的形成方法,其中該些遮光層由光阻、油墨、模製化合物、防焊材料或上述之組合所形成。 The method for forming an optical sensing structure as described in Item 16 of the patent application range, wherein the light-shielding layers are formed of photoresist, ink, molding compound, solder resist material, or a combination thereof. 如申請專利範圍第16項所述之光學感測結構的形成方法,其中該些遮光層包括金屬材料。 The method for forming an optical sensing structure as described in item 16 of the patent application scope, wherein the light-shielding layers include metal materials. 如申請專利範圍第16項所述之光學感測結構的形成方法,更包括於該遮光層之上設置一遮光蓋,其中該遮光蓋為一樹脂遮光蓋,並且該樹脂遮光蓋在300奈米至1200波長範圍下的光穿透率小於1%。 The method for forming an optical sensing structure as described in item 16 of the patent application scope further includes providing a light-shielding cover on the light-shielding layer, wherein the light-shielding cover is a resin light-shielding cover, and the resin light-shielding cover is at 300 nm The light transmittance in the wavelength range up to 1200 is less than 1%.
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