TW202018547A - Integrated circuit design, and method and design system of generating integrated circuit design - Google Patents

Abstract

A method of generating an integrated circuit design includes receiving input data defining input cells of the integrated circuit design, selecting first standard cells from a first standard cell library to represent the input cells having a first characteristic, selecting second standard cells from a second standard cell library to represent the input cells having a second characteristic different from the first characteristic, and generating output data representing the integrated circuit design by performing placement and routing on the selected first standard cells and the selected second standard cells. The first standard cell library includes a first type of standard cells manufactured using a first diffusion break scheme. The second standard cell library includes a second type of standard cells manufactured using a second diffusion break scheme. Each of the second type of standard cells has a same function as a respective one of the first type of standard cells.

Description

Integrated circuit including different kinds of units and method and system for designing the same

Exemplary embodiments of the present invention relate generally to semiconductor integrated circuits, and more specifically to the design (eg, layout) of integrated circuits including different types of cells, and the design of the integrated circuits Method and design system for producing the integrated circuit design.

Standard cells with fixed functions can be used to produce integrated circuit designs. The standard cell is designed to have a predetermined architecture and is stored in the cell library. When generating an integrated circuit design, extract standard cells from the cell library and place the standard cells in a desired location on the integrated circuit layout. Routing is then carried out to connect standard units to each other and to other units. For example, a metal routing wire may be used to connect the standard unit and the other unit to route signals between the standard unit and the other unit. The predetermined structure of the standard unit may include the unit width, the unit height, the power rail width, the position and number of pin points, and so on. There may be standard units with the same function but different performance and area (for example, different types of standard units). Since standard cells having the same function have different areas, the standard cells have different cell boundaries, and therefore have different cell boundary positions when placed on the integrated circuit layout. However, due to different cell boundary locations, the process of implementing self-aligned double patterning cannot be used in conjunction with existing placement and routing schemes that perform automatic placement of cells based on cell boundaries. Specifically, due to different cell boundary positions, it is not possible to vertically align these placed cells. Therefore, standard cells with the same function but different areas and/or performance cannot be placed in a single integrated circuit design.

At least one exemplary embodiment of the present disclosure provides a method of generating an integrated circuit design that can include different types of standard cells in an integrated circuit and an integrated circuit that can then be manufactured using the integrated design.

At least one exemplary embodiment of the present disclosure provides an integrated circuit design that can include different types of standard cells and an integrated circuit that can then be manufactured using the integrated design.

At least one exemplary embodiment of the present disclosure provides a design system that produces an integrated circuit design that can include different types of standard cells in an integrated circuit design and an integrated circuit that can then be manufactured using integrated design.

According to an exemplary embodiment of the inventive concept, a method of generating an integrated circuit design includes: receiving input data defining input units of the integrated circuit design; and selecting a first standard cell to represent from a first standard cell library The input unit having the first characteristic; selecting a second standard unit from the second standard unit library to represent the input unit having a second characteristic different from the first characteristic; and by selecting the selected The first standard unit and the selected second standard unit perform placement and routing to generate output data representing the integrated circuit design. The first standard cell library includes first type standard cells manufactured using a first diffusion discontinuity scheme. The second standard cell library includes second type standard cells manufactured using a second diffusion discontinuity scheme. Each of the second type standard cells has the same function as the corresponding one of the first type standard cells. The second diffusion discontinuity scheme is different from the first diffusion discontinuity scheme. The output data can then be used to fabricate an integrated circuit.

According to an exemplary embodiment of the inventive concept, a design system for generating an integrated circuit design includes a storage device and a processor. The storage device stores a placer module and a router module. The processor accesses the storage device to execute the module. The placer module places at least one of the first type standard cell and at least one of the second type standard cell on the volume based on the input data, the first standard cell library, and the second standard cell library In the circuit. The input data defines the integrated circuit design. The first standard cell library includes the first type standard cells manufactured using a first diffusion discontinuity scheme. The second standard cell library includes the second type standard cells manufactured using a second diffusion discontinuity scheme. Each of the second type standard cells has the same function as the corresponding one of the first type standard cells. The second diffusion discontinuity scheme is different from the first diffusion discontinuity scheme. The router module performs by connecting the at least one of the first type standard cells and the at least one of the second type standard cells placed in the integrated circuit design Routing to generate output data representing the design of the integrated circuit. The output data can then be used to fabricate an integrated circuit.

According to an exemplary embodiment of the inventive concept, an integrated circuit design includes a first type standard cell and a second type standard cell. The first type of standard cell is manufactured using a first diffusion discontinuity scheme. The second type of standard cell is manufactured using a second diffusion discontinuity scheme. Each of the second type standard cells has the same function as the corresponding one of the first type standard cells. The second diffusion discontinuity scheme is different from the first diffusion discontinuity scheme.

In an integrated circuit design, a method for generating an integrated circuit design, and a design system for generating an integrated circuit design according to an exemplary embodiment, the integrated circuit design may be generated and implemented so that an integrated circuit Different types of standard units are included in the design. The different types of standard cells may have the same function, but may differ in manufacturing method, performance, and/or area. Various types of standard cells can be implemented in one integrated circuit design by using various design optimization schemes, and thus integrated circuits can be manufactured from the resulting integrated circuits having excellent characteristics such as performance and area.

The inventive concept will be explained more fully with reference to the accompanying drawings, in which embodiments of the inventive concept are shown. However, the present disclosure can be implemented in many different forms and should not be considered limited to the embodiments described herein. The same reference numbers refer to the same elements throughout the application.

FIG. 1 is a flowchart illustrating a method of generating an integrated circuit design according to an exemplary embodiment of the inventive concept.

Referring to FIG. 1, a method of generating an integrated circuit design according to an exemplary embodiment may be a method of designing a layout of an integrated circuit and may be implemented in a tool for designing an integrated circuit. For example, a tool for designing an integrated circuit may be a program including multiple instructions executed by a processor. The tools and programs will be explained with reference to FIGS. 5 and 6.

In the method of generating an integrated circuit design according to an exemplary embodiment, input data defining the integrated circuit is received (step S100). The integrated circuit may be defined by a plurality of cells and may be designed using a cell library containing information of the plurality of cells. Hereinafter, the unit may be a standard unit, and the unit library may be a standard unit library. In an exemplary embodiment, the standard unit is to provide a Boolean logic function (Boolean logic function) (eg, AND (AND), OR (OR), mutually exclusive OR (XOR), anti-mutually exclusive OR (XNOR), inverse ) Or a set of transistors and interconnecting structures for storage functions (for example, flip-flops or latches).

In an exemplary embodiment, the input data is data generated in an abstract form regarding the behavior of the integrated circuit. For example, input data can be defined in register transfer level (RTL) by using standard cell library for synthesis. For example, the input data can be determined by a hardware description language (HDL) (such as a very high speed integrated circuit (VHSIC) hardware description language (VHSIC hardware description language, VHDL) ) Or Verilog) defined by the integrated circuit design synthesis to produce a bit stream (bitstream) or netlist (netlist).

In an exemplary embodiment, the input data may be data defining the layout of the integrated circuit. For example, the input data may include geometric information defining structures implemented as semiconductor materials, conductors (eg, metals), and insulators. For example, a layered integrated circuit design indicated by input data may have a layout made up of cells and wires used to connect one cell to other cells.

A first standard cell library including first type standard cells is provided (step S200). The first type of standard cell is a standard cell that is manufactured using or based on the first diffusion discontinuity scheme. The first type of standard unit will be explained with reference to FIG. 2A.

The standard cell may refer to a unit of an integrated circuit whose layout size meets a preset rule or criterion. The standard unit may include input pins and output pins and may process signals received through the input pins to output signals through the output pins. For example, standard cells may include basic cells (such as AND logic gates, OR logic gates, NOR logic gates or inverters), and complex cells (eg OR/AND/INVERTER , OAI) or and/or/inverter (AND/OR/INVERTER, AOI)) and storage elements (such as master-slave flip flop or latch).

The first standard cell library may contain information about multiple standard cells having the first type. For example, the first standard cell library may include the names and functions of the specific standard cells with the first type and the timing information, power information, and layout information of the specific standard cells with the first type. The first standard cell library may be stored in the storage device, and the first standard cell library may be provided by accessing the storage device.

A second standard cell library including second type standard cells is provided (step S300). The second type of standard cell is a standard cell that is manufactured using or based on the second diffusion discontinuity scheme. The second type is different from the first type, and the second diffusion discontinuity scheme is different from the first diffusion discontinuity scheme. Each of the second-type standard cells has the same function as the corresponding one of the first-type standard cells. The second type of standard unit will be explained with reference to FIG. 2B.

The various transistor devices formed on the layer (eg, substrate) of the integrated circuit must be electrically isolated from each other to properly function in the circuit. This can be achieved by forming a trench in the substrate and filling the trench with an insulating material (such as silicon dioxide). These isolation zones may sometimes be called diffusion breaks. The width of the diffusion discontinuity and the number of cells overlapping with each diffusion discontinuity may be different in different diffusion discontinuity schemes. A diffusion discontinuity scheme may include a plurality of diffusion discontinuities, where each diffusion discontinuity is formed to divide a portion of the substrate into a pair of spaced apart active regions on which cells are formed. When the width of a given diffusion discontinuity is less than or equal to a single cell, or the size is designed so that only a single cell can be provided above the diffusion discontinuity, the given diffusion discontinuity can be referred to as a single diffusion discontinuity. For example, the left part of the first unit may be disposed on the first active region of the pair of active regions, the middle part of the first unit may be disposed on the single diffusion discontinuity, and the right part of the first unit It can be arranged on the second active area of the pair of active areas. When the width of a given diffusion discontinuity is greater than a single cell and less than or equal to two cells, or the size is designed such that two cells can be placed above the diffusion discontinuity, the given diffusion discontinuity may be referred to as a double diffusion discontinuity. For example, the left part of the first unit may be disposed on the first active region of the pair of active regions, and the right part of the second unit may be disposed on the second active region of the pair of active regions, And the double diffusion discontinuity may overlap with the rest of the first unit and the second unit. Cells manufactured according to a given diffusion discontinuity scheme may use one or more of the above diffusion discontinuities so that the elements of the cell are properly spaced. Therefore, elements of cells manufactured according to different diffusion discontinuity schemes may have different pitches within a given cell or elements of a first cell may have different pitches relative to elements of a second cell placed adjacent to the first cell.

One of the standard cells with the first type and the corresponding one of the standard cells with the second type may have the same function, but with different performance and/or area. In other words, a target cell to be included and placed in an integrated circuit design can be implemented as one of the first type standard cells with a specific function or the corresponding one of the second type standard cells with the specific function By.

The second standard cell library may contain information about multiple standard cells of the second type. For example, the second standard cell library may include the names and functions of the specific standard cells with the second type, the names of the corresponding standard cells with the first type, and the timing information and power information of the specific standard cells with the second type And layout information. The second standard cell library may be stored in the storage device, and the second standard cell library may be provided by accessing the storage device.

The output data is generated by performing placement and routing based on the input data, the first standard cell library and the second standard cell library (step S400).

In some exemplary embodiments, when the received input data is data such as a bit stream or a netlist generated by synthesizing an integrated circuit design, the output data may also be a bitstream or a netlist. In other exemplary embodiments, when the received input data is data defining the layout of the integrated circuit (for example, data in the format of graphic data system II (GDSII)), the output data The format can also be data defining the layout of the integrated circuit.

According to at least one exemplary embodiment, different types of standard cells having the same function may be included and placed in an integrated circuit design representing a single integrated circuit. In other words, different types of standard cells can be applied to an integrated circuit design.

2A is a layout diagram illustrating an example of a first type standard cell included in an integrated circuit design according to an exemplary embodiment of the inventive concept. 2B is a layout diagram illustrating an example of a second type standard cell included in an integrated circuit design according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 1 and 2A, when a first standard cell library including first type standard cells is provided (step S200), the first standard cell STC1 having the first function may be provided as one of the first type standard cells .

For example, as shown by the thick solid line in FIG. 2A, the first standard cell STC1 may be formed to include two cell boundaries parallel to the first direction D1 and two cell boundaries BD11 parallel to the second direction D2 and The quadrilateral of the BD12 (for example, a rectangular shape), the second direction D2 crosses the first direction D1 (for example, perpendicular to the first direction D1).

In addition, the first standard cell STC1 may be formed to include a plurality of first wirings PC11, PC12, PC13, and PC14 that are spaced apart from each other in the first direction D1 and are separated by a first constant interval W in the inner portion. Each of the plurality of first wires PC11, PC12, PC13, and PC14 may extend in the second direction D2. For example, the plurality of first wires PC11, PC12, PC13, and PC14 may be gate lines. Although not shown in FIG. 2A, the first standard unit STC1 may further include wiring other than the plurality of first wirings PC11, PC12, PC13, and PC14, such as a power supply formed on the first standard unit STC1 Rails, routing grids or routing tracts, conductive contacts that connect multilayer wiring in the vertical direction, etc.

1 and 2B, when a second standard cell library including second type standard cells is provided (step S300), a second standard cell STC2 having a first function (for example, the same function as the first standard cell STC1) It can be provided as one of the second type standard units.

For example, as shown by the thick solid line in FIG. 2B, the second standard cell STC2 may be formed to include two cell boundaries parallel to the first direction D1 and two cell boundaries BD21 parallel to the second direction D2 and The quadrilateral of BD22 (for example, rectangular shape).

In addition, the second standard cell STC2 may be formed to include a plurality of second wirings PC21, PC22, PC23, and PC24 that are spaced apart from each other in the first direction D1 and are separated by a second constant interval W in the inner portion. Each of the plurality of second wires PC21, PC22, PC23, and PC24 may extend in the second direction D2. The first constant interval W in FIG. 2A and the second constant interval W in FIG. 2B may be substantially equal to each other. For example, like the first standard cell STC1, the plurality of second wirings PC21, PC22, PC23, and PC24 included in the second standard cell STC2 may be gate lines. Although not shown in FIG. 2B, the second standard unit STC2 may further include wiring other than the plurality of second wirings PC21, PC22, PC23, and PC24, for example, power rails, routing grids, or routing channels, Conductive contacts, etc.

In some exemplary embodiments, the first type of the first standard unit STC1 and the second type of the second standard unit STC2 may be classified or distinguished according to the characteristics of the manufacturing process (eg, manufacturing scheme).

For example, the first diffusion discontinuity scheme used to manufacture the first standard cell STC1 may be a single diffusion discontinuity scheme. When the first standard cell STC1 is manufactured using a single diffusion discontinuity scheme, the cell boundaries BD11 and BD12 of the first standard cell STC1 may use only the outermost two of the plurality of first wirings PC11, PC12, PC13, and PC14 PC11 and PC14 are formed, and therefore the outermost two wires PC11 and PC14 of the plurality of first wirings PC11, PC12, PC13 and PC14 are positioned to overlap the cell boundaries BD11 and BD12 of the first standard cell STC1 . For example, when the plurality of first wirings PC11, PC12, PC13, and PC14 are gate lines, the first wirings PC12 and PC13 on the inner side may be actually used gate lines, and are on the outer side The first wirings PC11 and PC14 may be virtual gate lines.

The second diffusion discontinuity scheme used to manufacture the second standard unit STC2 may be a double diffusion discontinuity scheme. When the second standard cell STC2 is manufactured using the double diffusion discontinuity scheme, the cell boundaries BD21 and BD22 of the second standard cell STC2 can use the outermost two wires PC21 among the plurality of first wires PC21, PC22, PC23, and PC24 And PC24, and further formed using two wires adjacent to the outermost two wires PC21 and PC24 and not included in the second standard unit STC2, and therefore the plurality of first wires PC21, PC22, The two outermost wires PC21 and PC24 of PC23 and PC24 are positioned so as not to overlap the cell boundaries BD21 and BD22 of the second standard cell STC2.

In other words, the interval W between the inside of the first wiring PC11, PC12, PC13, and PC14 provided in the first standard unit STC1 and the inside of the second wiring PC21, PC22, PC23, and PC24 provided in the second standard unit STC2 The interval W may be substantially equal to each other, however, the arrangement relationship between the cell boundaries BD11 and BD12 of the first standard cell STC1 and the first wiring PC11 and PC14 and the cell boundaries BD21 and BD22 of the second standard cell STC2 and the second wiring The arrangement relationship between PC21 and PC24 may be different from each other.

In some exemplary embodiments, the first type of the first standard unit STC1 and the second type of the second standard unit STC2 may be classified or distinguished according to the attributes (eg, performance and area) of the unit.

For example, as described above, the first standard unit STC1 and the second standard unit STC2 may have the same function (for example, the first function), however, the first standard unit STC1 and the second standard unit STC2 may be implemented as For different promotion purposes. For example, compared to the first standard unit STC1, the second standard unit STC2 may be implemented to have improved performance for performance improvement purposes, compared to the first standard unit STC1, the second standard unit STC2 may be formed by further inserting a specific front-end layer, and thus the second standard cell STC2 may have a larger area than the first standard cell STC1. For example, assuming that the first standard cell STC1 and the second standard cell STC2 have the same cell height, the first standard cell STC1 may have a cell width of 3W, since the cell width of 0.5W is added to the cell boundaries BD21 and BD22 For each of these, the second standard cell STC2 may have a cell width of 4W, and thus the area of the second standard cell STC2 may be larger than the area of the first standard cell STC1.

In other words, the second standard unit STC2 may be formed to have a relatively large area and improved performance, and the first standard unit STC1 may be formed to have a relatively small area and lower performance than the second standard unit STC2. Therefore, the first type of the first standard unit STC1 may be referred to as an area-oriented unit type, and the second type of the second standard unit STC2 may be referred to as an efficiency-oriented unit type.

3 and 4 are diagrams showing an example of the layout of an integrated circuit according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 3 and 4, an integrated circuit design according to an exemplary embodiment may substantially simultaneously include one of the first type standard cells (eg, the first standard cell STC1) and the second type at the same time or concurrently One of the standard units (for example, the second standard unit STC2). In other words, different types of standard cells can be placed or included in an integrated circuit or a circuit design. In addition, in the examples of FIGS. 3 and 4, the first standard cell STC1 and the second standard cell STC2 are shown as single-height cells arranged or placed corresponding to one column of the integrated circuit design.

In some exemplary embodiments, the first standard cell STC1 may be arranged or placed to correspond to the plurality of first reference lines RL1 in the integrated circuit design, and the second standard cell STC2 may be arranged in the integrated circuit design Or placed so as to correspond to the plurality of second reference lines RL2. Each of the plurality of first reference lines RL1 and the plurality of second reference lines RL2 extends in the second direction D2. The plurality of first reference lines RL1 may be spaced apart from each other in the first direction D1 by a constant interval. The plurality of second reference lines RL2 may be spaced apart from each other and separated by a constant interval in the first direction D1. Each of the plurality of second reference lines RL2 may be arranged between two adjacent first reference lines RL1. For example, the interval between two adjacent first reference lines RL1 and the interval between two adjacent second reference lines RL2 may be W, respectively, and one adjacent first reference line RL1 and The interval between one second reference line RL2 may be 0.5W.

When the first standard cell STC1 has the structure shown in FIG. 2A and the second standard cell STC2 has the structure shown in FIG. 2B, and when the first standard cell STC1 is arranged to correspond to the plurality of first reference lines RL1 and When the second standard unit STC2 is arranged to correspond to the plurality of second reference lines RL2, the plurality of first wirings PC11, PC12, PC13 and PC14 included in the first standard unit STC1, the second standard unit STC2 The plurality of second wires PC21, PC22, PC23, and PC24 and the other wires PC2A and PC2B included in the owner may be arranged to overlap the plurality of first reference lines RL1.

In the example shown in FIG. 3, the first standard cell STC1 and the second standard cell STC2 may be placed or arranged adjacent to each other in the same column (eg, column R1) of the integrated circuit design. In this example, the first standard unit STC1 and the second standard unit STC2 are spaced apart from each other by a distance greater than or equal to a predetermined reference distance WSD. For example, the reference distance WSD may be 1.5W. In other words, when different types of standard cells are placed or arranged adjacent to each other in the same column, there should be a blank space area with a minimum space equal to the reference distance WSD between the different types of standard cells adjacent to each other in the same column, And the first type standard unit and the second type standard unit are both arranged in the blank space area.

In the example shown in FIG. 4, the first standard cell STC1 and the second standard cell STC2 may be placed or arranged adjacent to each other in different columns (eg, columns R1 and R2) of the integrated circuit design. In this example, the first standard unit STC1 and the second standard unit STC2 need not be separated from each other by a distance greater than or equal to the reference distance WSD. As described above, since the plurality of first wires PC11, PC12, PC13, and PC14 and the plurality of first wires PC21, PC22, PC23, and PC24 are arranged to overlap the plurality of first reference lines RL1, Therefore, one of the plurality of first wires PC11, PC12, PC13, and PC14 and one of the plurality of second wires PC21, PC22, PC23, and PC24 can be positioned on the same straight line. For example, the first wiring PC12 and the second wiring PC21 may be positioned on the same straight line. In other words, at least some of the wires PC11, PC12, PC13, PC14, PC21, PC22, PC23, and PC24 can be aligned along the second direction D2.

As described above, when the first standard cell STC1 is manufactured using a single diffusion discontinuity scheme, one cell boundary of the first standard cell STC1 can be formed using the first wiring PC11, and the other cell boundary of the first standard cell STC1 can be used A wiring PC14 is formed. When the second standard cell STC2 is manufactured using the double diffusion discontinuity scheme, one cell boundary of the second standard cell STC2 may be formed using the second wiring PC21 and the wiring PC2A adjacent to the second wiring PC21, and the second standard cell STC2 Another cell boundary can be formed using the second wiring PC24 and the wiring PC2B adjacent to the second wiring PC24.

Although FIGS. 3 and 4 show that the first standard cell STC1 of the first type and the second standard cell STC2 having the same function (for example, the first function) are placed or arranged in the same column of the integrated circuit design and Examples in different columns, however, exemplary embodiments of the inventive concept are not so limited. For example, the exemplary embodiment may be applied to or used in various examples in which different types of standard cells are placed or included in an integrated circuit design of an integrated circuit, and the same type of standard cells may be arranged adjacent to each other, As will be explained with reference to FIG. 13B.

In addition, although FIGS. 3 and 4 show an example in which the first standard cell STC1 and the second standard cell STC2 are single-height cells, exemplary embodiments of the inventive concept are not limited thereto. For example, the integrated circuit design may include multi-height cells arranged or placed to correspond to two or more columns of the integrated circuit design.

5 and 6 are block diagrams showing a design system that generates an integrated circuit design according to an exemplary embodiment of the inventive concept.

Referring to FIG. 5, a design system 1000 for integrated circuit design includes a processor 1100, a storage device 1200, a design module 1300, and an analysis module or analyzer 1400.

In this article, the term "module" may indicate but is not limited to software and/or hardware components that perform certain tasks, such as field programmable gate array (FPGA) or application-specific integrated circuits (application specific integrated circuit, ASIC). The module may be configured to reside in a tangible addressable storage medium and configured to execute on one or more processors. For example, "modules" may include components (such as software components, object-oriented software components, category components, and task components) and processes, functions, routines, code fragments, drivers, firmware, microcode , Circuit systems, data, databases, data structures, tables, arrays and variables. "Modules" can be divided into multiple "modules" that perform detailed functions.

The processor 1100 may be used when the design module 1300 and/or the analyzer 1400 perform calculations. For example, the processor 1100 may include a microprocessor, an application processor (AP), a digital signal processor (DSP), a graphics processing unit (GPU), and so on. In FIG. 5, only one processor 1100 is shown, but exemplary embodiments of the inventive concept are not limited thereto. For example, the design system 1000 may include multiple processors. In addition, the processor 1100 may include a cache memory (cache memory) to improve computing power.

The storage device 1200 may include a first standard cell library (SCL1) 1210 and a second standard cell library (SCL2) 1220, and may further include design rules (DR) 1230. The first standard cell library 1210, the second standard cell library 1220, and the design rules 1230 may be provided from the storage device 1200 to the design module 1300 and/or the analyzer 1400. The design rules 1230 may provide a set of guidelines for constructing various masks required in the fabrication of integrated circuits. For example, the design rules 1230 may include minimum width and minimum spacing requirements between cells on the same layer and minimum width and minimum spacing requirements between cells on different layers. In addition, the design rule 1230 may include a minimum line width of routing wiring.

The first standard cell library 1210 may include a first type standard cell, and the second standard cell library 1220 may include a second type standard cell. As an example of the first type standard unit, the first standard unit STC1 will be explained with reference to FIGS. 2A, 3 and 4. As an example of the second type standard unit, the second standard unit STC2 will be explained with reference to FIGS. 2B, 3 and 4.

In some exemplary embodiments, the storage medium or storage device 1200 may include any non-transitory computer-readable storage medium for providing commands and/or data to the computer. For example, the non-transitory computer-readable storage medium 1200 may include volatile memory (volatile memory) (eg, random access memory (RAM), read only memory (ROM)) Etc.) and non-volatile memory (non-volatile memory) (such as flash memory (flash memory), magnetoresistive RAM (magnetoresistive RAM, MRAM), phase-change RAM (phase-change RAM, PRAM), resistive RAM ( resistive RAM, RRAM, etc.). The non-transitory computer-readable storage medium 1200 can be inserted into the computer, can be integrated into the computer, or can be coupled to the computer through a communication medium (such as a network and/or wireless link).

The design module 1300 may include a placer 1310 (for example, a placer module) and a router 1320 (for example, a routing module).

The placer 1310 may use the processor 1100 to place the first type standard cell and the second type standard cell based on the input data DI defining the integrated circuit design, the first standard cell library 1210 and the second standard cell library 1220 or Layout. The router 1320 can implement signal routing for the unit placement provided from the placer 1310.

The analyzer 1400 can analyze and verify the results of placement and signal routing. If it is determined based on the analysis result that the routing is unsuccessful, the placer 1310 may modify the previous unit placement and the router 1320 may use the modified unit placement to implement signal routing. When it is determined based on the analysis result that the routing has been successfully completed, the router 1320 may provide output data DO that defines the integrated circuit design.

According to an exemplary embodiment, the placer 1310 and the router 1320 may be implemented by a single integrated design module 1300 or may be implemented by separate and different modules.

The design module 1300 and/or the analyzer 1400 may be implemented as software, but exemplary embodiments of the inventive concept are not limited thereto. When both the design module 1300 and the analyzer 1400 are implemented as software, the design module 1300 and the analyzer 1400 may be stored in the storage device 1200 in the form of codes, or may be stored in a separate form from the storage device 1200 in the form of codes In another storage device (not shown).

6, a design system 2000 for generating an integrated circuit design includes a processor 2100, an input/output (I/O) device 2200, a network interface 2300, a random access memory (RAM) 2400, and read-only Memory (ROM) 2500 and storage device 2600. FIG. 6 shows an example in which both the design module 1300 and the analyzer 1400 in FIG. 5 are implemented as software.

The design system 2000 may be a computing system. For example, the computing system may be a fixed computing system (such as a desktop computer, workstation, or server) or may be a portable computing system (such as a laptop computer).

The processor 2100 in FIG. 6 may be substantially the same as the processor 1100 in FIG. 5. For example, the processor 2100 may include a core or a processor core that executes any instruction set (for example, Intel architecture-32 (intel architecture-32, IA-32), 64-bit extension IA-32 (64 bit extension IA-32), x86-64, PowerPC, Sparc, Microprocessor without interlocked piped stages (MIPS), Advanced Reduced Instruction Set Computer (RISC) Machine, ARM), Intel Architecture-64 (IA-64), etc.). For example, the processor 2100 can access a memory (such as RAM 2400 or ROM 2500) through a bus, and can execute instructions stored in the RAM 2400 or ROM 2500. As shown in FIG. 6, the RAM 2400 can store the program PR or at least some elements of the program PR corresponding to the design module 1300 and the analyzer 1400 in FIG. 5, and the program PR can enable the processor 2100 to implement the integrated circuit design. Operation.

In other words, the program PR may include a plurality of instructions and/or programs that can be executed by the processor 2100, and the plurality of instructions and/or programs included in the program PR may enable the processor 2100 to implement an example according to the inventive concept The design method of the integrated circuit of the first embodiment. Each of the programs may represent a series of instructions for performing a specific task. Programs can be called functions, routines, subroutines, or subroutines. Each of the programs can process data provided from outside and/or data generated by another program.

The storage device 2600 in FIG. 6 may be substantially the same as the storage device 1200 in FIG. 5. For example, the storage device 2600 can store the program PR, and can store the first standard cell library SCL1, the second standard cell library SCL2, and the design rule DR. The program PR or at least some elements of the program PR may be loaded from the storage device 2600 to the RAM 2400 before being executed by the processor 2100. The storage device 2600 may store files written in a programming language, and the program PR or at least some elements of the program PR generated by the compiler may be loaded into the RAM 2400.

The storage device 2600 may store data to be processed by the processor 2100 or data obtained by processing by the processor 2100. The processor 2100 may process the data stored in the storage device 2600 based on the program PR to generate new data, and may store the generated data in the storage device 2600.

The input/output device 2200 may include an input device (eg, keyboard, pointing device, etc.), and may include an output device (eg, display device, printer, etc.). For example, the user can trigger the execution of the program PR by the processor 2100 through the input/output device 2200 or can input the input data DI in FIG. 5, and can check the output data DO or the error message in FIG. 5.

The network interface 2300 can provide access to the network outside the design system 2000. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of link. The input data DI in FIG. 5 may be provided to the design system 2000 through the network interface 2300, and the output data DO in FIG. 5 may be provided to another computing system through the network interface 2300.

7 is a flowchart illustrating an example of the operation of a design system that generates an integrated circuit design according to an exemplary embodiment of the inventive concept. FIG. 8 is a flowchart showing an example of placing and routing in FIG. 7.

Referring to FIG. 7, one of the design module 1300 in FIG. 5 or the input/output device 2200 and the network interface 2300 in FIG. 6 receives input data DI that defines an integrated circuit design (step S1100).

The design module 1300 and the analyzer 1400 in FIG. 5 or the program PR in FIG. 6 may refer to the use of the processor 1100 in FIG. 5 or the processor 2100 in FIG. 6, the first standard cell library 1210, and the second standard cell library At 1220, the first type standard unit and the second type standard unit corresponding to the input data DI are extracted, and the extracted standard unit is used to perform placement and routing based on a predetermined rule or criterion (step S1200).

Referring to FIG. 8, when placement and routing are performed (step S1200 ), a part of the placer 1310 included in the design module 1300 in FIG. 5 or a part of the program PR in FIG. 6 corresponding to the placer 1310 can use the extracted The standard unit performs unit placement (step S2110), and clock tree synthesis (CTS) can be implemented (step S2120). The first type standard unit and the second type standard unit can be appropriately used or applied based on predetermined rules or criteria in the placement process and the pulse tree synthesis process, as will be described later.

In addition, a part of the router 1320 included in the design module 1300 in FIG. 5 or the program PR in FIG. 6 corresponding to the router 1320 can perform signal routing for the placed unit (step S2130), and the optimal timing can be implemented (Step S2140). The first-type standard cell and the second-type standard cell can be appropriately used or applied based on predetermined rules or criteria in the timing optimization process, as will be described later.

The analyzer 1400 in FIG. 5 or the part of the program PR in FIG. 6 corresponding to the analyzer 1400 may check whether the placement and routing have been successfully completed (step S2150). When placement and routing are unsuccessful (step S2150: No), for example, when at least one of signal routing and timing optimization is unsuccessful, steps S2110, S2120, S2130, and S2140 may be repeatedly performed or recursively performed. In other words, the above process of FIG. 8 can be repeated until the placement and routing are successfully completed.

Referring again to FIG. 7, when the placement and routing have been successfully completed (step S2150 in FIG. 8: Yes), one of the design module 1300 in FIG. 5 or the input/output device 2200 and the network interface 2300 in FIG. 6 The author will generate output data DO that defines the integrated circuit design (step S1300).

In some exemplary embodiments, as will be described with reference to FIGS. 9 to 15, the first type standard unit and the second type standard unit may be used together to perform placement and routing. In other exemplary embodiments, as will be described with reference to FIGS. 16 to 19, the first type standard unit may be preferentially used for placement and routing, and then the first type standard satisfying certain conditions may be replaced with the second type standard unit Some of the units.

9 is a flowchart illustrating an example of performing placement and routing in a method of generating an integrated circuit design according to an exemplary embodiment of the inventive concept.

Referring to FIG. 9, when output data is generated by performing placement and routing, when the first type standard unit is required, the first type standard unit is used to perform placement and routing (step S2210), and when the second type standard unit is required, Use the second type standard unit to implement placement and routing (step S2220). For example, the first type of standard unit or the second type of standard unit may be determined according to the performance and/or area of the target unit.

FIG. 10 is a flowchart showing an example of performing placement and routing shown in FIG. 9. 11 is a layout diagram showing an example in which the first type standard cell and the second type standard cell are placed in an integrated circuit design representing a single integrated circuit by the operations shown in FIGS. 9 and 10.

Referring to FIG. 10, the pin density of the target standard cell (for example, the standard cell to be placed in the integrated circuit design) is checked to determine whether the target standard cell requires the first type standard cell or the target standard cell requires the second type standard Unit (step S2310).

When the pin density of the target standard unit is less than the reference density (step S2310: YES), the placement and routing of the target standard unit are performed using the first type standard unit (step S2320). When the pin density of the target standard cell is greater than or equal to the reference density (step S2310: No), the placement and routing of the target standard cell are performed using the second type standard cell (step S2330).

As described with reference to FIGS. 2A and 2B, one of the second type standard cells (for example, the second standard cell STC2) may have a corresponding one (for example, the first Standard unit STC1) Large area. Therefore, when the pin density of the target standard cell is greater than or equal to the reference density, for example, when the number of pins and the pin density required for network connection are relatively large with respect to the cell area of the target standard cell, it can be used Or apply a second type of standard cell with a relatively large area. Therefore, pin-to-pin connection routing can be facilitated, and routing congestion can be reduced.

In some exemplary embodiments, the target standard cell having a pin density greater than or equal to the reference density may include, for example, a basic cell (eg, and logic gate, or logic gate) or a relatively small driving strength in the combination cell Units, complex units including multiple basic units or combined units (for example, OAI, AOI), etc.

Although FIG. 10 shows an example in which the type of the target standard cell is determined based on the pin density (for example, the area of the cell), exemplary embodiments of the inventive concept are not limited thereto. For example, the first type standard cell (for example, the first standard cell STC1) may be an area-oriented cell formed to have a relatively small area, and the second type standard cell (for example, the second standard cell STC2) may be It is formed as a performance-oriented unit with relatively improved performance, as described with reference to FIGS. 2A and 2B. Therefore, when the target standard unit needs relatively improved performance, the second type standard unit with relatively improved performance can be used or applied to the target standard unit. In other words, the type of target standard unit can be determined based on the unit's performance. Alternatively, the type of target standard unit may be determined based on at least one of various criteria or rules.

11, including the first type standard unit STC11, STC12, STC13, STC14, STC15, STC16, STC17, STC18, STC19, STC1A, STC1B, STC1C, STC1D, STC1E, STC1F, STC1G, STC1H and STC1I and the second type standard The integrated circuit design of the units STC21, STC22, STC23, STC24, STC25, STC26, and STC27 can be designed based on the process described with reference to FIGS. 9 and 10. In other words, all the multiple standard cells to be placed or included in the integrated circuit design can be determined to be one of the first type and the second type, and placement and routing can be performed based on the determined type of standard cells.

The bidirectional arrow shown in FIG. 11 may indicate the reference distance WSD explained with reference to FIG. 3. Different types of standard cells (for example, STC11 and STC21) adjacent to each other in the same column of the integrated circuit design should be separated from each other by a distance greater than or equal to the reference distance WSD. On the other hand, the same type of standard cells (for example, STC13 and STC14) adjacent to each other in the same column of the integrated circuit design may be arranged closer to the reference distance WSD, and may be formed as direct contact, for example.

12 is a flowchart illustrating another example of performing placement and routing in a method of generating an integrated circuit design according to an exemplary embodiment of the inventive concept. 13A and 13B are layout diagrams showing an example in which the first type standard cell and the second type standard cell are placed in an integrated circuit design representing a single integrated circuit by the operation shown in FIG. 12. The description overlapping with FIG. 9, FIG. 10 and FIG. 11 will be omitted.

Referring to FIG. 12, steps S2210 and S2220 in FIG. 12 may be substantially the same as steps S2210 and S2220 in FIG. 9, respectively.

After using the first type standard cell and the second type standard cell to perform placement and routing, the placement and routing are re-executed so that the target standard cells among the plurality of standard cells placed in the integrated circuit design are physically adjacent to each other (step S2230). The target standard unit may correspond to the second type standard unit. In other words, placement and routing can be re-implemented so that the second type standard cells in the integrated circuit design are physically adjacent to each other, and thus can be additionally obtained by arranging the same type standard cells to be physically adjacent to each other Additional space for unit placement.

Referring to FIG. 13A, an integrated circuit design substantially the same as the integrated circuit design shown in FIG. 11 can be designed by steps S2210 and S2220 shown in FIG. In this example, a blank space area for the reference distance WSD may be required between the different types of standard cells STC21 and STC12 and the different types of standard cells STC12 and STC22 in the first column of the integrated circuit design. Similarly, between different types of standard units STC16 and STC23, between different types of standard units STC23 and STC17, between different types of standard units STC19 and STC24, between different types of standard units STC25 and STC1A, between different types of standard units STC26 and A blank space area may also be required between STC1C and between different types of standard units STC1D and STC27.

Since the space for cell placement can be reduced due to the blank space area, the positions of the standard cells STC12 and STC23 can be interchanged by step S2230 in FIG. 12 (for example, arrow 1 in FIG. 13A), so that the second The type standard cells STC21, STC22, and STC23 are adjacent to each other in the first column. Similarly, the positions of the standard units STC24 and STC1C can be interchanged (for example, arrow 2 in FIG. 13A), and the positions of the standard units STC25 and STC1D can be interchanged (for example, arrow 3 in FIG. 13A).

13B, including the first type of standard units STC11, STC12', STC13, STC14, STC15, STC16, STC17, STC18, STC19, STC1A, STC1B, STC1C', STC1D', STC1E, STC1F, STC1G, STC1H and STC1I and The integrated circuit design of the two types of standard cells STC21, STC22, STC23', STC24', STC25', STC26, and STC27 can be designed by re-executing and routing using step S2230 in FIG.

Compared to the layout shown in FIG. 13A, the second type standard cells STC21, STC22, and STC23′ can be arranged adjacent to each other in the same column in the layout shown in FIG. 13B, and the second type standard cells STC24′ and STC26 It may be arranged to be adjacent to each other in the same column in the layout shown in FIG. 13B, and the second type standard cells STC25' and STC27 may be arranged to be adjacent to each other in the same column in the layout shown in FIG. 13B. As described above, the standard cells of the same type can be arranged closer to the reference distance WSD in the same column, and thus the standard cells STC12' and STC16 and between standard cells STC1A and STC1D' for cell placement can be further obtained space.

14 is a flowchart illustrating an example of performing placement and routing in a method of generating an integrated circuit design according to an exemplary embodiment of the inventive concept. 15 is a layout diagram showing an example in which the first type standard cell and the second type standard cell are placed in an integrated circuit design representing one integrated circuit by the operation shown in FIG. 14. The description overlapping with FIG. 9, FIG. 10 and FIG. 11 will be omitted.

Referring to FIG. 14, steps S2210 and S2220 in FIG. 14 may be substantially the same as steps S2210 and S2220 in FIG. 9, respectively.

After performing placement and routing using the first type standard unit and the second type standard unit, a filling unit is inserted between the different type standard units (step S2240). The filling unit may be a third type unit, and may be different from the first type standard unit and the second type standard unit.

Referring to FIG. 15, an integrated circuit design having the same layout as the layout shown in FIG. 11 can be designed by steps S2210 and S2220 shown in FIG. 14, and can be implemented by the standard cells STC21 and STC12 by step S2240 in FIG. 14. Filling units FC1, FC2, FC3, FC4 and FC5 are inserted between the standard units STC12 and STC22, standard units STC23 and STC17, standard units STC25 and STC1A, and standard units STC1B and STC26. The hollow space in the bulk circuit design can be filled by inserting filling units FC1, FC2, FC3, FC4 and FC5.

In the exemplary embodiment, the filling units FC1, FC2, FC3, FC4, and FC5 are virtual units. In the exemplary embodiment, the filling units FC1, FC2, FC3, FC4, and FC5 are used with the first type standard units STC11, STC12, STC13, STC14, STC15, STC16, STC17, STC18, STC19, STC1A, STC1B, STC1C, STC1D, STC1E, STC1F, STC1G, STC1H and STC1I solutions (for example, the first diffusion discontinuity solution) and the second type standard unit STC21, STC22, STC23, STC24, STC25, STC26 and STC27 solutions (for example, the second diffusion discontinuity solution) Scheme) Units manufactured by different schemes. According to an exemplary embodiment, all the filling units FC1, FC2, FC3, FC4, and FC5 are of the same type, or at least some of the filling units FC1, FC2, FC3, FC4, and FC5 may be of different types.

Although FIG. 15 shows an example in which the filling units FC1, FC2, FC3, FC4, and FC5 are inserted into only a part of the integrated circuit design, exemplary embodiments of the inventive concept are not limited to this. For example, the filling unit can be inserted into all empty spaces of the integrated circuit design.

16 is a flowchart illustrating an example of performing placement and routing in a method of generating an integrated circuit design according to an exemplary embodiment of the inventive concept. FIG. 17 is a diagram showing an example of an integrated circuit designed by the operation shown in FIG. 16.

Referring to FIG. 16, when the output data is generated by performing placement and routing, the placement is performed using the first type standard unit (step S2410), by replacing the placement of the result with step S2410 with one of the second type standard units The target standard cell among the plurality of standard cells in the obtained integrated circuit design performs placement change (step S2420), and performs routing based on the result of the placement change (step S2430). In other words, the first type standard cell can be preferentially used or applied to the integrated circuit design to implement the placement process first, and then the target standard cell that is part of the first type standard cell can be replaced with one of the second type standard cell. Routing can be implemented after placement and placement changes.

In at least one exemplary embodiment, the target standard unit is a standard unit used in a clock network. As described with reference to FIGS. 2A and 2B, since the second type standard unit (for example, the second standard unit STC2) is formed as a performance-oriented unit with relatively improved performance, it is necessary to improve the performance in terms of clock The standard unit used in the network may only be implemented as a second type standard unit to minimize the skew between clock signals, and therefore the integrated circuit may have improved performance. In an exemplary embodiment, the clock network is a clock tree or clock mesh. The clock network may include multiple clock sinks, such as flip-flops and integrated clock gates. The clock gating device may be a circuit or component that controls the application or non-application (eg, enabling/disabling) of one or more clock signals associated with one or more clock receivers. The clock network found in the integrated circuit includes a clock gating device connected by a plurality of inverters and a plurality of flip-flops. The inverter can be used to control the clock skew.

Referring to FIG. 17, the placement of the first type standard cell can be performed by step S2410 in FIG. 16 to implement the flip-flops FF1, FF2, ..., FFN and the clock generator CG included in the integrated circuit 3100. In order to improve the performance of the clock network CN (eg, clock path) associated with the generation and transmission of the clock signal CK instead of the data path associated with the input data DIN and output data DOUT, it can Step S2420 replaces the first type standard unit included in the clock network CN with the second type standard unit. After this, routing can be implemented by step S2430 in FIG. 16 to complete the design of the integrated circuit 3100.

18 is a flowchart illustrating an example of performing placement and routing in a method of generating an integrated circuit design according to an exemplary embodiment of the inventive concept. FIG. 19 is a diagram showing an example of an integrated circuit designed by the operation shown in FIG. 18.

Referring to FIG. 18, when output data is generated by performing placement and routing, the first type standard unit is used to perform placement and routing (step S2510), by replacing one of the second type standard units in the placement step The target standard cell among the plurality of standard cells in the integrated circuit design obtained in the result of S2510 implements placement change (step S2520), and re-executes routing based on the result of the placement change (step S2530). In other words, the first type standard cell can be preferentially used or applied to the integrated circuit design to implement the placement and routing process first, and then the target standard cell that is part of the first type standard cell can be replaced with one of the second type standard cell . The routing can be re-executed after the placement change.

In at least one exemplary embodiment, the target standard cell is a standard cell used in a timing critical data path among a plurality of data paths included in an integrated circuit design. As described with reference to FIGS. 2A and 2B, since the second type standard unit (for example, the second standard unit STC2) is formed as a performance-oriented unit with relatively improved performance, it is used in a data path sensitive to timing characteristics The standard unit of the IC may only be implemented as a standard unit of the second type, and thus the integrated circuit may have improved performance.

Referring to FIG. 19, placement and routing can be performed using the first type of standard unit through step S2510 in FIG. 18 to implement flip-flops FFA and FFB, inverters INVA and INVB, and inverters included in the integrated circuit 3200. AND gates NANDA, NANDB, NANDC and NANDD and AND gates ANDA, ANDB, ANDC and ANDD. The shaded components INVB, ANDA, included in the data path most sensitive to the timing characteristics among the multiple data paths associated with the input data DIN and the output data DOUT can be replaced by the second type standard unit by step S2520 in FIG. 18 The first type of target standard cell included in ANDB, NANDB, and NANDC. After this, the routing can be re-executed by step S2530 in FIG. 18 to complete the design of the integrated circuit 3200.

Although only the first type of standard unit is used in step S2410 shown in FIG. 16 and step S2510 shown in FIG. 18, exemplary embodiments of the inventive concept are not limited to this. For example, both the first type standard unit and the second type standard unit can be used for placement or both the first type standard unit and the second type standard unit can be used for placement and routing, and then the second type standard unit can be used It replaces the first type of target standard cell included in the clock network or timing critical data path.

In an integrated circuit design according to an exemplary embodiment, a method for generating an integrated circuit design, and a design system for generating an integrated circuit design, the integrated circuit design may be generated and implemented so that when an integrated circuit is represented The integrated circuit design includes different types of standard cells. The different types of standard cells have the same function, but may differ in manufacturing method, performance, or area. Various types of standard cells can be implemented in an integrated circuit design that represents a single integrated circuit by using various design optimization schemes, and therefore an integrated body with excellent characteristics (such as performance and area) can be efficiently designed and obtained Circuit.

The operation of using or applying different types of standard units according to the needs as described with reference to FIG. 9, the operation of using or applying different types of standard units according to the pin density as described with reference to FIG. The adjacent operation and the operation of inserting the filling unit described with reference to FIG. 14 can be used for design optimization in the placement process in the process described with reference to FIG. 8. The operation of performing placement change described with reference to FIG. 16 and performing routing after the placement change can be used for design optimization in the clock tree synthesis process in the process described with reference to FIG. 8. The operation of implementing the placement change described with reference to FIG. 18 and re-executing the routing after the placement change can be used for design optimization in the timing optimization process in the process described with reference to FIG. 8.

The integrated circuit may be designed to combine two or more of the above-described various operations according to an exemplary embodiment of the inventive concept. In addition, although the exemplary embodiments in which various operations are performed in modules and/or tools for automatic placement and routing are described, the exemplary embodiments are not limited thereto. For example, the various operations can also be applied to the process of generating Verilog netlists before placing and routing (for example, in a synthesis process).

Although it is explained that the first type standard cell is manufactured using a single diffusion discontinuity method and the second type standard cell is manufactured using a double diffusion discontinuity method, the exemplary embodiment is not limited thereto. For example, the first type and the second type may vary according to exemplary embodiments. In addition, although an exemplary embodiment in which two standard cells of different types are placed or included in an integrated circuit design representing one integrated circuit is explained, the exemplary embodiment is not limited to this. For example, three or more different types of standard cells can be placed or included in an integrated circuit design that represents an integrated circuit.

FIG. 20 is a block diagram illustrating an electronic system according to an exemplary embodiment of the inventive concept.

Referring to FIG. 20, the electronic system 4000 includes at least one processor 4100, a communication module 4200, a display/touch module 4300, a storage device 4400, and a memory device 4500. For example, the electronic system 4000 can be any mobile system or any computing system.

As described above, the components of the electronic system 4000 can be designed and implemented to include different types of standard cells in an integrated circuit design representing an integrated circuit, and thus the electronic system 4000 can be implemented to have various improved characteristics (such as improved Performance or improved area), the various improved characteristics are superior to those of traditional electronic devices.

The processor 4100 can control the operation of the electronic system 4000. The processor 4100 can execute an operating system and at least one application to provide an Internet browser, game, or video. The communication module 4200 is implemented to perform wireless or wired communication with external devices. The communication module 4200 may include a transceiver to implement communication. The display/touch module 4300 is implemented to display data processed by the processor 4100 and/or receive data through the touch panel. The storage device 4400 is implemented to store user data, and is driven based on the method of operating the storage device according to an exemplary embodiment. The memory device 4500 temporarily stores data for processing the operation of the electronic system 4000.

The inventive concept can be applied to the design of various electronic devices and electronic systems. For example, the inventive concept can be applied to devices and systems such as: mobile phones, smart phones, tablets, laptops, personal digital assistants (PDAs), portable multimedia players (portable multimedia player (PMP), digital camera, portable game console, music player, camcorder, video player, navigation device, wearable device, internet of things (IoT) device, internet of everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, etc.

Due to at least one of the above methods of generating integrated circuit designs (eg, layouts), self-aligned double patterning can be used in conjunction with placement and routing schemes that perform placement of cells based on cell boundaries. Therefore, vertical alignment of these placed cells can now be performed, and standard cells with the same function but different areas and/or performance can be placed in a single integrated circuit design. Therefore, a more efficient integrated circuit can be created from the resulting integrated design.

The above is a description of exemplary embodiments of the inventive concept and is not to be considered as a limitation of the exemplary embodiments. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made in the exemplary embodiments without substantially departing from the present disclosure. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments.

1000, 2000: design system 1100, 2100, 4100: processor 1200: storage device/non-transitory computer readable storage medium 1210, SCL1: the first standard cell library 1220, SCL2: second standard cell library 1230, DR: Design rules 1300: Design module / integrated design module 1310: Placer 1320: Router 1400: Analysis module/analyzer 2200: Input/output (I/O) device 2300: Network interface 2400: Random Access Memory (RAM) 2500: read only memory (ROM) 2600, 4400: storage device 3100, 3200: integrated circuit 4000: Electronic system 4200: Communication module 4300: display/touch module 4500: memory device 1, 2, 3: arrow ANDA, ANDB: and gate/shadow components ANDC, ANDD: And brake BD11, BD12, BD21, BD22: cell boundary CG: clock generator CK: clock signal CN: Clock Network D1: First direction D2: Second direction DI, DIN: input data DO, DOUT: output data FF1, FF2, FFN, FFA, FFB: flip-flop FC1, FC2, FC3, FC4, FC5: filling unit INVA: Inverter INVB: inverter/shadow element PC11, PC12, PC13, PC14: first wiring/wiring PC21, PC22, PC23, PC24: second wiring/wiring PC2A, PC2B: wiring PR: Program NANDA, NANDD: anti-gate NANDB, NANDC: Inverting gate/shadow element R1, R2: column RL1: first reference line RL2: second reference line S100, S200, S300, S400, S1100, S1200, S1300, S2110, S2120, S2130, S2140, S2150, S2210, S2220, S2230, S2240, S2310, S2320, S2330, S2410, S2420, S2430, S2510, S2520, S2530: step STC1: the first standard unit STC2: Second standard unit STC11, STC12, STC12', STC13, STC14, STC15, STC16, STC17, STC18, STC19, STC1A, STC1B, STC1C, STC1C', STC1D, STC1D', STC1E, STC1F, STC1G, STC1H, STC1I: standard STC21, STC22, STC23, STC23', STC24, STC24', STC25, STC25', STC26, STC27: second type standard unit W: first constant interval/second constant interval/interval WSD: predetermined reference distance/reference distance

By reading the following detailed description in conjunction with the accompanying drawings, the exemplary embodiments of the present disclosure will be more clearly understood. FIG. 1 is a flowchart illustrating a method of generating an integrated circuit design according to an exemplary embodiment of the inventive concept. 2A is a layout diagram illustrating an example of a first type standard cell included in an integrated circuit design according to an exemplary embodiment of the inventive concept. 2B is a layout diagram illustrating an example of a second type standard cell included in an integrated circuit design according to an exemplary embodiment of the inventive concept. 3 and 4 are diagrams showing an example of the layout of an integrated circuit according to an exemplary embodiment of the inventive concept. 5 and 6 are block diagrams showing a design system that generates an integrated circuit design according to an exemplary embodiment of the inventive concept. 7 is a flowchart illustrating an example of the operation of a design system that generates an integrated circuit design according to an exemplary embodiment of the inventive concept. FIG. 8 is a flowchart showing an example of placing and routing in FIG. 7. 9 is a flowchart illustrating an example of performing placement and routing in a method of generating an integrated circuit design according to an exemplary embodiment of the inventive concept. FIG. 10 is a flowchart showing an example of performing placement and routing shown in FIG. 9. FIG. 11 is a layout diagram showing an example in which the first type standard cell and the second type standard cell are placed in one integrated circuit design by the operations shown in FIGS. 9 and 10. 12 is a flowchart illustrating another example of performing placement and routing in a method of generating an integrated circuit design according to an exemplary embodiment of the inventive concept. 13A and 13B are layout diagrams showing an example in which the first type standard cell and the second type standard cell are placed in one integrated circuit by the operation shown in FIG. 12. 14 is a flowchart illustrating an example of performing placement and routing in a method of generating an integrated design according to an exemplary embodiment of the inventive concept. 15 is a layout diagram showing an example in which the first type standard cell and the second type standard cell are placed in one integrated circuit by the operation shown in FIG. 14. 16 is a flowchart illustrating an example of performing placement and routing in a method of generating an integrated circuit design according to an exemplary embodiment of the inventive concept. FIG. 17 is a diagram showing an example of an integrated circuit designed by the operation shown in FIG. 16. 18 is a flowchart illustrating an example of performing placement and routing in a method of generating an integrated circuit design according to an exemplary embodiment of the inventive concept. FIG. 19 is a diagram showing an example of an integrated circuit designed by the operation shown in FIG. 18. FIG. 20 is a block diagram illustrating an electronic system according to an exemplary embodiment of the inventive concept.

S100, S200, S300, S400: steps

Claims (20)

A method for generating an integrated circuit design, the method comprising: Receiving input data defining multiple input units of the integrated circuit design; Selecting a first standard cell from the first standard cell library to represent the input cell having a first characteristic, the first standard cell library including a first type standard cell manufactured using a first diffusion discontinuity scheme; A second standard cell is selected from the second standard cell library to represent the input cell having a second characteristic different from the first characteristic, the second standard cell library includes a second type manufactured using a second diffusion discontinuity scheme Standard cells, each of the second type standard cells has the same function as the corresponding one of the first type standard cells, the second diffusion discontinuity scheme is different from the first diffusion discontinuity scheme; as well as The output data representing the integrated circuit design is generated by performing placement and routing on the selected first standard cell and the selected second standard cell. The method according to item 1 of the patent application scope, wherein one of the first standard units has a first function, and the one first standard unit includes a plurality of first units separated at constant intervals Wiring, and the two outermost first wirings of the plurality of first wirings are positioned to overlap the cell boundary of the first standard cell. The method according to item 2 of the patent application scope, wherein one of the second standard units has the first function, and the one second standard unit includes the units separated by the constant interval A plurality of second wirings, and the two outermost second wirings of the plurality of second wirings are positioned so as not to overlap the cell boundary of the one second standard cell. The method of claim 3, wherein the first diffusion discontinuity scheme is a single diffusion discontinuity scheme, and the second diffusion discontinuity scheme is a double diffusion discontinuity scheme. The method according to item 1 of the patent application range, wherein the first characteristic indicates a pin density less than a reference density and the characteristic indicates a pin density greater than or equal to the reference density. The method as described in item 5 of the patent application scope, wherein generating the output data further includes: The placement and routing are re-executed so that target standard cells placed in the plurality of standard cells in the integrated circuit design are physically adjacent to each other, and the target standard cells correspond to the second type standard cells. The method as described in item 5 of the patent application scope, in which: Standard cells of different types are separated from each other in the same column of the integrated circuit by a distance greater than or equal to a predetermined reference distance, and Standard cells of the same type are arranged closer than the predetermined reference distance in the same column of the integrated circuit design. The method as described in item 5 of the patent application scope, wherein generating the output data further includes: Insert filled cells between different types of standard cells. The method as described in item 1 of the patent application scope, wherein generating the output data includes: Using the first type standard unit to perform the placement; Performing a placement change by replacing the target standard cell among the plurality of standard cells placed in the integrated circuit design with one of the second type standard cells; and The routing is carried out based on the result of the placement change. The method as described in item 9 of the patent application scope, wherein the target standard unit is a standard unit used in a clock network. The method as described in item 1 of the patent application scope, wherein generating the output data includes: Using the first type standard unit to perform the placement and routing; Performing a placement change by replacing the target standard cell among the plurality of standard cells placed in the integrated circuit design with one of the second type standard cells; and The routing is re-executed based on the result of the placement change. The method according to item 11 of the patent application scope, wherein the target standard unit is a standard unit used in a time-critical data path among multiple data paths. A design system for generating integrated circuit designs, including: The storage device is configured to store the placer module and the router module; and A processor configured to access the storage device to execute the module, Wherein the placer module is configured to assign at least one of the first type standard cells and the second based on the input data representing the input unit of the integrated circuit, the first standard cell library and the second standard cell library At least one of type standard cells is placed in the integrated circuit, the input data defines the integrated circuit design, and the first standard cell library includes the first type manufactured using a first diffusion discontinuity scheme Standard cells, the second standard cell library includes the second type standard cells manufactured using a second diffusion discontinuity scheme, each of the second type standard cells has a correspondence with the first type standard cells Of the same function, the second diffusion discontinuity scheme is different from the first diffusion discontinuity scheme, and Wherein the router module is configured to select the at least one of the first type standard cells and the at least one of the second type standard cells placed in the integrated circuit design The connection of the router is routed to generate output data representing the design of the integrated circuit. An integrated circuit design, including: The first type of standard cell is configured to be manufactured using the first diffusion discontinuity scheme; and The second type standard cell is configured to be manufactured using a second diffusion discontinuity scheme, and each of the second type standard cells has the same function as the corresponding one of the first type standard cells, the The second diffusion discontinuity scheme is different from the first diffusion discontinuity scheme. The integrated circuit design as described in item 14 of the patent application scope, in which: One first standard unit of the first type standard unit has a first function and includes a plurality of first wirings, and the two outermost first wirings of the plurality of first wirings are positioned to be The cell boundaries of a standard cell overlap, and One second standard unit of the second type standard unit has the first function and includes a plurality of second wirings, and the two outermost second wirings of the plurality of second wirings are positioned so as not to The cell boundaries of the second standard cell overlap. The integrated circuit design as described in item 15 of the patent application scope, in which: The plurality of first wires in the one first standard unit are separated by a first constant interval, The plurality of second wires in the one second standard unit are separated by a second constant interval, and The first constant interval and the second constant interval are the same as each other. The integrated circuit design according to item 15 of the patent application scope, wherein, when the one first standard cell and the one second standard cell are arranged adjacent to each other in different columns of the integrated circuit , One of the plurality of first wirings and one of the plurality of second wirings are positioned on the same straight line. The integrated circuit design according to item 15 of the patent application scope, wherein, when the one first standard cell and the one second standard cell are arranged adjacent to each other in the same column of the integrated circuit , The one first standard unit and the one second standard unit are separated from each other by a distance greater than or equal to a predetermined reference distance. The integrated circuit design as described in item 15 of the patent application scope, wherein the area of the one second standard cell is larger than the area of the one first standard cell. The integrated circuit design as described in item 15 of the patent application scope, in which: The one first standard cell is placed in the integrated circuit to correspond to a plurality of first reference lines separated at constant intervals, The one second standard cell is placed in the integrated circuit to correspond to a plurality of second reference lines separated at the constant interval, and Each of the plurality of second reference lines is arranged between two adjacent first reference lines.

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