TW202015347A - Encoder and associated encoding method and flash memory controller - Google Patents

Abstract

The present invention provides an encoder of a flash memory controller, where the encoder includes a barrel shifter module, an inverse matrix calculating circuit and a calculating circuit. In the operations of the encoder, the barrel shifter module processes a plurality of data blocks to generate a plurality of partial parity blocks including a first portion, a second portion and a third portion; the inverse matrix calculating circuit performs an inverse matrix calculating operations upon the first portion to generate a first portion of parity blocks; and the calculating circuit performs an inverse matrix calculating operations upon the second portion and the third portion according to the first portion of the parity blocks, to generate a second portion of the parity blocks and a third portion of the parity of blocks, wherein the first portion of the parity blocks, the second portion of the parity blocks, and the third portion of the parity of blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.

Description

Encoder and related encoding method and flash memory controller

The invention relates to an encoder, in particular to an encoder used in a flash memory controller.

In a general encoder, a parity-check matrix is provided for the encoder to check whether the generated parity code is correct. For example, after encoding the data to generate a check code, the encoder multiplies the data with the check code and the check code check matrix, and if the multiplication result is equal to "0", the encoding is determined to be correct; If the multiplication result is not equal to "0", the coding error is judged. In response to this check code check matrix, the encoder will have a corresponding check code generation matrix for generating a suitable check code, however, in some cases, the check code generation matrix may not be found, so encode The encoder may need to perform multiple matrix multiplication operations and/or compensation/adjustment operations to generate parity codes similar to those generated using parity code generation matrices, thus increasing the complexity of the encoder. In particular, the above-mentioned multiple matrix multiplication operations usually include circulant convolution calculations, so the hardware cost of the encoder is greatly increased.

Therefore, one of the objects of the present invention is to propose an encoder that can reduce the hardware required for the cyclic convolution calculation in the encoder to avoid the situation where the hardware cost described in the prior art increases significantly.

In one embodiment of the present invention, an encoder used in a flash memory controller is disclosed, which includes a barrel shifter module, an inverse matrix calculation circuit, and a calculation circuit. In the operation of the encoder, the barrel shifter module is used to process multiple data blocks to generate multiple local check code blocks, wherein the multiple local check code blocks include a The first part, a second part, and a third part; the first inverse matrix calculation circuit is coupled to the barrel shifter module, and is used to perform an inverse matrix operation on the first part to generate a first part of the calibration Verification code block; the calculation circuit is coupled to the barrel shifter module and the adjustment circuit, and used to invert the second part and the third part according to the verification code block of the first part Matrix operation to generate a second part check code block and a third part check code block; wherein the first part check code block, the second part check code block and the The check code block of the third part is used as multiple check code blocks generated by the encoder for the multiple data blocks, and the multiple data blocks and the multiple check code blocks are used Write to a flash memory.

In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes There is a memory, a microprocessor and an encoder, wherein the memory is used to store a code, the microprocessor is used to execute the code to control access to the flash memory module, and the code The device is used to encode the multiple data blocks to obtain multiple check code blocks. The encoder includes a barrel shifter module, an inverse matrix calculation circuit and a calculation circuit. In the operation of the encoder, the barrel shifter module is used to process multiple data blocks to generate multiple local check code blocks, wherein the multiple local check code blocks include a The first part, a second part, and a third part; the first inverse matrix calculation circuit is coupled to the barrel shifter module, and is used to perform an inverse matrix operation on the first part to generate a first part of the calibration Verification code block; the calculation circuit is coupled to the barrel shifter module and the adjustment circuit, and used to invert the second part and the third part according to the verification code block of the first part Matrix operation to generate a second part check code block and a third part check code block; wherein the first part check code block, the second part check code block and the The check code block of the third part is used as multiple check code blocks generated by the encoder for the multiple data blocks, and the multiple data blocks and the multiple check code blocks are used Write to a flash memory.

In another embodiment of the present invention, an encoding method applied to a flash memory controller is disclosed, which includes the following steps: processing multiple data blocks to generate multiple local check code blocks , Where the plurality of local check code blocks include a first part, a second part, and a third part; perform an inverse matrix operation on the first part to generate a first part of the check code block; according to the first A part of the check code block to perform an inverse matrix operation on the second part and the third part to generate a second part of the check code block and a third part of the check code block, wherein the first Part of the check code block, the second part of the check code block, and the third part of the check code block are used as the multiple check code areas generated by the encoder for the multiple data blocks Block; and the plurality of data blocks and the plurality of check code blocks are written to a flash memory.

FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (Read Only Memory, ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory module 120 (Access). The control logic 114 includes an encoder 132 and a decoder 134, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or, error correction) Error Correction Code (ECC), and the decoder 134 is used to decode the data read from the flash memory module 120.

Under typical conditions, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks, and the controller (for example, through a microprocessor 112 executes the flash memory controller 110 of the program code 112C) the operations of copying, erasing, and merging data to the flash memory module 120 are to copy, erase, and merge data in units of blocks. In addition, a block can record a certain number of data pages (Page), in which the controller (for example: the memory controller 110 that executes the program code 112C through the microprocessor 112) writes to the flash memory module 120 The operation of data is written in units of data pages.

In practice, the flash memory controller 110 that executes the program code 112C through the microprocessor 112 can use its own internal components to perform many control operations, such as: using the control logic 114 to control the flash memory module 120 Access operations (especially access operations on at least one block or at least one data page), using buffer memory 116 to perform required buffer processing, and using interface logic 118 to communicate with a host device 130 .

In one embodiment, the memory device 100 may be a portable memory device (for example, a memory card that conforms to SD/MMC, CF, MS, XD standards), and the main device 130 is an electronic device that can be connected to the memory device. For example, mobile phones, notebook computers, desktop computers... and so on. In another embodiment, the memory device 100 may be installed in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device. .

In this embodiment, the encoder 132 is a low-density parity check code (LDPC code) encoding circuit, and can generate a corresponding check code according to the data from the host device 130, and the generated Of the check codes conform to a check code check matrix. Specifically, referring to FIG. 2, it is assumed that the check code check matrix is a matrix of size c*t (for example, c=5, t=48, or any other suitable value), and the check code The check matrix can be divided into a matrix M on the left (size c*(tc)) and a matrix K on the right (size c*c). In order to find the check code generation matrix corresponding to the check code check matrix, You can first find the inverse matrix K ^-1 (inverse matrix) of the matrix K, and then multiply the inverse matrix (K ^-1 ) and the matrix M to obtain the matrix P, and the transpose matrix of the matrix P can be Generate a matrix as a check code. In other words, after finding the transpose matrix of the matrix P, the encoder 132 can multiply the data of the main device 130 by the transpose matrix of the matrix P to obtain the check code corresponding to the data, and the encoder will then The data and the check code are multiplied by the check code check matrix to determine whether the check code is correct. For example, if the multiplication result is equal to "0", it is judged that the coding is correct; and if the multiplication result is not equal to "0", it is judged that the coding is wrong. After determining that the encoding is correct, the data and the corresponding verification code are written to a data page in the flash memory module 120.

It should be noted that each unit of the check code check matrix described above is implemented as a block, and the block can be a square matrix (such as a 64*64 matrix or a 192*192 matrix). That is, the check code check matrix contains c*t blocks.

However, in some cases, the inverse matrix K ^-1 may not be easily found, so the encoder 132 may need to perform multiple matrix multiplication operations and/or compensation/adjustment operations to obtain a content similar to the inverse matrix K ^-1 , It is used to find the check code generation matrix to generate the check code. The present invention therefore proposes a circuit architecture so that the encoder 132 can complete the operation of the encoder 132 under the condition of saving hardware cost as much as possible. It should be noted that the encoding process in the encoder 132 involves many complicated mathematical operations, but since the focus of the present invention is on the design of the circuit architecture, the details of the relevant matrix content and the derivation process are not repeated here.

FIG. 3 is a schematic diagram of a matrix K according to an embodiment of the invention. The rows and columns of the matrix K can be divided into three segments, and each segment has a block, s blocks, and b blocks, respectively. In this embodiment, the area 302 in the upper right corner of the matrix K shown in FIG. 3 is a blank area, that is, all the values in all the blocks in the area 302 are "0"; It is a non-zero area, that is, all blocks in the area 304 must contain a non-zero value; in addition, other areas of the matrix K are not limited to blank areas or non-zero areas. The encoder 132 shown below is designed for the matrix K shown in FIG. 3, but the invention is not limited thereto.

FIG. 4 is a schematic diagram of an encoder 400 according to an embodiment of the present invention, where the encoder 400 can be used as the encoder 132 shown in FIG. As shown in FIG. 4, the encoder 400 includes a barrel shifter module 410, a first inverse matrix calculation circuit 420, and a calculation circuit 430, where the calculation circuit 430 includes three barrel shifter modules Groups 431, 434, and 435, a first adjustment circuit 432, a second inverse matrix calculation circuit 433, a second adjustment circuit 436, a third inverse matrix calculation circuit 437, and a calculation circuit 440, wherein the calculation circuit 440 includes A barrel shifter module 441, a fourth inverse matrix calculation circuit 442, and a third adjustment circuit 443. In this embodiment, the barrel shifter modules 410, 431, 434, 435, and 441 can be implemented using multiple barrel shifters and multiple accumulation circuits. The first inverse matrix calculation circuit 420, The inverse matrix calculation circuit 433, the third inverse matrix calculation circuit 437, and the fourth inverse matrix calculation circuit 442 may be implemented using a cyclic convolution calculation circuit and a compensation circuit. In this embodiment, the encoder 400 divides a piece of data from the main device 130 into multiple data blocks (in this embodiment, the multiple data blocks are N data blocks DB_1~DB_N), and the Multiple data blocks DB_1~DB_N are encoded to generate multiple check code blocks (in this embodiment, the multiple check code blocks are (a+s+b) check code blocks PB_a, PB_s , PB_b). It should be noted that the size of one data block and one check code block is the same, and the size of the data block can be determined by the designer, for example, 64*64 bits or 192*192 Bits.

In the operation of the encoder 400, first, the barrel shifter module 410 processes the data blocks DB_1~DB_N to generate multiple partial parity blocks. Specifically, the barrel shifter module 410 can shift the data blocks DB_1~DB_N through the first internal barrel shifter, and perform the shifted data block through the accumulation circuit Add to get the first local parity code block; then, through the internal second barrel shifter to shift the data blocks DB_1~DB_N respectively, and the accumulated data to shift the shifted data The blocks are added to obtain the second local parity code block... and so on, the barrel shifter module 410 generates a total of (a+s+b) local parity code blocks.

The local check code block will be divided into three parts for different processing, where the first part contains a local check code block, the second part contains s local check code block, and the third part Contains b local check code blocks. In the operation of the first inverse matrix calculation circuit 420, it performs an inverse matrix operation (that is, a cyclic convolution operation and a compensation operation) on the a local parity check code blocks to generate a parity check block PB_a . Next, the calculation circuit 430 generates s check code blocks PB_s and b checksums based on the a check code blocks PB_a, the s local check code blocks, and the b local check code blocks Code block PB_b.

In detail, first, the barrel shifter module 431 processes the a check code block PB_a to generate b processed blocks, and then the first adjustment circuit 432 processes the b processed blocks The b partial check code blocks are added to generate an adjusted third part of the data. Then, the second inverse matrix calculation circuit 433 performs an inverse matrix operation on the adjusted third portion of data to generate a first operation result, and the barrel shifter module 435 processes the a check code blocks PB_a to S first processed blocks are generated, the barrel shifter module 434 processes the first operation result to generate s second processed blocks, and the second adjustment circuit 436 processes the s first processed blocks The post-block, the s second processed blocks and the s local check code blocks are added to generate an adjusted second part of the data. Next, the third inverse matrix calculation circuit 437 performs an inverse matrix operation on the adjusted second part of data to generate the s check code blocks PB_s. Next, the barrel shifter module 441 processes the results of the s check code blocks PB_s to generate b processed blocks, and the fourth inverse matrix calculation circuit 442 performs an inverse matrix on the b processed blocks The operation generates a second operation result, and the third adjustment circuit 443 generates the b check code blocks PB_b according to the first operation result and the second operation result.

After generating the check code blocks PB_a, PB_s, PB_b, the encoder 300 multiplies the data blocks DB_1~DB_N together with the check code blocks PB_a, PB_s, PB_b and the check code check matrix to determine the check code Whether the blocks PB_a, PB_s, PB_b are correct. If it is correct, the flash memory controller 110 writes the data blocks DB_1~DB_N together with the verification code blocks PB_a, PB_s, PB_b into a data page of a block of the flash memory module 120 .

In the circuit architecture shown in FIG. 4, the barrel shifter module 410 can be compared to the matrix M shown in FIG. 2, and the first inverse matrix calculation circuit 420 and the calculation circuit 430 are used to generate A content similar to the inverse matrix K ^-1 shown in FIG. 2 can generate check code blocks PB_a, PB_s, and PB_b in the case where the inverse matrix K ^-1 cannot be actually found. In addition, the implementation of the encoder 400 can greatly reduce the number of cyclic convolution calculation circuits (included in the inverse matrix calculation circuit). For example, assuming that K is a square matrix of 10*10, and a=4, s=1, =5, the encoder in the prior art needs to use 100 cyclic convolution calculation circuits (10*10=100); In this embodiment, the first inverse matrix calculation circuit 420 requires 16 cyclic convolution calculation circuits (a=4, 4*4=16), and the second inverse matrix calculation circuit 433 requires 25 cyclic convolution calculation circuits (b= 5, 5*5=25), the third inverse matrix calculation circuit 437 only needs one cyclic convolution calculation circuit, and the fourth inverse matrix calculation circuit 442 needs 25 cyclic convolution calculation circuits, so this embodiment only needs 67 The cyclic convolution calculation circuit can reliably reduce the hardware cost of the encoder 400.

In addition, since the first inverse matrix calculation circuit 420 in this embodiment can immediately perform an inverse matrix calculation on the a local check code blocks output by the barrel shifter module 410 to generate a check code area Block to output to the back-end circuit, so if subsequent calculations of the second inverse matrix calculation circuit 433, the third inverse matrix calculation circuit 437, and the fourth inverse matrix calculation circuit 442 are not complicated, the encoder 400 can be used without delay The verification code block is continuously output to the back-end circuit to improve the overall system performance.

Referring to FIG. 5, which is a flowchart of an encoding method according to an embodiment of the present invention, and referring to the contents disclosed in FIGS. 1 to 5 and the above embodiments, the flow of the encoding method is as follows.

Step 500: The process begins.

Step 502: Process multiple data blocks to generate multiple local check code blocks, wherein the multiple local check code blocks include a first part, a second part, and a third part.

Step 504: Perform an inverse matrix operation on the first part to generate a check code block of the first part.

Step 506: Perform an inverse matrix operation on the second part and the third part according to the check code block of the first part to generate a second part check code block and a third part check code Block, wherein the check code block of the first part, the check code block of the second part, and the check code block of the third part are generated by the encoder for the plurality of data blocks Multiple check code blocks.

Step 508: Write the plurality of data blocks and the plurality of check code blocks into a flash memory.

To briefly summarize the present invention, in the encoder of the present invention, it operates by dividing the local parity code block into three parts to reduce the cycle in the encoder when the parity code block can be reliably generated The hardware required for convolution calculations. Therefore, the encoder of the present invention can avoid the situation where the hardware cost described in the prior art is greatly increased. The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: memory device 110: Flash memory controller 112: Microprocessor 112C: Code 112M: read-only memory 114: control logic 116: Buffer memory 118: Interface logic 120: Flash memory module 130: Main device 132, 300, 400, 500: encoder 134: decoder 302, 304: area 400: encoder 410: Barrel shifter module 420: First inverse matrix calculation circuit 430, 440: calculation circuit 431, 434, 435, 441: barrel shifter module 432: First adjustment circuit 433: Second inverse matrix calculation circuit 436: Second adjustment circuit 437: Third inverse matrix calculation circuit 442: Fourth inverse matrix calculation circuit 443: Third adjustment circuit 500~508: steps DB_1~DB_N: data block PB_a, PB_s, PB_b: check code block

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention. Figure 2 is a schematic diagram of a check code check matrix and a check code generation matrix. Figure 3 is a schematic diagram of the matrix K. FIG. 4 is a schematic diagram of an encoder according to an embodiment of the invention. FIG. 5 is a flowchart of an encoding method according to an embodiment of the invention.

400: encoder

410: Barrel shifter module

420: First inverse matrix calculation circuit

430, 440: calculation circuit

431, 434, 435, 441: barrel shifter module

432: First adjustment circuit

433: Second inverse matrix calculation circuit

436: Second adjustment circuit

437: Third inverse matrix calculation circuit

442: Fourth inverse matrix calculation circuit

443: Third adjustment circuit 443

DB_1~DB_N: data block

PB_a, PB_s, PB_b: check code block

Claims (9)

An encoder, including: A barrel shifter module is used to process multiple data blocks to generate multiple partial parity blocks, wherein the multiple partial parity blocks include a first part, A second part and a third part; A first inverse matrix calculation circuit, coupled to the barrel shifter module, for performing an inverse matrix operation on the first part to generate a check code block of the first part; and A calculation circuit, coupled to the barrel shifter module and the first inverse matrix calculation circuit, for inverse matrixing the second part and the third part according to the check code block of the first part Operation to generate a second part of the verification code block and a third part of the verification code block; The check code block of the first part, the check code block of the second part, and the check code block of the third part are used as the multiple corrections generated by the encoder for the multiple data blocks Code verification block. The encoder as described in item 1 of the patent application scope, wherein the calculation circuit includes: A first adjustment circuit, coupled to the first inverse matrix calculation circuit, for adjusting the third part of the plurality of local check code blocks according to the first part of the check code block to generate an adjusted the third part; A second inverse matrix calculation circuit, coupled to the first adjustment circuit, for performing an inverse matrix operation on the adjusted third part to generate a first operation result; A second adjustment circuit, coupled to the barrel shifter module, the first inverse matrix calculation circuit and the second inverse matrix calculation circuit, for adjusting the first part of the parity check block and the first An operation result to adjust the second part of the plurality of local check code blocks to generate an adjusted second part; A third inverse matrix calculation circuit, coupled to the second adjustment circuit, for performing an inverse matrix operation on the adjusted second part to generate a second part check code block; and Another calculation circuit, coupled to the second inverse matrix calculation circuit and the third inverse matrix calculation circuit, is used to generate a third part of the calibration based on the first operation result and the second part of the check code block Code verification block. The encoder as described in item 1 of the patent application scope is a low-density parity check code (LDPC code) coding circuit. A flash memory controller, including: A memory for storing a code; A microprocessor for executing the program code to control access to the flash memory module; and An encoder, including: A barrel shifter module is used to process multiple data blocks to generate multiple partial parity blocks, wherein the multiple partial parity blocks include a first part, A second part and a third part; A first inverse matrix calculation circuit, coupled to the barrel shifter module, for performing an inverse matrix operation on the first part to generate a check code block of the first part; and A calculation circuit, coupled to the barrel shifter module and the first inverse matrix calculation circuit, for inverse matrixing the second part and the third part according to the check code block of the first part Operation to generate a second part of the verification code block and a third part of the verification code block; The check code block of the first part, the check code block of the second part, and the check code block of the third part are used as the multiple corrections generated by the encoder for the multiple data blocks Code verification block. The flash memory controller as described in item 4 of the patent application scope, wherein the calculation circuit includes: A first adjustment circuit, coupled to the first inverse matrix calculation circuit, for adjusting the third part of the plurality of local check code blocks according to the first part of the check code block to generate an adjusted the third part; A second inverse matrix calculation circuit, coupled to the first adjustment circuit, for performing an inverse matrix operation on the adjusted third part to generate a first operation result; A second adjustment circuit, coupled to the barrel shifter module, the first inverse matrix calculation circuit and the second inverse matrix calculation circuit, for adjusting the first part of the parity check block and the first An operation result to adjust the second part of the plurality of local check code blocks to generate an adjusted second part; A third inverse matrix calculation circuit, coupled to the second adjustment circuit, for performing an inverse matrix operation on the adjusted second part to generate a second part check code block; and Another calculation circuit, coupled to the second inverse matrix calculation circuit and the third inverse matrix calculation circuit, is used to generate a third part of the calibration based on the first operation result and the second part of the check code block Code verification block. The flash memory controller as described in item 4 of the patent application scope, wherein the encoder is a low-density parity check code (LDPC code) coding circuit. An encoding method, including: Processing multiple data blocks to generate multiple partial parity blocks, wherein the multiple partial parity blocks include a first part, a second part, and a third part; Performing an inverse matrix operation on the first part to generate a check code block of the first part; and Performing an inverse matrix operation on the second part and the third part according to the check code block of the first part to generate a second part check code block and a third part check code block, The check code block of the first part, the check code block of the second part, and the check code block of the third part are used as the multiple calibrations generated by the encoder for the multiple data blocks Code verification block. The encoding method as described in item 7 of the patent application scope, wherein the second part and the third part are subjected to an inverse matrix operation according to the check code block of the first part to generate the check code area of the second part The steps of the block and the check code block of the third part include: Adjusting the third part of the plurality of local check code blocks according to the check code block of the first part to generate an adjusted third part; Performing an inverse matrix operation on the adjusted third part to generate a first operation result; Adjusting the second part of the plurality of local check code blocks according to the check code block of the first part and the first operation result to generate an adjusted second part; Performing an inverse matrix operation on the adjusted second part to generate a check code block of the second part; and According to the first operation result and the second part of the verification code block, a third part of the verification code block is generated. The encoding method described in item 7 of the patent application scope uses a low-density parity check code (LDPC code) encoding circuit to perform.

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