TWI759672B - Decoding method and associated flash memory controller and electronic device - Google Patents

Abstract

The present invention provides a decoding method, wherein the decoding method includes the steps of: reading a codeword from a flash memory module; and using a parity check matrix to decode the codeword, wherein the parity check matrix includes a plurality of circulant permutation matrixes, and an order of a parallel operation of the decoding step is less than a row number of any one of the circulant permutation matrixes.

Description

Decoding method and associated flash memory controller and electronic device

The present invention relates to a decoding method, especially a decoding method applied to a flash memory controller.

In the current decoding method applied to the flash memory controller, after the flash memory controller reads a codeword from a flash memory module, the codeword is checked with a parity check. The matrix (parity check matrix) is multiplied to perform the decoding operation. Specifically, theoretically, after multiplying the codeword and the parity check matrix, a matrix with all values of 0 should be obtained. Therefore, if the multiplication result is not all 0, it needs to be adjusted through some algorithms. The content of the codeword is 0 until the adjusted codeword is multiplied by the parity check matrix to complete the decoding operation. However, the above-mentioned decoding operation usually requires high parallel operation, thus increasing the hardware cost.

Therefore, one of the objectives of the present invention is to provide a decoding method applied in a flash memory controller, which can efficiently complete the decoding operation with low parallel operation, so as to solve the problems in the prior art.

In one embodiment of the present invention, a decoding method is disclosed, which includes: reading a codeword from a flash memory module; and decoding the codeword using a parity check matrix, wherein the Each layer in the parity check matrix includes N cyclic permutation matrices, and the decoding operation includes the following steps: for any group in the N groups, sequentially correspond to the M parts of the group with the corresponding Multiplying the M parts of the circular array matrix to obtain M processed data; storing the M processed data in M different addresses of a block in a memory; from the N blocks Each block reads two pieces of processed data, and combines them to generate a first data and a residual data, wherein the first data is used to calculate the first data corresponding to the multiplication of the codeword and the parity check matrix. A first part of a row of data, wherein N and M are positive integers greater than one, and the remaining data is the content after deducting the first data from the two processed data; perform parallel operations on the first data and Decoding is performed, wherein the order of the parallel operation is less than the number of columns of any circular permutation matrix.

In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes There is a ROM, a microprocessor and a decoder. The ROM system is used to store a code; the microprocessor is used to execute the code to control access to the flash memory module; and in operation of the flash memory controller, The microprocessor reads a codeword from the flash memory module, and the decoder decodes the codeword using a parity check matrix, wherein each layer of the parity check matrix includes N Circular arrangement matrices, and the microprocessor performs the decoding operation using the following steps: for any group in the N groups, sequentially, respectively, the M parts of the group and the corresponding M circulant arrangement matrices Partially multiply to obtain M processed data; store the M processed data in M different addresses of a block in a memory; read from each of the N blocks Two pieces of processed data are combined to generate a first data and a residual data, wherein the first data is used to calculate a first data corresponding to the first column of data after the codeword and the parity check matrix are multiplied. A part, wherein N and M are positive integers greater than one, and the remaining data is the content after deducting the first data from the two processed data; perform parallel operation and decoding on the first data, wherein the parallel The order of the operation is less than the number of columns of any circular array.

In another embodiment of the present invention, an electronic device is disclosed, which includes a flash memory module and a flash memory controller. In operation of the electronic device, the flash memory controller reads a codeword from the flash memory module, and the flash memory controller uses a parity check matrix to process the codeword decoding, wherein each layer in the parity check matrix includes N cyclic array matrices, and the flash memory controller uses the following steps to perform the decoding operation: for any group in the N groups, sequentially The M parts of the group are respectively multiplied by the M parts of the corresponding cyclic array matrix to obtain M processed data; the M processed data are stored in M parts of a block in a memory In different addresses; read two pieces of processed data from each of the N blocks, and combine them to generate a first data and a residual data, wherein the first data is used to calculate the code corresponding to the code A first part of the data in the first column after the word is multiplied by the parity check matrix, wherein N and M are positive integers greater than one, and the remaining data is the two processed data after deducting the first data content; perform parallel operation and decoding on the first data, wherein the order of the parallel operation is less than the number of columns of any cyclic array matrix.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110 , and the flash memory controller 110 is used for accessing the flash memory module 120 . According to this embodiment, the flash memory controller 110 includes a microprocessor 112 , a read only memory (ROM) 112M, a control logic 114 , a buffer memory 116 , and an interface logic 118 . The ROM 112M is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the flash memory module 120 . The control logic 114 includes an encoder 132 , a decoder 134 , a first memory 136 and a second memory 138 . In this embodiment, the encoder 132 and the decoder 134 are used for encoding and decoding operations of Quasi-Cyclic Low Density Party-Check (QC-LDPC) codes.

Typically, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks, and the controller (eg, through a microprocessor) 112. The flash memory controller 110 executing the program code 112C) performs operations such as erasing the flash memory module 120 on a block-by-block basis. In addition, a block can record a specific number of pages of data, wherein the controller (eg, the memory controller 110 that executes the code 112C through the microprocessor 112 ) writes to the flash memory module 120 The operation of data is written in units of data pages. In this embodiment, the flash memory module 120 is a three-dimensional NAND-type flash memory (3D NAND-type flash).

In practice, the flash memory controller 110 that executes the code 112C through the microprocessor 112 can use its own internal components to perform various control operations. For example, the control logic 114 is used to control the flash memory module 120. Access operations (especially access operations to at least one block or at least one data page), use the buffer memory 116 to perform required buffering, and use the interface logic 118 to communicate with a Host Device 130 . The buffer memory 116 may be a static random access memory (Static RAM, SRAM), but the invention is not limited thereto.

In one embodiment, the memory device 100 may be a portable memory device (eg, a memory card conforming to SD/MMC, CF, MS, XD standards), and the host device 130 is an electronic device that can be connected to the memory device, Such as mobile phones, laptops, desktops...etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage conforming to Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications The device is installed in an electronic device, such as a mobile phone, a notebook computer, a desktop computer, and the main device 130 may be a processor of the electronic device.

During the process of accessing the flash memory module 120 by the flash memory controller 110, when the flash memory controller 110 needs to write a data to the flash memory module 120, the encoder 132 will The data is multiplied by a generator matrix to obtain encoded data, and the encoded data is written into the flash memory module 120, wherein the encoded data includes the data and the corresponding calibration data code verification. On the other hand, when the flash memory controller 110 needs to read the data from the flash memory module 120, the decoder 134 will read the encoded data from the flash memory module 120, and encode the data The latter data is multiplied by a parity check matrix for decoding. In one embodiment, the parity check matrix and the generator matrix are correlated with each other, and after multiplying the generator matrix and the transposed matrix of the parity check matrix, a matrix with all values 0 will be obtained. Therefore, Since the encoded data may be in error due to voltage drift or other factors during the process of writing the encoded data to the flash memory module 120, the decoder 134 continuously adjusts the encoded data read by , so that after the adjusted encoded data is multiplied by the parity check matrix, a matrix whose all values are 0 can be obtained to complete error correction and decoding operations. Since the present invention focuses on the part of the decoding operation, the following description will only describe the part of the decoder 134 .

Referring to FIG. 2 , it is a schematic diagram of a codeword and a parity check matrix H read from the flash memory module 120 according to an embodiment of the present invention. As shown in FIG. 2, the parity check matrix H is composed of a plurality of circulant permutation matrices. In this embodiment, 8 circulant permutation matrices are used as an example for the subsequent description, but this is not the case. is a limitation of the present invention. The size of each circular array matrix is 64*64, and only one value in each column is "1", the rest of the values are "0", the content of the next column is generated by shifting the previous column to the right by 1 bit, and the figure The content in the square brackets is the address of the value "1" in the first column. Taking the first layer (layer) of the parity check matrix H shown in Figure 2 as an example, the 27th bit of the first column of the circular arrangement matrix CM0 is "1" and the rest are "0", and the second column is "0". The 28th bit is "1", the rest are "0", the 29th bit in the third column is "1", the rest are "0"... and so on; The bit is "1" and the rest is "0", the fourth bit in the second column is "1", the rest is "0", the fifth bit in the third column is "1", and the rest is "0"... And so on; the 55th bit of the first column of the circular arrangement matrix CM2 is "1" and the rest are "0", the 56th bit of the second column is "1", the rest are "0", and the third column is "0". The 57th bit is "1", the rest are "0"... and so on; the 12th bit of the first column of the circular arrangement matrix CM3 is "1" and the rest are "0", and the 13th column of the second column is "1". The one bit is "1", the rest are "0", the 14th bit in the third column is "1", and the rest are "0"... and so on.

In this embodiment, the codeword read from the flash memory module 120 is 256 bits, and the decoder 134 divides the codeword into 4 groups CW0-CW3, wherein each group CW0-CW3 CW3 is a 64-bit element, and the groups CW0~CW3 are multiplied by the cyclic array matrices CM0~CM3 of the parity check matrix H respectively for decoding. In this embodiment, the above matrix operation can be regarded as 128*256 parity. The check matrix H is multiplied by the 256*1 codeword to generate a 128*1 matrix multiplication result.

However, in the above operation, if the groups CW0 to CW3 are directly multiplied by the circular array matrices CM0 to CM3 for subsequent decoding, the decoder 134 will need to perform a parallel operation with an order of 64, and therefore requires Therefore, in the following embodiments of the present invention, parallel operations with an order of 16 are completed through special memory access and codeword processing methods to further save circuits and memory. body area.

Referring to Figure 3, each group CW0~CW3 is subdivided into 4 parts, of which group CW0 includes 4 parts CW0[0]~CW0[3], and group CW1 includes 4 parts CW1[0] ~CW1[3], group CW2 contains 4 sections CW2[0]~CW2[3], and group CW3 contains 4 sections CW3[0]~CW3[3], each of which is 16 bits. Next, the decoder 134 multiplies the groups CW0-CW3 by the circular array matrices CM0-CM3, respectively, to obtain 16 pieces of processed data, which are stored in 16 different addresses in the first memory 136 (for example, corresponding to 16 different word lines). Specifically, the first sub-layer SL0 in Figure 3 contains 4 pieces of processed data, which are CW0[0], CW1[0], CW2[0], and CW3[0] in the cyclic arrangement matrix CM0~ The result of the multiplication of the first part of CM3, wherein the processed data generated by multiplying CW0[0] and the circular array matrix CM0 are stored in the second to third addresses of the first memory 136, CW1[0] and the circular array The processed data generated by the multiplication of the arrangement matrix CM1 is stored in the fifth to sixth addresses of the first memory 136, and the processed data generated by the multiplication of CW2[0] and the circular arrangement matrix CM2 is stored in the first memory 136. The 9th and 12th addresses of the memory 136, and the processed data generated by multiplying CW3[0] by the circular arrangement matrix CM3 are stored in the 13th to 14th addresses of the first memory 136; FIG. 3 The second sub-layer SL1 contains 4 pieces of processed data, which are CW0[1], CW1[1], CW2[1], and CW3[1] are multiplied by the second part of the circular arrangement matrix CM0~CM3 respectively , wherein the processed data generated by multiplying CW0[1] by the circular array matrix CM0 are stored in the 3rd to 4th addresses of the first memory 136, where CW1[1] is multiplied by the circular array matrix CM1. The generated processed data is stored in the 6th to 7th addresses of the first memory 136 , and the processed data generated by multiplying CW2[1] by the circular arrangement matrix CM2 is stored in the 9th address of the first memory 136 . ~10 addresses, and the processed data generated by multiplying CW3[1] and the circular array matrix CM3 are stored in the 14th~15th addresses of the first memory 136; the third sublayer SL2 in FIG. 3 It contains 4 pieces of processed data, which are the results of multiplying CW0[2], CW1[2], CW2[2], and CW3[2] in the third part of the circular array matrix CM0~CM3 respectively, where CW0[ 2] The processed data generated by multiplying the circular array CM0 is stored in the first and fourth addresses of the first memory 136, and the processed data generated by multiplying CW1[2] by the circular array CM1 The 7th to 8th addresses stored in the first memory 136, the processed data generated by multiplying CW2[2] and the circular arrangement matrix CM2 are stored in the 10th to 11th addresses of the first memory 136, And the processed data generated by multiplying CW3[2] and the cyclic array matrix CM3 are stored in the 15th to 16th addresses of the first memory 136; the fourth sublayer SL3 in FIG. 3 includes 4 processed data data, which are the results of multiplying CW0[3], CW1[3], CW2[3], and CW3[3] respectively in the fourth part of the cyclic array matrix CM0~CM3, where CW0[3] and the cyclic array matrix The processed data generated by the multiplication of CM0 is stored in the first to second addresses of the first memory 136, and the processed data generated by the multiplication of CW1[3] and the circular array matrix CM1 The processed data stored in the 5th and 8th addresses of the first memory 136, and the processed data generated by multiplying CW2[3] and the circular arrangement matrix CM2 are stored in the 11th to 12th addresses of the first memory 136 , and the processed data generated by multiplying CW3[3] and the circular arrangement matrix CM3 are stored in the 13th and 16th addresses of the first memory 136 .

FIGS. 4-8 are schematic diagrams illustrating operations performed by the decoder 134 on multiple pieces of processed data stored in the first memory 136 according to an embodiment of the present invention. In FIG. 4, first, the first memory 136 can be divided into four parts, wherein the four parts respectively include the 1st to 4th addresses, the 5th to 8th addresses, and the 9th to 12th bits. address and the 13th to 16th addresses (that is, corresponding to the circular array matrices CM0 to CM3, respectively). The decoder 134 first fetches the first content related to the first sub-layer SL0 from each part of the first memory 136 , that is, from the second, fifth, and 12th parts of the first memory 136 shown in FIG. 4 . , 13 addresses to take out the first content about the first sublayer SL0. Next, the decoder 134 inverts the content retrieved from the first memory 136 , and stores the inverted content in four different addresses of the second memory 138 .

Next, in FIG. 5 , the decoder 134 first retrieves the first content related to the second sub-layer SL1 from each part of the first memory 136 , that is, from the first memory shown in FIG. 5 . The 3rd, 6th, 9th, and 14th addresses of 136 fetch the first content related to the second sub-layer SL1, and flip the content fetched from the first memory 136; at the same time, the decoder 134 also automatically The second memory 138 reads the content previously stored in FIG. 4, and performs multiplexing (combining operation) together with the content retrieved from the first memory 136 and flipped to generate a complete first sub The content of layer SL0 is used for subsequent parallel operations of order 16 (each column in the figure is 16 bits), and a 64-bit content composed of the second sub-layer SL1 and the fourth sub-layer SL3 is also generated. The remaining data is stored in four different addresses of the second memory 138 . In this embodiment, the first sublayer SL0 can be regarded as a first part used to calculate the first row of data corresponding to the codeword (including CW0~CW3) multiplied by the parity check matrix H share.

Next, in FIG. 6 , the decoder 134 first retrieves the first content related to the third sub-layer SL2 from each part of the first memory 136 , that is, from the first memory shown in FIG. 6 . The 4th, 7th, 10th, and 15th addresses of 136 fetch the first content related to the third sub-layer SL2, and flip the content fetched from the first memory 136; at the same time, the decoder 134 also automatically The second memory 138 reads the content previously stored in FIG. 5, and performs a multiplexing operation (combination operation) together with the content retrieved from the first memory 136 and flipped to generate a complete second sub The content of layer SL1 is used for subsequent parallel operations with an order of 16, and also generates a remaining data of 64-bit content composed of the third sub-layer SL2 and the fourth sub-layer SL3, and stores it in the second memory. 138 in four different addresses. In this embodiment, the second sublayer SL1 can be regarded as a second part used to calculate the data corresponding to the first column of the codeword (including CW0-CW3) multiplied by the parity check matrix H.

Next, in FIG. 7 , the decoder 134 first retrieves the first content related to the fourth sub-layer SL3 from each part of the first memory 136 , that is, from the first memory shown in FIG. 7 . The 1st, 8th, 11th, and 16th addresses of 136 fetch the first content related to the fourth sub-layer SL3, and flip the content fetched from the first memory 136; at the same time, the decoder 134 also automatically The second memory 138 reads the content previously stored in FIG. 6, and performs a multiplexing operation (combination operation) together with the content retrieved from the first memory 136 and flipped to generate a complete third subsection The content of layer SL2 is used for subsequent parallel operations of order 16, and a residual data of 64-bit content composed entirely of the fourth sub-layer SL3 is also generated and stored in the second memory 138. Four different at the address. In this embodiment, the third sublayer SL2 can be regarded as a third part used to calculate the data corresponding to the first column of the codeword (including CW0-CW3) multiplied by the parity check matrix H.

Next, in FIG. 8 , the decoder 134 directly reads the 64-bit content completely composed of the fourth sub-layer SL3 previously stored in FIG. 7 from the second memory 138 , and performs an order of 16. parallel operation. In this embodiment, the fourth sublayer SL3 can be regarded as a fourth part used to calculate the data corresponding to the first column of the codeword (including CW0-CW3) multiplied by the parity check matrix H. The above-mentioned parallel operation is used to perform a min-sum decoding operation on these data. Since the decoding method of the quasi-cyclic low-density parity check (QC-LDPC) code performed by the decoder 134 and the related parallel operation details have been It is well known to those with ordinary knowledge in the art, so the details are not repeated here.

Through the content disclosed in the above embodiments, the decoder 134 can complete the relevant decoding operations using only parallel operations with an order of 16. Therefore, the circuit elements inside the decoder 134, such as barrel shifters ) is also simpler in design to save hardware costs. On the other hand, since each piece of data stored in the first memory 136 of this embodiment is 16 bits, the memory structure can be designed to have a deeper depth, so that the storage capacity can be kept unchanged. This saves more memory chip area.

In addition, in another embodiment of the present invention, the contents of the complete first sub-layer SL0 to the fourth sub-layer SL3 generated in FIGS. 5 to 8 can be immediately restored to the first memory 136 . Specifically, in Fig. 5, since the data of the 2nd, 5th, 12th, and 13th addresses in the first memory 136 have been fetched, the decoder 136 can convert the generated complete first sub-layer The content of SL0 is stored back to the 2nd, 5th, 12th, and 13th addresses in the first memory 136 for subsequent use; similarly, in FIG. The data of the 6th, 9th, and 14th addresses have been fetched, so the decoder 136 can store the generated content of the complete second sublayer SL0 back to the 3rd, 6th, 9th, and 14th addresses in the first memory 136 address for later use...and so on.

Summarizing the present invention briefly, in the decoding method of the present invention applied in a flash memory controller, the decoding operation can be efficiently completed by using a lower order parallel operation through the configuration of the memory, and since the The lower-order parallel operation can reduce the complexity of the internal circuit elements of the decoder, and can also save the chip area of the memory under the condition that the storage capacity remains unchanged. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Memory Device 110: Flash memory controller 112: Microprocessor 112C: Code 112M: read-only memory 114: Control logic 116: Buffer memory 118: Interface logic 120: Flash memory module 130: Main unit 132: Encoder 134: decoder 136: first memory 138:Second memory H: Parity check matrix CM0~CM3: Circular arrangement matrix CW0~CW3: codeword group SL0: first sublayer SL1: Second sublayer SL2: The third sublayer SL3: Fourth sublayer

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a codeword and a parity check matrix read from a flash memory module according to an embodiment of the present invention. FIG. 3 is a schematic diagram of each group CW0-CW3 and each sub-layer SL0-SL1 stored in the first memory according to an embodiment of the present invention. FIGS. 4 to 8 are schematic diagrams illustrating operations performed by a decoder according to an embodiment of the present invention on multiple pieces of processed data stored in the first memory.

100: Memory Device

110: Flash memory controller

112: Microprocessor

112C: Code

112M: read-only memory

114: Control logic

116: Buffer memory

118: Interface logic

120: Flash memory module

130: Main unit

132: Encoder

134: decoder

136: first memory

138:Second memory

Claims (10)

A decoding method, including: reading a codeword from a flash memory module; and use a parity check matrix to decode the codeword, wherein the parity check matrix includes a plurality of circulant permutation matrices, and the parallel operation used for decoding the codeword is of order lower than the number of columns of any cyclic permutation matrix. The decoding method as described in claim 1, wherein each layer (layer) in the parity check matrix includes N cyclic array matrices, and the step of decoding the codeword by using the parity check matrix Contains: dividing the codeword into N groups; For any one of the N groups, the M parts of the group are sequentially multiplied by the M parts of the corresponding circular arrangement matrix, respectively, to obtain M processed data; and storing the M processed data in M different addresses of a block in a memory; Among them, N and M are positive integers greater than one. The decoding method as described in claim 2, wherein the M processed data of the N groups are stored in N blocks of the memory, and the parity check matrix is used to decode the code The step of decoding the word also includes: Two pieces of processed data are read from each of the N blocks, and combined to generate a first data and a residual data, wherein the first data is used to calculate the corresponding codeword and the parity A first part of the data in the first row (row) after the multiplication of the test matrix, and the remaining data is the content after deducting the first data from the two processed data. The decoding method as described in item 3 of the scope of the application, wherein the step of using the parity check matrix to decode the codeword further comprises: Another piece of processed data is read from each of the N blocks, and combined with the remaining data to generate a second data and another remaining data, wherein the second data is used to calculate the corresponding data to the a second part of the data in the first column after the codeword is multiplied by the parity check matrix, the other remaining data is the content of the remaining data and the other processed data after deducting the second data, and the Another residual data is used for subsequent generation to calculate a third portion corresponding to the first column of data after the codeword is multiplied by the parity check matrix. The decoding method as described in item 3 of the scope of the application, wherein the step of using the parity check matrix to decode the codeword further comprises: A parallel operation is performed on the first data and decoded, wherein the order of the parallel operation is a quotient of dividing the number of columns of the circular array matrix by N. The decoding method as described in item 3 of the scope of the application, wherein the step of using the parity check matrix to decode the codeword further comprises: The first data are respectively stored back into the N blocks. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller comprises: a ROM, used to store a code; a microprocessor for executing the code to control access to the flash memory module; and a decoder; The microprocessor reads a codeword from the flash memory module, and the decoder uses a parity check matrix to decode the codeword, wherein the parity check matrix includes A plurality of circular permutation matrices are formed, and the order of parallel operations used to decode the codeword is lower than the number of columns of any circular permutation matrix. The flash memory controller as described in claim 7, wherein each layer in the parity check matrix includes N circulant matrices, and the decoder divides the codeword into N pieces group, and for any one of the N groups, sequentially multiply the M parts of the group by the M parts of the corresponding cyclic array matrix, respectively, to obtain M processed data; and the The decoder stores the M processed data into M different addresses of a block in a memory, wherein N and M are positive integers greater than one. The flash memory controller as described in claim 8, wherein the M processed data of the N groups are stored in N blocks of the memory, and the decoder extracts from the N Each block of the blocks reads two pieces of processed data, and combines them to generate a first data and a residual data, wherein the first data is used to calculate the correlation between the codeword and the parity check matrix. A first part of the multiplied first row (row) data, and the remaining data is the content after deducting the first data from the two processed data. The flash memory controller as described in claim 9, wherein the decoder reads another piece of processed data from each of the N blocks, and combines with the remaining data to generate a The second data and another residual data, wherein the second data is used to calculate a second part corresponding to the first column of data after the codeword is multiplied by the parity check matrix, and the other residual data is The remaining data and the other processed data are the contents after deducting the second data, and the other remaining data is used to calculate the first row (row corresponding to the multiplication of the codeword and the parity check matrix) ) of a third part of the information.

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