TW202015142A - Testing device and chip carrier board thereof - Google Patents

Abstract

A testing device and a chip carrier board are provided. The chip carrier board includes a chip carrier area, a plurality of edges, a plurality of first conductive pads, a plurality of second conductive pads and a plurality of first conductive wires. The chip carrier area is disposed on a first surface of the chip carrier board to carry at least one chip. Each of the first edge and the second edge has a plurality of concave areas. The first conductive pads are respectively disposed in the concave areas of the first edge. The second conductive pads are respectively disposed in the concave areas of the second edge. The fist edge is opposite to the second edge. The first conductive wires are disposed between the first conductive pads and the chip carrier area, and between the second conductive pads and the chip carrier area.

Description

Test device and its chip carrier board

The invention relates to a testing device and its wafer carrier board, and in particular to a stamp type wafer carrier board and a testing device using the wafer carrier board.

With the advancement of semiconductor technology, integrated circuits have become the most important role in electronic products. In the manufacturing process of the integrated circuit, the phenomenon that the integrated circuit cannot work normally due to defects in the manufacturing process or materials. Therefore, it is a necessary task to provide a test device that performs an integrated circuit test action.

In the conventional technical field, the integrated circuit under test can be placed on a test substrate, and an integrated circuit test operation is performed by providing a circuit carrier for testing to be connected to the test substrate. The circuit carrier board is provided with a test circuit or a controller for executing a test program, and is connected to the test substrate of the integrated circuit through a socket. This type of test device requires a higher price for the required socket. In addition, through the switching operation of the socket, the quality of the test signal transmitted between the circuit carrier and the test substrate may be reduced, or it may cause malfunctions in the test. Especially when transmitting high-frequency test signals, the reliability of test results is reduced.

The invention provides a test device and a chip carrier board, which can improve the transmission quality of the test signal.

The wafer carrier board of the present invention includes a wafer carrier region, a plurality of edges, a plurality of first conductive bonding pads, a plurality of second conductive bonding pads, and a plurality of first wires. The wafer carrying area is arranged on the first surface of the wafer carrying plate and used for carrying at least one wafer. Each of the first edge and the second edge has a plurality of concave regions. The first conductive pads are respectively disposed in the concave regions of the first edge of the edge. The second conductive pads are respectively disposed in the concave regions of the second edge of the edge, wherein the first edge is opposite to the second edge. The first wires are respectively arranged in the first conductive pad and the chip carrying section, and are arranged in the second conductive pad and the chip carrying section.

The test device of the present invention includes a test carrier board and the wafer carrier board as described above. The test carrier has a first area and a second area. The first area is used to carry at least one device under test. The wafer carrier board is detachably disposed on the second area of the test carrier board, and is used to carry at least one test control chip.

Based on the above, the wafer carrier board proposed by the present invention can be directly pasted on the test carrier board through the first conductive pad and the second conductive pad on the edge. In this way, the signal transmission between the test control chip on the wafer carrier board and the device under test on the test carrier board may be affected by the effects of parasitic elements that can be effectively reduced to improve the quality of the test signal. In the embodiment of the present invention, the wafer carrier board is detachably attached to the test carrier board. Therefore, when the test conditions of the device under test are changed, the test control chip can be changed simply by replacing the wafer carrier board, the equipment can be updated in real time, and the cost required for the update is saved.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

Please refer to FIG. 1, which is a schematic diagram of a chip carrier according to an embodiment of the invention. The wafer carrier board 100 includes a wafer carrier region 110, edges EG1~EG4, conductive pads PD~PDM, and wires W1~WM. The wafer carrying area 110 is disposed on the surface 101 of the wafer carrying plate for carrying at least one wafer. When the wafer carrier board 100 is disposed on the testing device, the wafer carrier area 110 can be used to carry a test control wafer that performs a test action. The wafer carrier board 100 also has multiple edges EG1~EG4. In this embodiment, the wafer carrier board 100 has four edges EG1~EG4. Of course, in other embodiments of the present invention, the wafer carrier board 100 may have a plurality of edges with different numbers. The shape of the wafer carrier board 100 and the number of edges are not particularly limited.

In this embodiment, the edge EG2 of the wafer carrier board 100 has multiple recessed regions, and the edge EG4 of the wafer carrier board 100 also has multiple recessed regions. In addition, the conductive pads PD1~PDN correspond to the edge EG4, in addition, the conductive pads PDN+1~PDM correspond to the edge EG2, and the conductive pads PD1~PDN are respectively disposed in a plurality of recessed areas on the edge EG4, The conductive pads PDN+1~PDM are respectively disposed in a plurality of concave regions on the edge EG2. The edge EG2 is opposite to the edge EG4.

For the implementation details of the recessed area and the bonding pad, please refer to FIG. 2A which is a schematic diagram of an embodiment of the edge of the wafer carrier board according to an embodiment of the present invention. In FIG. 2A, the edge 200 includes a plurality of concave regions CV1. The shape of the recessed area CV1 is an arc shape (semicircle) and is continuously arranged on the edge 200. In addition, the plurality of conductive pads PD disposed on the edge 200 are respectively disposed corresponding to the plurality of concave regions CV1.

Please also refer to FIG. 2B and FIG. 2C. FIG. 2B and FIG. 2C are schematic diagrams illustrating different implementations of the recessed area in different embodiments of the present invention. In the embodiment of FIG. 2B, the concave region CV2 of the edge may be square, and in the embodiment of FIG. 2C, the concave region CV3 of the edge may be triangular. Specifically, the shape of the concave area of the edge may be an arc or a polygon, and there is no specific limit.

Please refer back to FIG. 1. In the wafer carrier board 100 in FIG. 1, the opposite edges EG1 and EG3 may not have recessed areas, and no bonding pads may be disposed on the edges EG1 and EG3.

On the other hand, a plurality of wires W1~WM are disposed on the wafer carrier 100. The wires W1~WM can be arranged corresponding to the conductive pads PD1~PDM and connected between the conductive pads PD1~PDM and the chip carrying area 110. When the test control chip is carried on the chip loading area 110, the conductive pads PD1~PDM are electrically connected to the test control chip through wires W1~WM respectively, and serve as a medium for signal transmission.

Incidentally, the welding surfaces of the plurality of conductive pads PD1 to PDM on the wafer carrier board 100 can be disposed on any surface of the wafer carrier board 100. The bonding surfaces of the plurality of conductive pads PD1 to PDM may be disposed on the same surface as the wafer carrying area 110 or on opposite surfaces, without specific restrictions.

Please refer to FIG. 3 below. FIG. 3 is a schematic diagram of a chip carrier according to another embodiment of the invention. The wafer carrier board 300 includes a wafer carrier region 310, edges EG1~EG4, wires W1~WQ, and conductive pads PD11~PD1N, PD21~PD2M, PD31~PD3A, PD41~PD4B. In this embodiment, the conductive pads PD11~PD1N are arranged in the concave area of the edge EG1 of the wafer carrier board 300; the conductive pads PD21~PD2M are arranged in the concave area of the edge EG2 of the wafer carrier board 300; The pads PD31~PD3A are disposed in the concave region of the edge EG3 of the wafer carrier board 300; and the conductive pads PD41~PD4B are disposed in the concave region of the edge EG4 of the wafer carrier board 300.

The wafer carrier board 300 has wires W1~WQ. The wires W1~WQ are respectively connected to the conductive pads PD11~PD4B, and connected to the chip carrying area 310. Through the wires W1~WQ, the test control chip on the chip carrier 300 can perform signal transmission through the conductive pads PD11~PD4B and the device under test in the chip carrier area.

In this embodiment, the device under test may be a flash memory chip or another flash memory control chip. Among them, the conductive pads PD11~PD1N and the conductive pads PD21~PD2M can be electrically coupled to the device under test, the conductive pads PD31~PD3A can be used to receive multiple power supply voltages, and the conductive pads PD41~PD4B can be used to couple Connected to a communication interface. The above communication interface may be a Universal Serial Bus (USB) interface or other standard bus interfaces, such as a standard flash memory interface (including single data rate (SDR), switchable) Toggle Double Data Rate (Toggle DDR) and Open NAND Flash Interface (ONFI) DDR and other previous standards). The communication interface may also be a wireless transceiver communication interface.

By providing a plurality of concave regions on the edges EG1~EG4 of the wafer carrier 300, and a plurality of conductive pads PD11~PD4B are respectively disposed in the concave regions. The edges EG1 to EG4 of the wafer carrier 300 may be formed with a plurality of saw-tooth edges as stamps have. The wafer carrier board 300 of the present invention may also be referred to as a stamp type wafer carrier board.

Please refer to FIG. 4A below. FIG. 4A is a schematic diagram of a testing device according to an embodiment of the invention. The test device 400 includes a wafer carrier board 420 and a test carrier board 410. The implementation of the wafer carrier board 420 has been described in detail in the foregoing examples and implementations, and will not be repeated here.

The test carrier 410 has a first zone Z1 and a second zone Z2. The first zone Z1 is used to carry the devices under test DUT1~DUT4. The second zone Z2 is used to carry the wafer carrier board 420. In this embodiment, the wafer carrier board 420 can carry the test control chip CIC1, and is detachably disposed on the second zone Z2 of the test carrier board 410. To further explain, a plurality of conductive pads ZPD can be disposed on the second zone Z2 of the test carrier 410. The conductive pads ZPD on the second zone Z2 of the test carrier 410 may correspond to the plurality of conductive pads PD on the wafer carrier 420 in number and position. In this way, by attaching (welding) the conductive pad ZPD and the conductive pad PD to each other one by one, the chip carrier 420 can be disposed on the test carrier 410.

By sticking the chip carrier 420 directly to the test carrier 410, the interference between the test control chip CIC1 and the devices under test DUT1~DUT4 due to parasitic elements can be effectively reduced. The signal transmission quality between the test control chip CIC1 and the devices under test DUT1~DUT4 can be improved (especially with regard to high-speed transmission signals), and the reliability of the generated test results can also be improved.

In contrast, when the wafer carrier board 420 is to be detached from the test carrier board 410, a de-soldering operation can be performed between the conductive pad ZPD and the conductive pad PD to complete the disassembly of the wafer carrier board 420.

In this embodiment, a plurality of sockets SC1 to SC4 are provided in the first zone Z1 of the test carrier 410. The devices under test DUT1 to DUT4 are respectively disposed on the test carrier 410 through the sockets SC1 to SC4. Of course, not all sockets SC1~SC4 need to be configured with devices under test DUT1~DUT4. The tester can select some or all of the required sockets SC1~SC4 to configure a sufficient number of devices under test. In addition, FIG. 4A shows that providing four sockets SC1 to SC4 in the first zone Z1 of the test carrier 410 is only an illustrative example. The number of sockets provided in the first zone Z1 of the test carrier 410 can be At the discretion of the designer, there are no specific restrictions.

On the other hand, the conductive pad ZPD can be connected to the sockets SC1~SC4 through a plurality of wires (not shown), and allows the test control chip CIC1 to perform signal transmission between the devices under test DUT1~DUT4, and thereby Perform test actions for the devices under test DUT1~DUT4. In addition, in the embodiment of the present invention, the test carrier 410 may be further configured with a transmission interface connector CN, and is connected to an external electronic device through the transmission interface connector CN. For example, the transmission interface connector CN may be a universal serial bus (USB) connector or other standard bus or a wireless transceiver device. The test device 400 can be connected to a computer, mobile phone, or various external electronic devices through the transmission interface connector CN. In this way, in the embodiment of the present invention, the external electronic device can obtain the test results of the devices under test DUT1 to DUT4 through the transmission interface connector CN. In another embodiment of the present invention, the external electronic device can also transmit a new test program and/or test command to the test control chip CIC1 through the transmission interface connector CN, and adjust the test actions performed by the test control chip CIC1.

In this embodiment, the first zone Z1 and the second zone Z2 of the test carrier 410 may be planned on the same surface of the test carrier 410.

Please refer to FIG. 4B below. FIG. 4B is a schematic diagram of a testing device according to another embodiment of the present invention. In FIG. 4B, the test device 400 includes a test carrier 410 and wafer carriers 451-454 and 461-464. The chip carrier boards 451~454 are used to carry the control test control chips CIC1~CIC4 respectively, and the chip carrier boards 461~464 are used to carry the device under test DUT1~DUT4, respectively. The wafer carrier boards 451-454 are directly pasted (welded) on the plurality of second zones Z11-Z14 of the test carrier board 410, respectively, and the wafer carrier boards 461-464 are directly pasted (welded) on the first part of the test carrier board 410, respectively. In multiple zones of zone Z1. The chip carrier boards 451-454 and 461-464 can be implemented by applying the structure of the chip carrier board mentioned in the previous embodiments, and improve the signal transmission quality between the devices under test DUT1~DUT4 and the control test control chips CIC1~CIC4. In this embodiment, the control test control chips CIC1~CIC4 can correspond to the devices under test DUT1~DUT4, respectively. Control Test The control chips CIC1~CIC4 can perform test actions for the devices under test DUT1~DUT4, respectively.

Please refer to FIG. 5 below. FIG. 5 is a schematic diagram of another embodiment of the testing device according to the embodiment of the present invention. In the test apparatus 500, the first area and the second area of the test carrier 510 may be respectively planned on the first surface SF1 and the second surface SF2 of the test carrier 510, wherein the first surface SF1 and the second surface SF2 For the two opposite surfaces. The socket SC of the integrated circuit is provided on the first surface SF1 of the test carrier 510, and the device under test DUT is carried through the socket SC. The second surface SF2 of the test carrier 510 is directly adhered to the stamp-shaped wafer carrier 520, and the test control chip CIC is carried on the wafer carrier 520.

In this embodiment, the first area and the second area of the test carrier 510 may completely overlap, partially overlap, or not overlap at all.

In summary, the present invention proposes a stamp-type wafer carrier board, and directly sticks the wafer carrier board to the test carrier board. In this way, the signal transmission quality between the test control chip on the wafer carrier board and the device under test on the test carrier board can be improved to ensure the correct test results. In addition, the wafer carrier board is a detachable design, corresponding to different types of devices under test. The chip carrier board can be removed and replaced. The appropriate test control chip can be set to perform test actions against the device under test, increasing the number of test devices. Adjustability and reduce the required test procedures.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100, 300, 420, 520, 451~454, 461~464: wafer carrier 101: surface 110: wafer carrier 400, 500: test device 410, 510: test carrier EG1~EG4, 200: edge PD1~PDM , PD, PD11~PD4B, ZPD: conductive pads W1~WM, WQ: wire CV1, CV2, CV3: recessed zone Z1: first zone Z2, Z11~Z14: second zone DUT1~DUT4, DUT: tested Device CIC1~CIC4: test control chip SC1~SC4, SC: socket CN: transmission interface connector SF1: first surface SF2: second surface

FIG. 1 is a schematic diagram of a wafer carrier board according to an embodiment of the invention. FIG. 2A is a schematic diagram of an embodiment of an edge of a wafer carrier according to an embodiment of the invention. 2B and 2C are schematic diagrams illustrating different implementations of the recessed area in different embodiments of the present invention. FIG. 3 is a schematic diagram of a wafer carrier board according to another embodiment of the invention. 4A is a schematic diagram of a testing device according to an embodiment of the invention. 4B is a schematic diagram of a testing device according to another embodiment of the invention. FIG. 5 is a schematic diagram of another embodiment of the test device according to the embodiment of the invention.

100: wafer carrier board

101: surface

110: wafer carrier area

EG1~EG4: edge

PD1~PDM: conductive pad

W1~WM: wire

Claims (13)

A wafer carrier board includes: a wafer carrier region, which is disposed on a first surface of the wafer carrier board and is used to carry at least one wafer; a plurality of edges, a first edge and a second edge of the edges Having a plurality of recessed regions; a plurality of first conductive pads respectively arranged in the recessed regions of the first edge; a plurality of second conductive pads respectively arranged in the recesses of the second edge In the area, wherein the first edge is opposite to the second edge; and a plurality of first wires are respectively disposed in the first conductive pads and the chip bearing section, and in the second conductive pads and the Wafer loading interval. The wafer carrier board as described in item 1 of the scope of the patent application further includes: a plurality of third conductive pads, which are respectively disposed in a plurality of concave areas of at least one third edge of the edges; a plurality of fourth conductive The pads are respectively disposed in a plurality of concave regions of at least one fourth edge of the edges, wherein the at least one third edge is opposite to the at least one fourth edge; and a plurality of second wires are respectively disposed on the edges The third conductive pads and the chip carrying section, and the fourth conductive pads and the chip carrying section. The chip carrier board as described in item 1 of the patent application range, wherein the at least one chip is a test control chip, the first conductive pads are used to electrically couple to a device under test, and the second conductive pads The pads are used to receive the device under test, the third conductive pads are used to couple to multiple power supply voltages, and the fourth conductive pads are used to couple to a communication interface. The chip carrier board as described in item 3 of the patent application scope, wherein the device under test is a flash memory chip or another flash memory control chip, and the communication interface is a universal serial bus interface, other standard bus interfaces Or wireless transceiver interface. The wafer carrier board as described in item 1 of the patent application scope, wherein each of the concave regions is arc-shaped or polygonal. A test device includes: a test carrier board having a first zone and a second zone, the first zone is used to carry at least one device under test; and at least a first chip carrier board, which is detachably arranged at On the second area of the test carrier board, the at least one first wafer carrier board includes: a chip carrier region disposed on a first surface of the wafer carrier board for carrying at least one test control chip; a plurality of Edges, a first edge and a second edge of the edges each have a plurality of recessed regions; a plurality of first conductive pads are respectively disposed in the recessed regions of the first edge; a plurality of second regions Conductive pads are respectively disposed in the concave regions of the second edge, wherein the first edge is opposite to the second edge; and a plurality of first wires are respectively disposed on the first conductive pads and the A chip-carrying section and the second conductive pads and the chip-carrying section, wherein the at least one test control chip passes through the first conductive pads and the second conductive pads to electrically It is coupled to the at least one device under test. The test device as described in item 6 of the patent application scope, wherein the at least one first wafer carrier board further comprises: a plurality of third conductive pads, respectively disposed on a plurality of recesses of at least one third edge of the edges In the area; a plurality of fourth conductive pads are respectively disposed in a plurality of recessed areas of at least one fourth edge of the edges, wherein the at least one third edge is opposed to the at least one fourth edge; and The two wires are respectively arranged in the third conductive pads and the chip carrying section, and are arranged in the fourth conductive pads and the chip carrying section. The test device as described in item 7 of the patent application range, wherein the first conductive pads are electrically coupled to a device under test, and the second conductive pads are coupled to the device under test, the The third conductive pads are used to receive multiple power supply voltages, and the fourth conductive pads are coupled to a communication interface. The test device according to item 8 of the patent application scope, wherein the at least one device under test is a flash memory chip, and the communication interface is a universal serial bus interface. The test device according to item 6 of the patent application scope, wherein the second area of the test carrier has a plurality of third conductive pads and a plurality of fourth conductive pads, the third conductive pads are respectively The first conductive pads are opposite, and the fourth conductive pads are respectively opposite to the second conductive pads. The test device as described in item 6 of the patent application scope further includes: at least one second wafer carrier board, disposed in the first area of the test carrier board, for supporting the at least one device under test. The test device as described in item 6 of the patent application scope further includes: at least one chip socket, which is arranged in the first area of the test carrier and is used to carry the at least one device under test. The test device according to item 6 of the patent application scope, wherein the first area and the second area of the test carrier are disposed on the same surface of the test carrier, or the first area of the test carrier The second area and the second area are respectively disposed on two opposite surfaces of the test carrier.

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