TW202012699A - Film forming device and film forming method - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000002994 raw material Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 description 33
- 238000010586 diagram Methods 0.000 description 18
- 239000004065 semiconductor Substances 0.000 description 15
- 230000000052 comparative effect Effects 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 239000003507 refrigerant Substances 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
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- 238000002474 experimental method Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
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- 230000007423 decrease Effects 0.000 description 3
- 238000010494 dissociation reaction Methods 0.000 description 3
- 230000005593 dissociations Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000498 cooling water Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
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Abstract
Description
本揭示關於成膜裝置及成膜方法。The present disclosure relates to a film forming apparatus and a film forming method.
半導體集積電路之製造中,藉由成膜裝置對半導體晶圓等之基板進行成膜。成膜裝置中,基板被配置於設定為規定之真空度的腔室(處理容器)內,對腔室內供給成膜原料氣體而生成電漿,據此,對基板進行成膜。作為成膜技術習知有例如電漿CVD(Chemical Vapor Deposition)、電漿ALD(Atomic Layer Deposition)等。 [先前技術文獻] [專利文獻]In the manufacture of a semiconductor integrated circuit, a film is formed on a substrate such as a semiconductor wafer by a film forming device. In the film forming apparatus, the substrate is arranged in a chamber (processing container) set to a predetermined vacuum degree, and a film-forming raw material gas is supplied into the chamber to generate a plasma, thereby forming a film on the substrate. As a film forming technique, for example, plasma CVD (Chemical Vapor Deposition), plasma ALD (Atomic Layer Deposition), etc. are known. [Prior Technical Literature] [Patent Literature]
[專利文獻1]特開2009-239012號公報[Patent Literature 1] JP 2009-239012
[發明所欲解決的課題][Problems to be solved by the invention]
如電漿CVD或電漿ALD這樣在數百mTorr~數Torr之高壓條件下,需要產生能夠獲得高電子密度化的電漿。相對於此,氧化膜成膜製程中,為了高電子密度化而需要數MHz以下之低頻,另一方面,為了低離子能量化而需要數十MHz以上之高頻。但是,氮化膜成膜製程中,為了高電子密度化而需要數百MHz以上之高頻,另一方面,為了高均勻性而需要數十MHz以下之低頻。Under high-pressure conditions of hundreds of mTorr to several Torr, such as plasma CVD or plasma ALD, it is necessary to generate a plasma capable of obtaining a high electron density. On the other hand, in the oxide film forming process, a low frequency of several MHz or less is required to increase the electron density, and a high frequency of several tens of MHz or more is required to reduce the ion energy. However, in the process of forming a nitride film, a high frequency of several hundred MHz or more is required for increasing electron density, while a low frequency of several tens of MHz or less is required for high uniformity.
因此,習知之成膜裝置中,同時達成高電子密度化、低離子能量化及高均勻性是困難的。因此,期待著不論對那一種成膜製程,能夠同時達成高電子密度化、低離子能量化及高均勻性的成膜裝置。Therefore, in the conventional film-forming apparatus, it is difficult to achieve high electron density, low ion energy, and high uniformity at the same time. Therefore, no matter what kind of film forming process, it is expected that a film forming apparatus that can achieve high electron density, low ion energy, and high uniformity can be achieved at the same time.
本揭示提供能夠同時達成高電子密度化、低離子能量化及高均勻性的技術。 [解決課題的手段]The present disclosure provides techniques that can simultaneously achieve high electron density, low ion energy, and high uniformity. [Means to solve the problem]
本揭示之一態樣之成膜裝置具有:可以真空排氣的處理容器;下部電極;上部電極;氣體供給部;及電壓施加部。於下部電極載置有被處理基板。上部電極,係在處理容器內與下部電極呈對向配置。氣體供給部,係將在上部電極與下部電極之間之處理空間電漿化的成膜原料氣體供給至處理空間。電壓施加部,係將基準電位伴隨時間之經過而上下交替變化的交流電壓施加於上部電極。 [發明效果]A film forming apparatus according to one aspect of the present disclosure includes: a processing container that can be vacuum-evacuated; a lower electrode; an upper electrode; a gas supply unit; and a voltage application unit. The substrate to be processed is placed on the lower electrode. The upper electrode is arranged to face the lower electrode in the processing container. The gas supply unit supplies the film-forming raw material gas plasmatized in the processing space between the upper electrode and the lower electrode to the processing space. The voltage applying unit applies an alternating voltage whose reference potential alternates up and down with the passage of time to the upper electrode. [Effect of the invention]
依據本揭示的技術,能夠同時達成高電子密度化、低離子能量化及高均勻性。According to the disclosed technology, high electron density, low ion energy, and high uniformity can be achieved at the same time.
以下參照圖面說明本揭示的技術之實施形態。The embodiments of the disclosed technology will be described below with reference to the drawings.
<成膜裝置之構成> 圖1係表示實施形態的成膜裝置之構成例之圖。<Structure of film forming device> FIG. 1 is a diagram showing a configuration example of a film forming apparatus of an embodiment.
圖1中,成膜裝置1具有例如由鋁或不鏽鋼等形成的金屬製之處理容器亦即腔室10。腔室10安全接地。In FIG. 1, the
在腔室10內以水平方式配置有圓盤狀之承受器12,該承受器12供作為載置作為被處理基板之半導體晶圓W。承受器12亦作為下部電極之功能。於腔室10之側壁安裝有對半導體晶圓W之搬出入口進行開關的閘閥28。承受器12例如由AlN陶瓷形成,被從腔室10之底部向垂直上方延伸之絕緣性之筒狀支撐部14支撐。In the
沿著筒狀支撐部14之外周在從腔室10之底部向垂直上方延伸之導電性之筒狀支撐部(內壁部)16與腔室10之側壁之間形成有環狀之排氣路18。於排氣路18之底部設置有排氣口22。An annular exhaust path is formed along the outer circumference of the
於排氣口22透過排氣管24與排氣裝置26連接。排氣裝置26例如具有渦輪分子泵等之真空泵,將腔室10內之處理空間減壓至期待之真空度。腔室10內例如保持於200mTorr~1700mTorr之範圍之一定之壓力為較佳。The
在作為下部電極使用的承受器12與接地之間,經由連接棒36電連接有具有線圈101與可變電容器102的阻抗調整電路100。Between the
於承受器12之上載置有處理對象之半導體晶圓W,以圍繞半導體晶圓W的方式設置有環部38。環部38係由導電材(例如Ni、Al等)形成,可以裝拆地安裝於承受器12之上面。The semiconductor wafer W to be processed is placed on the
於承受器12之上面設置有晶圓吸附用之靜電吸盤40。靜電吸盤40,係在膜狀或板狀之介電質之間夾持薄片狀或網孔狀之導電體而形成。於靜電吸盤40內之導電體,經由開啟/斷開切換開關44及供電線46電連接有配置於腔室10之外部的直流電源42。藉由直流電源42所施加的直流電壓並藉由靜電吸盤40產生的庫侖力,使半導體晶圓W被吸附保持於靜電吸盤40上。An
於承受器12之內部設置有向圓周方向延伸之環狀之冷媒室48。於冷媒室48,從冷卻器單元(未圖示)經由配管50、52將規定溫度之冷媒(例如冷卻水)進行循環供給。藉由冷媒之溫度對靜電吸盤40上之半導體晶圓W之溫度進行控制。另外,為了進一步提高晶圓溫度之精度,因此使來自導熱氣體供給部(未圖示)之導熱氣體(例如He氣體),透過氣體供給管51及承受器12內之氣體通路56供給至靜電吸盤40與半導體晶圓W之間。An
於腔室10之天井,與承受器12平行相對(亦即對置),且以同心狀設置有圓盤狀之內側上部電極60及環狀之外側上部電極62。作為徑向之較佳的尺寸,內側上部電極60具有和半導體晶圓W相同程度之口徑(直徑),外側上部電極62具有和環部38相同程度之口徑(內徑・外徑)。但是,內側上部電極60與外側上部電極62相互被電氣(更正確為DC(直流))絕緣。在兩電極60、62之間例如插入有由陶瓷形成的環狀之絕緣體63。The patio of the
內側上部電極60具有:與承受器12真正面對面的電極板64;及對電極板64從其背後(上方)以可以裝拆地進行支撐的電極支撐體66。作為電極板64之材質以Ni或Al等之導電材為較佳。電極支撐體66例如由已陽極氧化處理的鋁構成。外側上部電極62亦具有:與承受器12對向的電極板68;及將電極板68從其背後(上方)以可以裝拆地進行支撐的電極支撐體70。電極板68及電極支撐體70較好是分別與電極板64及電極支撐體66由相同材質構成。以下有時將內側上部電極60與外側上部電極62總稱為「上部電極60、62」。如此般,於成膜裝置1中,圓盤狀之承受器12(亦即下部電極),與圓盤狀之上部電極60、62相互平行對置。The inner
又,本實施形態中舉出,上部電極60、62由內側上部電極60與外側上部電極62之2個構件構成之情況之一例。但是,上部電極由1個構件構成亦可。In this embodiment, an example is given in which the
為了對上部電極60、62與承受器12之間所設定的處理空間PS供給成膜原料氣體,因此內側上部電極60亦兼用作為噴淋頭。更詳細言之,在電極支撐體66之內部設置氣體擴散室72,使從氣體擴散室72貫穿承受器12側的多個氣體吐出孔74被形成於電極支撐體66及電極板64。在設置於氣體擴散室72之上部的氣體導入口72a,連接著從原料氣體供給部76延伸的氣體供給管78。又,不僅在內側上部電極60,在外側上部電極62亦設置噴淋頭之構成亦可。In order to supply the film forming raw material gas to the processing space PS set between the
於腔室10之外部配置有輸出施加電壓的電壓施加部5。電壓施加部5經由供電線88與上部電極60、62連接。電壓施加部5具有:高頻電源30;匹配單元34;可變直流電源80;脈衝產生器84;過濾器86;重疊器91;及開啟/斷開切換開關92。A
高頻電源30,係產生有助於電漿之生成的高頻率之交流電壓(以下有時稱為「高頻電壓」),並將產生的高頻電壓經由匹配單元34及開啟/斷開切換開關92供給至重疊器91。開啟/斷開切換開關92成為開啟時,高頻電壓被供給至重疊器91,另一方面,開啟/斷開切換開關92成為斷開時,高頻電壓未被供給至重疊器91。高頻電源30所產生的高頻電壓之頻率例如為13MHz以上為較佳。The high-
圖2係表示實施形態的高頻電壓之一例之圖。如圖2所示,高頻電源30例如產生以0V為基準電位RP的-250V~250V之高頻電壓V1。匹配單元34取得高頻電源30側之阻抗與負載(主要為電極、電漿、腔室)側之阻抗之間之匹配。Fig. 2 is a diagram showing an example of a high-frequency voltage according to an embodiment. As shown in FIG. 2, the high-
可變直流電源80之輸出端子連接於脈衝產生器84,可變直流電源80將負之直流電壓(亦即負之DC電壓)輸出至脈衝產生器84。脈衝產生器84使用從可變直流電源80輸入的負之直流電壓,產生矩形波之直流脈衝電壓(亦即DC脈衝電壓),將產生的直流脈衝電壓經由過濾器86供給至重疊器91。脈衝產生器84產生的直流脈衝電壓之頻率例如為10kHz~1MHz為較佳。又,脈衝產生器84產生的直流脈衝電壓之工作比以10%~90%為較佳。The output terminal of the variable
圖3係表示實施形態的直流脈衝電壓之一例之圖。如圖3所示,脈衝產生器84產生例如-500V~0V之矩形波之直流脈衝電壓V2。過濾器86構成為,使脈衝產生器84所輸出的直流脈衝電壓通過並輸出至重疊器91,另一方面,使高頻電源30所輸出的高頻電壓流入接地線而不流入脈衝產生器84側。Fig. 3 is a diagram showing an example of a DC pulse voltage according to the embodiment. As shown in FIG. 3, the pulse generator 84 generates a square-wave DC pulse voltage V2 of, for example, -500V to 0V. The
重疊器91,藉由使高頻電源30所輸出的高頻電壓與脈衝產生器84所輸出的直流脈衝電壓重疊,而產生重疊了高頻電壓與直流脈衝電壓的電壓(以下有時稱為「重疊電壓」)。產生的重疊電壓係經由供電線88施加於上部電極60、62。重疊器91為電壓重疊部之一例。The overlapping
圖4係表示實施形態的重疊電壓之一例之圖。圖2所示高頻電壓V1與圖3所示直流脈衝電壓V2被重疊了之情況下,產生圖4所示重疊電壓V3。藉由在高頻電壓重疊直流脈衝電壓,如圖4所示,於重疊電壓V3中,配合矩形波之直流脈衝電壓V2(參照圖3)之波形,使高頻電壓V1(參照圖2)之基準電位RP伴隨著時間之經過而上下交替變化。亦即電壓施加部5,在開啟/斷開切換開關92成為開啟之情況下,係將以脈衝狀(亦即矩形波狀)變化的高頻電壓輸出。4 is a diagram showing an example of the superimposed voltage in the embodiment. When the high-frequency voltage V1 shown in FIG. 2 and the DC pulse voltage V2 shown in FIG. 3 are superimposed, the superimposed voltage V3 shown in FIG. 4 is generated. By superimposing the DC pulse voltage on the high-frequency voltage, as shown in FIG. 4, the superimposed voltage V3 is matched with the waveform of the square-wave DC pulse voltage V2 (see FIG. 3) to make the high-frequency voltage V1 (see FIG. 2) The reference potential RP alternates up and down with the passage of time. That is, when the on/off
又,開啟/斷開切換開關92成為開啟時,匹配單元34輸出的高頻電壓係被供給至重疊器91,因此從重疊器91輸出重疊電壓。另一方面,開啟/斷開切換開關92成為斷開時,匹配單元34輸出的高頻電壓未被供給至重疊器91,因此過濾器86輸出的直流脈衝電壓直接從重疊器91輸出。In addition, when the on/off
又,在腔室10內在面對處理空間PS的適當的部位(例如外側上部電極62之半徑方向外側)安裝例如由Ni、Al等之導電性構件形成的環狀之接地部件96。接地部件96例如安裝於由陶瓷形成的環狀之絕緣體98,並且連接於腔室10之天井壁,經由腔室10被接地。電漿處理中從電壓施加部5對上部電極60、62施加重疊電壓時,電子電流透過電漿而在上部電極60、62與接地部件96之間流動。In addition, a ring-shaped
成膜裝置1內之各構成(例如排氣裝置26、高頻電源30、開啟/斷開切換開關44、92、原料氣體供給部76、冷卻器單元(未圖示)、導熱氣體供給部(未圖示)等)之各個之動作及成膜裝置1整體之動作(序列),例如係藉由微電腦形成的控制部(未圖示)進行控制。The components in the film forming apparatus 1 (for example, the
<成膜裝置之成膜處理>
成膜裝置1中,進行成膜時,首先將閘閥28設為開啟狀態將加工對象之半導體晶圓W搬入腔室10內,載置於靜電吸盤40之上。接著,將開啟/斷開切換開關44設為開啟,藉由靜電吸附力使半導體晶圓W吸附保持於靜電吸盤40上。接著,從原料氣體供給部76將成膜原料氣體按規定之流量導入腔室10內,藉由排氣裝置26將腔室10內之壓力調節為設定值。作為成膜原料氣體例如可以使用Ar/O2
氣體等之負性氣體或N2
氣體。另外,將高頻電源30及可變直流電源80設為開啟,將重疊電壓施加於上部電極60、62。又,對靜電吸盤40與半導體晶圓W之間供給導熱氣體。從上部電極60吐出的成膜原料氣體,係藉由在上部電極60、62與作為下部電極使用的承受器12之間之放電被電漿化,藉由該電漿所生成的自由基或離子在半導體晶圓W表面生成被膜。<Film Forming Process of Film Forming Apparatus> In the
<比較例之實驗結果(成膜原料氣體:Ar/O2
)>
圖5及圖6係表示比較例中的實驗結果之一例之圖。於圖5,作為比較例中的實驗結果而表示的,並非對上部電極60、62施加重疊電壓,而是對上部電極60、62僅施加450kHz、2MHz、13MHz或40MHz之頻率之交流電壓之情況下的壓力與電子密度之關係。於圖6,作為比較例中的實驗結果而表示的,並非對上部電極60、62施加重疊電壓,而是將腔室10內之壓力設為500mTorr之狀態下,對上部電極60、62僅施加450kHz之頻率之交流電壓之情況下之離子能量與離子能量分布(IED:Ion Energy Distribution)之關係。<Experimental results of comparative example (film forming raw material gas: Ar/O 2 )> FIGS. 5 and 6 are diagrams showing an example of experimental results in comparative examples. As shown in FIG. 5 as an experimental result in a comparative example, instead of applying an overlapping voltage to the
僅頻率為450kHz之低頻之交流電壓被施加於上部電極60、62之情況下,如圖5所示,包含O2
的負性氣體電漿中之電子密度亦高,特別是在腔室10內之壓力為0.7Torr附近,可以獲得為了成膜之充分的電子密度。另一方面,如圖6所示,交流電壓之功率為1000W之情況下,離子能量變高,帶給產生的膜的損傷亦變大。又,即使在將交流電壓之功率設為1000W之狀態下提高壓力時亦無法期待離子能量之大幅降低。相對於此,如圖6所示,藉由將交流電壓之功率設為300W、150W等之低功率化可以達成低離子能量化,但因為低功率化降低電子密度而使成膜速率降低。When only a low-frequency AC voltage with a frequency of 450 kHz is applied to the
又,如圖5所示,若為了降低離子能量而使交流電壓之頻率設為2MHz、13MHz、40MHz等之高頻化時,電子溫度降低,因此電子附著於自由基而作成負離子致使電子密度降低。又,如圖5所示,為了降低離子能量而高壓化時,電子溫度降低,因此和高頻化同樣地,負離子被作成導致電子密度降低。Also, as shown in FIG. 5, if the frequency of the AC voltage is set to a high frequency of 2MHz, 13MHz, 40MHz, etc. in order to reduce the ion energy, the temperature of electrons decreases, so the electrons adhere to radicals and create negative ions to reduce the electron density. . In addition, as shown in FIG. 5, when the pressure is increased in order to reduce the ion energy, the electron temperature decreases. Therefore, as in the case of high frequency, negative ions are made to reduce the electron density.
如此般,對上部電極60、62僅施加交流電壓時,難以達成兼顧高電子密度化與低離子能量化。In this way, when only an alternating voltage is applied to the
<實施形態之實驗結果1(成膜原料氣體:Ar/O2
)>
圖7係表示實施形態的實驗結果1之一例之圖。於圖7,作為實施形態的實驗結果1所表示者,並非對上部電極60、62施加重疊電壓,而是將腔室10內之壓力設為500mTorr之狀態下,對上部電極60、62僅施加500kHz之頻率之直流脈衝電壓之情況下之離子能量與離子能量分布之關係。亦即實驗結果1係將圖1所示開啟/斷開切換開關92設為斷開之情況下之實驗結果。<Experiment
僅頻率為500kHz之低頻之直流脈衝電壓被施加於上部電極60、62之情況下,如圖7所示,不受直流脈衝電壓之功率影響,離子能量和圖6之情況比較變為非常低。又,如圖7所示,藉由提高直流脈衝電壓之功率,可以維持低離子能量之狀態下,僅提高電子密度。When only a low-frequency DC pulse voltage with a frequency of 500 kHz is applied to the
如此般,藉由對上部電極60、62僅施加直流脈衝電壓,可以達成兼顧為了高成膜速率之高電子密度化以及為了低損傷之低離子能量化。In this way, by applying only a DC pulse voltage to the
<實施形態之實驗結果2(成膜原料氣體:Ar/O2
)>
圖8及圖9係表示實施形態的實驗結果2之一例之圖。於圖8,作為實施形態的實驗結果2,係表示在將腔室10內之壓力設為500mTorr之狀態下,對上部電極60、62施加重疊電壓之情況下之離子能量與離子能量分布之關係。圖8中,直流脈衝電壓之頻率為500kHz,直流脈衝電壓之功率為300W,交流電壓之頻率為40.68MHz,交流電壓之功率為200W或500W。又,於圖9作為實施形態的實驗結果2係表示,對上部電極60、62施加重疊電壓之情況下之壓力與電子密度之關係。圖9中,直流脈衝電壓之頻率為500kHz,直流脈衝電壓之功率為300W。又,圖9中,450kHz、2MHz、13MHz及40MHz之描繪係和圖5相同,40MHz+DC之描繪為施加有重疊電壓之情況下者。<Experiment result 2 of the embodiment (film forming raw material gas: Ar/O 2 )> FIGS. 8 and 9 are diagrams showing an example of the experiment result 2 of the embodiment. In FIG. 8, as the experimental result 2 of the embodiment, the relationship between the ion energy and the ion energy distribution when the overlapping voltage is applied to the
依據上述實驗結果1,如圖7所示,即使變化直流脈衝電壓之功率,離子能量亦幾乎無變化。According to the above
相對於此,實驗結果2中,如圖8所示,藉由變化成為重疊電壓之基礎的交流電壓之功率,可以將電子密度維持於和圖7之情況同等之狀態下,變化離子能量。On the other hand, in the experimental result 2, as shown in FIG. 8, by changing the power of the AC voltage that becomes the basis of the superimposed voltage, the electron density can be maintained in the same state as in the case of FIG. 7, and the ion energy can be changed.
如此般,對上部電極60、62施加重疊電壓之情況下,和對上部電極60、62僅施加直流脈衝電壓之情況下比較,可以分別獨立進行基於直流脈衝電壓的電子密度之控制以及基於交流電壓的離子能量之控制。亦即藉由對上部電極60、62施加重疊電壓,可以達成兼顧高電子密度化與低離子能量化,且可以獨立進行電子密度之控制與離子能量之控制。In this way, when the superimposed voltage is applied to the
又,如圖9所示,對上部電極60、62施加重疊電壓之情況下,特別是在腔室10內之壓力為0.7Torr附近,和圖5同樣地,可以獲得成膜之充分的電子密度。Furthermore, as shown in FIG. 9, when the superimposed voltage is applied to the
<實施形態之實驗結果3(成膜原料氣體:N2
)>
圖10係表示實施形態的實驗結果3之一例之圖。於圖10作為實施形態的實驗結果3所表示者,係在將腔室10內之壓力設為500mTorr之狀態下,對上部電極60、62施加重疊電壓之情況下之波長與發光強度之關係。<Experimental result 3 of the embodiment (film forming raw material gas: N 2 )> FIG. 10 is a diagram showing an example of the experimental result 3 of the embodiment. As shown in FIG. 10 as the experimental result 3 of the embodiment, the relationship between the wavelength and the luminous intensity when the superimposed voltage is applied to the
僅將交流電壓施加於上部電極60、62來產生N2
電漿時,氮化力弱,良好膜質之氮化膜之成膜變為困難。一般,交流電壓之頻率越高氮化膜之品質越好,因此藉由μ波電漿成膜的膜成為最良質之膜。μ波電漿為在上部電極60、62之正下方電子溫度成為非常高,成為向承受器12(亦即下部電極)擴散的電漿。When only an alternating voltage is applied to the
藉由將直流脈衝電壓施加於上部電極60、62,和μ波電漿同樣地可以將上部電極60、62之正下方之電子溫度維持於非常高,因此可以產生和μ波電漿同樣之電漿。N2
之解離需要高能量之電子,藉由僅將直流脈衝電壓或重疊電壓施加於上部電極60、62,則如圖10所示,可以高效率地使N2
解離。圖10中顯示,藉由直流脈衝電壓之施加促進N2
之解離之進展,N2
之發光強度減少,另一方面,N自由基之發光強度增加。By applying a direct current pulse voltage to the
另外,越是高頻波長越短,因此波長效應使電漿分布之均勻性惡化。相對於此,習知的技術中,難以兼顧N2 之高解離度與電漿均勻性,因此需要加大上部電極與下部電極之間隔,或對上部電極之形狀採取對策。相對於此,平板狀之上部電極與圓盤狀之下部電極相互平行呈對置之情況下,藉由直流脈衝電壓之施加使電漿均勻性成為良好。因此,藉由僅直流脈衝電壓之施加、或重疊電壓之施加,可以兼顧N2 之高解離度與電漿均勻性,並且可以縮小上部電極與下部電極之間隔。因此,本揭示的技術可以適用於氣體之置換時間對製程之生產能力帶來大影響的PEALD(Plasma Enhanced Atomic Layer Deposition)這樣的製程。In addition, the higher the high frequency, the shorter the wavelength, so the wavelength effect deteriorates the uniformity of the plasma distribution. In contrast, in the conventional technology, it is difficult to reconcile the high dissociation degree of N 2 and the plasma uniformity. Therefore, it is necessary to increase the distance between the upper electrode and the lower electrode or take measures for the shape of the upper electrode. On the other hand, when the plate-shaped upper electrode and the disc-shaped lower electrode are parallel to each other and face each other, the uniformity of the plasma becomes good by the application of the DC pulse voltage. Therefore, by applying only the DC pulse voltage or the overlapping voltage, the high dissociation degree of N 2 and the plasma uniformity can be taken into consideration, and the distance between the upper electrode and the lower electrode can be reduced. Therefore, the disclosed technology can be applied to a process such as PEALD (Plasma Enhanced Atomic Layer Deposition) which has a large impact on the production capacity of the process.
如以上,實施形態中,成膜裝置1具有:可以實施真空排氣的腔室10;作為下部電極使用的承受器12;上部電極60、62;原料氣體供給部76;及電壓施加部5。於承受器12載置有被處理基板。上部電極60、62在腔室10內與承受器12呈對置配置。原料氣體供給部76將在上部電極60、62與承受器12之間之處理空間PS電漿化的成膜原料氣體供給至處理空間PS。電壓施加部5將基準電位伴隨時間之經過而上下交替變化的交流電壓與直流脈衝電壓被重疊後的電壓亦即重疊電壓施加於上部電極60、62。As described above, in the embodiment, the
據此,成膜時,能夠同時達成高電子密度化、低離子能量化及高均勻性。另外,可以達成兼顧高電子密度化與低離子能量化,可以獨立進行電子密度之控制與離子能量之控制。According to this, at the time of film formation, high electron density, low ion energy, and high uniformity can be simultaneously achieved. In addition, both high electron density and low ion energy can be achieved, and electron density and ion energy can be controlled independently.
又,實施形態中,成膜裝置1具有在承受器12與接地之間被連接的阻抗調整電路100。In addition, in the embodiment, the
據此,可以減少上部電極60、62與承受器12之間之阻抗,因此重疊電壓之交流電壓成分容易到達承受器12。According to this, the impedance between the
又,本揭示之實施形態全部之點僅為例示並非用來限制者。實際上,上述實施形態可以多樣的形態具體實現。又,上述實施形態,在不脫離申請專利範圍及其趣旨之範圍內可以進行各種形態之省略、置換、變更。In addition, all the points of the embodiment of the present disclosure are only examples and are not intended to be limiting. In fact, the above-mentioned embodiments can be realized in various forms. In addition, the above embodiments can be omitted, replaced, or changed in various forms without departing from the scope of the patent application and its purport.
1:成膜裝置 5:電壓施加部 10:腔室 12:承受器 60:內側上部電極 62:外側上部電極 76:原料氣體供給部1: film forming device 5: Voltage application section 10: chamber 12: receiver 60: inner upper electrode 62: outer upper electrode 76: Raw material gas supply unit
[圖1】圖1係表示實施形態的成膜裝置之構成例之圖。
[圖2]圖2係表示實施形態的高頻電壓之一例之圖。
[圖3]圖3係表示實施形態的直流脈衝電壓之一例之圖。
[圖4]圖4係表示實施形態的重疊電壓之一例之圖。
[圖5]圖5係表示比較例中的實驗結果之一例之圖。
[圖6]圖6係表示比較例中的實驗結果之一例之圖。
[圖7]圖7係表示實施形態的實驗結果1之一例之圖。
[圖8]圖8係表示實施形態的實驗結果2之一例之圖。
[圖9]圖9係表示實施形態的實驗結果2之一例之圖。
[圖10]圖10係表示實施形態的實驗結果3之一例之圖。[FIG. 1] FIG. 1 is a diagram showing a configuration example of a film forming apparatus according to an embodiment.
[Fig. 2] Fig. 2 is a diagram showing an example of a high-frequency voltage according to an embodiment.
[Fig. 3] Fig. 3 is a diagram showing an example of a DC pulse voltage according to an embodiment.
[Fig. 4] Fig. 4 is a diagram showing an example of superimposed voltage according to the embodiment.
[Fig. 5] Fig. 5 is a diagram showing an example of experimental results in a comparative example.
[Fig. 6] Fig. 6 is a diagram showing an example of experimental results in a comparative example.
[Fig. 7] Fig. 7 is a diagram showing an example of the
1:成膜裝置 1: film forming device
5:電壓施加部 5: Voltage application section
10:腔室 10: chamber
12:承受器 12: receiver
14:筒狀支撐部 14: cylindrical support
16:筒狀支撐部(內壁部) 16: Tubular support (inner wall)
18:環狀之排氣路 18: Circular exhaust path
22:排氣口 22: Exhaust
24:排氣管 24: Exhaust pipe
26:排氣裝置 26: Exhaust
28:閘閥 28: Gate valve
30:高頻電源 30: High frequency power supply
34:匹配單元 34: matching unit
36:連接棒 36: connecting rod
38:環部 38: Ring
40:靜電吸盤 40: electrostatic chuck
42:直流電源 42: DC power supply
44:開啟/斷開切換開關 44: Turn on/off switch
46:供電線 46: Power supply line
48:冷媒室 48: refrigerant room
50、52:配管 50, 52: piping
51:氣體供給管 51: gas supply pipe
56:氣體通路 56: Gas passage
60:內側上部電極 60: inner upper electrode
62:外側上部電極 62: outer upper electrode
63:絕緣體 63: insulator
64:電極板 64: electrode plate
66:電極支撐體 66: electrode support
68:電極板 68: electrode plate
70:電極支撐體 70: electrode support
72:氣體擴散室 72: Gas diffusion chamber
72a:氣體導入口 72a: gas inlet
74:氣體吐出孔 74: gas discharge hole
76:原料氣體供給部 76: Raw material gas supply unit
78:氣體供給管 78: gas supply pipe
80:可變直流電源 80: variable DC power supply
84:脈衝產生器 84: pulse generator
86:過濾器 86: filter
88:供電線 88: power supply line
91:重疊器 91: Overlap
92:開啟/斷開切換開關 92: Turn on/off switch
96:接地部件 96: Grounded parts
98:絕緣體 98: insulator
100:阻抗調整電路 100: impedance adjustment circuit
101:線圈 101: coil
102:可變電容器 102: Variable capacitor
PS:處理空間 PS: processing space
W:半導體晶圓 W: Semiconductor wafer
Claims (3)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2018104200A JP2019212648A (en) | 2018-05-31 | 2018-05-31 | Film forming apparatus and film forming method |
JP2018-104200 | 2018-05-31 |
Publications (1)
Publication Number | Publication Date |
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TW202012699A true TW202012699A (en) | 2020-04-01 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108117049A TW202012699A (en) | 2018-05-31 | 2019-05-17 | Film forming device and film forming method |
Country Status (3)
Country | Link |
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JP (1) | JP2019212648A (en) |
TW (1) | TW202012699A (en) |
WO (1) | WO2019230526A1 (en) |
Families Citing this family (1)
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JP2022015848A (en) * | 2020-07-10 | 2022-01-21 | 東京エレクトロン株式会社 | Film deposition apparatus and film deposition method |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH1131685A (en) * | 1997-07-14 | 1999-02-02 | Hitachi Electron Eng Co Ltd | Plasma cvd device and its cleaning method |
JP2000313962A (en) * | 1999-04-26 | 2000-11-14 | Sekisui Chem Co Ltd | DEPOSITION OF TiO2 THIN FILM USING DISCHARGE PLASMA |
JP2005026063A (en) * | 2003-07-02 | 2005-01-27 | Sharp Corp | Plasma processing device and plasma processing method |
JP4553247B2 (en) * | 2004-04-30 | 2010-09-29 | 東京エレクトロン株式会社 | Plasma processing equipment |
JP4607930B2 (en) * | 2007-09-14 | 2011-01-05 | 株式会社東芝 | Plasma processing apparatus and plasma processing method |
-
2018
- 2018-05-31 JP JP2018104200A patent/JP2019212648A/en not_active Withdrawn
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2019
- 2019-05-17 TW TW108117049A patent/TW202012699A/en unknown
- 2019-05-22 WO PCT/JP2019/020314 patent/WO2019230526A1/en active Application Filing
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WO2019230526A1 (en) | 2019-12-05 |
JP2019212648A (en) | 2019-12-12 |
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