TW202011571A - Semiconductor device and manufacturing method thereof suitable for miniaturization and capable of reducing wiring delay or resistance losses - Google Patents

Abstract

Embodiments of the invention provide a semiconductor device having an electrode structure suitable for miniaturization and a method for manufacturing the same. The semiconductor device includes a first semiconductor circuit layer having a first conductive layer, a second semiconductor circuit layer having a second conductive layer, and a third semiconductor circuit layer which is provided between the first semiconductor circuit layer and the second semiconductor circuit layer, and which is composed of a third conductive layer in contact with the first conductive layer and a fourth conductive layer in contact with the second conductive layer, and a fifth conductive layer electrically that connects the third conductive layer to the fourth conductive layer and is in contact with the third conductive layer. The width of the fifth conductive layer is narrower than the width of the third conductive layer.

Description

Semiconductor device and its manufacturing method

An embodiment of the present invention relates to a semiconductor device and a method of manufacturing the same.

In order to increase the capacity or improve the performance of semiconductor devices, there is a technique of bonding a plurality of devices formed with semiconductor circuits of the same type or different types. By bonding the devices, for example, the memory capacity of the semiconductor device becomes larger. Also, for example, the wiring delay or resistance loss between semiconductor circuits is reduced, and the semiconductor device is improved in performance.

In the case where each device is attached to the upper and lower surfaces of the device, electrodes must be formed on the front and back of the device to electrically connect the devices. The industry expects that the electrode structure used to electrically connect the devices does not hinder the reduction in the size of the wafer of the semiconductor device.

Embodiments of the present invention provide a semiconductor device having an electrode structure suitable for wafer size reduction and a method of manufacturing the same.

The semiconductor device of the embodiment includes: a first semiconductor circuit layer having a first conductive layer; a second semiconductor circuit layer having a second conductive layer; and a third semiconductor circuit layer provided on the first semiconductor circuit layer and Between the second semiconductor circuit layer, a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a third conductive layer in contact with the fourth The conductive layer is electrically connected to the fifth conductive layer that is in contact with the third conductive layer; the width of the fifth conductive layer is narrower than the width of the third conductive layer.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In addition, in the following description, the same or similar components are denoted by the same symbols, and the description of components that have already been explained once is omitted as appropriate.

In this specification, the "semiconductor circuit layer" refers to a layer provided with wiring, transistors, diodes, etc. made of semiconductors at least in part. In addition, in this specification, the "semiconductor circuit board" refers to a substrate provided with wiring, transistors, diodes, etc. made of semiconductors at least in part.

Hereinafter, the semiconductor device and the manufacturing method of the embodiment will be described with reference to the drawings.

The semiconductor device of the embodiment includes: a first semiconductor circuit layer having a first conductive layer; a second semiconductor circuit layer having a second conductive layer; and a third semiconductor circuit layer provided on the first semiconductor circuit layer and the first 2 Between the semiconductor circuit layers and having a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and electrically connecting the third conductive layer and the fourth conductive layer And the fifth conductive layer connected to the third conductive layer; the width of the fifth conductive layer is narrower than the width of the third conductive layer.

FIG. 1 is a schematic cross-sectional view of a semiconductor device of an embodiment. FIG. 1 is an xz section of a semiconductor device.

The semiconductor memory of the embodiment includes a first memory layer 100 (third semiconductor circuit layer), a second memory layer 200 (first semiconductor circuit layer), a peripheral circuit layer 300 (second semiconductor circuit layer), and an electrode pad 400. The semiconductor device of the embodiment is a semiconductor memory formed by stacking a first memory layer 100, a second memory layer 200 having a three-dimensional structure of a memory cell array, and a peripheral circuit layer 300 having a control circuit for controlling the memory cell array. The first memory layer 100, the second memory layer 200, and the peripheral circuit layer 300 are stacked in the z direction in FIG.

The first memory layer 100 includes a first electrode 101 (third conductive layer), a second electrode 102 (fourth conductive layer), a contact plug 103 (fifth conductive layer), a wiring layer 104, an inter-electrode insulating layer 105, and a diffusion The prevention layer 106 (an insulating layer including nitrogen), the interlayer insulating layer 107, and the memory cell array 110. The memory cell array 110 includes a source line 111, a word line 112, a channel layer 113, and a bit line 114.

The second memory layer 200 includes an electrode 202 (first conductive layer), a contact plug 203 (sixth conductive layer), a wiring layer 204, an inter-electrode insulating layer 205, a diffusion prevention layer 206, an inter-layer insulating layer 207, and a blocking layer 208 , A sacrificial layer 209 (polycrystalline semiconductor layer), and a memory cell array 210. The memory cell array 210 includes a source line 211, a word line 212, a channel layer 213, and a bit line 214.

The peripheral circuit layer 300 includes an electrode 301 (second conductive layer), a contact plug 302, a wiring layer 303, a contact plug 304, a TSV305 (Through Silicon Via), a device isolation region 307, a silicon substrate 308, and a peripheral circuit 309 、和间层 insulating层330. The peripheral circuit 309 includes a first transistor 310 (MISFET: Metal Insulator Semiconductor Field Effect Transistor) and a second transistor 320. The first transistor 310 includes a source, a drain region 313, a gate electrode 311, and a gate insulating film 312. The second transistor 320 includes a source, a drain region 323, a gate electrode 321, and a gate insulating film 322.

The first memory layer 100 is disposed between the second memory layer 200 and the peripheral circuit layer 300. The second memory layer 200 is directly attached to one surface of the first memory layer 100. The peripheral circuit layer 300 is directly attached to the other surface of the first memory layer 100.

The first electrode 101 (third conductive layer) of the first memory layer 100 is directly connected to the electrode 202 (first conductive layer) of the second memory layer 200. The first electrode 101 and the electrode 202 are electrically connected. The second electrode 102 (fourth conductive layer) of the first memory layer 100 is directly connected to the electrode 301 (second conductive layer) of the peripheral circuit layer 300. The second electrode 102 and the electrode 301 are electrically connected.

The first electrode 101 is, for example, a metal containing copper (Cu). For example, in the area where the first electrode 101 is in contact with the contact plug 103, the area where the first electrode 101 is in contact with the stopper layer 108, and the area where the first electrode 101 is in contact with the inter-electrode insulating layer 105, for example, Barrier metal film. The barrier metal film is, for example, a metal nitride film. The metal nitride film is, for example, tantalum nitride (TaN), titanium nitride (TiN), or niobium nitride (NbN).

The second electrode 102 is, for example, a metal containing copper (Cu). For example, a barrier metal film is provided in the area where the second electrode 102 is in contact with the wiring layer 104 and the area where the second electrode 102 is in contact with the interlayer insulating layer 107. The barrier metal film is, for example, a metal nitride film. The metal nitride film is, for example, tantalum nitride (TaN), titanium nitride (TiN), or niobium nitride (NbN).

A contact plug 103 and a wiring layer 104 are provided between the first electrode 101 and the second electrode 102. The first electrode 101 and the second electrode 102 are electrically connected by the contact plug 103 and the wiring layer 104.

The wiring layer 104 is, for example, a metal containing tungsten (W).

2 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the embodiment. 2 is a schematic cross-sectional view of a region where the first electrode 101 is in contact with the contact plug 103. FIG. 2 shows an xz cross section of a semiconductor device as an example, but it is the same even in the yz cross section.

The first width (W1 in FIG. 2) of the contact plug 103 in the area where the first electrode 101 contacts the contact plug 103 is narrower than the second width (W2 in FIG. 2) of the first electrode 101 in the above area. In other words, the first width (W1 in FIG. 2) of the contact plug 103 in the vicinity of the contact surface between the first electrode 101 and the contact plug 103 is greater than the second width of the first electrode 101 (in FIG. 2) near the contact surface W2) Narrow. Also, in other words, the first width of the contact surface of the first electrode 101 and the contact plug 103 (W1 in FIG. 2) is larger than the second width of the surface of the first electrode 101 including the contact surface (W2 in FIG. 2) narrow. The difference between the second width and the first width is, for example, 0.1 µm or more, preferably 0.5 µm or more. If it is lower than the above range, there is a possibility that the contact plug 103 deviates from the first electrode 101 due to the misalignment of the lithography during manufacturing.

The surface shape of the first electrode 101 is, for example, a square, and the length of one side is, for example, 0.3 μm or more and 5 μm or less. The length of one side is 1 μm, for example. The side surface of the first electrode 101 may be, for example, tapered or stepped.

The material of the contact plug 103 is different from the material of the first electrode 101, for example. The contact plug 103 is, for example, a metal containing tungsten (W).

The contact plug 103 includes a barrier metal film 103a (metal nitride film) in contact with the first electrode 101. The barrier metal film 103a is, for example, a metal nitride film. The metal nitride film is, for example, tantalum nitride (TaN), titanium nitride (TiN), or niobium nitride (NbN). The barrier metal film 103a is also in contact with the inter-electrode insulating layer 105 and the inter-layer insulating layer 107.

The inter-electrode insulating layer 105 is, for example, silicon oxide, silicon oxynitride, or silicon nitride. From the viewpoint of suppressing the diffusion of copper from the electrode of the first electrode 101, it is preferable that the inter-electrode insulating layer 105 contains nitrogen (N) in the layer.

The diffusion prevention layer 106 is an insulating layer. The diffusion prevention layer 106 has a function of suppressing copper diffusion from the electrode of the first electrode 101 to the interlayer insulating layer 107. It is preferable that the diffusion prevention layer 106 contains nitrogen (N) in the layer. The diffusion prevention layer 106 is, for example, silicon nitride or silicon carbide added with nitrogen.

The interlayer insulating layer 107 is, for example, silicon oxide.

In the memory cell array 110, for example, memory cells with non-volatile memory are three-dimensionally arranged. The memory cell array 110 is disposed between two contact plugs 103.

A plurality of word lines 112 are stacked in the interlayer insulating layer 107 toward the z direction. The plural character lines 112 extend in the x direction parallel to the upper surface and the lower surface of the first memory layer 100. The number of stacked layers of the character line 112 is, for example, 20 layers or more and 100 layers or less. The character line 112 is, for example, metal.

The plurality of channel layers 113 are arranged to cross the word line 112. The channel layer 113 extends vertically with respect to the upper surface and the lower surface of the first memory layer 100. One end of the channel layer 113 is electrically connected to the source line 111. The channel layer 113 is, for example, polysilicon. The source line 111 is, for example, polysilicon.

The plurality of bit lines 114 extend parallel to the upper surface and the lower surface of the first memory layer 100. The end of the channel layer 113 opposite to the source line 111 is electrically connected to the bit line 114.

In a region where each of the word lines 112 and each of the channel layers 113 cross, for example, a charge storage layer (not shown) is provided. The area where each of the word lines 112 crosses each of the channel layers 113 functions as a non-volatile memory cell.

The second memory layer 200 differs from the first memory layer 100 in that it includes a blocking layer 208 and a sacrificial layer 209. The electrode 202, the contact plug 203, the wiring layer 204, the inter-electrode insulating layer 205, the diffusion prevention layer 206, and the inter-layer insulating layer 207 have the second electrode 102, the contact plug 103, the wiring layer 104, and the inter-electrode insulating layer 105, The diffusion prevention layer 106 and the interlayer insulating layer 107 have the same structure. In addition, the memory cell array 210 has the same structure as the memory cell array 110. The memory cell array 210 is disposed between two contact plugs 203.

The sacrificial layer 209 is provided via the inter-electrode insulating layer 205. Preferably, the sacrificial layer 209 is a material that can be selectively etched relative to the inter-electrode insulating layer 205. In addition, it is preferable that the sacrificial layer 209 be a material that can be etched by wet etching. The sacrificial layer 209 is, for example, a polycrystalline semiconductor. The polycrystalline semiconductor is, for example, polycrystalline silicon or polycrystalline silicon germanium compound.

The blocking layer 208 is disposed on the lower surface of the inter-electrode insulating layer 205. The blocking layer 208 is, for example, silicon oxide.

The width of the contact plug 203 in the area where the contact plug 203 is in contact with the sacrificial layer 209 is narrower than the width of the sacrificial layer 209 in the above area. In other words, the width of the contact plug 203 near the contact surface of the contact plug 203 and the sacrificial layer 209 is narrower than the width of the sacrificial layer 209 near the contact surface.

The peripheral circuit layer 300 is disposed on the first memory layer 100. The electrode 301 is, for example, a metal containing copper (Cu). For example, a barrier metal film is provided in a region where the electrode 301 is in contact with the contact plug 302 and a region where the electrode 301 is in contact with the interlayer insulating layer 330. The barrier metal film is, for example, a metal nitride film. The metal nitride film is, for example, tantalum nitride (TaN), titanium nitride (TiN), or niobium nitride (NbN).

The contact plug 302, the wiring layer 303, and the contact plug 304 are, for example, metals containing tungsten (W).

The peripheral circuit 309 is, for example, peripheral circuits of the memory cell array 110 and the memory cell array 210. The peripheral circuit 309 is, for example, a sense amplifier circuit, a word line driver circuit, a column decoder circuit, a row decoder circuit, a boost circuit, and the like.

The element separation region 307 is provided in the silicon substrate 308. The silicon substrate 308 is single crystal silicon. The element isolation region 307 is, for example, silicon oxide.

The TSV 305 penetrates the silicon substrate 308 and the element isolation region 307 and is in contact with the wiring layer 303. TSV305 is, for example, a metal containing copper.

The electrode pad 400 is provided to obtain electrical conduction between the semiconductor memory and the outside. For example, a bonding wire is connected to the electrode pad 400.

Next, a method of manufacturing the semiconductor device of the embodiment will be described. 3 to 15 are schematic cross-sectional views showing the semiconductor device in the middle of manufacturing in the method of manufacturing the semiconductor device of the embodiment.

The manufacturing method of the semiconductor device of the embodiment includes a semiconductor substrate, an insulating layer on the semiconductor substrate, a sacrificial layer on the insulating layer, a first conductive layer provided on a surface opposite to the semiconductor substrate, and a phase with the sacrificial layer The first semiconductor circuit board connected to the second conductive layer electrically connected to the first conductive layer is connected to the second semiconductor circuit board having the third conductive layer on the surface via the first conductive layer and the third conductive layer Bonding, and the semiconductor substrate and the insulating layer are removed with the sacrificial layer exposed, the sacrificial layer is removed to form an opening, the fourth conductive layer is buried in the opening, and the first semiconductor circuit board and the surface have a fifth The third semiconductor circuit board of the conductive layer is bonded so that the fourth conductive layer and the fifth conductive layer are in contact with each other.

First, the first semiconductor wafer 150 (first semiconductor circuit board) is manufactured. A blocking layer 108 (insulating layer) is formed on the silicon substrate 120 (semiconductor substrate). The blocking layer 108 functions as an etching blocking layer when the silicon substrate 120 is removed in the subsequent steps. The blocking layer 108 is, for example, silicon oxide. On the blocking layer 108, a sacrificial layer 109 is formed (FIG. 3). The sacrificial layer 109 is, for example, polysilicon.

Next, an inter-electrode insulating layer 105 is formed between the sacrificial layers 109. The inter-electrode insulating layer 105 is, for example, silicon oxide. A diffusion prevention layer 106 is formed on the inter-electrode insulating layer 105 (FIG. 4). The diffusion prevention layer 106 is, for example, silicon nitride.

Next, an interlayer insulating layer 107 is formed on the diffusion prevention layer 106. The interlayer insulating layer 107 is, for example, silicon oxide. In the interlayer insulating layer 107, a source line 111, a word line 112, and a channel layer 113 are formed. A contact hole 121 is formed from the upper surface of the interlayer insulating layer 107 to the sacrificial layer 109 (FIG. 5).

Next, a contact plug 103 (second conductive layer) is formed in the contact hole 121 (FIG. 6). The contact plug 103 is, for example, a metal containing tungsten.

Next, on the upper surface of the interlayer insulating layer 107, a wiring layer 104 in contact with the contact plug 103 and a bit line 114 in contact with the channel layer 113 are formed (FIG. 7). The wiring layer 104 and the bit line 114 are, for example, metals containing tungsten.

Next, it is integrated with the interlayer insulating layer 107 to form an insulating layer that becomes a part of the interlayer insulating layer 107. Next, the second electrode 102 (first conductive layer) in contact with the wiring layer 104 is formed (FIG. 8). The second electrode 102 is electrically connected to the contact plug 103. The second electrode 102 is, for example, a metal containing copper.

According to the above steps, the first semiconductor wafer 150 is manufactured.

Next, the second semiconductor wafer 350 (second semiconductor circuit board) manufactured in advance and the first semiconductor wafer 150 are bonded (FIG. 9 ). On the second semiconductor wafer 350, an electrode 301 (third conductive layer), a contact plug 302, a wiring layer 303, a contact plug 304, an element isolation region 307, a silicon substrate 308, a peripheral circuit 309, and an interlayer insulating layer are formed 330. The peripheral circuit 309 includes a first transistor 310 and a second transistor 320. The first transistor 310 includes a source, a drain region 311, a gate electrode 312, and a gate insulating film 313. The second transistor 320 includes a source, a drain region 321, a gate electrode 322, and a gate insulating film 323.

The first semiconductor wafer 150 and the second semiconductor wafer 350 are bonded in such a manner that the second electrode 102 of the first semiconductor wafer 150 directly contacts the electrode 301 of the second semiconductor wafer 350.

When bonding the first semiconductor wafer 150 and the second semiconductor wafer 350, for example, at least any one of the surface of the first semiconductor wafer 150 and the surface of the second semiconductor wafer 350 is subjected to plasma treatment.

Next, the silicon substrate 120 is removed (FIG. 10). After the silicon substrate 120 is thinned by back grinding, for example, it is completely removed using alkaline wet etching.

Next, the blocking layer 108 is removed with the sacrificial layer 109 exposed (FIG. 11). The blocking layer 108 of silicon oxide is removed by, for example, wet etching using a hydrofluoric acid system.

Next, the sacrificial layer 109 is selectively removed to form an opening 122 (FIG. 12). The sacrificial layer 109 of polysilicon is selectively removed by wet etching using an alkali system.

Next, the first electrode 101 (fourth conductive layer) is buried in the opening 122 (FIG. 13 ). The first electrode 101 is formed by, for example, embedding copper plating by electroless plating.

Next, the third semiconductor wafer 250 (third semiconductor circuit board) manufactured in advance is bonded to the first semiconductor wafer 150 (FIG. 14 ). On the third semiconductor wafer 250, an electrode 202 (fifth conductive layer), a contact plug 203, a wiring layer 204, an inter-electrode insulating layer 205, a diffusion prevention layer 206, an inter-layer insulating layer 207, and a stopper are formed on the silicon substrate 220 Layer 208, sacrificial layer 209, and memory cell array 210. The memory cell array 210 includes a source line 211, a word line 212, a channel layer 213, and a bit line 214. The third semiconductor wafer 250 has the same structure as the first semiconductor wafer shown in FIG. 8.

The first semiconductor wafer 150 and the third semiconductor wafer 250 are bonded in such a manner that the first electrode 101 of the first semiconductor wafer 150 and the electrode 202 of the third semiconductor wafer 250 directly contact each other.

When the first semiconductor wafer 150 and the third semiconductor wafer 250 are bonded, for example, at least any one of the surface of the first semiconductor wafer 150 and the surface of the third semiconductor wafer 250 is plasma-processed.

Next, the silicon substrate 220 is removed (FIG. 15). After the silicon substrate 220 is thinned by back grinding, for example, it is completely removed by wet etching using an alkali system.

Next, TSV 305 and electrode pad 400 are formed.

Next, for example, using a dicing device, a plurality of semiconductor memories formed on the laminated wafer formed by bonding the first semiconductor wafer 150, the second semiconductor wafer 350, and the third semiconductor wafer 250 are singulated. The semiconductor memory shown in FIG. 1 is formed by the above manufacturing method.

Next, the operation and effect of the semiconductor device of the embodiment will be described.

The semiconductor memory of the embodiment realizes a semiconductor memory having a larger memory capacity by stacking the first memory layer 100 and the second memory layer 200. In addition, by bonding the first memory layer 100 and the second memory layer 200 directly to the first memory layer 100 and the peripheral circuit layer 300, for example, the chip size of the semiconductor memory becomes smaller. In addition, for example, the wiring delay or resistance loss between semiconductor circuits is reduced, and the semiconductor memory is improved in performance.

When attaching different devices to the upper and lower surfaces of the device, electrodes must be formed on the front and back of the device to electrically connect the devices. It is required that the device be provided with a plurality of electrodes for input and output signal transmission, control signal transmission, and power supply. Therefore, for example, if the arrangement pitch of the electrodes determined by the processing accuracy becomes larger, it becomes an obstacle to shrinking the wafer size of the semiconductor device. In particular, it is difficult to reduce the distance between the electrodes on the back side and the distance between the electrodes on the front side of the finally formed device when manufacturing the device. The reason for this is that, for example, in the lithography on the back side, the bonding with the front side must be performed and the bonding accuracy is poor. Furthermore, the flatness of the substrate is inferior to the front side, and high-precision patterning is difficult.

16 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first comparative form. 16 is a schematic cross-sectional view of a part corresponding to FIG. 2 of the semiconductor device of the first comparative form.

The semiconductor device of the first comparative form shown in FIG. 16 includes an electrode 901, a contact plug 903, an inter-electrode insulating layer 905, a diffusion prevention layer 906, and an inter-layer insulating layer 907. Each corresponds to the first electrode 101, the contact plug 103, the inter-electrode insulating layer 105, the diffusion prevention layer 106, and the inter-layer insulating layer 107 of the embodiment.

The electrode 901 is, for example, a metal containing copper (Cu).

The material of the contact plug 903 is different from the material of the electrode 901, for example. The contact plug 103 is, for example, a metal containing tungsten (W).

The contact plug 903 includes a barrier metal film 903a in contact with the electrode 901. The barrier metal film 903a is, for example, a metal nitride film. The metal nitride film is, for example, tantalum nitride (TaN), titanium nitride (TiN), or niobium nitride (NbN). The barrier metal film 903a is also in contact with the interlayer insulating layer 907 and the diffusion prevention layer 906.

The width of the contact plug 903 in the contact area of the contact plug 903 and the electrode 901 (W3 in FIG. 16) is wider than the width of the electrode 901 in the above area (W2 in FIG. 16).

The width of the electrode 901 requires a specific width due to, for example, processing limitations or electrical characteristics. The specific width is set to W2 in FIGS. 2 and 16. In the case of the first comparative form, the width of the contact plug 903 (W3 in FIG. 16) is wider than the specific width W2. The distance between the two adjacent electrodes 901 must be larger than in the embodiment, and the contact plug 903 must be widened. Therefore, the arrangement pitch of the electrodes 901 becomes larger, which becomes an obstacle to shrinking the size of the wafer.

In the case of the semiconductor device of the embodiment, as shown in FIG. 2, the first width of the contact plug 103 (W1 in FIG. 2) is narrower than the second width of the first electrode 101 (W2 in FIG. 2). Therefore, the arrangement pitch of the first electrode 101 can be as small as the limit of lithography, for example, and does not become an obstacle to shrinking the wafer size of the semiconductor device. In other words, the electrode structure of the semiconductor device of the embodiment is suitable for the reduction of the wafer size of the semiconductor device.

17 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the second comparative form. 17 is a schematic cross-sectional view of a part corresponding to FIG. 2 of the semiconductor device of the second comparative form.

The semiconductor device of the second comparative embodiment shown in FIG. 17 is the same as that of FIG. 16, and the electrode 901, the contact plug 903, the inter-electrode insulating layer 905, the diffusion prevention layer 906, and the inter-layer insulating layer 907 are the same as the first electrode 101 of the embodiment. , The contact plug 103, the inter-electrode insulating layer 105, the diffusion prevention layer 106, and the inter-layer insulating layer 107 correspond.

The semiconductor device of the second comparative aspect further includes an intermediate layer 908. The intermediate layer 908 is a conductive layer. The intermediate layer 908 is, for example, a metal containing tungsten (W). The electrode 901 and the contact plug 903 are electrically connected via the intermediate layer 908.

The width of the intermediate layer 908 (W4 in FIG. 17) is wider than the width of the electrode 901 (W2 in FIG. 17).

The width of the electrode 901 requires a specific width due to, for example, processing limitations or electrical characteristics. The specific width is set to W2 in FIGS. 2 and 17. In the case of the second comparative form, the width of the intermediate layer 908 (W4 in FIG. 17) is wider than the specific width W2. It is necessary to make the distance between two adjacent electrodes 901 larger than the embodiment in accordance with the amount of the intermediate layer 908 becoming wider. Therefore, the arrangement pitch of the electrodes 901 becomes larger, which hinders the shrinking of the wafer size of the semiconductor device.

In the case of the semiconductor device of the embodiment, as shown in FIG. 2, the first width of the contact plug 103 (W1 in FIG. 2) is narrower than the second width of the first electrode 101 (W2 in FIG. 2). Therefore, the arrangement pitch of the first electrode 101 can be reduced to the limit of lithography, for example, and does not hinder the reduction in the size of the semiconductor device wafer. In other words, the electrode structure of the semiconductor device of the embodiment is suitable for the reduction of the wafer size of the semiconductor device.

The semiconductor device of the embodiment can be easily manufactured at low cost by using the method of manufacturing the semiconductor device of the embodiment.

Next, the function and effect of the manufacturing method of the embodiment will be described.

When attaching different devices to the upper and lower surfaces of the device, electrodes must be formed on the front and back of the device to electrically connect the devices. When an electrode is formed on the back side of the device, if lithography or dry etching with a relatively high process cost is used, the manufacturing cost of the semiconductor device manufactured by bonding the device increases. In addition, generally speaking, due to the influence of the flatness of the substrate and the like, the processing accuracy of the lithography on the back side is lower than the processing accuracy of the lithography on the front side, so the arrangement pitch of the electrodes may be increased. Therefore, it may be difficult to reduce the wafer size of the semiconductor device.

In the embodiment, for example, in the first semiconductor wafer 150, the sacrificial layer 109 shown in FIG. 8 is formed in a region that will become the first electrode 101 on the back side later. And, before bonding the first semiconductor wafer 150 and the third semiconductor wafer 250, the sacrificial layer 109 is removed (FIG. 12). The material of the sacrificial layer 109 can be selectively removed by wet etching. In this way, the first electrode 101 on the back side of the first semiconductor wafer 150 can be formed without using lithography or dry etching, which has a relatively high process cost. Therefore, the manufacturing cost of the semiconductor device can be reduced.

In addition, the first electrode 101 on the back side may be processed without using lithography and dry etching. Therefore, for example, it is not necessary to provide the intermediate layer 908 as shown in FIG. 17 as an etching stopper. Therefore, the arrangement pitch of the electrodes can be reduced. Therefore, the first electrode 101 on the back side does not hinder the reduction of the wafer size of the semiconductor device.

In addition, the arrangement pitch of the first electrode 101 on the back side becomes the arrangement pitch of the sacrificial layer 109. Since the sacrificial layer 109 is formed using the lithography on the front side with high processing accuracy, the arrangement pitch can be reduced. Therefore, the arrangement pitch of the first electrodes 101 on the back side can be reduced, and the wafer size of the semiconductor device can be reduced.

18 is a schematic cross-sectional view of a semiconductor device according to a modification. The arrangement of the contact plug 103 between the two memory cells 110 and the contact plug 203 between the two memory cells 210 is different from the embodiment.

In the embodiment, the case where the memory cell having the memory cell array is laminated in two layers has been described as an example, but it is also possible to increase the memory capacity of the semiconductor memory by laminating more than three layers.

In the embodiment, the case where the semiconductor device is a semiconductor memory has been described as an example. However, the present invention can also be applied to semiconductor devices other than semiconductor memory, such as logic devices, CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) sensors, and the like.

In the above, several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. For example, the constituent elements of one embodiment may be replaced or changed to those of other embodiments. These embodiments or their changes are included in the scope or gist of the invention, and are included in the invention described in the patent application and its equivalent scope.

100: first memory layer (third semiconductor circuit layer) 101: first electrode (third conductive layer) 102: second electrode (fourth conductive layer) 103: contact plug (fifth conductive layer) 103a: metal nitrogen Chemical film 104: wiring layer 105: inter-electrode insulating layer 106: diffusion prevention layer (insulating layer containing nitrogen) 107: inter-layer insulating layer 108: blocking layer 109: sacrificial layer 110: memory cell array 111: source line 112: Word line 113: channel layer 114: bit line 120: silicon substrate 121: contact hole 150: first wafer (first semiconductor circuit board) 200: second memory layer (first semiconductor circuit layer) 202: electrode ( (First conductive layer) 203: contact plug (sixth conductive layer) 204: wiring layer 205: inter-electrode insulating layer 206: diffusion prevention layer 207: inter-layer insulating layer 208: barrier layer 209: sacrificial layer (polycrystalline semiconductor layer) ) 210: memory cell array 211: source line 212: word line 213: channel layer 214: bit line 220: silicon substrate 250: third semiconductor wafer (third semiconductor circuit board) 300: peripheral circuit layer (first 2 semiconductor circuit layer) 301: electrode (second conductive layer) 302: contact plug 303: wiring layer 304: contact plug 305: TSV307: element separation region 308: silicon substrate 309: peripheral circuit 310: first transistor ( MISFET) 311: Gate electrode 312: Gate insulating film 313: Source and drain regions 320: Second transistor 321: Source and drain regions 322: Gate electrode 323: Gate insulating film 330: Interlayer insulation Layer 350: second semiconductor wafer (second semiconductor circuit board) 400: electrode pad 901: electrode 903: contact plug 903a: barrier metal film 905: inter-electrode insulating layer 906: diffusion prevention layer 907: inter-layer insulating layer 908: Middle layer W1: 1st width W2: 2nd width W3: width

FIG. 1 is a schematic cross-sectional view of a semiconductor device of an embodiment. 2 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the embodiment. 3 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 4 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 5 is a schematic cross-sectional view of a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 6 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 7 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 8 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 9 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 10 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 11 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 12 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 13 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 14 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 15 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 16 is an explanatory diagram of the function and effect of the semiconductor device of the embodiment. 17 is an explanatory diagram of the operation and effect of the semiconductor device of the embodiment. 18 is a schematic cross-sectional view of a semiconductor device according to a modification.

100: 1st memory layer (3rd semiconductor circuit layer)

101: 1st electrode (3rd conductive layer)

102: 2nd electrode (4th conductive layer)

103: Contact plug (5th conductive layer)

104: wiring layer

105: insulating layer between electrodes

106: Diffusion prevention layer (insulation layer containing nitrogen)

107: Interlayer insulation

110: memory cell array

111: source line

112: character line

113: Channel layer

114: bit line

200: 2nd memory layer (1st semiconductor circuit layer)

202: electrode (first conductive layer)

203: Contact plug (6th conductive layer)

204: wiring layer

205: insulating layer between electrodes

206: Diffusion prevention layer

207: Interlayer insulation

208: stop layer

209: Sacrificial layer (polycrystalline semiconductor layer)

210: memory cell array

211: Source line

212: character line

213: Channel layer

214: bit line

300: peripheral circuit layer (second semiconductor circuit layer)

301: electrode (second conductive layer)

302: contact plug

303: wiring layer

304: contact plug

305:TSV

307: component separation area

308: Silicon substrate

309: Peripheral circuit

310: The first transistor (MISFET)

311: Gate electrode

312: Gate insulating film

313: source and drain regions

320: 2nd transistor

321: source and drain regions

322: Gate electrode

323: Gate insulating film

330: Interlayer insulation

400: electrode pad

Claims (20)

A semiconductor device includes: a first semiconductor circuit layer having a first conductive layer; a second semiconductor circuit layer having a second conductive layer; and a third semiconductor circuit layer provided on the first semiconductor circuit layer and Between the second semiconductor circuit layer, a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a third conductive layer in contact with the fourth The conductive layer is electrically connected to the fifth conductive layer that is in contact with the third conductive layer; the width of the fifth conductive layer is narrower than the width of the third conductive layer. The semiconductor device according to claim 1, wherein the material of the third conductive layer is different from the material of the fifth conductive layer. The semiconductor device according to claim 1, wherein the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer include copper (Cu). The semiconductor device according to claim 1, wherein the fifth conductive layer contains tungsten. The semiconductor device according to claim 1, wherein the fifth conductive layer includes a metal nitride film in contact with the third conductive layer. The semiconductor device according to claim 1, wherein the third semiconductor circuit layer has a three-dimensional memory cell array in which a plurality of memory cells are stacked. The semiconductor device according to claim 1, wherein the second semiconductor circuit layer has a MISFET. The semiconductor device according to claim 6, wherein the second semiconductor circuit layer has peripheral circuits of the memory cell array. The semiconductor device according to claim 6, wherein an insulating layer containing nitrogen is provided between the third conductive layer and the memory cell array. The semiconductor device according to claim 1, wherein the first semiconductor circuit layer further includes: a polycrystalline semiconductor layer including silicon; and a sixth conductive layer provided between the first conductive layer and the polycrystalline semiconductor layer, It is electrically connected to the first conductive layer and is in contact with the polycrystalline semiconductor layer; the width of the sixth conductive layer is narrower than the width of the polycrystalline semiconductor layer. A method of manufacturing a semiconductor device comprising a semiconductor substrate, an insulating layer on the semiconductor substrate, a sacrificial layer on the insulating layer, a first conductive layer provided on a surface opposite to the semiconductor substrate, and The first semiconductor circuit substrate of the second conductive layer that is in contact with the sacrificial layer and electrically connected to the first conductive layer, and the second semiconductor circuit substrate that has a third conductive layer on the surface, and the first conductive layer and The third conductive layer is bonded together, the semiconductor substrate and the insulating layer are removed with the sacrificial layer exposed, the sacrificial layer is removed to form an opening, and the fourth conductive layer is buried in the opening , The first semiconductor circuit board and the third semiconductor circuit board having a fifth conductive layer on the surface are bonded so that the fourth conductive layer and the fifth conductive layer are in contact with each other. The method for manufacturing a semiconductor device according to claim 11, wherein the sacrificial layer is a polycrystalline semiconductor containing silicon. The method of manufacturing a semiconductor device according to claim 11, wherein the first conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer include copper (Cu). The method for manufacturing a semiconductor device according to claim 11, wherein when the first semiconductor circuit board and the second semiconductor circuit board are bonded, the surface of the first semiconductor circuit board and the surface of the second semiconductor circuit board At least any one performs plasma processing, and when bonding the first semiconductor circuit board and the third semiconductor circuit board, at least any one of the surface of the first semiconductor circuit board and the surface of the third semiconductor circuit board Perform plasma treatment. The method for manufacturing a semiconductor device according to claim 11, wherein the removal of the sacrificial layer is performed by wet etching. The method for manufacturing a semiconductor device according to claim 11, wherein the embedding of the fourth conductive layer is performed by a plating method. The method for manufacturing a semiconductor device according to claim 11, wherein the second conductive layer contains tungsten. The method for manufacturing a semiconductor device according to claim 11, wherein the first semiconductor circuit substrate has a memory cell array having a three-dimensional structure in which a plurality of memory cells are stacked. The method for manufacturing a semiconductor device according to claim 11, wherein the second semiconductor circuit board has a MISFET. The method for manufacturing a semiconductor device according to claim 18, wherein the second semiconductor circuit substrate has peripheral circuits of the memory cell array.

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