TW202011571A - Semiconductor device and manufacturing method thereof suitable for miniaturization and capable of reducing wiring delay or resistance losses - Google Patents

Semiconductor device and manufacturing method thereof suitable for miniaturization and capable of reducing wiring delay or resistance losses Download PDF

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TW202011571A
TW202011571A TW107130947A TW107130947A TW202011571A TW 202011571 A TW202011571 A TW 202011571A TW 107130947 A TW107130947 A TW 107130947A TW 107130947 A TW107130947 A TW 107130947A TW 202011571 A TW202011571 A TW 202011571A
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conductive layer
semiconductor
semiconductor device
electrode
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TWI701802B (en
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松尾浩司
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日商東芝記憶體股份有限公司
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Abstract

Embodiments of the invention provide a semiconductor device having an electrode structure suitable for miniaturization and a method for manufacturing the same. The semiconductor device includes a first semiconductor circuit layer having a first conductive layer, a second semiconductor circuit layer having a second conductive layer, and a third semiconductor circuit layer which is provided between the first semiconductor circuit layer and the second semiconductor circuit layer, and which is composed of a third conductive layer in contact with the first conductive layer and a fourth conductive layer in contact with the second conductive layer, and a fifth conductive layer electrically that connects the third conductive layer to the fourth conductive layer and is in contact with the third conductive layer. The width of the fifth conductive layer is narrower than the width of the third conductive layer.

Description

半導體裝置及其製造方法Semiconductor device and its manufacturing method

本發明之實施形態係關於一種半導體裝置及其製造方法。An embodiment of the present invention relates to a semiconductor device and a method of manufacturing the same.

為了半導體裝置之大容量化或高性能化,有將形成有相同種類或不同種類之半導體電路之複數個器件貼合之技術。藉由器件之貼合,例如,半導體裝置之記憶容量變大。又,例如,減少半導體電路間之配線延遲或電阻損耗,半導體裝置高性能化。In order to increase the capacity or improve the performance of semiconductor devices, there is a technique of bonding a plurality of devices formed with semiconductor circuits of the same type or different types. By bonding the devices, for example, the memory capacity of the semiconductor device becomes larger. Also, for example, the wiring delay or resistance loss between semiconductor circuits is reduced, and the semiconductor device is improved in performance.

當於器件之上表面及下表面之各者貼合其他器件之情形時,必須於器件之正面及背面形成用以將器件間電性地連接之電極。業者期望用以將器件間電性地連接之電極構造不妨礙半導體裝置之晶片尺寸之縮小。In the case where each device is attached to the upper and lower surfaces of the device, electrodes must be formed on the front and back of the device to electrically connect the devices. The industry expects that the electrode structure used to electrically connect the devices does not hinder the reduction in the size of the wafer of the semiconductor device.

本發明之實施形態提供一種具有適合於晶片尺寸之縮小之電極構造之半導體裝置及其製造方法。Embodiments of the present invention provide a semiconductor device having an electrode structure suitable for wafer size reduction and a method of manufacturing the same.

實施形態之半導體裝置具備:第1半導體電路層,其具有第1導電層;第2半導體電路層,其具有第2導電層;以及第3半導體電路層,其設置於上述第1半導體電路層與上述第2半導體電路層之間,且具有與上述第1導電層相接之第3導電層、與上述第2導電層相接之第4導電層、及將上述第3導電層與上述第4導電層電性地連接且與上述第3導電層相接之第5導電層;上述第5導電層之寬度較上述第3導電層之寬度更窄。The semiconductor device of the embodiment includes: a first semiconductor circuit layer having a first conductive layer; a second semiconductor circuit layer having a second conductive layer; and a third semiconductor circuit layer provided on the first semiconductor circuit layer and Between the second semiconductor circuit layer, a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a third conductive layer in contact with the fourth The conductive layer is electrically connected to the fifth conductive layer that is in contact with the third conductive layer; the width of the fifth conductive layer is narrower than the width of the third conductive layer.

以下,一面參照圖式一面對本發明之實施形態進行說明。再者,於以下之說明中,對相同或類似之構件等標註相同之符號,關於已經說明一次之構件等適當省略其說明。Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In addition, in the following description, the same or similar components are denoted by the same symbols, and the description of components that have already been explained once is omitted as appropriate.

於本說明書中,所謂「半導體電路層」,係指於至少一部分設置有以半導體為材料之配線、電晶體、二極體等之層。又,於本說明書中,所謂「半導體電路基板」,係指於至少一部分設置有以半導體為材料之配線、電晶體、二極體等之基板。In this specification, the "semiconductor circuit layer" refers to a layer provided with wiring, transistors, diodes, etc. made of semiconductors at least in part. In addition, in this specification, the "semiconductor circuit board" refers to a substrate provided with wiring, transistors, diodes, etc. made of semiconductors at least in part.

以下,參照圖式對實施形態之半導體裝置及其製造方法進行說明。Hereinafter, the semiconductor device and the manufacturing method of the embodiment will be described with reference to the drawings.

實施形態之半導體裝置具備:第1半導體電路層,其具有第1導電層;第2半導體電路層,其具有第2導電層;以及第3半導體電路層,其設置於第1半導體電路層與第2半導體電路層之間,且具有與第1導電層相接之第3導電層、與第2導電層相接之第4導電層、及將第3導電層與第4導電層電性地連接且與第3導電層相接之第5導電層;第5導電層之寬度較第3導電層之寬度窄。The semiconductor device of the embodiment includes: a first semiconductor circuit layer having a first conductive layer; a second semiconductor circuit layer having a second conductive layer; and a third semiconductor circuit layer provided on the first semiconductor circuit layer and the first 2 Between the semiconductor circuit layers and having a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and electrically connecting the third conductive layer and the fourth conductive layer And the fifth conductive layer connected to the third conductive layer; the width of the fifth conductive layer is narrower than the width of the third conductive layer.

圖1係實施形態之半導體裝置之模式剖視圖。圖1為半導體裝置之xz剖面。FIG. 1 is a schematic cross-sectional view of a semiconductor device of an embodiment. FIG. 1 is an xz section of a semiconductor device.

實施形態之半導體記憶體具備第1記憶體層100(第3半導體電路層)、第2記憶體層200(第1半導體電路層)、周邊電路層300(第2半導體電路層)、及電極墊400。實施形態之半導體裝置為將具有三維構造之記憶胞陣列之第1記憶體層100、第2記憶體層200、及具備控制上述記憶胞陣列之控制電路之周邊電路層300積層而成之半導體記憶體。第1記憶體層100、第2記憶體層200、及周邊電路層300於圖1中積層於z方向。The semiconductor memory of the embodiment includes a first memory layer 100 (third semiconductor circuit layer), a second memory layer 200 (first semiconductor circuit layer), a peripheral circuit layer 300 (second semiconductor circuit layer), and an electrode pad 400. The semiconductor device of the embodiment is a semiconductor memory formed by stacking a first memory layer 100, a second memory layer 200 having a three-dimensional structure of a memory cell array, and a peripheral circuit layer 300 having a control circuit for controlling the memory cell array. The first memory layer 100, the second memory layer 200, and the peripheral circuit layer 300 are stacked in the z direction in FIG.

第1記憶體層100具備第1電極101(第3導電層)、第2電極102(第4導電層)、接觸插塞103(第5導電層)、配線層104、電極間絕緣層105、擴散防止層106(包含氮之絕緣層)、層間絕緣層107、及記憶胞陣列110。記憶胞陣列110具備源極線111、字元線112、通道層113、及位元線114。The first memory layer 100 includes a first electrode 101 (third conductive layer), a second electrode 102 (fourth conductive layer), a contact plug 103 (fifth conductive layer), a wiring layer 104, an inter-electrode insulating layer 105, and a diffusion The prevention layer 106 (an insulating layer including nitrogen), the interlayer insulating layer 107, and the memory cell array 110. The memory cell array 110 includes a source line 111, a word line 112, a channel layer 113, and a bit line 114.

第2記憶體層200具備電極202(第1導電層)、接觸插塞203(第6導電層)、配線層204、電極間絕緣層205、擴散防止層206、層間絕緣層207、擋止層208、犧牲層209(多晶半導體層)、及記憶胞陣列210。記憶胞陣列210具備源極線211、字元線212、通道層213、及位元線214。The second memory layer 200 includes an electrode 202 (first conductive layer), a contact plug 203 (sixth conductive layer), a wiring layer 204, an inter-electrode insulating layer 205, a diffusion prevention layer 206, an inter-layer insulating layer 207, and a blocking layer 208 , A sacrificial layer 209 (polycrystalline semiconductor layer), and a memory cell array 210. The memory cell array 210 includes a source line 211, a word line 212, a channel layer 213, and a bit line 214.

周邊電路層300具備電極301(第2導電層)、接觸插塞302、配線層303、接觸插塞304、TSV305(Through Silicon Via,矽穿孔)、元件分離區域307、矽基板308、周邊電路309、及層間絕緣層330。周邊電路309具備第1電晶體310(MISFET:Metal Insulator Semiconductor Field Effect Transistor,金屬絕緣體半導體場效應電晶體)、及第2電晶體320。第1電晶體310具備源極、汲極區域313、閘極電極311、及閘極絕緣膜312。第2電晶體320具備源極、汲極區域323、閘極電極321、及閘極絕緣膜322。The peripheral circuit layer 300 includes an electrode 301 (second conductive layer), a contact plug 302, a wiring layer 303, a contact plug 304, a TSV305 (Through Silicon Via), a device isolation region 307, a silicon substrate 308, and a peripheral circuit 309 、和间层 insulating层330. The peripheral circuit 309 includes a first transistor 310 (MISFET: Metal Insulator Semiconductor Field Effect Transistor) and a second transistor 320. The first transistor 310 includes a source, a drain region 313, a gate electrode 311, and a gate insulating film 312. The second transistor 320 includes a source, a drain region 323, a gate electrode 321, and a gate insulating film 322.

第1記憶體層100設置於第2記憶體層200與周邊電路層300之間。於第1記憶體層100之一個面直接貼合有第2記憶體層200。於第1記憶體層100之另一個面直接貼合有周邊電路層300。The first memory layer 100 is disposed between the second memory layer 200 and the peripheral circuit layer 300. The second memory layer 200 is directly attached to one surface of the first memory layer 100. The peripheral circuit layer 300 is directly attached to the other surface of the first memory layer 100.

第1記憶體層100之第1電極101(第3導電層)與第2記憶體層200之電極202(第1導電層)直接相接。第1電極101與電極202電性地連接。第1記憶體層100之第2電極102(第4導電層)與周邊電路層300之電極301(第2導電層)直接相接。第2電極102與電極301電性地連接。The first electrode 101 (third conductive layer) of the first memory layer 100 is directly connected to the electrode 202 (first conductive layer) of the second memory layer 200. The first electrode 101 and the electrode 202 are electrically connected. The second electrode 102 (fourth conductive layer) of the first memory layer 100 is directly connected to the electrode 301 (second conductive layer) of the peripheral circuit layer 300. The second electrode 102 and the electrode 301 are electrically connected.

第1電極101例如為包含銅(Cu)之金屬。於第1電極101之與接觸插塞103相接之區域、第1電極101之與擋止層108相接之區域、及第1電極101之與電極間絕緣層105相接之區域,例如設置障壁金屬膜。障壁金屬膜例如為金屬氮化膜。金屬氮化膜例如為氮化鉭(TaN)、氮化鈦(TiN)、氮化鈮(NbN)。The first electrode 101 is, for example, a metal containing copper (Cu). For example, in the area where the first electrode 101 is in contact with the contact plug 103, the area where the first electrode 101 is in contact with the stopper layer 108, and the area where the first electrode 101 is in contact with the inter-electrode insulating layer 105, for example, Barrier metal film. The barrier metal film is, for example, a metal nitride film. The metal nitride film is, for example, tantalum nitride (TaN), titanium nitride (TiN), or niobium nitride (NbN).

第2電極102例如為包含銅(Cu)之金屬。於第2電極102之與配線層104相接之區域、第2電極102之與層間絕緣層107相接之區域,例如設置障壁金屬膜。障壁金屬膜例如為金屬氮化膜。金屬氮化膜例如為氮化鉭(TaN)、氮化鈦(TiN)、氮化鈮(NbN)。The second electrode 102 is, for example, a metal containing copper (Cu). For example, a barrier metal film is provided in the area where the second electrode 102 is in contact with the wiring layer 104 and the area where the second electrode 102 is in contact with the interlayer insulating layer 107. The barrier metal film is, for example, a metal nitride film. The metal nitride film is, for example, tantalum nitride (TaN), titanium nitride (TiN), or niobium nitride (NbN).

於第1電極101與第2電極102之間設置有接觸插塞103、配線層104。藉由接觸插塞103、及配線層104將第1電極101與第2電極102電性地連接。A contact plug 103 and a wiring layer 104 are provided between the first electrode 101 and the second electrode 102. The first electrode 101 and the second electrode 102 are electrically connected by the contact plug 103 and the wiring layer 104.

配線層104例如為包含鎢(W)之金屬。The wiring layer 104 is, for example, a metal containing tungsten (W).

圖2係實施形態之半導體裝置之一部分之放大模式剖視圖。圖2係第1電極101與接觸插塞103接觸之區域之模式剖視圖。圖2表示作為一例之半導體裝置之xz剖面,但即便於yz剖面中亦相同。2 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the embodiment. 2 is a schematic cross-sectional view of a region where the first electrode 101 is in contact with the contact plug 103. FIG. 2 shows an xz cross section of a semiconductor device as an example, but it is the same even in the yz cross section.

第1電極101與接觸插塞103接觸之區域之接觸插塞103之第1寬度(圖2中之W1)較上述區域之第1電極101之第2寬度(圖2中之W2)窄。換言之,第1電極101與接觸插塞103之接觸面附近之接觸插塞103之第1寬度(圖2中之W1)較上述接觸面附近之第1電極101之第2寬度(圖2中之W2)窄。又,換言之,第1電極101與接觸插塞103之接觸面之第1寬度(圖2中之W1)較第1電極101之包含上述接觸面之面之第2寬度(圖2中之W2)窄。第2寬度與第1寬度之差例如為0.1 µm以上,較佳為0.5 µm以上。若低於上述範圍,則有因製造時之微影之對準偏移,而接觸插塞103偏離第1電極101之虞。The first width (W1 in FIG. 2) of the contact plug 103 in the area where the first electrode 101 contacts the contact plug 103 is narrower than the second width (W2 in FIG. 2) of the first electrode 101 in the above area. In other words, the first width (W1 in FIG. 2) of the contact plug 103 in the vicinity of the contact surface between the first electrode 101 and the contact plug 103 is greater than the second width of the first electrode 101 (in FIG. 2) near the contact surface W2) Narrow. Also, in other words, the first width of the contact surface of the first electrode 101 and the contact plug 103 (W1 in FIG. 2) is larger than the second width of the surface of the first electrode 101 including the contact surface (W2 in FIG. 2) narrow. The difference between the second width and the first width is, for example, 0.1 µm or more, preferably 0.5 µm or more. If it is lower than the above range, there is a possibility that the contact plug 103 deviates from the first electrode 101 due to the misalignment of the lithography during manufacturing.

第1電極101之表面形狀例如為正方形,1邊之長度例如為0.3 μm以上且5 μm以下。1邊之長度例如為1 μm。第1電極101之側面例如既可為錐狀,亦可為階梯狀。The surface shape of the first electrode 101 is, for example, a square, and the length of one side is, for example, 0.3 μm or more and 5 μm or less. The length of one side is 1 μm, for example. The side surface of the first electrode 101 may be, for example, tapered or stepped.

接觸插塞103之材質例如與第1電極101之材質不同。接觸插塞103例如為包含鎢(W)之金屬。The material of the contact plug 103 is different from the material of the first electrode 101, for example. The contact plug 103 is, for example, a metal containing tungsten (W).

接觸插塞103具備與第1電極101相接之障壁金屬膜103a(金屬氮化膜)。障壁金屬膜103a例如為金屬氮化膜。金屬氮化膜例如為氮化鉭(TaN)、氮化鈦(TiN)、氮化鈮(NbN)。障壁金屬膜103a亦與電極間絕緣層105、及層間絕緣層107相接。The contact plug 103 includes a barrier metal film 103a (metal nitride film) in contact with the first electrode 101. The barrier metal film 103a is, for example, a metal nitride film. The metal nitride film is, for example, tantalum nitride (TaN), titanium nitride (TiN), or niobium nitride (NbN). The barrier metal film 103a is also in contact with the inter-electrode insulating layer 105 and the inter-layer insulating layer 107.

電極間絕緣層105例如為氧化矽、氮氧化矽、或氮化矽。自抑制銅自第1電極101之電極之擴散之觀點而言,較佳為電極間絕緣層105於層中包含氮(N)。The inter-electrode insulating layer 105 is, for example, silicon oxide, silicon oxynitride, or silicon nitride. From the viewpoint of suppressing the diffusion of copper from the electrode of the first electrode 101, it is preferable that the inter-electrode insulating layer 105 contains nitrogen (N) in the layer.

擴散防止層106為絕緣層。擴散防止層106具備抑制銅自第1電極101之電極向層間絕緣層107擴散之功能。較佳為擴散防止層106於層中包含氮(N)。擴散防止層106例如為氮化矽、或添加氮之碳化矽。The diffusion prevention layer 106 is an insulating layer. The diffusion prevention layer 106 has a function of suppressing copper diffusion from the electrode of the first electrode 101 to the interlayer insulating layer 107. It is preferable that the diffusion prevention layer 106 contains nitrogen (N) in the layer. The diffusion prevention layer 106 is, for example, silicon nitride or silicon carbide added with nitrogen.

層間絕緣層107例如為氧化矽。The interlayer insulating layer 107 is, for example, silicon oxide.

於記憶胞陣列110,例如三維地配置有非揮發性記憶體之記憶胞。記憶胞陣列110設置於2個接觸插塞103之間。In the memory cell array 110, for example, memory cells with non-volatile memory are three-dimensionally arranged. The memory cell array 110 is disposed between two contact plugs 103.

複數條字元線112於層間絕緣層107內,朝向z方向積層。複數條字元線112相對於第1記憶體層100之上表面、及下表面平行地於x方向延伸。字元線112之積層數例如為20層以上且100層以下。字元線112例如為金屬。A plurality of word lines 112 are stacked in the interlayer insulating layer 107 toward the z direction. The plural character lines 112 extend in the x direction parallel to the upper surface and the lower surface of the first memory layer 100. The number of stacked layers of the character line 112 is, for example, 20 layers or more and 100 layers or less. The character line 112 is, for example, metal.

複數個通道層113以與字元線112交叉之方式設置。通道層113相對於第1記憶體層100之上表面、及下表面於垂直方向延伸。通道層113之一端電性地連接於源極線111。通道層113例如為多晶矽。源極線111例如為多晶矽。The plurality of channel layers 113 are arranged to cross the word line 112. The channel layer 113 extends vertically with respect to the upper surface and the lower surface of the first memory layer 100. One end of the channel layer 113 is electrically connected to the source line 111. The channel layer 113 is, for example, polysilicon. The source line 111 is, for example, polysilicon.

複數條位元線114相對於第1記憶體層100之上表面、及下表面於平行方向延伸。通道層113之與源極線111為相反側之端部電性地連接於位元線114。The plurality of bit lines 114 extend parallel to the upper surface and the lower surface of the first memory layer 100. The end of the channel layer 113 opposite to the source line 111 is electrically connected to the bit line 114.

於字元線112之各者與通道層113之各者交叉之區域,例如設置有未圖示之電荷儲存層。字元線112之各者與通道層113之各者交叉之區域作為1個非揮發性之記憶胞而發揮功能。In a region where each of the word lines 112 and each of the channel layers 113 cross, for example, a charge storage layer (not shown) is provided. The area where each of the word lines 112 crosses each of the channel layers 113 functions as a non-volatile memory cell.

第2記憶體層200於具備擋止層208、犧牲層209之方面,與第1記憶體層100不同。電極202、接觸插塞203、配線層204、電極間絕緣層205、擴散防止層206、層間絕緣層207分別具有與第2電極102、接觸插塞103、配線層104、電極間絕緣層105、擴散防止層106、層間絕緣層107相同之構成。又,記憶胞陣列210具有與記憶胞陣列110相同之構成。記憶胞陣列210設置於2個接觸插塞203之間。The second memory layer 200 differs from the first memory layer 100 in that it includes a blocking layer 208 and a sacrificial layer 209. The electrode 202, the contact plug 203, the wiring layer 204, the inter-electrode insulating layer 205, the diffusion prevention layer 206, and the inter-layer insulating layer 207 have the second electrode 102, the contact plug 103, the wiring layer 104, and the inter-electrode insulating layer 105, The diffusion prevention layer 106 and the interlayer insulating layer 107 have the same structure. In addition, the memory cell array 210 has the same structure as the memory cell array 110. The memory cell array 210 is disposed between two contact plugs 203.

犧牲層209隔著電極間絕緣層205而設置。較佳為犧牲層209為可相對於電極間絕緣層205選擇性地蝕刻之材料。又,較佳為犧牲層209為能夠利用濕式蝕刻來蝕刻之材料。犧牲層209例如為多晶半導體。多晶半導體例如為多晶矽、或多晶矽鍺化物。The sacrificial layer 209 is provided via the inter-electrode insulating layer 205. Preferably, the sacrificial layer 209 is a material that can be selectively etched relative to the inter-electrode insulating layer 205. In addition, it is preferable that the sacrificial layer 209 be a material that can be etched by wet etching. The sacrificial layer 209 is, for example, a polycrystalline semiconductor. The polycrystalline semiconductor is, for example, polycrystalline silicon or polycrystalline silicon germanium compound.

擋止層208設置於電極間絕緣層205之下表面。擋止層208例如為氧化矽。The blocking layer 208 is disposed on the lower surface of the inter-electrode insulating layer 205. The blocking layer 208 is, for example, silicon oxide.

接觸插塞203與犧牲層209相接之區域之接觸插塞203之寬度較上述區域之犧牲層209之寬度窄。換言之,接觸插塞203與犧牲層209之接觸面附近之接觸插塞203之寬度較上述接觸面附近之犧牲層209之寬度窄。The width of the contact plug 203 in the area where the contact plug 203 is in contact with the sacrificial layer 209 is narrower than the width of the sacrificial layer 209 in the above area. In other words, the width of the contact plug 203 near the contact surface of the contact plug 203 and the sacrificial layer 209 is narrower than the width of the sacrificial layer 209 near the contact surface.

周邊電路層300設置於第1記憶體層100之上。電極301例如為包含銅(Cu)之金屬。於電極301之與接觸插塞302相接之區域、電極301之與層間絕緣層330相接之區域,例如設置有障壁金屬膜。障壁金屬膜例如為金屬氮化膜。金屬氮化膜例如為氮化鉭(TaN)、氮化鈦(TiN)、氮化鈮(NbN)。The peripheral circuit layer 300 is disposed on the first memory layer 100. The electrode 301 is, for example, a metal containing copper (Cu). For example, a barrier metal film is provided in a region where the electrode 301 is in contact with the contact plug 302 and a region where the electrode 301 is in contact with the interlayer insulating layer 330. The barrier metal film is, for example, a metal nitride film. The metal nitride film is, for example, tantalum nitride (TaN), titanium nitride (TiN), or niobium nitride (NbN).

接觸插塞302、配線層303、接觸插塞304例如為包含鎢(W)之金屬。The contact plug 302, the wiring layer 303, and the contact plug 304 are, for example, metals containing tungsten (W).

周邊電路309例如為記憶胞陣列110、及記憶胞陣列210之周邊電路。周邊電路309例如為感測放大器電路、字元線驅動器電路、列解碼器電路、行解碼器電路、升壓電路等。The peripheral circuit 309 is, for example, peripheral circuits of the memory cell array 110 and the memory cell array 210. The peripheral circuit 309 is, for example, a sense amplifier circuit, a word line driver circuit, a column decoder circuit, a row decoder circuit, a boost circuit, and the like.

元件分離區域307設置於矽基板308內。矽基板308為單晶之矽。元件分離區域307例如為氧化矽。The element separation region 307 is provided in the silicon substrate 308. The silicon substrate 308 is single crystal silicon. The element isolation region 307 is, for example, silicon oxide.

TSV305貫通矽基板308、及元件分離區域307而與配線層303相接。TSV305例如為包含銅之金屬。The TSV 305 penetrates the silicon substrate 308 and the element isolation region 307 and is in contact with the wiring layer 303. TSV305 is, for example, a metal containing copper.

電極墊400係為了獲得半導體記憶體與外部之電導通而設置。於電極墊400例如連接接合線。The electrode pad 400 is provided to obtain electrical conduction between the semiconductor memory and the outside. For example, a bonding wire is connected to the electrode pad 400.

其次,對實施形態之半導體裝置之製造方法進行說明。圖3~圖15係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。Next, a method of manufacturing the semiconductor device of the embodiment will be described. 3 to 15 are schematic cross-sectional views showing the semiconductor device in the middle of manufacturing in the method of manufacturing the semiconductor device of the embodiment.

實施形態之半導體裝置之製造方法係將具有半導體基板、半導體基板之上之絕緣層、絕緣層之上之犧牲層、設置於與半導體基板為相反側之表面之第1導電層、與犧牲層相接且與第1導電層電性地連接之第2導電層之第1半導體電路基板,與於表面具有第3導電層之第2半導體電路基板以第1導電層與第3導電層相接之方式貼合,且以犧牲層露出之方式將半導體基板與絕緣層去除,將犧牲層去除而形成開口部,於開口部埋入第4導電層,將第1半導體電路基板與於表面具有第5導電層之第3半導體電路基板以第4導電層與第5導電層相接之方式貼合。The manufacturing method of the semiconductor device of the embodiment includes a semiconductor substrate, an insulating layer on the semiconductor substrate, a sacrificial layer on the insulating layer, a first conductive layer provided on a surface opposite to the semiconductor substrate, and a phase with the sacrificial layer The first semiconductor circuit board connected to the second conductive layer electrically connected to the first conductive layer is connected to the second semiconductor circuit board having the third conductive layer on the surface via the first conductive layer and the third conductive layer Bonding, and the semiconductor substrate and the insulating layer are removed with the sacrificial layer exposed, the sacrificial layer is removed to form an opening, the fourth conductive layer is buried in the opening, and the first semiconductor circuit board and the surface have a fifth The third semiconductor circuit board of the conductive layer is bonded so that the fourth conductive layer and the fifth conductive layer are in contact with each other.

首先,製造第1半導體晶圓150(第1半導體電路基板)。於矽基板120(半導體基板)之上形成擋止層108(絕緣層)。擋止層108作為於後續步驟中將矽基板120去除時之蝕刻擋止層而發揮功能。擋止層108例如為氧化矽。於擋止層108之上,形成犧牲層109(圖3)。犧牲層109例如為多晶矽。First, the first semiconductor wafer 150 (first semiconductor circuit board) is manufactured. A blocking layer 108 (insulating layer) is formed on the silicon substrate 120 (semiconductor substrate). The blocking layer 108 functions as an etching blocking layer when the silicon substrate 120 is removed in the subsequent steps. The blocking layer 108 is, for example, silicon oxide. On the blocking layer 108, a sacrificial layer 109 is formed (FIG. 3). The sacrificial layer 109 is, for example, polysilicon.

其次,於犧牲層109之間形成電極間絕緣層105。電極間絕緣層105例如為氧化矽。於電極間絕緣層105之上形成擴散防止層106(圖4)。擴散防止層106例如為氮化矽。Next, an inter-electrode insulating layer 105 is formed between the sacrificial layers 109. The inter-electrode insulating layer 105 is, for example, silicon oxide. A diffusion prevention layer 106 is formed on the inter-electrode insulating layer 105 (FIG. 4). The diffusion prevention layer 106 is, for example, silicon nitride.

其次,於擴散防止層106之上形成層間絕緣層107。層間絕緣層107例如為氧化矽。於層間絕緣層107之中,形成源極線111、字元線112、及通道層113。形成自層間絕緣層107之上表面到達犧牲層109之接觸孔121(圖5)。Next, an interlayer insulating layer 107 is formed on the diffusion prevention layer 106. The interlayer insulating layer 107 is, for example, silicon oxide. In the interlayer insulating layer 107, a source line 111, a word line 112, and a channel layer 113 are formed. A contact hole 121 is formed from the upper surface of the interlayer insulating layer 107 to the sacrificial layer 109 (FIG. 5).

其次,於接觸孔121之中形成接觸插塞103(第2導電層)(圖6)。接觸插塞103例如為包含鎢之金屬。Next, a contact plug 103 (second conductive layer) is formed in the contact hole 121 (FIG. 6). The contact plug 103 is, for example, a metal containing tungsten.

其次,於層間絕緣層107之上表面,形成與接觸插塞103相接之配線層104、及與通道層113相接之位元線114(圖7)。配線層104、及位元線114例如為包含鎢之金屬。Next, on the upper surface of the interlayer insulating layer 107, a wiring layer 104 in contact with the contact plug 103 and a bit line 114 in contact with the channel layer 113 are formed (FIG. 7). The wiring layer 104 and the bit line 114 are, for example, metals containing tungsten.

其次,與層間絕緣層107一體化,形成成為層間絕緣層107之一部分之絕緣層。其次,形成與配線層104相接之第2電極102(第1導電層)(圖8)。第2電極102電性地連接於接觸插塞103。第2電極102例如為包含銅之金屬。Next, it is integrated with the interlayer insulating layer 107 to form an insulating layer that becomes a part of the interlayer insulating layer 107. Next, the second electrode 102 (first conductive layer) in contact with the wiring layer 104 is formed (FIG. 8). The second electrode 102 is electrically connected to the contact plug 103. The second electrode 102 is, for example, a metal containing copper.

根據以上之步驟,製造第1半導體晶圓150。According to the above steps, the first semiconductor wafer 150 is manufactured.

其次,使預先製造之第2半導體晶圓350(第2半導體電路基板)與第1半導體晶圓150貼合(圖9)。於第2半導體晶圓350,形成有電極301(第3導電層)、接觸插塞302、配線層303、接觸插塞304、元件分離區域307、矽基板308、周邊電路309、及層間絕緣層330。周邊電路309具備第1電晶體310、第2電晶體320。第1電晶體310具備源極、汲極區域311、閘極電極312、及閘極絕緣膜313。第2電晶體320具備源極、汲極區域321、閘極電極322、及閘極絕緣膜323。Next, the second semiconductor wafer 350 (second semiconductor circuit board) manufactured in advance and the first semiconductor wafer 150 are bonded (FIG. 9 ). On the second semiconductor wafer 350, an electrode 301 (third conductive layer), a contact plug 302, a wiring layer 303, a contact plug 304, an element isolation region 307, a silicon substrate 308, a peripheral circuit 309, and an interlayer insulating layer are formed 330. The peripheral circuit 309 includes a first transistor 310 and a second transistor 320. The first transistor 310 includes a source, a drain region 311, a gate electrode 312, and a gate insulating film 313. The second transistor 320 includes a source, a drain region 321, a gate electrode 322, and a gate insulating film 323.

第1半導體晶圓150與第2半導體晶圓350係以第1半導體晶圓150之第2電極102與第2半導體晶圓350之電極301直接相接之方式貼合。The first semiconductor wafer 150 and the second semiconductor wafer 350 are bonded in such a manner that the second electrode 102 of the first semiconductor wafer 150 directly contacts the electrode 301 of the second semiconductor wafer 350.

於將第1半導體晶圓150與第2半導體晶圓350貼合時,例如,對第1半導體晶圓150之表面及第2半導體晶圓350之表面之至少任一者進行電漿處理。When bonding the first semiconductor wafer 150 and the second semiconductor wafer 350, for example, at least any one of the surface of the first semiconductor wafer 150 and the surface of the second semiconductor wafer 350 is subjected to plasma treatment.

其次,將矽基板120去除(圖10)。矽基板120例如係於利用背面研削而薄膜化之後,使用鹼系之濕式蝕刻來完全去除。Next, the silicon substrate 120 is removed (FIG. 10). After the silicon substrate 120 is thinned by back grinding, for example, it is completely removed using alkaline wet etching.

其次,將擋止層108以犧牲層109露出之方式去除(圖11)。氧化矽之擋止層108例如利用氟酸系之濕式蝕刻來去除。Next, the blocking layer 108 is removed with the sacrificial layer 109 exposed (FIG. 11). The blocking layer 108 of silicon oxide is removed by, for example, wet etching using a hydrofluoric acid system.

其次,將犧牲層109選擇性地去除,形成開口部122(圖12)。多晶矽之犧牲層109係使用鹼系之濕式蝕刻而選擇性地去除。Next, the sacrificial layer 109 is selectively removed to form an opening 122 (FIG. 12). The sacrificial layer 109 of polysilicon is selectively removed by wet etching using an alkali system.

其次,於開口部122埋入第1電極101(第4導電層)(圖13)。第1電極101例如係藉由利用無電解鍍覆法埋入鍍銅而形成。Next, the first electrode 101 (fourth conductive layer) is buried in the opening 122 (FIG. 13 ). The first electrode 101 is formed by, for example, embedding copper plating by electroless plating.

其次,使預先製造之第3半導體晶圓250(第3半導體電路基板)與第1半導體晶圓150貼合(圖14)。於第3半導體晶圓250,於矽基板220形成有電極202(第5導電層)、接觸插塞203、配線層204、電極間絕緣層205、擴散防止層206、層間絕緣層207、擋止層208、犧牲層209、及記憶胞陣列210。記憶胞陣列210具備源極線211、字元線212、通道層213、及位元線214。第3半導體晶圓250具備與圖8所示之第1半導體晶圓相同之構造。Next, the third semiconductor wafer 250 (third semiconductor circuit board) manufactured in advance is bonded to the first semiconductor wafer 150 (FIG. 14 ). On the third semiconductor wafer 250, an electrode 202 (fifth conductive layer), a contact plug 203, a wiring layer 204, an inter-electrode insulating layer 205, a diffusion prevention layer 206, an inter-layer insulating layer 207, and a stopper are formed on the silicon substrate 220 Layer 208, sacrificial layer 209, and memory cell array 210. The memory cell array 210 includes a source line 211, a word line 212, a channel layer 213, and a bit line 214. The third semiconductor wafer 250 has the same structure as the first semiconductor wafer shown in FIG. 8.

第1半導體晶圓150與第3半導體晶圓250係以第1半導體晶圓150之第1電極101與第3半導體晶圓250之電極202直接相接之方式貼合。The first semiconductor wafer 150 and the third semiconductor wafer 250 are bonded in such a manner that the first electrode 101 of the first semiconductor wafer 150 and the electrode 202 of the third semiconductor wafer 250 directly contact each other.

於將第1半導體晶圓150與第3半導體晶圓250貼合時,例如,對第1半導體晶圓150之表面及第3半導體晶圓250之表面之至少任一者進行電漿處理。When the first semiconductor wafer 150 and the third semiconductor wafer 250 are bonded, for example, at least any one of the surface of the first semiconductor wafer 150 and the surface of the third semiconductor wafer 250 is plasma-processed.

其次,將矽基板220去除(圖15)。矽基板220例如係利用背面研削而薄膜化之後,使用鹼系之濕式蝕刻來完全去除。Next, the silicon substrate 220 is removed (FIG. 15). After the silicon substrate 220 is thinned by back grinding, for example, it is completely removed by wet etching using an alkali system.

其次,形成TSV305與電極墊400。Next, TSV 305 and electrode pad 400 are formed.

其次,例如,使用切割裝置,將形成於貼合第1半導體晶圓150、第2半導體晶圓350、第3半導體晶圓250而成之積層晶圓之複數個半導體記憶體單片化。利用以上之製造方法形成圖1所示之半導體記憶體。Next, for example, using a dicing device, a plurality of semiconductor memories formed on the laminated wafer formed by bonding the first semiconductor wafer 150, the second semiconductor wafer 350, and the third semiconductor wafer 250 are singulated. The semiconductor memory shown in FIG. 1 is formed by the above manufacturing method.

其次,對實施形態之半導體裝置之作用及效果進行說明。Next, the operation and effect of the semiconductor device of the embodiment will be described.

實施形態之半導體記憶體藉由將第1記憶體層100與第2記憶體層200積層來實現記憶容量較大之半導體記憶體。又,藉由將第1記憶體層100與第2記憶體層200,第1記憶體層100與周邊電路層300直接貼合,例如,半導體記憶體之晶片尺寸變小。又,例如,減少半導體電路間之配線延遲或電阻損耗,半導體記憶體高性能化。The semiconductor memory of the embodiment realizes a semiconductor memory having a larger memory capacity by stacking the first memory layer 100 and the second memory layer 200. In addition, by bonding the first memory layer 100 and the second memory layer 200 directly to the first memory layer 100 and the peripheral circuit layer 300, for example, the chip size of the semiconductor memory becomes smaller. In addition, for example, the wiring delay or resistance loss between semiconductor circuits is reduced, and the semiconductor memory is improved in performance.

當於器件之上表面及下表面之各者貼合不同之器件之情形時,必須於器件之正面及背面形成用以將器件間電性地連接之電極。要求於器件設置輸入輸出信號之傳遞用、控制信號之傳遞用、電源供給用等多數個電極。因此,例如,若自加工精度決定之電極之配置間距變大,則成為半導體裝置之晶片尺寸之縮小之障礙。尤其,於製造器件時之最終形成之器件之背面側之電極之間距與正面側之電極之間距相較變小較為困難。其原因在於,例如,於背面側之微影時,必須進行與正面之結合且結合精度較差,進而,與正面側相比基底之平坦性較差,高精度之圖案化困難。When attaching different devices to the upper and lower surfaces of the device, electrodes must be formed on the front and back of the device to electrically connect the devices. It is required that the device be provided with a plurality of electrodes for input and output signal transmission, control signal transmission, and power supply. Therefore, for example, if the arrangement pitch of the electrodes determined by the processing accuracy becomes larger, it becomes an obstacle to shrinking the wafer size of the semiconductor device. In particular, it is difficult to reduce the distance between the electrodes on the back side and the distance between the electrodes on the front side of the finally formed device when manufacturing the device. The reason for this is that, for example, in the lithography on the back side, the bonding with the front side must be performed and the bonding accuracy is poor. Furthermore, the flatness of the substrate is inferior to the front side, and high-precision patterning is difficult.

圖16係第1比較形態之半導體裝置之一部分之放大模式剖視圖。圖16係第1比較形態之半導體裝置之與圖2對應之部分之模式剖視圖。16 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first comparative form. 16 is a schematic cross-sectional view of a part corresponding to FIG. 2 of the semiconductor device of the first comparative form.

圖16所示之第1比較形態之半導體裝置具備電極901、接觸插塞903、電極間絕緣層905、擴散防止層906、及層間絕緣層907。分別與實施形態之第1電極101、接觸插塞103、電極間絕緣層105、擴散防止層106、及層間絕緣層107對應。The semiconductor device of the first comparative form shown in FIG. 16 includes an electrode 901, a contact plug 903, an inter-electrode insulating layer 905, a diffusion prevention layer 906, and an inter-layer insulating layer 907. Each corresponds to the first electrode 101, the contact plug 103, the inter-electrode insulating layer 105, the diffusion prevention layer 106, and the inter-layer insulating layer 107 of the embodiment.

電極901例如為包含銅(Cu)之金屬。The electrode 901 is, for example, a metal containing copper (Cu).

接觸插塞903之材質例如與電極901之材質不同。接觸插塞103例如為包含鎢(W)之金屬。The material of the contact plug 903 is different from the material of the electrode 901, for example. The contact plug 103 is, for example, a metal containing tungsten (W).

接觸插塞903具備與電極901相接之障壁金屬膜903a。障壁金屬膜903a例如為金屬氮化膜。金屬氮化膜例如為氮化鉭(TaN)、氮化鈦(TiN)、氮化鈮(NbN)。障壁金屬膜903a亦與層間絕緣層907、及擴散防止層906相接。The contact plug 903 includes a barrier metal film 903a in contact with the electrode 901. The barrier metal film 903a is, for example, a metal nitride film. The metal nitride film is, for example, tantalum nitride (TaN), titanium nitride (TiN), or niobium nitride (NbN). The barrier metal film 903a is also in contact with the interlayer insulating layer 907 and the diffusion prevention layer 906.

接觸插塞903與電極901接觸區域之接觸插塞903之寬度(圖16中之W3)較上述區域之電極901之寬度(圖16中之W2)寬。The width of the contact plug 903 in the contact area of the contact plug 903 and the electrode 901 (W3 in FIG. 16) is wider than the width of the electrode 901 in the above area (W2 in FIG. 16).

電極901之寬度例如由於起因於加工之限制、或者起因於電特性之限制而需要特定之寬度。特定之寬度設為圖2及圖16之W2。於第1比較形態之情形時,接觸插塞903之寬度(圖16中之W3)較特定之寬度W2寬。必須使相鄰之2個電極901之間之距離與實施形態之情況相比變大接觸插塞903變寬之量。因此,電極901之配置間距變大,成為晶片尺寸之縮小之障礙。The width of the electrode 901 requires a specific width due to, for example, processing limitations or electrical characteristics. The specific width is set to W2 in FIGS. 2 and 16. In the case of the first comparative form, the width of the contact plug 903 (W3 in FIG. 16) is wider than the specific width W2. The distance between the two adjacent electrodes 901 must be larger than in the embodiment, and the contact plug 903 must be widened. Therefore, the arrangement pitch of the electrodes 901 becomes larger, which becomes an obstacle to shrinking the size of the wafer.

於實施形態之半導體裝置之情形時,如圖2所示,接觸插塞103之第1寬度(圖2中之W1)較第1電極101之第2寬度(圖2中之W2)窄。因此,第1電極101之配置間距例如能夠小至微影之極限為止,不會成為半導體裝置之晶片尺寸之縮小之障礙。換言之,實施形態之半導體裝置之電極構造適合於半導體裝置之晶片尺寸之縮小。In the case of the semiconductor device of the embodiment, as shown in FIG. 2, the first width of the contact plug 103 (W1 in FIG. 2) is narrower than the second width of the first electrode 101 (W2 in FIG. 2). Therefore, the arrangement pitch of the first electrode 101 can be as small as the limit of lithography, for example, and does not become an obstacle to shrinking the wafer size of the semiconductor device. In other words, the electrode structure of the semiconductor device of the embodiment is suitable for the reduction of the wafer size of the semiconductor device.

圖17係第2比較形態之半導體裝置之一部分之放大模式剖視圖。圖17係第2比較形態之半導體裝置之與圖2對應之部分之模式剖視圖。17 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the second comparative form. 17 is a schematic cross-sectional view of a part corresponding to FIG. 2 of the semiconductor device of the second comparative form.

圖17所示之第2比較形態之半導體裝置與圖16相同,電極901、接觸插塞903、電極間絕緣層905、擴散防止層906、及層間絕緣層907分別與實施形態之第1電極101、接觸插塞103、電極間絕緣層105、擴散防止層106、及層間絕緣層107對應。The semiconductor device of the second comparative embodiment shown in FIG. 17 is the same as that of FIG. 16, and the electrode 901, the contact plug 903, the inter-electrode insulating layer 905, the diffusion prevention layer 906, and the inter-layer insulating layer 907 are the same as the first electrode 101 of the embodiment. , The contact plug 103, the inter-electrode insulating layer 105, the diffusion prevention layer 106, and the inter-layer insulating layer 107 correspond.

該第2比較形態之半導體裝置進而具備中間層908。中間層908為導電層。中間層908例如為包含鎢(W)之金屬。電極901與接觸插塞903經由中間層908而電性地連接。The semiconductor device of the second comparative aspect further includes an intermediate layer 908. The intermediate layer 908 is a conductive layer. The intermediate layer 908 is, for example, a metal containing tungsten (W). The electrode 901 and the contact plug 903 are electrically connected via the intermediate layer 908.

中間層908之寬度(圖17中之W4)較電極901之寬度(圖17中之W2)更寬。The width of the intermediate layer 908 (W4 in FIG. 17) is wider than the width of the electrode 901 (W2 in FIG. 17).

電極901之寬度例如由於加工所致之限制、或者因電特性之限制而需要特定之寬度。特定之寬度設為圖2及圖17之W2。如為第2比較形態之情形,中間層908之寬度(圖17中之W4)較特定之寬度W2更寬。必須對應於中間層908變寬之量,將相鄰之2個電極901之間之距離設為比實施形態更大。因此,電極901之配置間距變大,而阻礙半導體裝置之晶片尺寸之縮小。The width of the electrode 901 requires a specific width due to, for example, processing limitations or electrical characteristics. The specific width is set to W2 in FIGS. 2 and 17. In the case of the second comparative form, the width of the intermediate layer 908 (W4 in FIG. 17) is wider than the specific width W2. It is necessary to make the distance between two adjacent electrodes 901 larger than the embodiment in accordance with the amount of the intermediate layer 908 becoming wider. Therefore, the arrangement pitch of the electrodes 901 becomes larger, which hinders the shrinking of the wafer size of the semiconductor device.

如為實施形態之半導體裝置之情形,如圖2所示,接觸插塞103之第1寬度(圖2中之W1)較第1電極101之第2寬度(圖2中之W2)更窄。因此,第1電極101之配置間距例如能夠小至微影之極限,不會阻礙半導體裝置之晶片尺寸之縮小。換言之,實施形態之半導體裝置之電極構造適合於半導體裝置之晶片尺寸之縮小。In the case of the semiconductor device of the embodiment, as shown in FIG. 2, the first width of the contact plug 103 (W1 in FIG. 2) is narrower than the second width of the first electrode 101 (W2 in FIG. 2). Therefore, the arrangement pitch of the first electrode 101 can be reduced to the limit of lithography, for example, and does not hinder the reduction in the size of the semiconductor device wafer. In other words, the electrode structure of the semiconductor device of the embodiment is suitable for the reduction of the wafer size of the semiconductor device.

實施形態之半導體裝置藉由使用實施形態之半導體裝置之製造方法,能夠容易地以低成本製造。The semiconductor device of the embodiment can be easily manufactured at low cost by using the method of manufacturing the semiconductor device of the embodiment.

其次,對實施形態之製造方法之作用及效果進行說明。Next, the function and effect of the manufacturing method of the embodiment will be described.

當於器件之上表面及下表面之各者貼合不同之器件之情形時,必須於器件之正面及背面形成用以將器件間電性地連接之電極。當於器件之背面側形成電極之情形時,若使用製程成本較高之微影或乾式蝕刻,則將器件貼合而製造之半導體裝置之製造成本增大。又,一般而言,由於基底之平坦性之影響等,因而背面側之微影之加工精度與正面側之微影之加工精度相比精度較低,故而有電極之配置間距變大之虞。因此,有難以縮小半導體裝置之晶片尺寸之虞。When attaching different devices to the upper and lower surfaces of the device, electrodes must be formed on the front and back of the device to electrically connect the devices. When an electrode is formed on the back side of the device, if lithography or dry etching with a relatively high process cost is used, the manufacturing cost of the semiconductor device manufactured by bonding the device increases. In addition, generally speaking, due to the influence of the flatness of the substrate and the like, the processing accuracy of the lithography on the back side is lower than the processing accuracy of the lithography on the front side, so the arrangement pitch of the electrodes may be increased. Therefore, it may be difficult to reduce the wafer size of the semiconductor device.

於實施形態中,例如於第1半導體晶圓150中,將圖8所示之犧牲層109形成於之後成為背面側之第1電極101之區域。且,於將第1半導體晶圓150與第3半導體晶圓250貼合之前,將犧牲層109去除(圖12)。將犧牲層109之材料設為能夠利用濕式蝕刻而選擇性地去除之材料。藉此,不使用製程成本較高之微影或乾式蝕刻,便可形成第1半導體晶圓150之背面側之第1電極101。因此,可降低半導體裝置之製造成本。In the embodiment, for example, in the first semiconductor wafer 150, the sacrificial layer 109 shown in FIG. 8 is formed in a region that will become the first electrode 101 on the back side later. And, before bonding the first semiconductor wafer 150 and the third semiconductor wafer 250, the sacrificial layer 109 is removed (FIG. 12). The material of the sacrificial layer 109 can be selectively removed by wet etching. In this way, the first electrode 101 on the back side of the first semiconductor wafer 150 can be formed without using lithography or dry etching, which has a relatively high process cost. Therefore, the manufacturing cost of the semiconductor device can be reduced.

又,可不使用微影及乾式蝕刻而加工背面側之第1電極101。因此,例如,亦不需要設置如圖17所示之中間層908作為蝕刻之擋止層。因此,能夠將電極之配置間距縮小。因此,背面側之第1電極101不會阻礙半導體裝置之晶片尺寸之縮小。In addition, the first electrode 101 on the back side may be processed without using lithography and dry etching. Therefore, for example, it is not necessary to provide the intermediate layer 908 as shown in FIG. 17 as an etching stopper. Therefore, the arrangement pitch of the electrodes can be reduced. Therefore, the first electrode 101 on the back side does not hinder the reduction of the wafer size of the semiconductor device.

又,背面側之第1電極101之配置間距成為犧牲層109之配置間距。犧牲層109由於利用加工精度較高之正面側之微影來形成,故而可使配置間距變小。因此,可使背面側之第1電極101之配置間距變小,從而半導體裝置之晶片尺寸之縮小成為可能。In addition, the arrangement pitch of the first electrode 101 on the back side becomes the arrangement pitch of the sacrificial layer 109. Since the sacrificial layer 109 is formed using the lithography on the front side with high processing accuracy, the arrangement pitch can be reduced. Therefore, the arrangement pitch of the first electrodes 101 on the back side can be reduced, and the wafer size of the semiconductor device can be reduced.

圖18係變化例之半導體裝置之模式剖視圖。於將接觸插塞103設置於2個記憶胞110之間,將接觸插塞203設置於2個記憶胞210之間之方面與實施形態不同。18 is a schematic cross-sectional view of a semiconductor device according to a modification. The arrangement of the contact plug 103 between the two memory cells 110 and the contact plug 203 between the two memory cells 210 is different from the embodiment.

於實施形態中,以將具有記憶胞陣列之記憶體層積層2層之情況為例進行了說明,但亦能夠藉由積層3層以上,進而使半導體記憶體之記憶容量增大。In the embodiment, the case where the memory cell having the memory cell array is laminated in two layers has been described as an example, but it is also possible to increase the memory capacity of the semiconductor memory by laminating more than three layers.

於實施形態中,以半導體裝置為半導體記憶體之情況為例進行了說明。然而,亦能夠將本發明應用於半導體記憶體以外之半導體裝置,例如,邏輯裝置、CMOS(Complementary Metal Oxide Semiconductor,互補金屬氧化物半導體)感測器等。In the embodiment, the case where the semiconductor device is a semiconductor memory has been described as an example. However, the present invention can also be applied to semiconductor devices other than semiconductor memory, such as logic devices, CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) sensors, and the like.

以上,對本發明之幾個實施形態進行了說明,但該等實施形態係作為示例而提出,並不意圖限定發明之範圍。該等新穎之實施形態能夠以其他各種形態實施,可於不脫離發明之主旨之範圍內,進行各種省略、置換、變更。例如,亦可以將一實施形態之構成要素置換或變更為其他實施形態之構成要素。該等實施形態或其變化包含於發明之範圍或主旨中,並且包含於申請專利範圍所記載之發明與其均等之範圍中。In the above, several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. For example, the constituent elements of one embodiment may be replaced or changed to those of other embodiments. These embodiments or their changes are included in the scope or gist of the invention, and are included in the invention described in the patent application and its equivalent scope.

100:第1記憶體層(第3半導體電路層)101:第1電極(第3導電層)102:第2電極(第4導電層)103:接觸插塞(第5導電層)103a:金屬氮化膜104:配線層105:電極間絕緣層106:擴散防止層(包含氮之絕緣層)107:層間絕緣層108:擋止層109:犧牲層110:記憶胞陣列111:源極線112:字元線113:通道層114:位元線120:矽基板121:接觸孔150:第1晶圓(第1半導體電路基板)200:第2記憶體層(第1半導體電路層)202:電極(第1導電層)203:接觸插塞(第6導電層)204:配線層205:電極間絕緣層206:擴散防止層207:層間絕緣層208:擋止層209:犧牲層(多晶半導體層)210:記憶胞陣列211:源極線212:字元線213:通道層214:位元線220:矽基板250:第3半導體晶圓(第3半導體電路基板)300:周邊電路層(第2半導體電路層)301:電極(第2導電層)302:接觸插塞303:配線層304:接觸插塞305:TSV307:元件分離區域308:矽基板309:周邊電路310:第1電晶體(MISFET)311:閘極電極312:閘極絕緣膜313:源極、汲極區域320:第2電晶體321:源極、汲極區域322:閘極電極323:閘極絕緣膜330:層間絕緣層350:第2半導體晶圓(第2半導體電路基板)400:電極墊901:電極903:接觸插塞903a:障壁金屬膜905:電極間絕緣層906:擴散防止層907:層間絕緣層908:中間層W1:第1寬度W2:第2寬度W3:寬度100: first memory layer (third semiconductor circuit layer) 101: first electrode (third conductive layer) 102: second electrode (fourth conductive layer) 103: contact plug (fifth conductive layer) 103a: metal nitrogen Chemical film 104: wiring layer 105: inter-electrode insulating layer 106: diffusion prevention layer (insulating layer containing nitrogen) 107: inter-layer insulating layer 108: blocking layer 109: sacrificial layer 110: memory cell array 111: source line 112: Word line 113: channel layer 114: bit line 120: silicon substrate 121: contact hole 150: first wafer (first semiconductor circuit board) 200: second memory layer (first semiconductor circuit layer) 202: electrode ( (First conductive layer) 203: contact plug (sixth conductive layer) 204: wiring layer 205: inter-electrode insulating layer 206: diffusion prevention layer 207: inter-layer insulating layer 208: barrier layer 209: sacrificial layer (polycrystalline semiconductor layer) ) 210: memory cell array 211: source line 212: word line 213: channel layer 214: bit line 220: silicon substrate 250: third semiconductor wafer (third semiconductor circuit board) 300: peripheral circuit layer (first 2 semiconductor circuit layer) 301: electrode (second conductive layer) 302: contact plug 303: wiring layer 304: contact plug 305: TSV307: element separation region 308: silicon substrate 309: peripheral circuit 310: first transistor ( MISFET) 311: Gate electrode 312: Gate insulating film 313: Source and drain regions 320: Second transistor 321: Source and drain regions 322: Gate electrode 323: Gate insulating film 330: Interlayer insulation Layer 350: second semiconductor wafer (second semiconductor circuit board) 400: electrode pad 901: electrode 903: contact plug 903a: barrier metal film 905: inter-electrode insulating layer 906: diffusion prevention layer 907: inter-layer insulating layer 908: Middle layer W1: 1st width W2: 2nd width W3: width

圖1係實施形態之半導體裝置之模式剖視圖。 圖2係實施形態之半導體裝置之一部分之放大模式剖視圖。 圖3係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖4係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖5係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖6係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖7係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖8係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖9係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖10係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖11係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖12係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖13係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖14係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖15係表示於實施形態之半導體裝置之製造方法中,製造中途之半導體裝置之模式剖視圖。 圖16係實施形態之半導體裝置之作用及效果之說明圖。 圖17係實施形態之半導體裝置之作用及效果之說明圖。 圖18係變化例之半導體裝置之模式剖視圖。FIG. 1 is a schematic cross-sectional view of a semiconductor device of an embodiment. 2 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the embodiment. 3 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 4 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 5 is a schematic cross-sectional view of a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 6 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 7 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 8 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 9 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 10 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 11 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 12 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 13 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 14 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 15 is a schematic cross-sectional view showing a semiconductor device in the middle of manufacturing in the method of manufacturing a semiconductor device of the embodiment. 16 is an explanatory diagram of the function and effect of the semiconductor device of the embodiment. 17 is an explanatory diagram of the operation and effect of the semiconductor device of the embodiment. 18 is a schematic cross-sectional view of a semiconductor device according to a modification.

100:第1記憶體層(第3半導體電路層) 100: 1st memory layer (3rd semiconductor circuit layer)

101:第1電極(第3導電層) 101: 1st electrode (3rd conductive layer)

102:第2電極(第4導電層) 102: 2nd electrode (4th conductive layer)

103:接觸插塞(第5導電層) 103: Contact plug (5th conductive layer)

104:配線層 104: wiring layer

105:電極間絕緣層 105: insulating layer between electrodes

106:擴散防止層(包含氮之絕緣層) 106: Diffusion prevention layer (insulation layer containing nitrogen)

107:層間絕緣層 107: Interlayer insulation

110:記憶胞陣列 110: memory cell array

111:源極線 111: source line

112:字元線 112: character line

113:通道層 113: Channel layer

114:位元線 114: bit line

200:第2記憶體層(第1半導體電路層) 200: 2nd memory layer (1st semiconductor circuit layer)

202:電極(第1導電層) 202: electrode (first conductive layer)

203:接觸插塞(第6導電層) 203: Contact plug (6th conductive layer)

204:配線層 204: wiring layer

205:電極間絕緣層 205: insulating layer between electrodes

206:擴散防止層 206: Diffusion prevention layer

207:層間絕緣層 207: Interlayer insulation

208:擋止層 208: stop layer

209:犧牲層(多晶半導體層) 209: Sacrificial layer (polycrystalline semiconductor layer)

210:記憶胞陣列 210: memory cell array

211:源極線 211: Source line

212:字元線 212: character line

213:通道層 213: Channel layer

214:位元線 214: bit line

300:周邊電路層(第2半導體電路層) 300: peripheral circuit layer (second semiconductor circuit layer)

301:電極(第2導電層) 301: electrode (second conductive layer)

302:接觸插塞 302: contact plug

303:配線層 303: wiring layer

304:接觸插塞 304: contact plug

305:TSV 305:TSV

307:元件分離區域 307: component separation area

308:矽基板 308: Silicon substrate

309:周邊電路 309: Peripheral circuit

310:第1電晶體(MISFET) 310: The first transistor (MISFET)

311:閘極電極 311: Gate electrode

312:閘極絕緣膜 312: Gate insulating film

313:源極、汲極區域 313: source and drain regions

320:第2電晶體 320: 2nd transistor

321:源極、汲極區域 321: source and drain regions

322:閘極電極 322: Gate electrode

323:閘極絕緣膜 323: Gate insulating film

330:層間絕緣層 330: Interlayer insulation

400:電極墊 400: electrode pad

Claims (20)

一種半導體裝置,其具備: 第1半導體電路層,其具有第1導電層; 第2半導體電路層,其具有第2導電層;以及 第3半導體電路層,其設置於上述第1半導體電路層與上述第2半導體電路層之間,且具有與上述第1導電層相接之第3導電層、與上述第2導電層相接之第4導電層、及將上述第3導電層與上述第4導電層電性地連接且與上述第3導電層相接之第5導電層; 上述第5導電層之寬度較上述第3導電層之寬度更窄。A semiconductor device includes: a first semiconductor circuit layer having a first conductive layer; a second semiconductor circuit layer having a second conductive layer; and a third semiconductor circuit layer provided on the first semiconductor circuit layer and Between the second semiconductor circuit layer, a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a third conductive layer in contact with the fourth The conductive layer is electrically connected to the fifth conductive layer that is in contact with the third conductive layer; the width of the fifth conductive layer is narrower than the width of the third conductive layer. 如請求項1之半導體裝置,其中上述第3導電層之材質與上述第5導電層之材質不同。The semiconductor device according to claim 1, wherein the material of the third conductive layer is different from the material of the fifth conductive layer. 如請求項1之半導體裝置,其中上述第1導電層、上述第2導電層、上述第3導電層、上述第4導電層包含銅(Cu)。The semiconductor device according to claim 1, wherein the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer include copper (Cu). 如請求項1之半導體裝置,其中上述第5導電層包含鎢。The semiconductor device according to claim 1, wherein the fifth conductive layer contains tungsten. 如請求項1之半導體裝置,其中上述第5導電層包含與上述第3導電層相接之金屬氮化膜。The semiconductor device according to claim 1, wherein the fifth conductive layer includes a metal nitride film in contact with the third conductive layer. 如請求項1之半導體裝置,其中上述第3半導體電路層具有積層有複數個記憶胞之三維構造之記憶胞陣列。The semiconductor device according to claim 1, wherein the third semiconductor circuit layer has a three-dimensional memory cell array in which a plurality of memory cells are stacked. 如請求項1之半導體裝置,其中上述第2半導體電路層具有MISFET。The semiconductor device according to claim 1, wherein the second semiconductor circuit layer has a MISFET. 如請求項6之半導體裝置,其中上述第2半導體電路層具有上述記憶胞陣列之周邊電路。The semiconductor device according to claim 6, wherein the second semiconductor circuit layer has peripheral circuits of the memory cell array. 如請求項6之半導體裝置,其中於上述第3導電層與上述記憶胞陣列之間具有包含氮之絕緣層。The semiconductor device according to claim 6, wherein an insulating layer containing nitrogen is provided between the third conductive layer and the memory cell array. 如請求項1之半導體裝置,其中上述第1半導體電路層進而具備:多晶半導體層,其包含矽;及第6導電層,其設置於上述第1導電層與上述多晶半導體層之間,電性地連接於上述第1導電層,且與上述多晶半導體層相接;上述第6導電層之寬度較上述多晶半導體層之寬度更窄。The semiconductor device according to claim 1, wherein the first semiconductor circuit layer further includes: a polycrystalline semiconductor layer including silicon; and a sixth conductive layer provided between the first conductive layer and the polycrystalline semiconductor layer, It is electrically connected to the first conductive layer and is in contact with the polycrystalline semiconductor layer; the width of the sixth conductive layer is narrower than the width of the polycrystalline semiconductor layer. 一種半導體裝置之製造方法,其將具有半導體基板、上述半導體基板之上之絕緣層、上述絕緣層之上之犧牲層、設置於與上述半導體基板為相反側之表面之第1導電層、以及與上述犧牲層相接且與上述第1導電層電性地連接之第2導電層之第1半導體電路基板、與於表面具有第3導電層之第2半導體電路基板,以上述第1導電層與上述第3導電層相接之方式貼合, 以上述犧牲層露出之方式,將上述半導體基板與上述絕緣層去除, 將上述犧牲層去除而形成開口部, 於上述開口部埋入第4導電層, 將上述第1半導體電路基板與於表面具有第5導電層之第3半導體電路基板,以上述第4導電層與上述第5導電層相接之方式貼合。A method of manufacturing a semiconductor device comprising a semiconductor substrate, an insulating layer on the semiconductor substrate, a sacrificial layer on the insulating layer, a first conductive layer provided on a surface opposite to the semiconductor substrate, and The first semiconductor circuit substrate of the second conductive layer that is in contact with the sacrificial layer and electrically connected to the first conductive layer, and the second semiconductor circuit substrate that has a third conductive layer on the surface, and the first conductive layer and The third conductive layer is bonded together, the semiconductor substrate and the insulating layer are removed with the sacrificial layer exposed, the sacrificial layer is removed to form an opening, and the fourth conductive layer is buried in the opening , The first semiconductor circuit board and the third semiconductor circuit board having a fifth conductive layer on the surface are bonded so that the fourth conductive layer and the fifth conductive layer are in contact with each other. 如請求項11之半導體裝置之製造方法,其中上述犧牲層為包含矽之多晶半導體。The method for manufacturing a semiconductor device according to claim 11, wherein the sacrificial layer is a polycrystalline semiconductor containing silicon. 如請求項11之半導體裝置之製造方法,其中上述第1導電層、上述第3導電層、上述第4導電層、上述第5導電層包含銅(Cu)。The method of manufacturing a semiconductor device according to claim 11, wherein the first conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer include copper (Cu). 如請求項11之半導體裝置之製造方法,其中於將上述第1半導體電路基板與上述第2半導體電路基板貼合時,對上述第1半導體電路基板之表面及上述第2半導體電路基板之表面之至少任一者進行電漿處理, 於將上述第1半導體電路基板與上述第3半導體電路基板貼合時,對上述第1半導體電路基板之表面及上述第3半導體電路基板之表面之至少任一者進行電漿處理。The method for manufacturing a semiconductor device according to claim 11, wherein when the first semiconductor circuit board and the second semiconductor circuit board are bonded, the surface of the first semiconductor circuit board and the surface of the second semiconductor circuit board At least any one performs plasma processing, and when bonding the first semiconductor circuit board and the third semiconductor circuit board, at least any one of the surface of the first semiconductor circuit board and the surface of the third semiconductor circuit board Perform plasma treatment. 如請求項11之半導體裝置之製造方法,其中上述犧牲層之去除係藉由濕式蝕刻進行。The method for manufacturing a semiconductor device according to claim 11, wherein the removal of the sacrificial layer is performed by wet etching. 如請求項11之半導體裝置之製造方法,其中上述第4導電層之埋入係藉由鍍覆法進行。The method for manufacturing a semiconductor device according to claim 11, wherein the embedding of the fourth conductive layer is performed by a plating method. 如請求項11之半導體裝置之製造方法,其中上述第2導電層包含鎢。The method for manufacturing a semiconductor device according to claim 11, wherein the second conductive layer contains tungsten. 如請求項11之半導體裝置之製造方法,其中上述第1半導體電路基板具有積層有複數個記憶胞之三維構造之記憶胞陣列。The method for manufacturing a semiconductor device according to claim 11, wherein the first semiconductor circuit substrate has a memory cell array having a three-dimensional structure in which a plurality of memory cells are stacked. 如請求項11之半導體裝置之製造方法,其中上述第2半導體電路基板具有MISFET。The method for manufacturing a semiconductor device according to claim 11, wherein the second semiconductor circuit board has a MISFET. 如請求項18之半導體裝置之製造方法,其中上述第2半導體電路基板具有上述記憶胞陣列之周邊電路。The method for manufacturing a semiconductor device according to claim 18, wherein the second semiconductor circuit substrate has peripheral circuits of the memory cell array.
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US11647625B2 (en) 2020-07-22 2023-05-09 Samsung Electronics Co., Ltd. Memory device having a channel provided on a memory unit

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