JP2023040988A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

To provide a semiconductor device capable of suppressing a trouble resulting from a semiconductor layer, and a method for manufacturing the same.SOLUTION: According to one embodiment, a semiconductor device comprises a first substrate, a first insulation film provided on the first substrate, and a semiconductor layer provided on the first insulation film. The semiconductor device further comprises a first portion provided on the semiconductor layer, and a second portion provided on the first insulation film not via the semiconductor layer and including a bonding pad.SELECTED DRAWING: Figure 1

Description

TECHNICAL FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof.

If an unnecessary semiconductor layer remains in the semiconductor device, the performance of the semiconductor device may deteriorate due to the semiconductor layer, or the semiconductor layer may hinder the manufacture of the semiconductor device.

United States Patent Application Publication No. US2016/0079164 U.S. Pat. No. 9,558,945

A semiconductor device capable of suppressing problems caused by a semiconductor layer and a method for manufacturing the same are provided.

According to one embodiment, a semiconductor device includes a first substrate, a first insulating film provided on the first substrate, and a semiconductor layer provided on the first insulating film. The device further comprises a metal layer including a first portion provided on the semiconductor layer and a second portion including a bonding pad provided on the first insulating film without the semiconductor layer interposed therebetween. .

1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment; FIG. It is a sectional view showing the structure of the columnar part of a 1st embodiment. 2 is a cross-sectional view (1/2) showing the method for manufacturing the semiconductor device of the first embodiment; FIG. 2 is a cross-sectional view (2/2) showing the method for manufacturing the semiconductor device of the first embodiment; FIG. 3 is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the first embodiment; FIG. FIG. 4 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the first embodiment; FIG. 11 is a cross-sectional view (1/6) showing the method for manufacturing the semiconductor device of the first embodiment; It is a cross-sectional view (2/6) showing the method of manufacturing the semiconductor device of the first embodiment. FIG. 3 is a cross-sectional view (3/6) showing the method of manufacturing the semiconductor device of the first embodiment; FIG. 4 is a cross-sectional view (4/6) showing the method for manufacturing the semiconductor device of the first embodiment; FIG. 5 is a cross-sectional view (5/6) showing the method of manufacturing the semiconductor device of the first embodiment; 6 is a cross-sectional view (6/6) showing the method for manufacturing the semiconductor device of the first embodiment; FIG. FIG. 11 is another cross-sectional view (1/4) showing the method of manufacturing the semiconductor device of the first embodiment; FIG. 11 is another cross-sectional view (2/4) showing the method of manufacturing the semiconductor device of the first embodiment; FIG. 13 is another cross-sectional view (3/4) showing the method of manufacturing the semiconductor device of the first embodiment; 4 is another cross-sectional view (4/4) showing the method of manufacturing the semiconductor device of the first embodiment; FIG. It is a top view which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is another top view which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is another top view which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a top view which shows the manufacturing method of the semiconductor device of the modification of 2nd Embodiment. 14 is a cross-sectional view (1/14) showing the method of manufacturing the semiconductor device of the second embodiment; FIG. It is a sectional view (2/14) which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a cross-sectional view (3/14) showing the method of manufacturing the semiconductor device of the second embodiment. 14 is a cross-sectional view (4/14) showing the method of manufacturing the semiconductor device of the second embodiment; FIG. It is a cross-sectional view (5/14) showing the method of manufacturing the semiconductor device of the second embodiment. 14 is a cross-sectional view (6/14) showing the method for manufacturing the semiconductor device of the second embodiment; FIG. 14 is a cross-sectional view (7/14) showing the method for manufacturing the semiconductor device of the second embodiment; FIG. 14 is a cross-sectional view (8/14) showing the method of manufacturing the semiconductor device of the second embodiment; FIG. 14 is a cross-sectional view (9/14) showing the method for manufacturing the semiconductor device of the second embodiment; FIG. FIG. 10 is a cross-sectional view (10/14) showing the method of manufacturing the semiconductor device of the second embodiment; FIG. 11 is a cross-sectional view (11/14) showing the method of manufacturing the semiconductor device of the second embodiment; 14 is a cross-sectional view (12/14) showing the method for manufacturing the semiconductor device of the second embodiment; FIG. 13A and 14B are cross-sectional views (13/14) showing the method for manufacturing the semiconductor device of the second embodiment; 14 is a cross-sectional view (14/14) showing the method for manufacturing the semiconductor device of the second embodiment; FIG.

It is a cross-sectional view showing the structure of the semiconductor device of the third embodiment. FIG. 11 is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the third embodiment; It is a top view which shows the structure of the semiconductor device of 3rd Embodiment. It is a top view which shows the structure of the semiconductor device of the modification of 3rd Embodiment. It is a perspective view for explaining the structure of the semiconductor device of the third embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 39 , the same components are denoted by the same reference numerals, and overlapping descriptions are omitted.

(First embodiment)
FIG. 1 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. The semiconductor device of FIG. 1 is a three-dimensional memory in which an array chip 1 and a circuit chip 2 are bonded together.

The array chip 1 includes a memory cell array 11 including a plurality of memory cells and an interlayer insulating film 12 under the memory cell array 11. As shown in FIG. The interlayer insulating film 12 is, for example, a SiO ₂ film (silicon oxide film) or a laminated film including an SiO ₂ film and other insulating films. The interlayer insulating film 12 is an example of a first insulating film or a fourth insulating film.

A circuit chip 2 is provided below the array chip 1 . A symbol S indicates a bonding surface between the array chip 1 and the circuit chip 2 . The circuit chip 2 has an interlayer insulating film 13 and a substrate 14 under the interlayer insulating film 13 . The interlayer insulating film 13 is, for example, a SiO ₂ film or a laminated film including an SiO ₂ film and other insulating films. The interlayer insulating film 13 is an example of a first insulating film and a third insulating film. The substrate 14 is, for example, a semiconductor substrate such as a Si (silicon) substrate. Substrate 14 is an example of a first substrate.

FIG. 1 shows the X and Y directions parallel and mutually perpendicular to the surface of the substrate 14 and the Z direction perpendicular to the surface of the substrate 14 . In this specification, the +Z direction is treated as the upward direction and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

The array chip 1 has a plurality of word lines WL spaced apart from each other as a plurality of electrode layers in the memory cell array 11 . FIG. 1 shows the staircase structure portion 21 of the memory cell array 11 . Each word line WL is electrically connected to a word wiring layer 23 via a contact plug 22 . Each columnar portion CL passing through a plurality of word lines WL is electrically connected to a bit line BL via a via plug 24 and electrically connected to a source layer 51 (source line) described later. The word line WL is an example of the first electrode layer, and the source layer 51 is an example of the second electrode layer.

The circuit chip 2 has a plurality of transistors 31 . Each transistor 31 includes a gate electrode 32 provided on the substrate 14 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate 14 . In addition, the circuit chip 2 includes a plurality of contact plugs 33 provided on the gate electrode 32, the source diffusion layer, or the drain diffusion layer of these transistors 31, and a plurality of wirings provided on the contact plugs 33. and a wiring layer 35 provided on the wiring layer 34 and including a plurality of wirings.

The circuit chip 2 further includes a wiring layer 36 provided on the wiring layer 35 and including a plurality of wirings, a plurality of via plugs 37 provided on the wiring layer 36, and a plurality of metals provided on the via plugs 37. A pad 38 is provided. The metal pad 38 is, for example, a metal layer including a Cu (copper) layer. Metal pad 38 is an example of a first pad. The circuit chip 2 functions as a control circuit (logic circuit) that controls the operation of the array chip 1 . This control circuit is composed of a transistor 31 and the like, and is electrically connected to a metal pad 38 .

The array chip 1 has a plurality of metal pads 41 provided on the metal pads 38 and a plurality of via plugs 42 provided on the metal pads 41 . Also, the array chip 1 is provided on these via plugs 42 and includes a wiring layer 43 including a plurality of wirings, a wiring layer 44 provided on the wiring layer 43 and including a plurality of wirings, and a wiring layer 44 provided on the wiring layer 44. and a plurality of via plugs 45 connected to each other. The metal pad 41 is, for example, a metal layer containing a Cu layer. Metal pad 41 is an example of a second pad. The bit line BL described above is included in the wiring layer 44 . The control circuit described above is electrically connected to the memory cell array 11 via the metal pads 41, 38, etc., and controls the operation of the memory cell array 11 via the metal pads 41, 38, etc. FIG.

The array chip 1 further includes a semiconductor layer 51 a , a metal layer 51 b , an insulating film 52 a , an insulating film 52 , a passivation insulating film 53 , a solder layer 54 and bonding wires 55 . FIG. 1 further shows a source layer 51 including a portion of the semiconductor layer 51a and a portion of the metal layer 51b, and an insulating film 52 including insulating films 52a and 52b. The insulating film 52 is an example of a second insulating film.

The semiconductor layer 51 a is formed on the memory cell array 11 and the interlayer insulating film 12 above the substrate 14 . The semiconductor layer 51a is arranged on the columnar portion CL and electrically connected to the columnar portion CL. The semiconductor layer 51a is, for example, a polysilicon layer. The semiconductor layer 51a of this embodiment includes portions A1 and A2 that are separated from each other.

The insulating film 52a is formed on the semiconductor layer 51a. The insulating film 52a is, for example, a _SiO2 film.

The insulating film 52b is formed on the insulating film 52a. The insulating film 52b is, for example, a _SiO2 film. The insulating film 52b of this embodiment is formed on the upper surface of the insulating film 52a and on the side surfaces of the insulating film 52a and the semiconductor layer 51a.

The metal layer 52b is formed on the interlayer insulating film 12, the plurality of via plugs 45, the semiconductor layer 51a, and the insulating film 52b. The metal layer 52b includes, for example, an Al (aluminum) layer. The metal layer 51b of this embodiment includes portions B1, B2, and B3 that are separated from each other. Part B1 is an example of a first part and part B3 is an example of a second part.

Part B1 is formed on part A1 and electrically connected to part A1. The source layer 51 of this embodiment includes a portion of the semiconductor layer 51a and a portion of the metal layer 51b as described above, and more specifically includes portions A1 and B1.

The portion B2 is formed on the insulating film 52b. The portion B2 of this embodiment is electrically insulated from the portion B1. Part B2 is used, for example, as a power line.

Portion B3 is formed on interlayer insulating film 12 and a plurality of via plugs 45 and electrically connected to these via plugs 45 . A portion B3 shown in FIG. 1 is electrically connected to a predetermined transistor 31 through these via plugs 45, metal pads 41 and 38, and the like. Since the portion B3 of the present embodiment is formed on the interlayer insulating film 12 and the via plug 45 without interposing the semiconductor layer 51a, insulating film 52a, and insulating film 52b, it is in contact with the interlayer insulating film 12 and the via plug 45. there is The portion B3 of this embodiment is electrically insulated from the portions B1 and B2.

The passivation insulating film 53 is formed on the metal layer 51b and the insulating film 52b and partially covers the metal layer 51b. The passivation insulating film 53 of this embodiment has an opening P that exposes part of the upper surface of the portion B3. A region exposed in the opening P in the portion B3 functions as an external connection pad (bonding pad) of the semiconductor device of FIG. The portion B3 can be connected to a mounting substrate or other device from this opening P via bonding wires, solder balls, metal bumps, or the like. FIG. 1 shows a bonding wire 55 electrically connected by a solder layer 54 to portion B3. The passivation insulating film 53 is, for example, a laminated film including an _SiO2 film and other insulating films.

FIG. 2 is a cross-sectional view showing the structure of the columnar portion CL of the first embodiment.

As shown in FIG. 2, the memory cell array 11 includes a plurality of word lines WL and a plurality of insulating layers 61 alternately stacked on the interlayer insulating film 12 (FIG. 1). The word line WL is a metal layer including, for example, a W (tungsten) layer. The insulating layer 61 is, for example, a _SiO2 film.

The columnar portion CL includes a block insulating film 62, a charge storage layer 63, a tunnel insulating film 64, a channel semiconductor layer 65, and a core insulating film 66 in this order. The charge storage layer 63 is, for example, a SiN film (silicon nitride film), and is formed on the side surfaces of the word lines WL and the insulating layer 61 with the block insulating film 62 interposed therebetween. The charge storage layer 53 may be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 65 is, for example, a polysilicon layer, and is formed on the side surface of the charge storage layer 63 with the tunnel insulating film 64 interposed therebetween. The block insulating film 62, the tunnel insulating film 64, and the core insulating film 66 are, for example, _SiO2 films or metal insulating films.

3 and 4 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

FIG. 3 shows an array wafer W1 containing a plurality of array chips 1 and a circuit wafer W2 containing a plurality of circuit chips 2. As shown in FIG. The array wafer W1 is also called a "memory wafer", and the circuit wafer W2 is also called a "CMOS wafer".

Note that the orientation of array wafer W1 in FIG. 3 is opposite to the orientation of array chip 1 in FIG. In this embodiment, a semiconductor device is manufactured by bonding an array wafer W1 and a circuit wafer W2 together. FIG. 3 shows the array wafer W1 before its orientation is reversed for lamination, and FIG. 1 shows the array chip 1 after its orientation is reversed for lamination and after lamination and dicing. ing.

In FIG. 3, symbol S1 indicates the top surface of the array wafer W1, and symbol S2 indicates the top surface of the circuit wafer W2. It should be noted that array wafer W1 has substrate 15 provided under memory cell array 11 and interlayer insulating film 12 . The substrate 15 is, for example, a semiconductor substrate such as a silicon substrate. Substrate 15 is an example of a second substrate.

In this embodiment, first, as shown in FIG. 3, the memory cell array 11, the interlayer insulating film 12, the staircase structure portion 21, the metal pads 41, etc. are formed on the substrate 15 of the array wafer W1, and then formed on the substrate 14 of the circuit wafer W2. An interlayer insulating film 13, a transistor 31, a metal pad 38, etc. are formed. For example, a via plug 45 , a wiring layer 44 , a wiring layer 43 , a via plug 42 and a metal pad 41 are sequentially formed on the substrate 15 . Also, contact plugs 33 , wiring layers 34 , wiring layers 35 , wiring layers 36 , via plugs 37 and metal pads 38 are sequentially formed on the substrate 14 . Next, as shown in FIG. 4, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure. As a result, the interlayer insulating film 12 and the interlayer insulating film 13 are bonded together. Next, the array wafer W1 and the circuit wafer W2 are annealed at 400.degree. Thereby, the metal pad 41 and the metal pad 38 are joined.

After that, the substrate 14 is thinned by CMP (Chemical Mechanical Polishing), the substrate 15 is removed by CMP, and then the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. Thus, the semiconductor device of FIG. 1 is manufactured. In addition, the semiconductor layer 51a, the metal layer 51b, the source layer 51, the insulating film 52a, the insulating film 52b, the insulating film 52, the passivation insulating film 53, the solder layer 54, and the bonding wire 55 are formed by thinning the substrate 14 and is formed on memory cell array 11 and interlayer insulating film 12 after removal of .

Although the array wafer W1 and the circuit wafer W2 are bonded together in this embodiment, the array wafers W1 may be bonded together instead. The contents described above with reference to FIGS. 1 to 4 and the contents described later with reference to FIGS. 5 to 34 can also be applied to the bonding of the array wafers W1.

FIG. 1 also shows the interface between the interlayer insulating film 12 and the interlayer insulating film 13 and the interface between the metal pad 41 and the metal pad 38, but these interfaces are observed after the annealing. disappearing is common. However, the positions of these boundary surfaces can be estimated, for example, by detecting the inclination of the side surface of the metal pad 41 or the side surface of the metal pad 38 or the positional deviation between the side surface of the metal pad 41 and the metal pad 38. can.

The semiconductor device of this embodiment may be traded in the state shown in FIG. 1 after being cut into a plurality of chips, or may be traded in the state shown in FIG. 4 before being cut into a plurality of chips. May be targeted. 1 shows a semiconductor device in a chip state, and FIG. 4 shows a semiconductor device in a wafer state. In this embodiment, a plurality of chip-like semiconductor devices (FIG. 1) are manufactured from one wafer-like semiconductor device (FIG. 4). Also, the semiconductor device of this embodiment may be traded in any of the states shown in FIGS. 7 to 16 before being cut into a plurality of chips.

FIG. 5 is a cross-sectional view showing the structure of a semiconductor device as a comparative example of the first embodiment.

The semiconductor device (FIG. 5) of this comparative example has the same components as the semiconductor device (FIG. 1) of the first embodiment. However, the portion B3 of this comparative example is formed on the interlayer insulating film 12 in the region exposed to the opening portion P with the semiconductor layer 51a (portion A3), the insulating film 52a, and the insulating film 52b interposed therebetween. That is, the bonding pad of this comparative example is formed on the interlayer insulating film 12 with the semiconductor layer 51a, the insulating film 52a, and the insulating film 52b interposed therebetween. The portion A3 of the semiconductor layer 51a of this comparative example is separated from the portions A1 and A2.

In this comparative example, the following problems arise due to the semiconductor layer 51a and the like.

The portion B3 of this comparative example is formed on the interlayer insulating film 12 via the portion A3 as described above. Therefore, a parasitic capacitance is generated between the portion A3 and the portion B3, and the current and voltage passing through the portion B3 (bonding pad) are affected by the parasitic capacitance. For example, if this bonding pad is an I/O (Input/Output) pad for signal input/output, the propagation speed of this signal will be delayed due to parasitic capacitance.

Also, the portion B3 of this comparative example has a large step between the region near the opening P and the region near the via plug 45 . The reason is that the portion B3 of this comparative example is formed on the interlayer insulating film 12 and the via plug 45 in the region near the via plug 45 without interposing the semiconductor layer 51a, the insulating film 52a, and the insulating film 52b. be. This step may cause disconnection or increase in resistance of the portion B3.

On the other hand, the portion B3 of the present embodiment is entirely formed on the interlayer insulating film 12 without interposing the semiconductor layer 51a, the insulating film 52a, and the insulating film 52b (FIG. 1). As a result, it is possible to suppress the occurrence of the parasitic capacitance and the step as described above, so that it is possible to suppress the problems caused by the parasitic capacitance and the step.

FIG. 6 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the first embodiment.

The semiconductor device (FIG. 6) of this modification includes the same components as the semiconductor device (FIG. 1) of the first embodiment. However, although the portion B3 of this comparative example is formed on the interlayer insulating film 12 through the insulating film 52b in the region exposed to the opening portion P, the interlayer insulating film is formed without the semiconductor layer 51a or the insulating film 52a. It is formed on the membrane 12 . That is, the bonding pads of this modification are formed on the interlayer insulating film 12 with the insulating film 52b interposed therebetween and without the semiconductor layer 51a and the insulating film 52a interposed therebetween. As a result, it is possible to suppress the occurrence of parasitic capacitance as described above, so that problems caused by parasitic capacitance can be suppressed.

The portion B3 of this modified example has a step between the region near the opening P and the region near the via plug 45, like the portion B3 of the comparative example. However, since the step in this modified example is smaller than the step in the comparative example, problems caused by the step can be suppressed. In the portion B3 of this modified example, the region near the opening P is an example of the third portion, and the region near the via plug 45 is an example of the fourth portion.

7 to 12 are cross-sectional views showing the method of manufacturing the semiconductor device of the first embodiment, specifically showing the steps after the step shown in FIG.

In this embodiment, the substrate 15 (array wafer W1) and the substrate 14 (circuit wafer W2) are bonded together, the substrate 14 is thinned by CMP, and the substrate 15 is removed by CMP, and then the process shown in FIG. 7 is performed.

First, the semiconductor layer 51a is formed on the memory cell array 11, the interlayer insulating film 12, and the via plug 45, and the insulating film 52a is formed on the semiconductor layer 51a (FIG. 7). Next, openings H1 and H2 are formed in the insulating film 52a and the semiconductor layer 51a by lithography and RIE (Reactive Ion Etching) (FIG. 7). As a result, the semiconductor layer 51a is separated into portions A1 and A2. Next, an insulating film 52b is formed on the insulating film 52a (FIG. 7). As a result, the insulating film 52b is embedded in the openings H1 and H2. FIG. 7 shows an insulating film 52 including insulating films 52a and 52b.

Next, by lithography and RIE, openings H3 are formed in the insulating films 52b and 52a, and openings H4 are formed in the insulating films 52b and 52a and the semiconductor layer 51a (FIG. 8). As a result, the portion A1 is exposed in the opening H3, and the via plug 45 is exposed in the opening H4.

Next, a metal layer 51b is formed on the interlayer insulating film 12, the via plug 45, the semiconductor layer 51a, and the insulating film 52b (FIG. 9). As a result, the metal layer 51b is embedded in the openings H3 and H4.

Next, the metal layer 51b is processed by lithography and RIE (FIG. 10). As a result, metal layer 51b is separated into portions B1, B2, and B3. FIG. 10 shows source layer 51 including portion A1 and portion B1.

Next, a passivation insulating film 53 is formed on the metal layer 51b and the insulating film 52b (FIG. 11). As a result, the metal layer 51 b and the insulating film 52 b are covered with the passivation insulating film 53 .

Next, an opening H5 is formed in the passivation insulating film 53 by lithography and RIE (FIG. 12). As a result, part of the upper surface of the portion B3 is exposed in the opening H5. The opening H5 corresponds to the opening P described above. A region exposed in opening H5 in portion B3 is used as a bonding pad.

After that, the array wafer W1 and circuit wafer W2 are cut into a plurality of chips. Thus, the semiconductor device of FIG. 1 is manufactured.

13 to 16 are other cross-sectional views showing the method of manufacturing the semiconductor device of the first embodiment.

FIG. 13 shows the same steps as those shown in FIG. However, FIG. 13 shows chip regions R1 and dicing regions (scribe regions) R2 in the array wafer W1 and the circuit wafer W2. FIG. 13 also shows an interface S' between the chip region R1 and the dicing region R2.

Array wafer W1 and circuit wafer W2 include a plurality of chip regions R1, one of which is shown in FIG. In plan view, each chip region R1 has a rectangular shape, and the dicing region R2 has a mesh shape (see FIG. 17 described later). Therefore, each chip region R1 is arranged within one mesh of the dicing regions R2, and the dicing regions R2 are arranged between adjacent chip regions R1. When the array wafer W1 and the circuit wafer W2 are cut (diced) along the dicing regions R2, each chip region R1 becomes one chip (semiconductor device). In the substrate 14, the area within each chip area R1 is an example of a first area, and the area within the dicing area R2 is an example of a second area.

Array wafer W1 and circuit wafer W2 each have guard rings E1 and E2 in chip region R1, as shown in FIG. The guard rings E1 and E2 are provided near the boundary surface S' between the chip region R1 and the dicing region R2, and have a ring shape in plan view. The guard ring E1 of this embodiment is made of the same material as the wiring layer 43, the wiring layer 44, and the via plug 45. As shown in FIG. On the other hand, the guard ring E2 of this embodiment is made of the same material as the contact plug 33, the wiring layer 34, the wiring layer 35, and the wiring layer 36. FIG. The guard rings E1 and E2 are provided, for example, to protect the side surfaces of the chip after dicing and to prevent the interlayer insulating films 12 and 13 from peeling off.

As mentioned above, FIG. 13 shows the same steps as those shown in FIG. 14 shows the same steps as shown in FIG. 8, FIG. 15 shows the same steps as shown in FIGS. 9 and 10, and FIG. 16 shows the same steps as shown in FIGS. is shown.

The steps shown in FIGS. 13 to 16 will be described below. In this description, the description of the points in common with the steps shown in FIGS. 7 to 12 will be omitted as appropriate.

First, the semiconductor layer 51a is formed on the memory cell array 11, the interlayer insulating film 12, and the via plug 45, and the insulating film 52a is formed on the semiconductor layer 51a (FIG. 13). Next, openings H1 and H2 are formed in the insulating film 52a and the semiconductor layer 51a by lithography and RIE (FIG. 13). In this embodiment, openings H6 and H7 are further formed in the insulating film 52a and the semiconductor layer 51a by this lithography and RIE. As a result, the semiconductor layer 51a is separated into portions A1, A2, A3, and A4. Part A3 is formed on via plug 45 and part A4 is formed on guard ring E1. Next, an insulating film 52b is formed on the insulating film 52a (FIG. 13). As a result, the insulating film 52b is embedded in the openings H1, H2, H6 and H7.

The opening H7 of this embodiment is formed directly above the substrate 14 and the interlayer insulating films 13 and 12 in the dicing region R2. Therefore, in the process shown in FIG. 13, the semiconductor layer 51a and the insulating film 52a are removed from the dicing region R2, and the semiconductor layer 51a and the insulating film 52a remain only in the chip region R1 of the chip region R1 and the dicing region R2. . If the semiconductor layer 51a remains in the dicing region R2, this semiconductor layer 51a may adversely affect dicing, which will be described later. According to this embodiment, by removing the semiconductor layer 51a from the dicing region R2 in the process shown in FIG. 13, such adverse effects can be suppressed.

Next, by lithography and RIE, openings H3 are formed in the insulating films 52b and 52a, and openings H4 are formed in the insulating films 52b and 52a and the semiconductor layer 51a (FIG. 14). As a result, the portion A1 is exposed in the opening H3, and the via plug 45 is exposed in the opening H4.

Next, a metal layer 51b is formed on the interlayer insulating film 12, the via plug 45, the semiconductor layer 51a, and the insulating film 52b (FIG. 15). As a result, the metal layer 51b is embedded in the openings H3 and H4. Next, the metal layer 51b is processed by lithography and RIE (FIG. 15). As a result, metal layer 51b is separated into portions B1, B2, and B3.

Next, a passivation insulating film 53 is formed on the metal layer 51b and the insulating film 52b (FIG. 16). As a result, the metal layer 51 b and the insulating film 52 b are covered with the passivation insulating film 53 . Next, an opening H5 is formed in the passivation insulating film 53 by lithography and RIE (FIG. 16). The opening H5 corresponds to the opening P described above.

After that, the array wafer W1 and circuit wafer W2 are cut into a plurality of chips. Specifically, by cutting the array wafer W1 and the circuit wafer W2 along the dicing region R2, the chip regions R1 become chips. At this time, if the semiconductor layer 51a remains in the dicing region R2, the semiconductor layer 51a may be peeled off. According to the present embodiment, such peeling can be suppressed by removing the semiconductor layer 51a from the dicing region R2 in advance. Thus, the semiconductor device of FIG. 1 is manufactured.

As described above, the portion B3 (bonding pad) of the metal layer 51b of this embodiment is provided on the interlayer insulating film 12 without interposing the semiconductor layer 51a. Therefore, according to the present embodiment, it is possible to suppress problems caused by the semiconductor layer 51a, such as parasitic capacitance and steps caused by the semiconductor layer 51a.

(Second embodiment)
FIG. 17 is a plan view showing the method of manufacturing the semiconductor device of the second embodiment.

FIG. 17 shows the same process as that shown in FIG. 16, specifically showing a plurality of chip regions R1 and dicing regions R2 in array wafer W1 before dicing. The dicing region R2 includes a plurality of regions R2a extending in the X direction and a plurality of regions R2b extending in the Y direction. The dicing region R2 has a mesh shape formed by these regions R2a and R2b. FIG. 17 shows the chip region R1 in white and the dicing region R2 in cross hatching. The circuit wafer W2 has the structure shown in FIG. 17 in relation to the chip region R1 and the dicing region R2, similarly to the array wafer W1.

FIG. 18 is another plan view showing the method of manufacturing the semiconductor device of the second embodiment.

18 is an enlarged view of region K shown in FIG. 17. FIG. Each chip region R1 in this embodiment includes a cell region R1a and a peripheral region R1b, as shown in FIG. The cell region R1a includes a memory cell array 11 (see FIG. 1). The peripheral region R1b includes peripheral circuits, such as control circuits such as transistors 31 (see FIG. 1). FIG. 18 shows the columnar portion CL in the cell region R1a and the metal layer 51b exposed in the plurality of openings P in the peripheral region R1b. One of these openings P is shown, for example, in FIG. The metal layer 51b exposed in each opening P functions as one bonding pad.

FIG. 18 further shows recesses 71, 72, and 73 provided in the semiconductor layer 51a by dot hatching. In this embodiment, these concave portions 71, 72, and 73 are provided so as to penetrate the semiconductor layer 51a. Each opening P (bonding pad) of the present embodiment is provided in one recess 71 in plan view. Further details of the semiconductor layer 51a are described below with reference to FIG.

FIG. 19 is another plan view showing the method of manufacturing the semiconductor device of the second embodiment.

FIG. 19, like FIG. 18, is an enlarged view of region K shown in FIG. However, FIG. 19 shows the planar shape of the semiconductor layer 51a. In FIG. 19, regions where the semiconductor layer 51a exists are indicated by hatching, and regions where the semiconductor layer 51a does not exist are indicated by white.

As shown in FIG. 19, the semiconductor layer 51a of this embodiment includes recesses 71, 72, and 73. As shown in FIG. The recess 71 is a hole having a quadrangular planar shape. The recess 72 is a groove having an annular planar shape surrounding the recess 71 . The recess 73 is a groove that has a linear planar shape and intersects with the recess 72 . The concave portion 71 has four sides parallel to the X direction or the Y direction in plan view. The recess 72 extends in the X direction and the Y direction. The recess 73 extends in the X direction. Further, the semiconductor layer 51a of this embodiment remains only in the chip region R1 out of the chip region R1 and the dicing region R2.

Since the semiconductor layer 51a of the present embodiment has the concave portions 71, 72, and 73, in FIG. remains in If the semiconductor layer 51a remains in the entire chip region R1, peeling due to the semiconductor layer 51a is likely to occur when the memory cell array 11 is annealed. On the other hand, according to the present embodiment, such peeling can be suppressed by leaving the semiconductor layer 51a only in a partial region within the chip region R1.

In this embodiment, the ratio of the total area of the recesses 71, 72 and 73 to the total area of the semiconductor layer 51a and the recesses 71, 72 and 73 in plan view is set to 10% to 15%. When Sa represents the total area of the semiconductor layer 51a in plan view, and Sb represents the total area of the concave portions 71, 72, and 73 in plan view, this relationship is "0.10≦Sb/(Sa+Sb)≦0.15". is represented by The value of Sb/(Sa+Sb) can be calculated, for example, by dividing the total area of the recesses 71, 72 and 73 in each chip region R1 by the area of each chip region R1.

It is desirable to set the width of the concave portions 72 and 73 (grooves) in this embodiment to be narrow. The reason is that the recesses 72 and 73 can be filled with a thin insulating film. The width of the recesses 72 and 73 in this embodiment is set to, for example, 500 nm or less. If a portion of the recesses 72,73 extends in the X direction, the width of this portion of the recesses 72,73 is the dimension of the recesses 72,73 in the Y direction. Conversely, if a portion of the recesses 72,73 extends in the Y direction, the width of this portion of the recesses 72,73 is the dimension of the recesses 72,73 in the X direction.

FIG. 20 is a plan view showing a method of manufacturing a semiconductor device according to a modification of the second embodiment.

FIG. 20, like FIG. 18, is an enlarged view of region K shown in FIG. The semiconductor layer 51a of this modification includes recesses 74, 75, and 76 instead of the recesses 72 and 73, as shown in FIG. The recess 74 is a groove extending in the X and Y directions, and the recesses 75 and 76 are square holes. In this modification, recesses 71, 74, 75, and 76 are provided so as to penetrate the semiconductor layer 51a.

It is desirable that the widths of the concave portions 74, 75, and 76 in this modified example are also set narrow. The widths of the recesses 74, 75, and 76 in this modified example are set to, for example, 500 nm or less. The width of the recess 74 is determined in the same way as the width of the recesses 72 and 73 . On the other hand, the width of the recesses 75 and 76 is the length of the short sides of the recesses 75 and 76 . Also in this modification, the ratio of the total area of the recesses 71, 74, 75, and 76 to the total area of the semiconductor layer 51a and the recesses 71, 74, 75, and 76 in plan view is set to 10% to 15%. there is

21 to 34 are cross-sectional views showing the method of manufacturing the semiconductor device of the second embodiment. In this embodiment, a semiconductor device including recesses 71, 72, 73 is manufactured. The semiconductor device of this embodiment may be manufactured by the method described in the first embodiment, or may be manufactured by the method shown in FIGS.

FIG. 21 shows the manufacturing process of the array wafer W1. FIG. 21 shows a cell region R1a and a peripheral region R1b within the chip region R1. FIG. 21 further shows groove region r1, pad region r2, and groove region r3 in peripheral region R1b. As will be described later, recesses 72 (grooves) are formed in the groove regions r1 and r3, and recesses 71 (holes) are formed in the pad region r2.

First, an insulating film 81, a semiconductor layer 82, an insulating film 85, and a semiconductor layer 84 are sequentially formed over the entire surface of the substrate 15, and then a portion of the insulating film 85 is replaced with a semiconductor layer 83 (FIG. 21). The insulating film 81 is, for example, a _SiO2 film. The semiconductor layers 82, 83, 84 are polysilicon layers, for example, and are used to form the semiconductor layer 51a. The insulating film 85 is, for example, a SiN film. In this embodiment, the insulating film 85 is removed from the cell region R1a to form a cavity between the semiconductor layers 82 and 84, and the semiconductor layer 83 is embedded in this cavity to form the semiconductor layer 83 between the semiconductor layers 82 and 84. do. As a result, a semiconductor layer 51a including the semiconductor layers 82, 83 and 84 is formed in the cell region R1a, and a semiconductor layer 51a including the semiconductor layers 82 and 84 is formed in the peripheral region R1b.

Next, a resist film 86 is formed on the semiconductor layer 84, and one opening 86a is formed in the resist film 86 (FIG. 22). FIG. 22 shows two portions of the opening 86a having an annular planar shape. The openings 86a are formed in the groove regions r1 and r3.

Next, the opening 86a is transferred to the semiconductor layer 84, the insulating film 85, and the semiconductor layer 82 by RIE using the resist film 86 (FIG. 23). As a result, one recess 72 penetrating through the semiconductor layer 84, the insulating film 85, and the semiconductor layer 82 is formed in the trench regions r1 and r3. FIG. 23 shows two portions of the recess 72 having an annular planar shape. In the steps shown in FIGS. 22 and 23, recesses 73 may be further formed.

Next, the memory cell array 11, the interlayer insulating film 12, the columnar portions CL, the slit insulating film ST, the via plugs 45, etc. are formed on the semiconductor layer 51a (FIG. 24). As a result, part of the interlayer insulating film 12 is embedded in the recess 72 . The memory cell array 11 of this embodiment is formed by forming a laminated film alternately including a plurality of insulating layers 61 (FIG. 2) and a plurality of sacrificial layers, forming slits in the laminated film, and removing the sacrificial layers from the slits. , are formed by forming a plurality of word lines WL in a plurality of cavities obtained by removing the sacrificial layer, and forming a slit insulating film ST in the slits. The sacrificial layer is, for example, a SiN film. The process shown in FIG. 24 is performed in the same manner as the process shown in FIG. 3, for example.

Next, the array wafer W1 is bonded to a circuit wafer W2 (not shown) (FIG. 25). Therefore, the orientation of the array wafer W1 shown in FIG. 25 is opposite to the orientation of the array chip 1 shown in FIG. The process shown in FIG. 25 is performed in the same manner as the process shown in FIG. 4, for example.

Next, substrate 15 and insulating film 81 are removed (FIG. 26). As a result, the upper surface of the semiconductor layer 51a (semiconductor layer 82) is exposed. The substrate 15 and insulating film 81 are removed by CMP or etching, for example.

Next, insulating films 87 and 88 are sequentially formed on the semiconductor layer 51a (FIG. 27). As a result, an insulating film 52a including insulating films 87 and 88 is formed on the semiconductor layer 51a. The insulating film 87 is, for example, a SiCN film (silicon carbonitride film). The insulating film 88 is, for example, a _SiO2 film.

Next, a resist film 89 is formed on the insulating film 52a, and an opening 89a is formed in the resist film 89 (FIG. 28). Opening 89a is formed in pad region r2.

Next, the opening 89a is transferred to the insulating film 88, the insulating film 87, the semiconductor layer 84, the insulating film 85, and the semiconductor layer 82 by RIE using the resist film 89 (FIG. 29). As a result, a recess 71 penetrating through the insulating film 88, the insulating film 87, the semiconductor layer 84, the insulating film 85, and the semiconductor layer 82 is formed in the pad region r2. Furthermore, the via plug 45 is exposed inside the recess 71 .

Next, an insulating film 52b is formed on the insulating film 52a and the like, a resist film 91 is formed on the insulating film 52b, and two openings 91a and 91b are formed in the resist film 91 (FIG. 30). The opening 91a is formed in the cell region R1a, and the opening 91b is formed in the pad region r2.

Next, the openings 91a and 91b are transferred to the insulating film 52b by RIE using the resist film 91 (FIG. 31). As a result, openings H3 and H4 penetrating the insulating film 52b are formed in the cell region R1a and the pad region r2, respectively. Furthermore, via plug 45 is exposed in opening H4.

Next, a metal layer 51b is formed on the insulating film 52b and the like, a resist film 92 is formed on the metal layer 51b, and two openings 92a and 92b are formed in the resist film 92 (FIG. 32). The opening 92a is formed in the groove region r1, and the opening 92b is formed in the groove region r3. The metal layer 51b shown in FIG. 32 is also formed in the openings H3 and H4.

Next, the openings 92a and 92b are transferred to the metal layer 51b by RIE using the resist film 92 ( FIG. 33 ). As a result, the metal layer 51b is separated into portions P1, P2 and P3. The portion P1 is formed on the semiconductor layer 51a within the opening H3 and forms the source layer 51 together with the semiconductor layer 51a. Portion P1 is provided in cell region R1a and trench region r1. The portion P2 is formed on the via plug 45 within the opening H4. Portion P2 is formed within trench region r1 and pad region r2. The portion P3 is provided within the groove region r3.

Next, insulating films 93, 94 and 95 are sequentially formed on the metal layer 51b and the like, and openings H5 are formed through these insulating films 95, 94 and 93 (FIG. 34). As a result, passivation insulating film 53 including insulating films 95, 94 and 93 is formed on metal layer 51b. The insulating film 93 is, for example, a _SiO2 film. The insulating film 94 is, for example, a SiN film. The insulating film 95 is, for example, a polyimide film. Furthermore, part of the upper surface of the portion P2 is exposed in the opening H5. The opening H5 corresponds to the opening P described above. A region exposed in opening H5 in portion P2 is used as a bonding pad. In FIG. 34, part of the portion P2 is provided in the recess 71, and the portion P2 in the pad region r2 is provided on the interlayer insulating film 12 or the like without the semiconductor layer 51a interposed therebetween.

After that, the array wafer W1 and circuit wafer W2 are cut into a plurality of chips. Thus, the semiconductor device of this embodiment is manufactured.

As described above, the semiconductor layer 51a of the present embodiment is processed into a shape having recesses 71, 72, and 73. As shown in FIG. Therefore, according to the present embodiment, it is possible to suppress the problem caused by the semiconductor layer 51a, for example, the problem of peeling of layers and films in the array wafer W1 and the circuit wafer W2.

(Third embodiment)
FIG. 35 is a cross-sectional view showing the structure of the semiconductor device of the third embodiment.
The semiconductor device of this embodiment (FIG. 35) includes an array chip 1 and a circuit chip 2, like the semiconductor device of the first embodiment (FIG. 1). However, FIG. 35 omits illustration of various components on the substrate 14 and in the interlayer insulating films 12 and 13 . Substrate 14 is an example of a first substrate. The interlayer insulating films 12 and 13 are examples of the first insulating film.
As shown in FIG. 35, the array chip 1 of this embodiment includes a semiconductor layer 51a, a metal layer 51b, an insulating film 52a, an insulating film 52b, a passivation insulating film 53, a plurality of solder layers 54, a plurality of of bonding wires 55. FIG. 35 further shows insulating film 52 including insulating film 52a and insulating film 52b. The insulating film 52 is an example of a second insulating film.
The semiconductor layer 51 a is formed on the interlayer insulating film 12 . The semiconductor layer 51a of the present embodiment includes portions A1 and A2 (FIG. 1) separated from each other like the semiconductor layer 51a of the first embodiment, but FIG. Only part A2 is shown. FIG. 35 further shows three portions A2a, A2b, A2c included in portion A2. These three portions A2a, A2b, A2c are connected to each other in a cross section different from that shown in FIG. 35 (see FIG. 37).
The insulating film 52a is formed on the semiconductor layer 51a. The insulating film 52a is, for example, a SiO2 film _.
The insulating film 52 b is formed on the insulating film 52 a , the semiconductor layer 51 a and the interlayer insulating film 12 . The insulating film 52b is, for example, a SiO2 film _.
The metal layer 52b is formed on the insulating film 52b. The metal layer 52b is further formed on the semiconductor layer 51a and the plurality of via plugs 45 in a cross section different from that shown in FIG. 35 (see FIG. 37). The metal layer 51b of the present embodiment includes portions B1, B2, and B3 (FIG. 1) separated from each other, similar to the metal layer 51b of the first embodiment, but FIG. Only parts B2 and B3 of B3 are shown. Part B1 is an example of a first part. Portions B2 and B3 are examples of second portions.
The passivation insulating film 53 is formed on the metal layer 51b and the insulating film 52b and partially covers the metal layer 51b. The passivation insulating film 53 of this embodiment has an opening P that partially exposes the upper surface of the portion B3 and an opening P' that partially exposes the upper surface of the portion B2.
A region exposed in the opening P in the portion B3 functions as an external connection pad (bonding pad) of the semiconductor device of the present embodiment, for example, functions as an I/O (Input/Output) pad for inputting and outputting signals. . The portion B3 can be connected to a mounting substrate or other device from this opening P via bonding wires, solder balls, metal bumps, or the like. FIG. 35 shows a bonding wire 55 electrically connected by a solder layer 54 to portion B3.
As shown in FIG. 35, the bonding pad of portion B3 is formed on interlayer insulating film 12 without interposing semiconductor layer 51a. Specifically, the portion B3 of the present embodiment is entirely formed on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween. , is formed on the interlayer insulating film 12 without interposing the semiconductor layer 51a. This makes it possible to suppress the influence of parasitic capacitance on signals passing through this bonding pad. This bonding pad is an example of a first bonding pad. Part B3 is an example of a fifth part.
A region exposed in the opening P′ in the portion B2 functions as an external connection pad (bonding pad) of the semiconductor device of the present embodiment, for example, as a power supply pad for supplying a power supply voltage (eg, VDD voltage or GND voltage). Function. The portion B2 can be connected to a mounting substrate or other device from this opening P' via bonding wires, solder balls, metal bumps, or the like. FIG. 35 shows a bonding wire 55 electrically connected by a solder layer 54 to portion B2.
The bonding pad of portion B2 is also formed on interlayer insulating film 12 without interposing semiconductor layer 51a, as shown in FIG. Specifically, the portion B2 of this embodiment includes a portion formed on the interlayer insulating film 12 with the semiconductor layer 51a interposed therebetween and a portion formed on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween. The bonding pad of the portion B2 (the portion of the opening P') is formed on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween. This makes it possible to suppress the power supply voltage passing through this bonding pad from being affected by the parasitic capacitance. This bonding pad is an example of a second bonding pad. Part B2 is an example of a sixth part.
Here, the insulating film 52b of this embodiment will be described.
The insulating film 52b of this embodiment includes a portion formed directly on the interlayer insulating film 12 and a portion formed on the interlayer insulating film 12 via the semiconductor layer 51a and the insulating film 52a. There is a step at the boundary of the part. Near the step, the end surfaces of the semiconductor layer 51a and the insulating film 52a are tapered.
Therefore, the upper surface of the insulating film 52b of this embodiment includes an upper surface K1 substantially perpendicular to the Z direction and an upper surface K2 inclined with respect to the upper surface K1. The upper surface K2 is positioned near the step, and the upper surface K1 is positioned elsewhere. The upper surface K1 of this embodiment may be strictly perpendicular to the Z direction, or may be slightly inclined with respect to the Z direction. On the other hand, the upper surface K1 of this embodiment is greatly inclined with respect to the Z direction. The top surface K1 is an example of a first top surface. The upper surface K2 is an example of a second upper surface.
The portion B2 of this embodiment includes a portion formed on the upper surface K1 of the insulating film 52b and a portion formed on the upper surface K2 of the insulating film 52b. As a result, the portion B2 of this embodiment includes a portion formed on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween and a portion formed on the interlayer insulating film 12 with the semiconductor layer 51a interposed therebetween. there is
On the other hand, the portion B3 of this embodiment includes the portion formed on the upper surface K1 of the insulating film 52b, but does not include the portion formed on the upper surface K2 of the insulating film 52b. As a result, the portion B3 of the present embodiment includes the portion formed on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween, but the portion formed on the interlayer insulating film 12 with the semiconductor layer 51a interposed therebetween. does not include That is, the portion B3 of this embodiment is entirely formed on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween. However, the portion B3 of the present embodiment may be partially or wholly formed on the interlayer insulating film 12 with the semiconductor layer 51a interposed therebetween.
Further details of the upper surfaces K1 and K2 of the insulating film 52b will be described later.
FIG. 36 is a cross-sectional view showing the structure of a semiconductor device as a comparative example of the third embodiment.
The semiconductor device of this comparative example (FIG. 36) has the same components as the semiconductor device of the third embodiment (FIG. 35). However, the portion A2 of this comparative example includes portions A2d and A2e connected to each other instead of the portions A2a, A2b and A2c connected to each other. Further, the bonding pad (portion of the opening P') of the portion B2 of this comparative example is formed on the interlayer insulating film 12 via the semiconductor layer 51a (portion A2d). Therefore, a parasitic capacitance is generated between the portion A2d and the portion B2, and the power supply voltage passing through the bonding pad of the portion B2 is affected by the parasitic capacitance.
On the other hand, as shown in FIG. 35, the bonding pad (portion of the opening P') of the portion B2 of this embodiment is formed on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween. Therefore, according to this embodiment, it is possible to suppress the influence of the parasitic capacitance on the power supply voltage passing through the bonding pads of the portion B2. This also applies to the bonding pad (portion of the opening P) of the portion B3 of this embodiment. According to this embodiment, it is also possible to suppress the influence of parasitic capacitance on signals passing through the bonding pads of the portion B3.
Next, referring to FIG. 35 again, portions B2 and B3 of this embodiment will be described.
As described above, the bonding pad of the portion B2 of this embodiment is, for example, a power supply pad for supplying a power supply voltage. In this case, the portion B2, which is the power supply line, generally needs to be arranged over a wide range on the interlayer insulating film 12. FIG. Therefore, it is difficult to form the entire portion B2 on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween. be. Therefore, the portion B2 of the present embodiment includes a portion formed on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween and a portion formed on the interlayer insulating film 12 with the semiconductor layer 51a interposed therebetween. .
As a result, the portion B2 of this embodiment includes a portion formed on the upper surface K1 of the insulating film 52b and a portion formed on the upper surface K2 of the insulating film 52b. In this case, since the upper surface K2 is inclined, there is a problem that it is difficult to properly form the portion B2 on the upper surface K2. For example, the metal material for forming the metal layer 51b may remain excessively on the upper surface K2, causing a short circuit in the portion B2. This problem is dealt with by a method described later with reference to FIG. 39 in this embodiment.
On the other hand, the bonding pad of the portion B3 of this embodiment is, for example, an I/O pad for signal input/output. In this case, the signal line portion B3 generally does not need to be arranged over a wide area on the interlayer insulating film 12 . Therefore, it is easy to form the entire portion B3 on the interlayer insulating film 12 without interposing the semiconductor layer 51a. Therefore, the portion B3 of this embodiment includes the portion formed on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween, but the portion formed on the interlayer insulating film 12 with the semiconductor layer 51a interposed is not included.
As a result, the portion B3 of this embodiment includes the portion formed on the upper surface K1 of the insulating film 52b, but does not include the portion formed on the upper surface K2 of the insulating film 52b. This makes it possible to avoid the short-circuit problem described above for the portion B3.
FIG. 37 is a plan view showing the structure of the semiconductor device of the third embodiment.
In FIG. 37, the shape of the semiconductor layer 51a is indicated by diagonal hatching, and the shape of the metal layer 51b is indicated by thick lines. In FIG. 37, the portion A2 of the semiconductor layer 51a includes mutually connected portions A2a, A2b, A2c, and the metal layer 51b includes mutually separated portions B2, B3.
FIG. 37 also shows openings H, H' provided in the semiconductor layer 51a. An insulating film 52b is directly formed on the interlayer insulating film 12 in these openings H and H' (see FIG. 35). The opening H is provided between the portion A2a and the portion A2b. The opening H' is provided between the portion A2a and the portion A2c.
In FIG. 37, the opening H of the semiconductor layer 51a surrounds the portion B3 of the metal layer 51b. Although the portion B3 includes the portion formed on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween, it does not include the portion formed on the interlayer insulating film 12 with the semiconductor layer 51a interposed therebetween. It represents that.
In FIG. 37, the portion B2 of the metal layer 51b also surrounds the opening H' of the semiconductor layer 51a. This indicates that the portion B2 includes a portion formed on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween and a portion formed on the interlayer insulating film 12 with the semiconductor layer 51a interposed therebetween. ing.
FIG. 37 further includes an opening P for portion B3, an opening P′ for portion B2, a region Q in which a plurality of via plugs 45 electrically connected to portion B3 are arranged, and an area electrically connected to portion B2. and a region Q' in which a plurality of via plugs 45 connected to are arranged. In the plan view shown in FIG. 37, the regions Q and Q' are arranged in the X direction of the openings P and P', respectively. Also, the openings P and P' are arranged in the openings H and H', respectively.
FIG. 38 is a plan view showing the structure of a semiconductor device according to a modification of the third embodiment.
FIG. 38 shows a portion A2 of the semiconductor layer 51a and a portion B2 of the metal layer 51b. As shown in FIG. 38, portion B2 may include a plurality of branched portions F. FIG. Also, the portion B2 may include a plurality of regions Q'. These regions Q' may be arranged in any direction of the opening P'. In FIG. 38, these regions Q' are arranged in the +X, +Y, and -Y directions of the opening P'.
FIG. 39 is a perspective view for explaining the structure of the semiconductor device of the third embodiment.
FIG. 39(a) shows two upper surfaces K1 and one upper surface K2 of the insulating film 52. FIG. The upper surface K2 is inclined with respect to the upper surface K1.
FIG. 39(b) shows the portions B2 formed on the upper surfaces K1 and K2 by dot hatching for easy viewing. A portion B2 shown in FIG. 39(b) is formed on the upper surface K2 so as to cover the entire surface of the upper surface K2.
FIG. 39(c) also shows the portions B2 formed on the top surfaces K1 and K2 by dot hatching for easy viewing. A portion B2 shown in FIG. 39(c) is formed on the upper surface K2 so as not to cover the entire surface of the upper surface K2. The portion B2 shown in FIG. 39(c) includes portions B2a and B2b, and does not cover the upper surface K2 in the region between the portions B2a and B2b.
Here, the portion B2 shown in FIG. 39(b) and the portion B2 shown in FIG. 39(c) are compared.
When forming the portion B2 on the upper surface K2, there is a problem that it is difficult to properly form the portion B2 on the upper surface K2 because the upper surface K2 is inclined. For example, the metal material for forming the metal layer 51b may remain excessively on the upper surface K2, causing a short circuit in the portion B2. In FIG. 39(c), if excess metal material remains in the region between the portions B2a and B2b, the portions B2a and B2b are short-circuited.
Therefore, when forming the portion B2 on the upper surface K2, it is desirable to adopt the structure shown in FIG. 39(b) instead of the structure shown in FIG. 39(c). That is, when forming the portion B2 on the upper surface K2, it is desirable that the portion B2 be formed on the upper surface K2 so as to cover the entire surface of the upper surface K2. This makes it possible to suppress the occurrence of the short circuit as described above.
For example, when the insulating film 52 of this embodiment has N upper surfaces K2, each upper surface K2 is not covered at all by the portion B2 as shown in FIG. It is desirable to either cover the entire surface with the portion B2. That is, it is desirable not to provide the upper surface K2 partially covered with the portion B2 as shown in FIG. 39(c).
Specifically, the opening H' of the semiconductor layer 51a shown in FIG. 37 has a quadrangular planar shape. Therefore, the portion B2 shown in FIG. 37 is formed on the four upper surfaces K2 in the vicinity of the four sides of the rectangular opening H'. In this case, the portion B2 shown in FIG. 37 is desirably formed on these four upper surfaces K2 so as to cover the entire surface of these four upper surfaces K2.
As described above, the bonding pads of the portion B2 and the portion B3 of the metal layer 51b of this embodiment are provided on the interlayer insulating film 12 without the semiconductor layer 51a interposed therebetween. Therefore, according to this embodiment, it is possible to suppress the above-described problems caused by the semiconductor layer 51a.
Although several embodiments have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. The novel apparatus and methods described herein can be embodied in various other forms. In addition, various omissions, substitutions, and alterations may be made to the forms of the apparatus and methods described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications as fall within the scope and spirit of the invention.

1: array chip, 2: circuit chip,
11: memory cell array, 12: interlayer insulating film,
13: interlayer insulating film, 14: substrate, 15: substrate,
21: staircase structure, 22: contact plug,
23: word wiring layer, 24: via plug,
31: transistor, 32: gate electrode, 33: contact plug, 34: wiring layer,
35: wiring layer, 36: wiring layer, 37: via plug, 38: metal pad,
41: metal pad, 42: via plug,
43: wiring layer, 44: wiring layer, 45: via plug,
51: source layer, 51a: semiconductor layer, 51b: metal layer,
52: insulating film, 52a: insulating film, 52b: insulating film,
53: passivation insulating film, 54: solder layer, 55: bonding wire,
61: insulating layer, 62: block insulating film, 63: charge storage layer,
64: tunnel insulating film, 65: channel semiconductor layer, 66: core insulating film,
71: recessed portion, 72: recessed portion, 73: recessed portion, 74: recessed portion, 75: recessed portion, 76: recessed portion,
81: insulating film, 82: semiconductor layer, 83: semiconductor layer, 84: semiconductor layer,
85: insulating film, 86: resist film, 86a: opening, 87: insulating film,
88: insulating film, 89: resist film, 89a: opening,
91: resist film, 91a: opening, 91b: opening,
92: resist film, 92a: opening, 92b: opening,
93: Insulating film, 94: Insulating film, 95: Insulating film

Claims (27)

a first substrate;
a first insulating film provided on the first substrate;
a semiconductor layer provided on the first insulating film;
a metal layer including a first portion provided on the semiconductor layer and a second portion including a bonding pad provided on the first insulating film without interposing the semiconductor layer;
A semiconductor device comprising 2. The semiconductor device according to claim 1, wherein said second portion is separated from said first portion. a memory cell array provided in the first insulating film and including a plurality of first electrode layers;
a second electrode layer provided on the memory cell array and including the semiconductor layer and the first portion of the metal layer;
3. The semiconductor device according to claim 1, further comprising: The second portion is provided on the first insulating film through a second insulating film, and the third portion including the bonding pad is provided on the first insulating film without the second insulating film. 4. The semiconductor device according to any one of claims 1 to 3, comprising: a fourth portion; The first substrate includes a plurality of first regions, and a second region provided between the first regions and subject to dicing,
5. The semiconductor device according to claim 1, wherein said semiconductor layer is provided only on said first insulating film immediately above said first region out of said first and second regions. . a transistor provided on the first substrate;
a first pad provided in the first insulating film and electrically connected to the transistor;
a second pad provided on the first pad within the first insulating film and electrically connected to the bonding pad;
6. The semiconductor device according to any one of claims 1 to 5, further comprising: 7. The semiconductor device according to claim 1, wherein said semiconductor layer comprises a recess provided within said semiconductor layer. 8. The semiconductor device according to claim 7, wherein said recess penetrates said semiconductor layer. 9. The semiconductor device according to claim 7, wherein said bonding pad is provided inside said recess in plan view. 10. The semiconductor device according to claim 7, wherein at least part of said second portion is provided within said recess. 11. The semiconductor device according to claim 7, wherein a portion of said first insulating film is provided within said recess. 12. The semiconductor device according to claim 7, wherein said recess has a width of 500 nm or less. 13. The semiconductor device according to claim 7, wherein the ratio of the area of said recess to the areas of said semiconductor layer and said recess is 10% to 15% in plan view. The second portion includes a fifth portion including a first bonding pad provided on the first insulating film without the semiconductor layer interposed therebetween, and a fifth portion provided on the first insulating film without the semiconductor layer interposed therebetween. 14. The semiconductor device according to any one of claims 1 to 13, comprising a sixth portion including a second bonding pad. 15. The semiconductor according to claim 14, wherein said first bonding pad is an I/O (Input/Output) pad for signal input/output, and said second bonding pad is a power supply pad for supplying power supply voltage. Device. 16. The semiconductor device according to claim 14, wherein said sixth portion is separated from said fifth portion. The fifth portion does not include a portion provided on the first insulating film with the semiconductor layer interposed therebetween, and the sixth portion is provided on the first insulating film with the semiconductor layer interposed therebetween. 17. A semiconductor device as claimed in any one of claims 14 to 16, comprising a portion. further comprising a second insulating film provided on the first insulating film;
the upper surface of the second insulating film includes a first upper surface and a second upper surface that is inclined with respect to the first upper surface;
18. The semiconductor device according to claim 14, wherein said sixth portion includes a portion provided on said second upper surface of said second insulating film. 19. The semiconductor device according to claim 18, wherein said sixth portion is provided on said second upper surface so as to cover the entire surface of said second upper surface. 20. The semiconductor device according to claim 18, wherein said fifth portion does not include a portion provided on said second upper surface of said second insulating film. forming a first insulating film on a first substrate;
forming a semiconductor layer on the first insulating film;
forming a metal layer including a first portion provided on the semiconductor layer and a second portion including a bonding pad provided on the first insulating film without interposing the semiconductor layer;
A method of manufacturing a semiconductor device, comprising: The first substrate includes a plurality of first regions, and a second region provided between the first regions and subject to dicing,
22. The method of manufacturing a semiconductor device according to claim 21 , wherein said semiconductor layer is formed directly above said first and second regions, and is removed from a region directly above said second region before dicing. 23. The method of manufacturing a semiconductor device according to claim 21 , further comprising forming a recess in said semiconductor layer. forming a third insulating film, which is a part of the first insulating film, on the first substrate;
forming a first pad on the third insulating film;
forming a fourth insulating film, which is another part of the first insulating film, on a second substrate;
forming a second pad on the fourth insulating film;
By bonding the first substrate and the second substrate together, the fourth insulating film is arranged on the third insulating film and the second pad is arranged on the first pad;
23. The method of manufacturing a semiconductor device according to claim 21 , further comprising: 25. The method of manufacturing a semiconductor device according to claim 24 , wherein said semiconductor layer is formed after bonding said first substrate and said second substrate together. The semiconductor layer is formed before bonding the first substrate and the second substrate together,
25. The method of manufacturing a semiconductor device according to claim 24 , further comprising forming a recess in said semiconductor layer before bonding said first substrate and said second substrate together. The semiconductor layer is formed before bonding the first substrate and the second substrate together,
25. The method of manufacturing a semiconductor device according to claim 24 , further comprising forming a recess in said semiconductor layer after bonding said first substrate and said second substrate together.

Images