TW202011521A - Device substrate - Google Patents

Abstract

A device substrate includes a flexible substrate, scan lines, data lines, a first insulation layer, active devices, and a buffer structure. The scan lines are disposed on the flexible substrate and extending along a first direction. The data lines are disposed on the flexible substrate and extending along a second direction. The first direction is staggered with the second direction. The first insulation layer is disposed between the scan lines and the data lines. The active devices are electrically connected with the scan lines and the data lines. The buffer structure is disposed on the flexible substrate and includes first buffer lines and second buffer lines. The first buffer lines are extending along a third direction. The second buffer lines are extending along a fourth direction. The third direction is staggered with the fourth direction.

Description

Component substrate

The present invention relates to an element substrate, and particularly relates to an element substrate including a flexible substrate.

With the development of technology, the appearance rate of flexible electronic products on the market has gradually increased, and various related technologies have also emerged. Flexible electronic products are usually manufactured on a hard substrate before removing the hard substrate during the back end of line (BEOL) process. However, when the hard substrate is removed, the flexible electronic product is easily deformed due to stress pulling, so that the flexible electronic product cannot be accurately aligned when it is joined with other components, which affects the yield of the product.

The invention provides an element substrate, which can improve the problem of deformation caused by stress pulling.

At least one embodiment of the present invention provides a device substrate, including a flexible substrate, a plurality of scanning lines, a plurality of data lines, a first insulating layer, a plurality of active components, and a buffer structure. A plurality of scan lines are located on the flexible substrate and extend along the first direction. Multiple data lines are located on the flexible substrate and extend along the second direction. The first direction is interleaved with the second direction. The first insulating layer is located between the scan line and the data line. Multiple active components are electrically connected to the scan line and the data line. The buffer structure is located on the flexible substrate. The buffer structure includes a plurality of first buffer lines and a plurality of second buffer lines. A plurality of first buffer lines extend along the third direction. A plurality of second buffer lines extend along the fourth direction. The third direction is interleaved with the fourth direction. The first direction, the second direction, the third direction, and the fourth direction are different from each other.

Based on the above, the buffer structure can distribute the stress received by the element substrate to a two-dimensional plane, and can improve the problem of deformation of the element substrate due to stress pulling.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or portions, these elements, components, regions, and/or Or part should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, the "first element", "component", "region", "layer" or "portion" discussed below may be referred to as a second element, component, region, layer or section without departing from the teachings herein.

FIG. 1A is a schematic top view of a device substrate according to an embodiment of the invention. FIG. 1B is a partially enlarged schematic view of the element substrate of FIG. 1A. Fig. 1C is a schematic sectional view taken along the line aa' of Fig. 1B. For convenience of description, some components of the element substrate are omitted in FIGS. 1A, 1B, and 1C.

Please refer to FIGS. 1A, 1B, and 1C, where FIG. 1B is, for example, a schematic top view of the four pixel structures PX in FIG. 1A. The element substrate 10 includes a flexible substrate SB, a plurality of scan lines SL, a plurality of data lines DL, a first insulating layer I1, a plurality of active elements T, and a buffer structure B. In this embodiment, the element substrate 10 further includes a first driving circuit DR1, a second driving circuit DR2, a pixel electrode PE, a common electrode CE, and an alignment layer AL.

Examples of the flexible substrate SB include polyamide (PA), polyimide (PI), polymethyl methacrylate (PMMA), and polyethylene naphthalate Polyethylene naphthalate (PEN), polyethylene terephthalate (PET), fiber reinforced plastics (FRP), polyetheretherketone (PEEK), epoxy resin or other A suitable material or a combination of at least two of the foregoing, but the invention is not limited thereto. In addition, the materials of the flexible substrate SB may be all organic material mixtures, organic material mixed inorganic materials, organic molecules bonded to inorganic molecules, or other suitable materials. The flexible substrate SB includes an active area AR and a peripheral area BR located on at least one side of the active area AR.

A plurality of scanning lines SL, a plurality of data lines DL, a first driving circuit DR1 and a second driving circuit DR2 are located on the flexible substrate SB. In this embodiment, the first driving circuit DR1 and the second driving circuit DR2 are located on the peripheral area BR, the scan line SL extends from the position of the first driving circuit DR1 into the active area AR, and the data line DL is from the second driving circuit DR2 The location of the extension extends into the active area AR, but the invention is not limited to this. In some embodiments, the first driving circuit DR1 and/or the second driving circuit DR2 may also be disposed in the active area AR. In some embodiments, the first driving circuit DR1 and the second driving circuit DR2 are, for example, a circuit board or a chip, and are electrically connected to the scan respectively through a plurality of pads (not shown) located on the peripheral area BR The line SL and the data line DL, but the invention is not limited thereto. In some embodiments, the first driving circuit DR1 and the second driving circuit DR2 may be driving circuits formed directly on the flexible substrate SB.

The scanning line SL extends along the first direction E1. The data line DL extends along the second direction E2. The first direction E1 is staggered with the second direction E2. In this embodiment, the first direction E1 is orthogonal to the second direction E2, but the invention is not limited thereto.

Multiple scan lines SL and multiple data lines DL define multiple pixel structures PX. The range of each pixel structure PX is, for example, the range between two adjacent data lines DL and between two adjacent scanning lines SL.

1B and 1C, the active element T is located on the active area AA of the flexible substrate SB, and is electrically connected to the scan line SL and the data line DL. In this embodiment, a shielding metal layer SM and an insulating layer I0 are also sandwiched between the active device T and the flexible substrate SB. The shielding metal layer SM overlaps the active device T, and the shielding metal layer SM is located between the active device T and the flexible substrate SB. The shielding metal layer SM can improve the leakage problem of the active device T.

The active device T includes a semiconductor channel layer CH, a gate G, a source S and a drain D. The gate G is electrically connected to the corresponding scan line SL. The semiconductor channel layer CH overlaps the gate G, and a gate insulating layer GI is sandwiched between the gate G and the semiconductor channel layer CH. The first insulating layer I1 covers the gate G, and the first insulating layer I1 is located between the scan line SL and the data line DL. The source electrode S and the drain electrode D are located on the first insulating layer I1, and are electrically connected to the semiconductor channel layer CH through the openings H1 and H2, respectively. The openings H1 and H2 penetrate at least the first insulating layer I1. In this embodiment, the openings H1 and H2 penetrate the gate insulating layer GI and the first insulating layer I1. The source electrode S is electrically connected to the corresponding data line DL.

Although in this embodiment, the active element T is an example of a top gate type thin film transistor, the invention is not limited to this. In other embodiments, the active element T may also be a bottom gate type or other type of thin film transistor. When the active element T is a bottom gate type thin film transistor, the third element between the scan line SL and the data line DL An insulating layer can be used as the gate insulating layer.

The second insulating layer I2 covers the source electrode S and the drain electrode D. The common electrode CE is located on the second insulating layer I2 and has an opening O1 corresponding to the active element T. The third insulating layer I3 covers the common electrode CE. The pixel electrode PE covers the third insulating layer I3 and is separated from the common electrode CE. The pixel electrode PE is electrically connected to the drain electrode D of the active device T through the opening O3. The opening O3 penetrates the third insulating layer I3 and is provided corresponding to the opening O2 of the second insulating layer I2 and the opening O1 of the common electrode CE. The alignment layer AL is located on the pixel electrode PE and the third insulating layer I3.

Although in this embodiment, the common electrode CE is positioned between the pixel electrode PE and the flexible substrate SB, and the pixel electrode PE has a plurality of slits t, the invention is not limited thereto. In other embodiments, the pixel electrode PE is located between the common electrode CE and the flexible substrate SB, and the common electrode CE has a plurality of slits t.

Please refer to FIGS. 1A, 1B and 1C, the buffer structure B is located on the flexible substrate SB. For example, the buffer structure B may be located on the active area AA and/or the peripheral area BR of the flexible substrate SB. The buffer structure B includes a plurality of first buffer lines B1 and a plurality of second buffer lines B2. A plurality of first buffer lines B1 extend along the third direction E3. A plurality of second buffer lines B2 extend E4 along the fourth direction. The third direction E3 is interleaved with the fourth direction E4. The first direction E1, the second direction E2, the third direction E3, and the fourth direction E4 are different from each other. In some embodiments, the angle between the third direction E3 and the first direction E1 is, for example, greater than 0 degrees and less than 90 degrees, preferably between 15 degrees and 75 degrees, or between 30 degrees and 60 degrees, or more It is preferably between 40 degrees and 50 degrees, and the included angle between the fourth direction E4 and the second direction E2 is, for example, greater than 0 degrees and less than 90 degrees, preferably between 15 degrees and 75 degrees, or between 30 degrees and 60 degrees, Or more preferably between 40 degrees and 50 degrees.

In this embodiment, the first buffer line B1 and the second buffer line B2 are located in the same film layer. It can also be said that the first buffer line B1 and the second buffer line B2 are formed by the same patterning process. The invention is not limited to this. In other embodiments, the first buffer line B1 and the second buffer line B2 belong to different film layers. It can also be said that the first buffer line B1 and the second buffer line B2 can be formed by different patterning processes.

In this embodiment, at least one of the first buffer line B1 and the second buffer line B2 belongs to the same film layer as the scan line SL, and the scan line SL is separated from the first buffer line B1 and the second buffer line B2. There is a gap between the scan line SL and the first buffer line B1 and the two are not in contact, and there is a gap between the scan line SL and the second buffer line B2 and the two are not in contact. For example, the first buffer line B1, the second buffer line B2, and the scan line SL all belong to the same film layer and are formed of the same conductive material, such as metal materials, alloys, nitrides of metal materials, and metal materials Oxides, oxynitrides of metal materials or other suitable materials or stacked layers of metal materials and other conductive materials. Therefore, the first buffer line B1, the second buffer line B2, and the scan line SL can be defined in the same patterning process.

In this embodiment, each pixel structure PX has a first buffer line B1 and a second buffer line B2, and each first buffer line B1 is only interleaved with a corresponding second buffer line B2, but The invention is not limited to this. In other embodiments, each first buffer line B1 and/or each second buffer line B2 may span multiple pixel structures PX.

In some embodiments, the device substrate 10 is formed on a hard substrate, and the hard substrate needs to be removed in the back end of line (BEOL) process, for example, the device substrate 10 is peeled from the hard substrate. A force is applied along the extending direction of the scanning line SL or the data line DL to peel off the element substrate 10, and the stress received by the element substrate 10 is still dispersed to the two-dimensional plane by the buffer structure B, making the element substrate 10 not easy to be stressed due to the stress after peeling Pulling and deforming improves the product yield of the element substrate 10.

Based on the above, the buffer structure B of the element substrate 10 includes the first buffer line B1 and the second buffer line B2 in different extending directions, and the extending direction of the first buffer line B1 and the second buffer line B2 is different from the scan line SL and the data line DL, therefore, can solve the problem of the element substrate 10 being deformed due to stress pulling.

FIG. 2 is a partially enlarged schematic view of a device substrate according to an embodiment of the invention. For the convenience of description, FIG. 2 omits the drawing of some components of the element substrate. It must be noted here that the embodiment of FIG. 2 continues to use the element labels and partial contents of the embodiments of FIGS. 1A to 1C, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the same technical content is omitted. Instructions. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

The main difference between the device substrate 20 of FIG. 2 and the device substrate 10 of FIG. 1A is that at least one of the first buffer line B1 and the second buffer line B2 of the device substrate 20 and the data line DL belong to the same film layer.

Please refer to FIG. 2. In this embodiment, the first buffer line B1 and the second buffer line B2 both belong to the same film layer as the data line DL and are formed of the same conductive material, such as metal materials, alloys, metals The nitride of the material, the oxide of the metal material, the oxynitride of the metal material or other suitable materials or the stacked layer of the metal material and other conductive materials. Therefore, the first buffer line B1, the second buffer line B2, and the data line DL can be defined in the same patterning process.

The data line DL is separated from the first buffer line B1 and the second buffer line B2. For example, there is a gap between the data line DL and the first buffer line B1 and the two are not in contact, and there is a gap between the data line DL and the second buffer line B2 and the two are not in contact.

Based on the above, the buffer structure B of the element substrate 20 includes the first buffer line B1 and the second buffer line B2 in different extending directions, and the extending direction of the first buffer line B1 and the second buffer line B2 is different from the scan line SL and the data line DL, therefore, can solve the problem that the element substrate 20 is deformed due to stress pulling.

3 is a partially enlarged schematic view of a device substrate according to an embodiment of the present invention. For convenience of description, FIG. 3 omits a part of components of the element substrate. It must be noted here that the embodiment of FIG. 3 continues to use the element labels and partial contents of the embodiments of FIGS. 1A to 1C, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the same technical content is omitted. Instructions. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

The main difference between the element substrate 30 of FIG. 3 and the element substrate 10 of FIG. 1A is that at least one of the first buffer line B1 and the second buffer line B2 of the element substrate 30 belongs to the same film layer as the shielding metal layer SM.

Please refer to FIG. 3, in this embodiment, the first buffer line B1 and the second buffer line B2 both belong to the same film layer as the shielding metal layer SM and are formed of the same conductive material, such as metal materials, alloys, A nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material or other suitable materials or a stacked layer of a metal material and other conductive materials.

In this embodiment, the film layer where the buffer structure B is located is different from the film layer where the scanning line SL is located and the film layer where the data line DL is located.

Although in this embodiment, it is exemplified that both the first buffer line B1 and the second buffer line B2 belong to the same film layer as the shielding metal layer SM, the present invention is not limited thereto. In other embodiments, at least one of the first buffer line B1 and the second buffer line B2 belongs to the same film layer as the semiconductor channel layer CH and is formed of the same conductive material, such as amorphous silicon, polysilicon, Microcrystalline silicon, single crystal silicon organic semiconductor materials, oxide semiconductor materials (for example: indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or a combination of the above), or other suitable materials, or containing The dopant is in the above materials or a combination of the above. In some embodiments, both the first buffer line B1 and the second buffer line B2 belong to the same film layer as the semiconductor channel layer CH.

In this embodiment, since the film layer where the first buffer line B1 and the second buffer line B2 are located is different from the scan line SL and the data line DL, the first buffer line B1 and the second buffer line B2 need not be different from the scan line SL It is disconnected from the data line DL, and the first buffer line B1, the second buffer line B2, and the shielding metal layer SM are connected to each other and are substantially connected together. It can also be said that part of the shielding metal layer SM belongs to the first buffer line B1 Part of and part of the shielding metal layer SM belongs to a part of the second buffer line B2. Each first buffer line B1 and each second buffer line B2 in the buffer structure B may span multiple pixel structures PX, and each first buffer line B1 is interleaved with more than one corresponding second buffer line B2 .

Based on the above, the buffer structure B of the element substrate 30 includes the first buffer line B1 and the second buffer line B2 in different extending directions, and the extending direction of the first buffer line B1 and the second buffer line B2 is different from the scan line SL and the data line DL, therefore, can solve the problem that the element substrate 30 is deformed due to stress pulling.

FIG. 4 is a schematic top view of a device substrate according to an embodiment of the invention. For convenience of description, FIG. 4 omits a part of components of the element substrate. It must be noted here that the embodiment of FIG. 4 uses the element numbers and partial contents of the embodiment of FIG. 1, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

The main difference between the element substrate 40 of FIG. 4 and the element substrate 10 of FIG. 1 is that the first buffer line B1 and the second buffer line B2 of the element substrate 40 belong to different film layers.

Please refer to FIG. 4, the first buffer line B1 and the second buffer line B2 belong to different film layers. The film of the first buffer line B1 in the buffer structure B is different from the scan line SL and the data line DL. Each first buffer line B1 can span multiple pixel structures PX, and each first buffer line B1 and one The second buffer lines B2 corresponding to the above are interleaved. The first buffer line B1 and the second buffer line B2 belong to the same or different materials. In an embodiment, the first buffer line B1 may belong to the same film layer as the shielding metal layer SM, for example.

In this embodiment, the film layer where the second buffer line B2 is located is the same as the scan line SL or the data line DL. Therefore, the second buffer line B2 is separated from the scan line SL or the data line DL to prevent the element substrate 40 from being short-circuited.

Based on the above, the buffer structure B of the element substrate 40 includes the first buffer line B1 and the second buffer line B2 in different extending directions, and the extending direction of the first buffer line B1 and the second buffer line B2 is different from the scan line SL and the data line DL, therefore, can solve the problem that the element substrate 40 is deformed due to stress pulling.

5 is a schematic top view of a device substrate according to an embodiment of the invention. For convenience of description, FIG. 5 omits a part of components of the element substrate. It must be noted here that the embodiment of FIG. 5 uses the element numbers and partial contents of the embodiment of FIG. 3, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

The main difference between the element substrate 50 of FIG. 5 and the element substrate 30 of FIG. 3 is that the distribution of the buffer structure B of the element substrate 50 is sparse than that of the buffer structure B of the element substrate 30.

Please refer to FIG. 5, part of the pixel structure PX does not have the buffer structure B. In this embodiment, the buffer structure B is not taken as an example in about half of the pixel structure PX, but the invention is not limited to this. The distribution of the buffer structure B can be adjusted according to actual needs.

Although in this embodiment, it is exemplified that the first buffer line B1 and the second buffer line B2 belong to the same film layer, the invention is not limited thereto. In other embodiments, the first buffer line B1 and the second buffer line B2 belong to different film layers. In other embodiments, the film layer where the first buffer line B1 and/or the second buffer line B2 is located is the same as the scan line SL or the data line DL, therefore, the first buffer line B1 and/or the second buffer line B2 and the scan The line SL or the data line DL is separated to avoid short circuit of the element substrate 50.

Based on the above, the buffer structure B of the element substrate 50 includes the first buffer line B1 and the second buffer line B2 in different extending directions, and the extending direction of the first buffer line B1 and the second buffer line B2 is different from the scan line SL and the data line DL, therefore, can solve the problem that the element substrate 50 deforms due to stress pulling.

6A is a schematic top view of a device substrate according to an embodiment of the invention. Fig. 6B is a schematic sectional view taken along the line bb' of Fig. 6A. For convenience of description, some components of the element substrate are omitted in FIGS. 6A and 6B. It must be noted here that the embodiments of FIGS. 6A and 6B continue to use the element numbers and partial contents of the embodiments of FIGS. 1A to 1C, wherein the same or similar reference numbers are used to indicate the same or similar elements, and the same is omitted. Description of technical content. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

The main difference between the element substrate 60 of FIGS. 6A and 6B and the element substrate 10 of FIG. 1B is that the active element T of the element substrate 60 is electrically connected to the light sensing element LS.

Please refer to FIG. 6A and FIG. 6B, the active element T is a bottom gate type thin film transistor. For example, the gate G of the active device T is located between the semiconductor channel layer CH and the flexible substrate SB, and the first insulating layer I1 is located between the gate G and the semiconductor channel layer CH and the scan line SL and the data line DL between. The source electrode S and the drain electrode D are located on the first insulating layer I1 and the semiconductor channel layer CH, and are electrically connected to the semiconductor channel layer CH. In some embodiments, there may be an ohmic contact layer (not shown) between the source S and the semiconductor channel layer CH and between the drain D and the semiconductor channel layer CH, but the invention is not limited thereto.

The light sensing element LS has a first electrode X1, a photosensitive layer SN, and a second electrode X2 that are sequentially stacked. The first electrode X1 is electrically connected to the drain electrode D of the active device T, and the first electrode X1 and the drain electrode D are connected together, for example. The second insulating layer I2 covers the source electrode S, the drain electrode D, and the first electrode X1. The opening O2 of the second insulating layer I2 is provided corresponding to the first electrode X1. The photosensitive layer SN is located in the opening O2 and is electrically connected to the first electrode X1. The material of the photosensitive layer SN includes silicon-rich oxide, silicon-rich nitride, silicon-rich oxynitride, silicon-rich carbide, silicon-rich carbon oxide, hydrogenated silicon-rich oxide, hydrogenated silicon-rich nitride, hydrogenated silicon-rich carbide Or other suitable materials or combinations of the above materials. The material of the photosensitive layer SN may also be PIN material, PN material or other suitable materials. The second electrode X2 is located on the photosensitive layer SN. The second electrode X2 is, for example, a transparent conductive material.

The third insulating layer I3 covers the light sensing element LS and the second insulating layer I2. The conductive layer CL is located on the third insulating layer I3 and overlaps the active device T. The active element T is located between the conductive layer CL and the flexible substrate SB. The conductive layer CL can improve the leakage problem of the active device T.

At least one of the first buffer line B1 and the second buffer line B2 belongs to the same film layer as the conductive layer CL. In this embodiment, both the first buffer line B1 and the second buffer line B2 belong to the same film layer as the conductive layer CL and are formed of the same conductive material, such as metal materials, alloys, nitrides of metal materials, Oxides of metal materials, oxynitrides of metal materials or other suitable materials or stacked layers of metal materials and other conductive materials. In this embodiment, the buffer structure B and the conductive layer CL can be used as a common electrode, and are electrically connected to the second electrode X2 of the light sensing element LS through the opening O3 of the third insulating layer I3. The fourth insulating layer I4 covers the third insulating layer I3, the buffer structure B, and the conductive layer CL.

Based on the above, the buffer structure B of the element substrate 60 includes the first buffer line B1 and the second buffer line B2 in different extending directions, and the extending direction of the first buffer line B1 and the second buffer line B2 is different from the scan line SL and the data line DL, therefore, can solve the problem that the element substrate 60 is deformed due to stress pulling.

7 is a schematic cross-sectional view of a device substrate according to an embodiment of the invention. For convenience of description, FIG. 7 omits a part of components of the element substrate. It must be noted here that the embodiment of FIG. 7 follows the element numbers and partial contents of the embodiment of FIG. 3, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

The main difference between the element substrate 70 of FIG. 7 and the element substrate 30 of FIG. 3 is that the active element T of the element substrate 70 is electrically connected to the organic light emitting diode OLED.

Referring to FIG. 7, the gate G of the active device T is connected to the scan line SL, and the source S is connected to the data line DL. A shielding metal layer SM, an insulating layer I0, and a third insulating layer I3 are sandwiched between the active device T and the flexible substrate SB. The shielding metal layer SM overlaps the active device T, and the shielding metal layer SM is located between the insulating layer I0 and the third insulating layer I3. In this embodiment, the buffer structure B belongs to the same film layer as the shielding metal layer SM, for example.

The second insulating layer I2 covers the source S, the drain D, and the first insulating layer I1, and has an opening O2 corresponding to the active element T. The second insulating layer I2 may be a single insulating layer or a multiple insulating layer.

The organic light emitting diode OLED has a first electrode X1, an organic light emitting layer OL, and a second electrode X2 that are sequentially stacked. The first electrode X1 is located on the second insulating layer I2 and is electrically connected to the drain D of the active device T through the opening O2. The opening O4 of the pixel definition layer PDL exposes the first electrode X1, the organic light-emitting layer OL is located in the opening O4, and the organic light-emitting layer OL is electrically connected to the first electrode X1. The second electrode E2 is located on the organic light-emitting layer OL and the pixel definition layer PDL, and the second electrode X2 is electrically connected to the organic light-emitting layer OL. In this embodiment, the element substrate 70 further includes an encapsulation layer TFE, which is located on the organic light emitting diode OLED and the pixel definition layer PDL.

8 is a schematic cross-sectional view of an element substrate according to an embodiment of the invention. For the convenience of explanation, FIG. 8 omits a part of components of the element substrate. It must be noted here that the embodiment of FIG. 8 follows the element numbers and partial contents of the embodiment of FIG. 7, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

The main difference between the element substrate 80 of FIG. 8 and the element substrate 70 of FIG. 7 is that the buffer structure B of the element substrate 80 is located on the first insulating layer I1.

Please refer to FIG. 8, the third insulating layer I3 is located between the first insulating layer I1 and the scanning line SL, wherein at least one of the first buffer line and the second buffer line of the buffer structure B is located between the third insulating layer I3 and the third Between an insulating layer I1.

In this embodiment, the element substrate 80 selectively includes a capacitor electrode M, which is located on the gate insulating layer GI and overlaps the buffer structure B. The capacitor electrode M and the buffer structure B can form a capacitor together, but the invention is not limited thereto.

In summary, the buffer structure of the device substrate includes first buffer lines and second buffer lines with different extension directions, and the extension directions of the first buffer lines and the second buffer lines are different from the scan lines and the data lines, so it can be improved The component substrate is deformed due to stress pulling.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10, 20, 30, 40, 50, 60, 70, 80: Element substrate AR: Active area AL: Alignment layer aa', bb': Section line B: Buffer structure B1: First buffer line B2: Second buffer line BR: Peripheral area CE: Common electrode CH: Semiconductor channel layer D: Drain DL: Data line DR1: First drive circuit DR2: Second drive circuit E1, E2, E3, E4: Direction G: Gate GI: Gate insulation Layers H1, H2, O1, O2, O3: openings I0, I1, I2, I3: insulating layer LS: sensing element OL: organic light-emitting layer OLED: organic light-emitting diode PDL: pixel definition layer PE: pixel electrode PX: pixel structure S: source electrode SB: flexible substrate SL: scan line SM: shielding metal layer SN: photosensitive layer T: active element t: slit TFE: encapsulation layer X1: first electrode X2: second electrode

FIG. 1A is a schematic top view of a device substrate according to an embodiment of the invention. FIG. 1B is a partially enlarged schematic view of the element substrate of FIG. 1A. Fig. 1C is a schematic sectional view taken along the line aa' of Fig. 1B. FIG. 2 is a partially enlarged schematic view of a device substrate according to an embodiment of the invention. 3 is a partially enlarged schematic view of a device substrate according to an embodiment of the present invention. FIG. 4 is a schematic top view of a device substrate according to an embodiment of the invention. 5 is a schematic top view of a device substrate according to an embodiment of the invention. 6A is a partially enlarged schematic view of a device substrate according to an embodiment of the present invention. Fig. 6B is a schematic sectional view taken along the line bb' of Fig. 6A. 7 is a schematic cross-sectional view of a device substrate according to an embodiment of the invention. 8 is a schematic cross-sectional view of an element substrate according to an embodiment of the invention.

10: component substrate

AR: Active area

B: buffer structure

B1: First buffer line

B2: second buffer line

BR: surrounding area

DL: data cable

DR1: the first driving circuit

DR2: second drive circuit

E1, E2, E3, E4: direction

PX: pixel structure

SB: Flexible substrate

SL: Scan line

Claims (12)

A device substrate, including: a flexible substrate; a plurality of scanning lines on the flexible substrate and extending along a first direction; a plurality of data lines on the flexible substrate and along A second direction extends, the first direction intersects the second direction; a first insulating layer is located between the scan lines and the data lines; a plurality of active elements are electrically connected to the scan lines and The data lines; and a buffer structure on the flexible substrate, the buffer structure comprising: a plurality of first buffer lines extending along a third direction; and a plurality of second buffer lines along a first The four directions extend, and the third direction intersects the fourth direction, wherein the first direction, the second direction, the third direction, and the fourth direction are different from each other. The device substrate as claimed in item 1 of the patent scope, wherein at least one of the first buffer lines and the second buffer lines and the scan lines belong to the same film layer, and the scan lines and the scan lines The first buffer line and the second buffer lines are separated. The device substrate according to item 1 of the patent application scope, wherein at least one of the first buffer lines and the second buffer lines and the data lines belong to the same film layer, and the data lines and the data lines The first buffer line and the second buffer lines are separated. The device substrate as described in item 1 of the patent application scope further includes: a shielding metal layer overlapping the active components, and the shielding metal layer is located between the active components and the flexible substrate, wherein the At least one of the first buffer line and the second buffer lines belongs to the same film layer as the shielding metal layer. The device substrate as described in item 1 of the patent application scope further includes: a conductive layer overlapping the active devices, and the active devices are located between the conductive layer and the flexible substrate, wherein the first At least one of the buffer line and the second buffer lines and the conductive layer belong to the same film layer. The device substrate as described in item 1 of the patent application scope, wherein each of the active devices includes: a gate electrically connected to the corresponding scan line; a semiconductor channel layer overlapping the gate, wherein the first At least one of the buffer line and the second buffer lines belongs to the same film layer as the semiconductor channel layer; a source electrode electrically connected to the semiconductor channel layer and the corresponding data line; and a drain electrode electrically connected The semiconductor channel layer. The element substrate as described in item 1 of the patent application scope, wherein the first buffer lines and the second buffer lines belong to different film layers. The element substrate as described in item 1 of the patent application scope, wherein the first buffer lines and the second buffer lines are of different materials. The device substrate as described in item 1 of the patent application scope, wherein each of the first buffer lines is only interlaced with a corresponding second buffer line. The device substrate as described in item 1 of the patent application scope, wherein each of the first buffer lines is interleaved with more than one corresponding second buffer lines. The element substrate as described in item 1 of the patent application range, wherein the first direction is orthogonal to the second direction, the angle between the third direction and the first direction is 15 degrees to 75 degrees, and the fourth The angle between the direction and the second direction is 15 degrees to 75 degrees. The device substrate as described in item 1 of the patent application scope further includes: a second insulating layer between the first insulating layer and the scan lines, wherein the first buffer lines and the second buffer lines At least one of them is located between the second insulating layer and the first insulating layer.

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