TW202010279A - Reception device, timing detection device, and timing detection method - Google Patents

Abstract

The reception device is provided with: a spreading code multiplication unit (232) which generates a correlation value sequence by multiplying a receive signal to which direct sequence spread spectrum is applied by a complex conjugate of a spreading code used for direct sequence spread spectrum; a first correlation power calculation unit (23A) which adds correlation values in the correlation value sequence generated with each multiplication by the spreading code multiplication unit (232) to generate a correlation addition value and calculates a first correlation power value which is a power value representing the correlation addition value; a second correlation power calculation unit (23B) which divides the correlation value sequence into multiple blocks, adds correlation values in each block to generate a partial correlation value and determine a power value representing the partial correlation value per block, and adds the power values obtained for each block to calculate a second correlation power value; and a timing detection unit (23C) for detecting, on the basis of the first correlation power value and the second correlation power value, a timing at which the transmission device originating the receive signal multiplied a transmit signal by the spreading code in direct sequence spread spectrum.

Description

Receiver, timing detection device and timing detection method

The invention relates to a receiving device, a timing detection device and a timing detection method for receiving a signal that performs direct spreading.

In direct spread spectrum communication, the transmitter expands the signal in a wide frequency band by multiplying the modulated signal by the expansion symbol, and transmits the expanded signal to the receiver. The receiver demultiplexes the received signal after inverse expansion by multiplying the received signal by the same expansion symbol as the expansion symbol used by the transmitter. In order for the receiver to perform the correct inverse expansion and to estimate the timing of the expansion symbol, that is, the transmitter acquires the timing of multiplying the modulation signal by the timing of the expansion symbol, the received signal must be multiplied by the expansion symbol at the estimated timing.

In the method described in Non-Patent Document 1, an example of a conventional initial acquisition method, a selector that divides a matched filter (Matched Filter) by which the received signal is multiplied by the expansion sign to a complex number is detected, and the signal output from each selector is detected. 'S phase difference. In addition, the average detected phase difference is the phase difference detected in the symbols received in the past, and the expansion sequence timing for expanding the symbol timing is estimated based on the averaged phase difference. As a result, in an environment where there is a frequency shift, the initial acquisition can be completed with good accuracy and in a short time. [Advanced technical documents] [Non-Patent Document]

[Non-Patent Document 1] Hiroshi Yasushi et al., "Initial acquisition method of direct spread spectrum communication that simultaneously infers the sequence timing and frequency offset", Journal of Electronic Information and Communications Society, Journal B J98-B Volume 12, No. 1277-1288 , 2015.

[Problems to be solved by the invention]

In the initial acquisition method described in Non-Patent Document 1, the resistance to frequency offset is improved by increasing the number of divisions of the matched filter, but in the sampling timing other than the expansion sequence timing, a sidelobe of the correlation value appears, and, Not only does the number of divisions increase, but sidelobes also appear due to oversampling. Therefore, the possibility of erroneously judging that the timing of the side lobe is the timing of the unfolding sequence increases, and there is a problem that the accuracy of judgment deteriorates.

The present invention has been made in view of the foregoing, and an object thereof is to obtain a receiving device that can improve the estimation accuracy of the expansion symbol timing. [Means to solve the problem]

In order to solve the above-mentioned problems and achieve the objective, the receiving device according to the present invention includes a spread symbol multiplying unit that multiplies the conjugate complex number of the spread symbol used in direct spread spectrum for the received signal subjected to direct spread spectrum to generate a sequence of correlation values; and The first correlation power calculation unit, the addition expansion symbol multiplication unit generates each correlation value of the correlation value sequence generated by multiplication, generates a correlation addition value, and calculates the first correlation power value of the power value of the correlation addition value. In addition, the receiving device includes a second correlation power calculation unit, which divides the correlation value sequence into complex blocks, and for each block, adds the correlation values in the block to generate partial correlation values while calculating partial correlation values The power value of each is added to the power value obtained in each block to calculate the second related power value; and the timing detection unit detects the transmission of the transmission source of the received signal based on the first related power value and the second related power value The device multiplies the transmitted signal by the timing of the spread symbol in direct spreading. [Effect of the invention]

According to the receiving device of the present invention, the effect that the estimation accuracy of the expansion symbol timing can be improved can be achieved.

Hereinafter, the receiving device, the timing detection device, and the timing detection method according to the embodiments of the present invention will be described in detail based on the drawings. In addition, this invention is not limited by this embodiment.

First embodiment First, the configuration and operation of the transmitter of the transmission device that transmits signals to the reception device of the embodiment of the present invention will be described. Fig. 1 is a diagram showing a configuration example of a conveyor according to the first embodiment. The transmitter 1 of this embodiment includes a modulation unit 11, a developed symbol generating unit 12, an expanded unit 13, a transmission filter 14, and a transmission antenna 15.

The outline of the operation of the conveyor 1 shown in FIG. 1 will be described. FIG. 2 is a flowchart showing an example of the operation of the conveyor 1 of the first embodiment. FIG. 3 is a diagram showing the structure of the signal frame transmitted by the conveyor 1 of the first embodiment. As shown in FIG. 3, the signal transmitted by the transmitter 1 is composed of text and data. In the foregoing, the receiving side transmits a known bit pattern (hereinafter, referred to as a known sequence). The known sequence transmitted in the previous text is used by the acquisition unit and the synchronization tracking unit at the initial stage of the process of estimating the symbol timing expansion. The modulation section 11 of the transmitter 1 inputs a known sequence at the timing of the previous transmission, and inputs information bits at the timing of the transmission of data.

The modulation unit 11 modulates the input known sequence and information bits, generates a modulation signal of the transmission signal, and outputs the generated modulation signal to the expansion unit 13 (step S11). The modulation unit 11 can use, for example, PSK (Phase Shift Keying) and FSK (Frequency Shift Keying) as modulation methods. The modulation section 11 uses QPSK (Quadrature Phase Shift Keying) of PSK 1 to modulate the information bit, and receives the information bit in 2-bit units and outputs the information bit corresponding to the 2-bit Complex signal of the value indicated by the element.

The expansion symbol generating unit 12 generates the expansion symbol used by the expansion unit 13 to expand the modulation signal input from the modulation unit 11 in a wide frequency band, and transfers the generated expansion symbol to the expansion unit 13 (step S12). In this embodiment, a symbol with good correlation characteristics is used as the expansion symbol. The so-called symbol with good correlation characteristics is a symbol whose auto-correlation function is at its maximum when there is no timing gap, and becomes low when there is a gap. An example of a symbol with good correlation characteristics is the Zadoff-Chu sequence. When the sequence length N _C is an even number, the t-th element C(t) of the Zadoff-Chu sequence C is expressed by equation (1). C(t)=exp(jM _c πt ² /N _c ) (1)

Here, M _C is the sequence parameter, and N _C are coprime. Upon receiving a signal of the present embodiment, the transfer conveyor receives a Zadoff-Chu sequence is used for initial acquisition, to expand the center symbol timing sampling timing for a certain period of use of the correlation value becomes large M _C = 1. When M _C ≠1, the correlation value becomes larger due to the timing farther away from the expansion symbol timing.

The expansion unit 13 multiplies the modulation signal input from the modulation unit 11 by the expansion symbol input from the expansion symbol generation unit 12 to perform direct spreading (step S13). The unfolding unit 13 transfers the direct spread signal of the modulated signal after direct spread to the transmission filter 14.

The transmission filter 14 performs band limitation on the direct spread signal input from the expansion unit 13 and delivers the band-limited signal to the transmission antenna 15 (step S14).

The transmission antenna 15 transmits the signal handed over from the transmission filter 14 (step S15).

In addition, although the description is omitted in FIGS. 1 and 2, the signal output from the transmission filter 14 is converted from a digital signal to an analog signal, upconverted, and then transmitted from the transmission antenna 15.

Next, the configuration and operation of the receiver of the receiving device of this embodiment will be described. FIG. 4 is a diagram showing a configuration example of the receiver according to the first embodiment. The receiver 2 according to this embodiment includes a receiving antenna 21, a receiving filter 22, an initial acquisition unit 23, a developed symbol generating unit 24, a de-expanding unit 25, a synchronization tracking unit 26, and a demodulation unit 27.

The outline of the operation of the receiver 2 shown in FIG. 4 will be described. FIG. 5 is a flowchart showing an example of the operation of the receiver 2 of the first embodiment.

The receiving antenna 21 receives the signal transmitted from the transmitter 1 and transfers the received signal to the receiving filter 22 (step S21).

The reception filter 22 performs band limitation on the received signal delivered from the receiving antenna 21, and delivers the received signal after the implementation of the band limitation to the initial acquisition unit 23 and the reverse expansion unit 25 (step S22).

In addition, although description is omitted in FIGS. 4 and 5, the signal received by the reception antenna 21 is downconverted, and after conversion from an analog signal to a digital signal, the reception filter 22 performs band limitation.

The initial acquisition unit 23 performs initial acquisition based on the signal delivered from the reception filter 22 (step S23). Specifically, the initial acquisition unit 23 performs coarse synchronization of the estimated timing using an accuracy that is within 1/2 wafer of the error from the development symbol timing. That is, the initial acquisition unit 23 becomes a positive detection when it is estimated that the timing is "(expanded symbol timing)-(1/2 wafer)" or more and "(expanded symbol timing) + (1/2 wafer)" or less. Here, the expansion symbol timing is the timing at which the expansion unit 13 multiplies the modulation signal by the expansion symbol in the conveyor 1, and the so-called wafer means one element unit of the expansion symbol. When one chip of the unfolded symbol is processed by double-oversampling, the initial acquisition unit 23 becomes a positive detection even if it estimates the timing that is ±1 sampled from the unfolded symbol timing. The operation details of the initial acquisition unit 23 will be described later. The initial acquisition unit 23 notifies the estimated timing of the coarse synchronization detection by the expansion symbol generation unit 24. The initial acquisition unit 23 constitutes the timing detection device of the present invention.

The expansion symbol generator 24 generates an expansion symbol used by the reverse expansion unit 25 to perform the reverse expansion described later (step S24). The expansion symbol generated by the expansion symbol generation unit 24 is the same as the expansion symbol generated by the expansion symbol generation unit 12 of the conveyor 1. The expansion symbol generation unit 24 outputs the generated expansion symbol to the inverse expansion unit 25 based on the estimated timing notified by the initial acquisition unit 23.

The inverse expansion unit 25 multiplies the band-limited reception signal input by the reception filter 22 by the conjugate complex number of the expansion symbol input by the expansion symbol generation unit 24 to inversely expand the received signal (step S25). The reverse expansion unit 25 delivers the signal after reverse expansion to the synchronization tracking unit 26 in step S25.

The synchronization tracking unit 26 performs synchronization tracking processing based on the signal input from the reverse expansion unit 25 (step S26). The synchronization tracking unit 26 corrects the expansion by applying the synchronization tracking technology of any symbol timing known to those skilled in the art when the error between the estimated timing and the expanded symbol timing detected by the initial acquisition unit 23 is within 1/2 chip Symbol timing error. The synchronization tracking unit 26 notifies the expanded symbol generation unit 24 of the corrected timing.

The expansion symbol generation unit 24 generates expansion symbols used by the reverse expansion unit 25 to perform reverse expansion (step S27). The expansion symbol generation unit 24 outputs the generated expansion symbol to the inverse expansion unit 25 based on the corrected timing notified by the synchronization tracking unit 26. That is, the expansion symbol generation unit 24 outputs the expansion symbol at the corrected timing notified by the synchronization tracking unit 26 when the synchronization tracking unit 26 notifies the corrected timing. Further, the expansion symbol generation unit 24 outputs the expansion symbol at the estimated timing notified by the initial acquisition unit 23 when the synchronization acquisition unit 26 does not notify the corrected timing and the initial acquisition unit 23 notifies the estimated timing.

The inverse expansion unit 25 inversely expands the band-limited reception signal input from the reception filter 22 based on the expansion symbol input from the expansion symbol generation unit 24 in step S27 (step S28). That is, the inverse expansion unit 25 multiplies the band-limited reception signal input by the reception filter 22 by the conjugate complex number of the expansion symbol input by the expansion symbol generation unit 24 in step S27 to inversely expand the reception signal. The inverse expansion unit 25 delivers the received signal subjected to inverse expansion in step S28 to the demodulation unit 27.

The demodulation unit 27 demodulates the de-expanded received signal received from the de-expansion unit 25 (step S29).

Next, the configuration and operation of the initial acquisition unit 23 of the receiver 2 will be described in detail. The initial acquisition unit 23 corresponding to the timing detection device performs a characteristic operation in this embodiment. FIG. 6 is a diagram showing a configuration example of the initial acquisition unit 23 of the first embodiment. The initial acquisition unit 23 includes a developed symbol generation unit 231, a developed symbol multiplication unit 232, a correlation value addition unit 233, a partial correlation value addition unit 234, power calculation units 235 and 236, an addition processing unit 237, related power memories 238 and 239 , A sample synthesis unit 240, a weighted synthesis unit 241, and a threshold value determination unit 242. The correlation value addition unit 233 and the power calculation unit 235 constitute a first correlation power calculation unit 23A, and the partial correlation value addition unit 234, the power calculation unit 236, and the addition processing unit 237 constitute a second correlation power calculation unit 23B. In addition, the sample synthesis unit 240, the weighted synthesis unit 241, and the threshold value determination unit 242 constitute a timing detection unit 23C.

The operation of the initial acquisition unit 23 shown in FIG. 6 will be described. FIG. 7 is a flowchart showing an example of the operation of the initial acquisition unit 23 of the first embodiment.

The expansion symbol generation unit 231 generates the expansion symbol used by the transmitter 1, that is, the conjugate complex number of the expansion symbol used when the expansion unit 13 directly spreads the modulated signal in the transmitter 1, and outputs it to the expansion symbol multiplication unit 232 (step S31) . Assuming that the expansion symbols used by the conveyor 1 are c0 to c7, the expansion symbol generation unit 231 generates c0* to c7*.

The expansion symbol multiplication unit 232 multiplies the band-limited reception signal delivered from the reception filter 22 preceding the initial acquisition unit 23 by the conjugate complex number of the expansion symbol delivered from the expansion symbol generation unit 231 (step S32). The expansion symbol multiplication unit 232 multiplies the reception signal after the band-limiting reception by the conjugate complex number of the expansion symbol to the correlation value addition unit 233 and the partial correlation value addition unit 234. The multiplication result output by the expanded symbol multiplication unit 232 is the correlation value between the band-limited received signal and the expanded symbol.

The expanded sign multiplication unit 232 can be configured using a complex delay element and a complex multiplier shown in FIG. 8. Fig. 8 shows a configuration example of the expansion symbol multiplication unit 232 when the expansion symbol length N _C = 8 and the number of oversampling _NOVS = 2. At this time, the delay elements constituting the expansion symbol multiplication unit 232 are N _C ×N _OVS =16. The delay elements 251 to 266 are respectively equivalent to 1/N _OVS wafer length, and hold signals in sampling units. c0* to c7* are the conjugate complex numbers of the expansion symbols input from the expansion symbol generation unit 231. The multiplier constituting the expansion symbol multiplication unit 232 is N _C = 8 equal to the expansion symbol length. The expanded sign multiplication unit 232 shown in FIG. 8 inputs the band-limited reception signal input from the reception filter 22 to the delay element 251 in units of samples, and shifts to the right delay element every sampling timing. Furthermore, the expansion symbol multiplication unit 232 multiplies the frequency-limited received signals input to the delay elements 252, 254, 256, 258, 260, 262, 264, and 266 by the conjugate complex numbers c0* to c7* of the expansion symbol, The multiplication results a0 to a7 of each sampling timing are obtained. The sign multiplication unit 232 is developed, and the multiplication results a0 to a7 of the correlation value sequence are transferred to the correlation value addition unit 233 and the partial correlation value addition unit 234.

Here, in the initial acquisition unit 23, the developed symbol multiplication unit 232, correlation value addition unit 233, partial correlation value addition unit 234, power calculation units 235 and 236, and addition processing unit 237 operate not at the symbol timing but at the sampling timing . The related power memories 238 and 239 memorize the input signal at the sampling timing.

The correlation value addition unit 233 of the first correlation power calculation unit 23A adds all the multiplication results a0 to a7 like b0 = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7 + a7 + a7 + a7 delivered from the expanded sign multiplication unit 232, and generates a correlation addition value every sampling timing (step S33). The correlation value addition unit 233 transfers the correlation value addition value b0 to the power calculation unit 235.

The partial correlation value addition unit 234 of the second correlation power calculation unit 23B divides the block in which the multiplication results a0 to a7 passed from the expansion symbol multiplication unit 232 are complex numbers, and adds the multiplication results of the same block to generate a partial correlation addition value (Step S34). The partial correlation value addition unit 234, for example, divides the multiplication results a0 to a7 by two into two blocks, and performs an addition operation for each block to generate two partial correlation addition values. (2) When the multiplication results a0 to a7 are divided and then added, the partial correlation value addition unit 234 will add the multiplication results a0 to a7 from the expanded sign multiplication unit 232, like b1 = a0 + a1 + a2 + a3, b2 = a4 + a5 + a6 + a7, and add after the addition The two partial correlation addition values b1 and b2 are given to the power calculation unit 236.

，交接算出的電力值給相關電力記憶體238作為第1相關電力值(步驟S35)。The power calculation unit 235 of the first related power calculation unit 23A calculates the power value of the correlation value addition value b0 transferred from the correlation value addition unit 233

And hand over the calculated power value to the related power memory 238 as the first related power value (step S35).

以及

，交接算出的2個電力值的2個部分相關電力值給加法處理部237(步驟S36)。The power calculation unit 236 of the second correlation power calculation unit 23B calculates the power values of the partial correlation addition values b1 and b2 handed over from the partial correlation value addition unit 234

as well as

Then, the two partial related power values of the calculated two power values are transferred to the addition processing unit 237 (step S36).

合成2個部分相關電力值，產生部分相關合成電力值，交接產生的部分相關合成電力值作為第2相關電力值給相關電力記憶體239(步驟S37)。The addition processing unit 237 of the second correlation power calculation unit 23B synthesizes the complex partial correlation power values handed over from the power calculation unit 236. In this embodiment, the addition processing unit 237, like

The two partial correlation power values are combined, the partial correlation combined power value is generated, and the generated partial correlation combined power value is transferred to the related power memory 239 as the second correlation power value (step S37).

The correlation power memory 238 in the second stage of the first correlation power calculation unit 23A is configured to be able to hold the correlation power value corresponding to one cycle of the expansion symbol length × the number of oversampling. The power memory 238 stores the first relevant power value from the power calculation unit 235 for one cycle (step S38). After accumulating the first correlation power value for one cycle, the correlation power memory 238 outputs and holds the first correlation power value for one cycle to the weighted synthesis unit 241.

The related power memory 239 in the second stage of the second related power calculation unit 23B is the same as the related power memory 238, and is configured to be able to hold the related power value for one cycle. The related power memory 239 stores the second related power value of the partial related synthesized power value transferred from the addition processing unit 237 for one cycle (step S39). After accumulating the second correlation power value for one cycle, the correlation power memory 239 outputs the held second correlation power value for one cycle to the sample synthesis unit 240 and the threshold value determination unit 242. In addition, the processing after the related power memories 238 and 239 is converted to the operation in the symbol sequence by the operation in the sampling sequence.

The sampling synthesis unit 240 synthesizes the second correlation power value for one cycle transferred from the correlation power memory 239 in the second stage of the second correlation power calculation unit 23B at the adjacent sampling timing (step S40). Specifically, the sample synthesis unit 240 synthesizes the second relevant power value of log ₂ (N _OVS ) (N _OVS : number of oversampling) time sequences before and after the synthesis at each time sequence. For example, when the number of oversampling _NOVS = 2, the sample synthesis unit 240 adds two second correlation power values when the timing is k+1 and the second correlation power value when the timing is k. In addition, when the number of oversampling _NOVS = 4, the sample synthesis unit 240 adds the fourth relevant power value when the timing is k to the fourth time when the timing is k+1, k-1, k+2, and k-2 2 Related power value. Hereinafter, the combined second combined power value output by the sample combining unit 240 is referred to as a sample combined power value.

Next, taking the case where the expansion symbol length N _C = 8 and the number of oversamplings N _OVS = 2 as an example, the processing of the sample combining unit 240 will be described in detail using FIGS. 9 and 10. FIG. 9 is an example diagram showing that the second correlation power value of one cycle is transferred from the relevant power memory 239 to the sampling and synthesis unit 240, and FIG. 10 is a sample synthesis power value of one cycle output from the sampling and synthesis unit 240. An example. In FIGS. 9 and 10, the sequence k=0 to 15 is a sequence candidate detected by the initial acquisition unit 23. Here, the timing k=15 is the expansion symbol timing, and at this timing, the expansion symbol included in the output signal from the reception filter 22 coincides with the expansion symbol included in the expansion symbol multiplication unit 232. In addition, in order to make the error with the unfolding symbol timing within 1/2 wafer, the initial acquisition unit 23 estimates that the timing k=14 and k=0 when the error is within 1/2 wafer due to the coarse synchronization of the detection timing. Next, the correct timing is judged and becomes positive detection. Assuming that the second relevant power values in the sequence k=0 to 15 are d0 to d15, the sampling and synthesis unit 240 looks like e0=d15+d0+d1, e1=d0+d1+d2, e2=d1+d2+d3,...e15=d14+d15+d0, lasts 1 cycle, and synthesizes each The second correlation power value of log ₂ (N _OVS ) before and after the sequence generates sample combined power values e0 to e15 (see FIG. 10 ). As shown in FIG. 10, by using the sample combination, the power values at the timing k=14, 15, and 0, which are positive detections, are relatively increased. After the synthesis, the sample synthesis unit 240 transfers one cycle of the sample synthesis power value (e0, e1, ..., e15) to the weighted synthesis unit 241.

The weighted synthesis unit 241 weight-synthesizes the first correlation power value handed over from the relevant power memory 238 and the sample combined power value handed over from the sample synthesis unit 240 at every sampling timing, that is, between the same sampling timings (step S41). After the weighted combination, the weighted combination unit 241 delivers the weighted combined power value obtained by the weighted combination to the threshold value determination unit 242.

In step S41, the weighting synthesis unit 241 multiplies the previously calculated weighting coefficient by the sample synthesis power value delivered from the sample synthesis unit 240, and performs weighted synthesis by adding the first correlation power value. Here, the calculation method of the weighting coefficient will be described using FIGS. 11 and 12. FIG. 11 is a diagram showing an example of the first correlated power value output by the first correlated power calculation unit 23A, and FIG. 12 is a diagram showing an example of the sample combined power value output from the sample synthesis unit 240. The designer of the receiver 2 calculates the weighting coefficient based on the maximum value of the first correlation power and the maximum value of the sample combined power value, for example. In this case, the designer first confirms the maximum power value of the expanded symbol in one cycle with respect to the first relevant power value and the sample combined power value. At this time, the first correlation power value and the sample combined power value do not include noise components. After that, the designer calculates the weighting coefficients of the two maximum power values confirmed by equal power synthesis. The weighting coefficient changes according to the expanded symbol length N _C , the number of oversampling _NOVs , and the frequency offset value. In addition, the weighting synthesis unit 241 has a function of calculating weighting coefficients. When performing a predetermined operation on the receiver 2, the weighting synthesis unit 241 may calculate the weighting coefficients.

The threshold value determination unit 242 detects the maximum power value from the weighted combined power value of one cycle received by the weighted combination unit 241, and performs threshold value determination, that is, comparison of the maximum power value with a predetermined threshold value (step S42). When the maximum power value exceeds the critical value, the timing corresponding to the maximum power value is handed over to the expansion symbol generation unit 24 of the receiver 2 as the estimated timing, that is, the expansion symbol timing estimation result. In the receiver 2, the following method is used as a method of setting the critical value used by the critical value determination unit 242 for critical value determination. The threshold value determination unit 242 calculates the average value of the partial correlation power values of one cycle before the synthesis of the samples transferred from the correlation power memory 239 in the second stage of the second correlation power calculation unit 23B, and sets the constant α (1≦α) times of the average value As a critical value. Here, the larger the constant α is set, the lower the false alarm for establishing the wrong synchronization point, but the initial acquisition takes time. The smaller the value of the constant α is set, the shorter the initial acquisition time can be, but the increase in false alarms relationship.

After the threshold value determination unit 242, the receiver 2 performs the processing after the expansion symbol generation unit 24 according to the aforementioned operation.

As described above, the initial acquisition unit 23 of the receiver 2 of this embodiment includes the first correlation power calculation unit 23A and the second correlation power calculation unit 23A and the second correlation power sequence obtained by multiplying the received signal and the conjugate complex number of the expansion symbol by different addition ranges. Related power calculation unit 23B. Specifically, the first correlation power calculation unit 23A adds all correlation values in the correlation value sequence, and outputs the obtained power value of the addition result as the first correlation power value. The second correlation power calculation unit 23B divides the correlation value sequence into complex blocks, and adds the correlation value in the block to each block, calculates the power value of the obtained addition result, and outputs each block to obtain The result of the power value addition of is used as the second relevant power value. In addition, the initial acquisition unit 23 weight-synthesizes the first correlation power value calculated by the first correlation power calculation unit 23A and the second correlation power value calculated by the second correlation power calculation unit 23B. Then, the initial acquisition unit 23 compares the power value (weighted combined power value) obtained by the weighted synthesis with the threshold value, and determines that the sampling timing corresponding to the power value exceeding the threshold value is the estimated timing. Furthermore, in the present embodiment, the weighting coefficient used for weighted combination is calculated from the first relevant power value and the second relevant power value. Specifically, for each of the first correlation power value and the second correlation power value, the state in which the noise component is removed from the maximum power value within one cycle of the expansion symbol is confirmed in advance, and the two maximum power values are used in the weighting coefficient to equalize power synthesis Value. According to the configuration in which the initial acquisition unit 23 uses the first related power calculation unit 23A and the second related power calculation unit 23B in parallel, it becomes possible to observe the related power value of a large expansion symbol timing, and it is possible to improve the initial stage of the conventional knowledge described in Non-Patent Document 1. The accuracy of synchronization due to the sidelobe of the relevant characteristics of the subject of the acquisition method is degraded. In addition, since the initial acquisition unit 23 is configured to perform weighted synthesis of the correlation power value calculated by the first correlation power calculation unit 23A and the correlation power value calculated by the second correlation power calculation unit 23B, the condition that the frequency offset is small can be increased. If the ratio of the first relevant power value is large and the frequency shift is large, the ratio of the second relevant power value can be increased.

Here, the reason why the second correlation power value calculated by the second correlation power calculation unit 23B is strong against frequency offset will be described using FIG. 13. FIG. 13 is a diagram for explaining the reason why the second correlation power value calculated by the second correlation power calculation unit 23B is resistant to frequency offset. FIG. 13 is a diagram showing the multiplication results a0 to a7 obtained by the expansion symbol multiplication unit 232 of the initial acquisition unit 23 of FIG. 8 on a complex number plane with a frequency offset of 1/N _C. In this case, when the first correlation power calculation unit 23A adds all the multiplication results a0 to a7 and converts it to a power value, it becomes equation (2). | A0 + a1 + a2 + a3 + a4 + a5 + a6 + a7 | ² = 0… (2)

In addition, when the second correlation power calculation unit 23B divides the multiplication results a0 to a7 to 2 and adds them, converts them into power values, and then combines them, it becomes Equation (3). ｜a0＋a1＋a2＋a3｜ ² +｜a4＋a5＋a6＋a7｜ ² ＞0 …(3)

In this way, the second correlation power calculation unit 23B divides the multiplication result to be shorter than the first correlation power calculation unit 23A, and then performs addition calculation to improve the resistance to frequency offset by performing power calculation. However, the second correlation power calculation unit 23B calculates the correlation power because of the result of the division and multiplication. If the frequency offset is small, the correlation characteristic is worse than that of the first correlation power calculation unit 23A. Therefore, in this embodiment, by performing weighted synthesis of the first correlation power value and the second correlation power value, whether or not there is a frequency offset, the synchronization determination accuracy is improved.

Including the first correlation power calculation unit 23A and the second correlation power calculation unit 23B, by forming a weighted combination of the first correlation power value and the second correlation power value, because the synchronization determination accuracy can be improved, the second correlation power can also be omitted The sample synthesis unit 240 in the latter stage of the calculation unit 23B. However, when the sample synthesis unit 240 shown in FIG. 6 is provided, the synchronization determination accuracy can be further improved.

In other words, the second correlation power value calculated by the second correlation power calculation unit 23B is combined with the second correlation power value of the sequence of log ₂ (N _OVS ) before and after the expansion symbol for one cycle. When the power value of the sampling sequence before and after synthesis is combined By relatively increasing the power value at the time sequence being detected, it is possible to relatively reduce the power value at the time sequence that is a false alarm. As a result, it is possible to improve the deterioration of synchronization accuracy caused by sidelobe accompanying an increase in the number of divisions.

According to the present embodiment, by using the above-described first correlation power calculation unit 23A and second correlation power calculation unit 23B, regardless of whether there is a frequency offset, initial acquisition can be accurately performed.

In this embodiment, the initial acquisition unit 23 of the receiver 2 forms a multiplication result a0 to a7 using the two-split expansion symbol multiplication unit 232 as b1 = a0 + a1 + a2 + a3, b2 = a4 + a5 + a6 + a7, and a second correlation power calculation unit for addition operation The configuration of 23B is not limited to the configuration of the multiplication result of two divisions. The second correlated power calculation unit 23B may be configured to use other division numbers such as 3 divisions, 4 divisions, etc. that can equally divide the expansion symbol. For example, when the 4-division multiplication results a0 to a7, like b1 = a0 + a1, b2 = a2 + a3, b3 = a4 + a5, b4 = a6 + a7, calculate the partial correlation addition value. In general, when increasing the division, since the resistance to frequency offset is increased, it is preferable that the system has a configuration of the second correlation power calculation unit 23B that uses the number of divisions corresponding to the assumed maximum frequency offset. In this embodiment, the first correlation power calculation unit 23A and the two-divided second correlation power calculation unit 23B are connected in parallel. However, the second correlation power calculation unit 23B may be configured to use a different complex division number. For example, the configuration of the first correlation power calculation unit 23A, the two-divided second correlation power calculation unit 23B, and the four-divided second correlation power calculation unit 23B are used. Compared with the configuration shown in FIG. 6, by using this configuration, the timing of the positive detection can be detected even if the frequency shift is large. In addition, when the second correlation power calculation unit 23B having a different number of divisions than the two divisions and the four divisions are used in parallel, since the appearance patterns of side lobes according to the division number correlation power values are different, compared to using the first correlation power calculation unit 23A with The configuration of the second divided power calculation unit 23B divided into four can improve the accuracy of synchronization determination.

In this embodiment, the initial acquisition unit 23 of the receiver 2 is configured to transfer the processing results of the power calculation units 235 and 236 to the related power memories 238 and 239, but it is not limited to this. For example, the correlation power values held in the correlation power memories 238 and 239 before one symbol and the correlation power values calculated by the new power calculation units 235 and 236 may be averaged. In this case, the related power memories 238 and 239 maintain the averaged related power value, and a good critical value for suppressing noise components can be determined.

Furthermore, in the present embodiment, the initial acquisition unit 23 of the receiver 2 is configured such that the second correlation power calculation unit 23B uses the partial correlation value addition unit 234, the power calculation unit 236, and the addition processing unit 237, but it is not limited to this. . The configuration including the phase difference calculator in the initial acquisition unit disclosed in Non-Patent Document 1 can also be applied. The configuration of the initial acquisition unit 23 at this time is illustrated in FIG. 14. FIG. 14 is a diagram showing a modification of the initial acquisition unit provided in the receiver 2 of the first embodiment. The difference between the initial acquisition unit 23a described in FIG. 14 and the initial acquisition unit 23 described in FIG. 6 is that the second correlation power calculation unit 23B-2 in FIG. 14 includes a phase in the second stage of the partial correlation value addition unit 234. The difference calculation unit 281 and the addition processing unit 282 delete the points of the addition processing unit 237, and in FIG. 14, where the same processing as in FIG. 6 is performed, the same numbers are attached and detailed descriptions are omitted. It is assumed that the two-divided partial correlation value addition unit 234 adds the multiplication results handed over from the expansion symbol multiplication unit 232 to obtain partial correlation addition values b0 and b1. The bit difference calculation unit 281 calculates the phase difference between the partial correlation addition values b0 and b1 handed over from the partial correlation value addition unit 234 like d0=b1×b0*, and the d0 handing over the calculation result of the phase difference is given to the addition processing unit 282. The addition processing unit 282 adds the phase difference calculation result d0 received from the phase difference calculation unit 281, and delivers the addition result to the power calculation unit 236. The processing after the power calculation unit 236 is the same as described above. In the case where such a phase difference is obtained, the second correlation power value output from the second correlation power calculation unit 23B-2 is based on the process of acquiring the phase difference, because it performs more than the first correlation power calculation unit 23A The multiplication operation has a larger power value than the first correlation power value output from the first correlation power calculation unit 23A. Therefore, the weighted synthesis unit 241 performs weighted synthesis at an appropriate power ratio, and can achieve good initial acquisition performance. According to this configuration, even if there is a frequency shift condition, the initial acquisition can be performed in a short time with good accuracy.

Furthermore, in this embodiment, in the initial acquisition unit 23 of the receiver 2, the sample synthesis unit 240 is configured not to be used in the latter stage of the first correlation power calculation unit 23A but only used in the latter stage of the second correlation power calculation unit 23B However, the present invention is not limited to this, and the sample synthesis unit may be used in the latter stage of the first related power calculation unit 23A. At this time, the new sample synthesis unit is arranged in the latter stage of the relevant power memory 238. The operation of the sample synthesis unit in the latter stage of the first correlation power calculation unit 23A is the same as the sample synthesis unit 240 described in the first embodiment. When the Zadoff-Chu sequence with the sequence parameter M _C =1 is used as the spread symbol for direct spreading, when the number of oversampling _{NOVs is} greater than 1, there is a side lobe of the correlation value of the first correlation power calculation unit, and the correlation characteristic deteriorates . Therefore, in the case of _NOVS >1, by forming not only the second correlation power calculation unit, but also a configuration in which the sample synthesis unit is used in the latter stage of the first correlation power calculation unit, the synchronization determination accuracy can be improved.

Furthermore, in the present embodiment, the weighted synthesis unit 241 of the initial acquisition unit 23 of the receiver 2 confirms in advance the maximum power of the first correlation power value in the state of removing noise components and the sampled combined power value within one cycle of the expansion symbol, respectively As the value, a weighting coefficient such as two maximum power values combined with equal power is used, but it is not limited to this. As a method for determining other weighting coefficients, for the first correlation power value in the state where the noise component is removed and the sample combined power value, the average value of the expansion symbol for one cycle is obtained (see FIGS. 11 and 12). A weighting factor that the average value becomes equal may be used. In this case, the ratio of the first relevant power value can be increased as compared with the above-described case where the maximum power value is used as a weighting factor for equal power, and the frequency deviation is small, thereby improving the synchronization accuracy. However, when the frequency offset is large, the accuracy deteriorates. In addition, there is a method of using the intermediate value using the maximum power value as the weighting coefficient of the equal power and the average value as the weighting coefficient of the equal power as the weighting coefficient. In this case, compared with the above-described case where the maximum power value is used as a weighting coefficient for equal power, the accuracy deterioration is still small when the frequency offset is large, and the accuracy can be improved when the frequency offset is small. By determining the weighting coefficient as described above, the ratio of the first relevant power value to the sample combined power value can be adjusted.

In addition, instead of using the weighting coefficient as a fixed value set in advance, it may be adapted to change every symbol. For example, there is also a method of calculating a weighting coefficient that equals the average value of the first correlation power value held by the correlation power memory 238 and the average value of the sample combined power value held by the sample combining unit 240 to be equal to each symbol. In this case, the weighting coefficient is appropriately updated by the weighting and synthesis unit, for example. By forming a structure with more weight coefficients along the strain, it is possible to achieve weighted synthesis of the reception level that varies with time, and it is possible to achieve good synchronization determination accuracy.

In addition, in this embodiment, in order to calculate the critical value used by the critical value determination unit 242, the average value of the relevant power values held by the relevant power memory 239 is used, but it is not limited thereto. For example, the average value of the weighted combined power values output from the weighted combining unit 241 may be used. With such a configuration, it is possible to generate a critical value that includes both the first correlation power value and the sample combined power value output by the sample combining unit 240 with good accuracy, and good synchronization determination accuracy can be achieved.

Moreover, instead of using the threshold value used by the threshold value determination unit 242 as a predetermined fixed value, it may be changed accordingly. For example, when the average value and the maximum value of the first relevant power value in one cycle held by the relevant power memory 238 are obtained, and the maximum value exceeds γ times the average value (γ is a predetermined constant and γ>1), the critical value The value determination unit 242 uses a constant α times the average value of the weighted combined power value as the critical value. On the other hand, when the maximum value of the weighted combined power value does not exceed γ times the average value, there is a method of using the value of the constant α times the constant β (β<1) as the critical value. The maximum correlation power value of the first correlation power calculation unit held by the correlation power memory 238 becomes smaller when the frequency shift is large. Due to such a configuration, the threshold value can be changed according to the magnitude of the frequency offset, and the initial acquisition time can be shortened regardless of the condition of the frequency offset.

Next, the hardware configuration of the receiver 2 of the first embodiment will be described. In the receiver 2, the receiving antenna 21 is realized by an antenna device. The reception filter 22 is realized by a filter circuit.

In the initial acquisition unit 23, the sign multiplication unit 232 is developed, and as described above, it is realized by the configuration circuit shown in FIG. Each component other than the expanded sign multiplication unit 232 of the initial acquisition unit 23 is realized by a processing circuit. These processing circuits may be realized by dedicated hardware, or may be a control circuit using a CPU (Central Processing Unit).

When the above processing circuits are implemented by dedicated hardware, these are implemented by the processing circuit 100 shown in FIG. 15. Fig. 15 shows a processing circuit diagram for realizing the receiver 2 of the first embodiment. The processing circuit 100 is a single circuit, a compound circuit, a programmed processor, a parallel programmed processor, an ASIC (Integrated Circuit for Special Applications), an FPGA (Field Programmable Gate Array), or a combination of these.

When the above-mentioned processing circuit is realized by a control circuit using a CPU, this control circuit is, for example, the control circuit 200 having the configuration shown in FIG. 16. Fig. 16 is a diagram showing an example of the configuration of a control circuit that realizes the receiver 2 of the first embodiment. The control circuit 200 shown in FIG. 16 includes a processor 201 such as a CPU and a memory 202. When the above processing circuit is implemented by the control circuit 200, the memory 202 first memorizes a program for realizing the functions of each constituent element other than the expanded sign multiplication unit 232 of the initial acquisition unit 23. Then, the processor 201 reads and executes the above-mentioned program stored in the memory 202 to realize each component other than the expanded sign multiplication unit 232 of the initial acquisition unit 23. In addition, the memory 202 is also used as a temporary memory for each process performed by the processor 201.

In addition, among the constituent elements other than the expanded sign multiplication section 232 of the initial acquisition section 23, some of the constituent elements are realized by the processing circuit 100 shown in FIG. 15, and the remaining constituent elements are implemented by the control circuit 200 shown in FIG. Implementation is also possible.

The initial acquisition unit 23a shown in FIG. 14 is realized by the same circuit as the circuit that realizes the initial acquisition unit 23a.

The expansion symbol generating unit 24 is realized by the processing circuit 100 shown in FIG. 15 or the control circuit 200 shown in FIG. 16. The inverse expansion unit 25 is realized by a circuit combining a complex delay element and a complex multiplier. The synchronization tracking unit 26 is realized by the processing circuit 100 shown in FIG. 15 or the control circuit 200 shown in FIG. 16. The demodulation unit 27 is realized by a demodulator.

In addition, the modulator 11 of the conveyor 1 of the first embodiment is realized by a modulator. The expansion symbol generating unit 12 is realized by the same circuit as the processing circuit 100 shown in FIG. 15 or the control circuit 200 shown in FIG. 16. The expansion unit 13 is realized by a circuit combining a complex delay element and a complex multiplier. The transmission filter 14 is realized by a filter circuit. The transmission antenna 15 is realized by an antenna device.

Second embodiment Next, the second embodiment will be described. In the second embodiment, the transmitter generates a transmission signal by repeatedly spreading the signal directly over a plurality of times. This is a well-known method as one of spread spectrum techniques. According to this technique, the transmitter distributes the transmission signal spectrum at equal intervals on the frequency axis. The initial acquisition unit of the receiver of the second embodiment determines the correlation value addition period of the first correlation power calculation unit and the second correlation power calculation unit based on the number of times of direct spread spectrum signal transmission on the transmission side. In this embodiment, the configuration and operation of the transmitter and the operation of the receiver are different from those of the first embodiment. In the present embodiment, description will be made on the differences from the first embodiment. The description of the same parts as in the first embodiment will be omitted.

The structure and operation of the conveyor according to the second embodiment will be described. Fig. 17 is a diagram showing a configuration example of a conveyor according to the second embodiment. As shown in FIG. 17, the conveyor 1a of the second embodiment is an additional upsampling section between the expansion section 13 and the transmission filter 14 of the conveyor 1 (refer to FIG. 1) described in the first embodiment. 31. Structure of the frequency shift unit 32 and the CP addition unit 33.

The outline of the operation of the conveyor 1a shown in Fig. 17 will be described. Fig. 18 is a flowchart showing an example of the operation of the conveyor 1a according to the second embodiment. The flowchart shown in FIG. 18 adds steps S51 to S53 between step S13 and step S14 of the flowchart shown in FIG. 2.

The up-sampling unit 31 repeatedly compresses the direct spread spectrum signal P times after the compressed signal grows to 1/P for the direct spread spectrum signal input from the expansion unit 13 (step S51). Here, P is an integer of 2 or more. The up-sampling unit 31 generates a direct spread signal of the length N _C × P of the expansion symbol of the P-time repetition length N _C by performing the iterative processing. Fig. 19 is a diagram for explaining the processing of an upsample unit 31 provided in the conveyor 1a of the second embodiment. FIG. 19 shows an example of compression and repetition of the direct spread signal of the up-sampling unit 31 when the developed symbol period N _C =4 and the repetition number P=4. The hatched part of the signal indicates the first element of the expansion symbol. In the case of the example shown in FIG. 19, the up-sampling unit 31 has a compression rate of 1/4 because the sampling rate is four times. The up-sampling unit 31, secondly, repeats the compressing to a signal of 1/4 length four times to generate a direct spread frequency signal after upsampling. As shown in Figure 19, the direct spread signal after upsampling has two unfolded symbol periods. The unfolded symbol period #1 becomes the same number of chips as the unfolded symbol period N _C = 4 used for direct spread-spectrum signal generation before upsampling, and the unfolded symbol period #2 becomes the number of repetitions P=4 times N _{C of the} unfolded symbol period #1 ×P = 16 wafers. The up-sampling unit 31 transfers the up-sampled direct spread spectrum signal to the frequency shift unit 32.

The frequency shift unit 32 performs phase rotation on the signal input from the up-sampling unit 31 by a predetermined phase rotation amount, and frequency shifts the input signal (step S52). When the amount of phase rotation is θ, the frequency shift unit 32 multiplies the input signal by exp(j2πθn/N _C ) (n=1,..., An integer of N _C ) to perform phase rotation. The frequency shift unit 32 delivers the direct spread signal after the frequency shift to the CP adding unit 33.

The CP addition unit 33 copies a predetermined number of samples from the end of the signal input from the frequency shift unit 32 as shown in FIG. 20 and appends it to the beginning as CP (Cyclic Prefix) (step S53) . In addition, FIG. 20 is an operation diagram for explaining the CP (Cyclic Prefix) adding unit 33 provided in the conveyor 1a of the second embodiment. The CP addition unit 33 transfers the direct spread signal with the CP added to the transmission filter 14. The processing of the subsequent conveyor 1a is the same as the conveyor 1 of the first embodiment.

The up-sampling unit 31, frequency shift unit 32, and CP adding unit 33 of the conveyor 1a are realized by the processing circuit 100 or the control circuit 200 described in the first embodiment.

Next, the configuration and operation of the receiver of the second embodiment will be described. The configuration of the receiver of the second embodiment is the same as that of the receiver 2 (see FIG. 4) of the first embodiment. However, the operation of the initial acquisition unit 23 is different. Here, the initial acquisition unit 23 of the second embodiment will be described with reference to FIG. 6 showing the configuration of the initial acquisition unit 23 of the first embodiment. The flowchart showing the operation of the receiver 2 of the second embodiment is the same as the flowchart showing the operation of the receiver 2 of the first embodiment (see FIG. 5).

The initial acquisition unit 23 estimates the timing of the unfolded symbol period #2 shown in the figure for the direct spread spectrum signal after CP addition shown in FIG. 20.

The spread symbol generating unit 231 shown in FIG. 6 generates a spread symbol of length N _C ×P based on the number P of the direct spread signal repeated by the up-sampling unit 31 of the transmitter 1a. For example, when the up-sampling unit 31 of the conveyor 1a generates the up-sampled direct signal of the configuration shown in FIG. 19, the expanded symbol generating unit 231 generates a period corresponding to the cycle of N _C ×P=16 of the expanded symbol period #2 Expand symbol.

The expanded sign multiplication unit 232 may be composed of N _C ×P×N _OVS (N _OVS : oversampling number) delay elements and N _C ×P multipliers. For example, when N _OVS = 2 in Fig. 19, the expansion symbol multiplication unit 232 may be configured by N _C × P × N _OVS = 32 delay elements and N _C × P = 16 multipliers.

The correlation value addition unit 233 of the first correlation power calculation unit 23A adds the multiplication result transferred from the expansion symbol multiplication unit 232 to a length equal to the expansion symbol period #2 shown in FIG. 19.

The partial correlation value addition unit 234 of the second correlation power calculation unit 23B adds the multiplication result transferred from the expansion symbol multiplication unit 232 to a length equal to the expansion symbol period #1 shown in FIG. 19. In other words, the partial correlation value addition unit 234 divides and expands the symbol period #2 and then adds. For example, when the receiver 2 receives the up-sampled direct spread signal of the configuration shown in FIG. 19, the partial correlation value addition unit 234 divides the expanded symbol period #2 and adds.

The processing performed by the constituent elements in the latter stage of the correlation value addition unit 233 and the constituent elements in the latter stage of the partial correlation value addition unit 234 is the same as those of the constituent elements of the initial acquisition unit 23 of the first embodiment with the same reference signs.

The inverse expansion unit 25 (refer to FIG. 4) of the receiver 2 of the second embodiment is the same as the first embodiment, and uses the expansion symbols input from the expansion symbol generation unit 24 to inversely expand the signal input from the reception filter 22. However, based on the estimated timing detected by the initial acquisition unit 23 or the synchronization tracking unit 26 or the corrected timing, only the CP portion is removed by inverse diffusion.

The demodulation unit 27 performs demodulation processing corresponding to the signal transmitted by the transmitter 1a shown in FIG. This processing can be realized with the following configuration, for example. The demodulation unit 27 first performs equalization processing for correcting the waveform distortion received by the transmission channel for the de-expanded signal received from the de-expansion unit 25. After performing the equalization process, the demodulation unit 27 performs a process of removing the frequency shift given by the frequency shift unit 32 of the transmitter 1a. The demodulation unit 27 then synthesizes the number of repetitions P performed by the up-sampling unit 31 of the transmitter 1a. The synthesis is carried out as described below. The demodulation unit 27 synthesizes the samples with the same element number of the unfolded symbol before the repeating by the upsampling unit 31 of the synthesis conveyor 1a for the signal of the unfolded symbol period N _C ×P after frequency shifting to form a signal of length N _C. After the synthesis, the demodulation unit 27 performs demodulation processing in accordance with the modulation processing by the modulation unit 11 of the transmitter 1a.

As described above, in the present embodiment, the up-sampling section 31 of the transmitter 1a is configured to generate a transmission signal by repeatedly spreading the signal a plurality of times. In addition, the initial acquisition unit 23 of the receiver 2 is formed to correspond to the length of the unfolded symbol period after the upsampling unit 31 is repeated and the unfolded symbol period before the repetition, and the correlation value is added to the first correlation power calculation unit and the second The structure of the relevant power calculation unit. By using the second correlation power calculation unit corresponding to the short expanded symbol period, the correlation characteristic of the suppressed sidelobe is obtained because the correlation characteristic of the entire expanded symbol period is obtained instead of partial correlation. Because of this characteristic, the correlation characteristic of the first correlation power calculation unit is used to improve the synchronization determination accuracy.

The configuration shown in the above embodiment is an example showing the content of the present invention, and may be combined with other well-known technologies, and a part of the configuration may be omitted or changed without departing from the gist of the present invention.

1. 1a‧‧‧Conveyor 2‧‧‧Receiver 11‧‧‧ Modulation Department 12‧‧‧Expand Symbol Generation Department 13‧‧‧ Development Department 14‧‧‧Transmission filter 15‧‧‧Transmitting antenna 21‧‧‧Receiving antenna 22‧‧‧Receive filter 23‧‧‧ Initial Acquisition Department 23A‧‧‧The first relevant power calculation department 23B, 23B－2‧‧‧Second related power calculation unit 23C‧‧‧ Timing Detection Department 23a‧‧‧ Initial Acquisition Department 24‧‧‧Expand Symbol Generation Department 25‧‧‧Reverse Development Department 26‧‧‧Tracking Department 27‧‧‧ Demodulation Department 31‧‧‧Upsampling Department 32‧‧‧ Frequency shift 33‧‧‧CP Additional Department 100‧‧‧ processing circuit 200‧‧‧Control circuit 201‧‧‧ processor 202‧‧‧Memory 231‧‧‧Expand Symbol Generation Department 232‧‧‧Expand sign multiplication section 233‧‧‧Relevant value addition department 234‧‧‧Partial correlation value addition department 235, 236‧‧‧ Electricity Calculation Department 237‧‧‧Additional Processing Department 238, 239‧‧‧ related power memory 240‧‧‧Sampling and Synthesis Department 241‧‧‧ Weighted synthesis 242‧‧‧Critical Value Judgment Department 251~266‧‧‧ Delay element 281‧‧‧Phase difference calculation department 282‧‧‧Additional Processing Department

[Figure 1] is a diagram showing a configuration example of a conveyor according to the first embodiment; [Figure 2] is a flowchart showing an example of the conveyor operation of the first embodiment; [Figure 3] is a diagram showing the structure of a signal frame transmitted by a conveyor according to the first embodiment; [Fig. 4] A diagram showing an example of the configuration of the receiver according to the first embodiment; [Figure 5] A flowchart showing an example of the operation of the receiver of the first embodiment; [Figure 6] This is a diagram showing a configuration example of an initial acquisition unit in the first embodiment; [Figure 7] It is a flowchart showing an example of the operation of the initial acquisition unit of the first embodiment; [Figure 8] A diagram showing the configuration of the expanded sign multiplication unit of the first embodiment; [Figure 9] This is an example of the second correlation power value delivered to the sampling and synthesis unit in one cycle; [Figure 10] This is an example of a sample synthesis power value output by the sample synthesis unit for one period; [Figure 11] An example of a graph showing the first related power value output by the first related power calculation unit; [Figure 12] It is an example of a sample synthesis power value output by the sample synthesis unit; [Figure 13] It is used to explain the reason why the second correlation power value calculated by the second correlation power unit is strong against frequency offset; [Figure 14] A diagram showing a modification example of the initial acquisition unit provided in the receiver of the first embodiment; [Figure 15] is a circuit diagram showing the processing of the receiver implementing the first embodiment; [Figure 16] is a diagram showing an example of the configuration of a control circuit that realizes the receiver of the first embodiment; [Figure 17] This is a diagram showing a configuration example of a conveyor according to the second embodiment; [Figure 18] It is a flowchart showing an example of the conveyor operation of the second embodiment; [Figure 19] It is a processing diagram for explaining the upsample section provided in the conveyor of the second embodiment; and [Fig. 20] This is an operation diagram for explaining the CP (Cyclic Prefix) attachment part provided in the conveyor of the second embodiment.

23‧‧‧ Initial Acquisition Department

23A‧‧‧The first relevant power calculation department

23B‧‧‧The second relevant power calculation unit

23C‧‧‧ Timing Detection Department

231‧‧‧Expand Symbol Generation Department

232‧‧‧Expand sign multiplication section

233‧‧‧Relevant value addition department

234‧‧‧Partial correlation value addition department

235, 236‧‧‧ Electricity Calculation Department

237‧‧‧Additional Processing Department

238, 239‧‧‧ related power memory

240‧‧‧Sampling and Synthesis Department

241‧‧‧ Weighted synthesis

242‧‧‧Critical Value Judgment Department

Claims (12)

A receiving device, characterized in that it includes: The expanded symbol multiplying unit multiplies the conjugate complex number of the expanded symbol used in the direct spreading to the received signal that is subjected to direct spreading to generate a sequence of correlation values; The first correlation power calculation unit adds the respective correlation values of the correlation value sequence generated by the multiplication by the expansion symbol multiplication unit, generates a correlation addition value, and calculates the first correlation power value of the power value of the correlation addition value; The second correlation power calculation unit divides the correlation value sequence into complex blocks, and for each of the blocks, adds the correlation values in the block to generate partial correlation values, and at the same time calculates the power values of the partial correlation values, The power values obtained for each of the above blocks are added together to calculate the second relevant power value; and The timing detection unit detects, based on the first correlation power value and the second correlation power value, the transmission device that detects the transmission source of the reception signal multiplies the transmission signal by the timing of the expansion symbol in the direct spread spectrum. The receiving device according to item 1 of the patent application scope, wherein the first related power calculation unit calculates the first related power value per sampling timing; The second related power calculation unit calculates the second related power value at each sampling timing; The timing detection unit includes: A weighted synthesis unit that weight-synthesizes the first relevant power value and the second relevant power value to generate a weighted combined power value per sampling timing; and The threshold value determination unit compares the weighted combined power value per sampling timing with the largest value of the expansion symbol in one cycle to the threshold value, and detects the timing. The receiving device according to item 1 of the patent application scope, wherein the first related power calculation unit calculates the first related power value per sampling timing; The second related power calculation unit calculates the second related power value at each sampling timing; The timing detection unit includes: The sampling synthesis unit synthesizes the above-mentioned second relevant power value included in the range of the sampling timing and the number of oversampling for each sampling timing, and generates a sample combined power value for each sampling timing; A weighted synthesis unit, weightedly synthesizes the first related power value and the sampled combined power value to generate a weighted combined power value per sampling timing; and The threshold value determination unit compares the weighted combined power value per sampling timing with the largest value of the expansion symbol in one cycle to the threshold value, and detects the timing. The receiving device according to item 1 of the patent application scope, wherein the first related power calculation unit calculates the first related power value per sampling timing; The second related power calculation unit calculates the second related power value at each sampling timing; The timing detection unit includes: The sampling synthesis unit synthesizes the first relevant power value included in the range of the sampling timing and the oversampling number for each sampling timing, and generates a sample combined power value for each sampling timing; A weighted synthesis unit that weight-synthesizes the sampled combined power value and the second related power value to generate a weighted combined power value per sampling timing; and The threshold value determination unit compares the weighted combined power value per sampling timing with the largest value of the expansion symbol in one cycle to the threshold value, and detects the timing. The receiving device according to any one of claims 2 to 4, wherein the weighting coefficient used in the weighted synthesis is determined based on the characteristics of the first related power value and the characteristics of the second related power value. The receiving device according to claim 5 of the patent application, wherein the weighting coefficient is based on the maximum value of the first correlation power value without noise component state and the second correlation power value without noise component state The maximum value is determined. The receiving device according to item 5 of the patent application range, wherein the weighting coefficient is based on an average value of the first correlated power value without noise components and a second correlated power value without noise components The average value is determined. The receiving device according to item 5 of the patent application range, wherein the weighting coefficient is updated in accordance with the average value of the first correlation power value and the average value of the second correlation power value by the weighting synthesis unit. The receiving device according to any one of items 1 to 4 of the patent application scope, wherein the unfolding symbol is a sequence of the second length repeating the sequence of the first length a plurality of times; The second correlation power calculation unit divides the correlation value sequence so that the length of the block is the first length when dividing the correlation value sequence into a complex block. The receiving device according to item 5 of the patent application scope, wherein the expansion symbol is a sequence of the second length repeating the sequence of the first length a plurality of times; The second correlation power calculation unit divides the correlation value sequence so that the length of the block is the first length when dividing the correlation value sequence into a complex block. A timing detection device, including a receiving device that receives signals that implement direct frequency spreading, Its characteristics include: The expanded symbol multiplying unit multiplies the conjugate complex number of the expanded symbol used in the direct spreading for the above signal to generate a sequence of correlation values; The first correlation power calculation unit adds the respective correlation values of the correlation value sequence generated by the multiplication by the expansion symbol multiplication unit, generates a correlation addition value, and calculates the first correlation power value of the power value of the correlation addition value; The second correlation power calculation unit divides the correlation value sequence into complex blocks, and for each of the blocks, adds the correlation values in the block to generate partial correlation values, and at the same time calculates the power values of the partial correlation values, The power values obtained for each of the above blocks are added together to calculate the second relevant power value; and The timing detection unit detects, based on the first correlation power value and the second correlation power value, the transmission device of the transmission source of the signal received by the reception device multiplies the transmission signal by the timing of the expansion symbol in the direct spread spectrum. A timing detection method is a timing detection method implemented by a receiving device that receives a signal that implements direct spreading, Its characteristics include: The expanded symbol multiplication step, multiplying the above signal by the conjugate complex number of the expanded symbol used in the above direct spreading to generate a sequence of correlation values; and In the first correlation power calculation step, each correlation value of the correlation value sequence generated by performing the expansion sign multiplication step is added to generate a correlation addition value, and the first correlation power value of the power value of the correlation addition value is calculated; The second correlation power calculation step divides the correlation value sequence into complex blocks, and for each of the blocks, each correlation value in the block is added to generate a partial correlation value, and at the same time, the power value of the partial correlation value is obtained, The power values obtained for each of the above blocks are added together to calculate the second relevant power value; and The timing detection unit detects, based on the first correlation power value and the second correlation power value, the transmission device of the transmission source of the signal received by the reception device multiplies the transmission signal by the timing of the expansion symbol in the direct spread spectrum.

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