TW202010124A - Semiconductor devices and methods for forming same - Google Patents

Abstract

A semiconductor device is provided, including a substrate; a dielectric structure over the substrate; and a capping layer over the dielectric structure, wherein a bottom of the capping layer has an M-shaped cross section, and the capping layer and the dielectric structure are formed of different materials.

Description

Semiconductor device and its manufacturing method

The embodiments of the present invention relate to semiconductor manufacturing technologies, and in particular, to semiconductor devices and manufacturing methods thereof.

As the size of semiconductor devices shrinks, the difficulty of manufacturing semiconductor devices also increases greatly. Undesirable defects may be generated during the manufacturing process of semiconductor devices. These defects may cause the performance of the device to be reduced or damaged. Therefore, it is necessary to continuously improve the semiconductor device to improve the yield and improve the process margin.

The invention provides a semiconductor device. The semiconductor device includes a substrate; a dielectric structure above the substrate; and a cap layer above the dielectric structure, wherein the bottom of the cap layer has an M-shaped cross-sectional profile, and the cap layer and the dielectric structure are formed of different materials.

The invention also provides a method for manufacturing a semiconductor device. This method includes providing a substrate; forming a dielectric structure above the substrate; forming a first cap layer having a U-shaped cross-sectional profile above the dielectric structure; forming a second cap layer above the first cap layer, wherein the second cap layer is located at the first The two sides of a cover layer have a pair of feet extending toward the base, so that a plurality of bottom portions of the first cover layer and the second cover layer form an M-shaped cross-sectional profile.

100‧‧‧ base

110, 120‧‧‧ isolation structure

130‧‧‧ Barrier layer

140‧‧‧ character line

150、200‧‧‧Insulation structure

185‧‧‧Silicide area

190‧‧‧lining

195‧‧‧Second conductive structure

210, 210’‧‧‧ groove

220‧‧‧First cover material

225, 265‧‧‧Trench

230‧‧‧First cover

240‧‧‧ gap

250‧‧‧Second cover material

255‧‧‧foot

160, 160A, 160B, 160C, 160D, 270‧‧‧ dielectric structure

165‧‧‧Etching stop layer

170‧‧‧Protective layer

180‧‧‧The first conductive structure

260‧‧‧Second cover

275‧‧‧ Air gap

280‧‧‧Capacitor

282‧‧‧Lower electrode layer

284, 290‧‧‧ dielectric layer

286‧‧‧Upper electrode layer

1000, 2000, 3000, 4000 ‧‧‧ semiconductor device

A, B‧‧‧Arrow

The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to industry standard practices, various features are not drawn to scale and are for illustrative purposes only. In fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

1A-1E are schematic cross-sectional views at various stages of manufacturing a semiconductor device according to some embodiments of the present invention.

2A-2E are schematic cross-sectional views at various stages of manufacturing a semiconductor device according to other embodiments of the present invention.

FIGS. 3-4 are schematic cross-sectional views of semiconductor devices according to still other embodiments of the present invention.

The following summarizes some embodiments so that those with ordinary knowledge in the technical field to which the present invention belongs can more easily understand the present invention. However, these examples are not intended to limit the invention. It can be understood that those with ordinary knowledge in the technical field to which the present invention belongs can adjust the embodiments described below according to needs, for example, changing the process sequence and/or including more or fewer steps than described herein.

In addition, other elements may be added on the basis of the embodiments described below. For example, the description of "forming a second element on a first element" may include an embodiment where the first element and the second element are in direct contact, or may include other elements between the first element and the second element, so that An embodiment in which an element does not directly contact the second element, and the up-down relationship of the first element and the second element may change as the device is operated or used in different orientations.

The present invention uses a capping layer with an M-shaped bottom profile to protect the underlying film layer from being exposed to subsequent processes such as an etching process and generating undesirable leakage or short-circuit paths, thereby improving the yield of semiconductor devices . In the following embodiments, the fabrication of a memory device is taken as an example for description, but the cap layer of the present invention can also be applied to the fabrication of other semiconductor devices, such as analog/logic circuits, optoelectronic semiconductors, and micro-electromechanical systems.

FIGS. 1A-1H are schematic cross-sectional views illustrating various stages of manufacturing a semiconductor device 1000 according to some embodiments. As shown in FIG. 1A, a substrate 100 is first provided. Any substrate material suitable for semiconductor devices may be used, and may be a monolithic semiconductor substrate or a composite substrate including different materials. In addition, different semiconductor elements may be formed on the substrate 100 in advance.

In some embodiments, as shown in FIG. 1A, an isolation structure 110 and an isolation structure 120 are formed in the substrate 100, wherein the isolation structure 110 and the isolation structure 120 extend in the same direction, and the isolation structure 110 is located in an adjacent isolation structure 120 in the substrate 100. In some embodiments, the isolation structure 110 and the isolation structure 120 may each independently comprise a single-layer, double-layer, or multi-layer structure.

In some embodiments, the formation of the isolation structure 110 and the isolation structure 120 includes forming a trench using an etching process, and then filling the trench with an insulating material of the isolation structure 110 and the isolation structure 120 by a deposition process. The deposition process may include a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process. The insulating materials of the isolation structure 110 and the isolation structure 120 may include silicon oxide, silicon nitride, silicon oxynitride, a combination of the foregoing, or similar materials. Moreover, the isolation structure 110 and the isolation structure 120 may use the same or different materials.

Then, through an etching process and a deposition process, a barrier layer 130, a word line 140, and an insulating structure 150 are formed in the isolation structure 120. The barrier layer 130 may include silicon oxide, silicon nitride, silicon oxynitride, a combination of the foregoing, or similar materials. The word line 140 may include a conductive material, such as amorphous silicon, polysilicon, metal, metal silicide, metal nitride, conductive metal oxide, a combination of the foregoing, or similar materials. The insulating structure 150 may include silicon oxide, silicon nitride, silicon oxynitride, a combination of the foregoing, or similar materials.

As shown in FIG. 1B, next, an etch stop layer 165 and a dielectric layer 160 are sequentially formed over the substrate 102. The dielectric layer 160 is an interlayer dielectric layer, and may include phosphosilicate glass, borosilicate glass, fluorine-doped silicate glass, boron-doped phosphosilicate glass, undoped silicon Salt glass, tetraethoxysilane oxide, low dielectric constant materials, silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, combinations of the foregoing, or similar materials. The etch stop layer 165 may include silicon nitride, silicon oxynitride, a combination of the foregoing, or similar materials. In one embodiment, the formation of the dielectric layer 160 and the etch stop layer 165 may include a deposition process, such as chemical vapor deposition, spin coating, or the like.

Next, an opening through the dielectric layer 160 and the etch stop layer 165 is formed by, for example, a patterning process to expose the substrate, and a protective layer 170, a first conductive structure 180, a silicide region 185, a liner 190 and The second conductive structure 195, wherein the protective layer 170 covers both sides of the dielectric layer 160 and the etch stop layer 165 to protect the dielectric layer 160 from forming the first conductive structure 180, the silicide region 185, the liner layer 190, and the first The two conductive structures 195 are damaged during the manufacturing process. The protective layer 170 may include silicon nitride, silicon oxynitride, a combination of the foregoing, or the like, and the protective layer 170 may be formed using, for example, a chemical vapor deposition process.

Then, the first conductive structure 180 may be formed through a deposition process and an etch-back process. The first conductive structure 180 may include a semiconductor material, such as doped or undoped polysilicon. In an embodiment, the first conductive structure 180 may include a metal material, such as copper, aluminum, tungsten, a combination of the foregoing, or similar metal materials. After that, a silicide region 185, a liner layer 190, and a second conductive structure 195 are sequentially formed on the first conductive structure 180, wherein the formation of the silicide region 185 is selective. In the embodiment where the first conductive structure 180 includes polysilicon, the first conductive structure 180 has a silicide region 185 on it. The material of the liner 190 may include titanium nitride, tantalum nitride, tungsten nitride, a combination of the foregoing, or similar materials. The second conductive structure 195 may include a metal material, such as tungsten, copper, aluminum, gold, chromium, nickel, platinum, titanium, a combination of the foregoing, or similar metal materials.

Then, the openings through the first conductive structure 180, the silicide region 185, the liner layer 190, and the second conductive structure 195 are etched to expose the isolation structure 110 in the substrate 100. And an insulating material is deposited in the opening to form an insulating structure 200.

Then, the dielectric structure 160 may be etched back by an etching process to form a cap layer for protecting the dielectric structure 160 above the dielectric structure 160. As shown in FIG. 1C, the etching process recesses the groove in the middle portion of the dielectric structure 160 to form the dielectric structure 160A having the top groove 210. The etching process may include a dry etching process, such as reactive ion etching, electron cyclotron resonance etching, inductively coupled plasma etching, neutron beam etching, or similar etching processes. In addition, the shape of the groove 210 is not limited to the U-shape in the figure, and may be V-shaped or other shapes.

Then, as shown in FIG. 1D, the first capping material 220 may be overfilled in the groove 210 by a deposition process. The deposition process may include atomic layer deposition, chemical vapor deposition, a combination of the foregoing, or similar processes. The first capping material 220 may include materials having different etching selection ratios from the dielectric structure 160A. In an embodiment, the first capping material 220 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride carbide, a combination of the foregoing, or similar materials.

Next, a capacitor is formed on this structure. As shown in FIG. 1E, a dielectric layer 270 is formed over the first capping material 220, and then the dielectric layer 270 is etched to form a trench 225 exposing the second conductive structure 195 to fabricate a capacitor therein.

However, at this time, due to process variation and other problems, the adjacent dielectric structure 160A may be exposed, resulting in unwanted leakage or short-circuit paths (as indicated by arrow A), causing damage to the semiconductor device 1000. Therefore, the present invention further provides the following embodiments to improve the above problems.

2A-2E are schematic cross-sectional views of the semiconductor device 2000 according to some other embodiments. FIG. 2A is a process step following FIG. 1D. For simplicity, the same components are described below with the same symbols. The formation methods and materials of these elements are as described above, so they will not be repeated here. Compared with the embodiment shown in FIGS. 1A-1E, the following embodiment will further adjust the shape of the cap layer to prevent the dielectric structure 160A from being exposed by subsequent etching.

As shown in FIG. 2A, the first capping material 220 may be etched back until a plurality of surrounding portions of the dielectric structure 160A are exposed, and the first capping layer 230 and the groove 210' above the first capping layer 230 are formed. In one embodiment, the etching back of the first capping material 220 may be a dry etching process, such as reactive ion etching, electron cyclotron resonance etching, inductively coupled plasma etching, neutron beam etching, a combination of the foregoing, or the like Etching process.

In addition, the shape of the upper surface of the first capping layer 230 is not limited to the concave surface in the drawings, but may also be a convex surface, a substantially horizontal plane or other topography, and the shape of the bottom of the first capping layer 230 is not limited to the U-shaped section The outline can also be V-shaped or other shapes.

Then, as shown in FIG. 2B, the surrounding portion of the dielectric structure 160A exposed by the first cap layer 230 can be etched by using the first cap layer 230 as a mask through an etching process, A gap 240 is formed on both sides. In some embodiments, the bottom of these gaps 240 is not lower than the bottom of the first cap layer 230. The etched dielectric structure 160A forms a dielectric structure 160B. Compared to the dielectric structure 160A, the dielectric structure 160B has a reduced top height. In one embodiment, the etching process may include a dry etching process and/or a wet etching process having different etching rates for the first capping layer 230 and the dielectric structure 160A.

Then, as shown in FIG. 2C, the second capping material 250 is overfilled in the grooves 210' above the first capping layer 230 and these gaps 240 by a deposition process to separate the top of the dielectric structure 160B from The top of the protection layer 170 is used to protect the dielectric structure 160B from defects caused by subsequent processes, thereby improving the yield of the semiconductor device 2000.

As shown in FIG. 2C, the second capping material 250 deposited in these gaps 240 forms a pair of feet 255 extending toward the substrate 100, and the bottom of the pair of feet 255 and the bottom of the first capping layer 230 form M Profile profile. In addition, since the etching process removes a portion of the dielectric structure 160A above the first capping layer 230, the edges of the second capping material 250 of the pair of feet 255 and the edge of the dielectric structure 160B form a common sidewall on the protective layer 170 .

In one embodiment, the deposition process of the second capping material 250 may include atomic layer deposition, chemical vapor deposition, a combination of the foregoing, or a similar process. In an embodiment, the second capping material 250 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride carbide, a combination of the foregoing, or similar materials. In a particular embodiment, the second capping material 250 may be the same material as the first capping layer 230, such as silicon nitride. In other embodiments, the second capping material 250 may be a different material from the first capping layer 230. It should be understood that although the interface between the first capping layer 230 and the second capping material 250 is not shown in the drawings, the second capping material 250 is implemented by using a material different from the first capping layer 230 In an example, there is an interface between the first capping layer 230 and the second capping material 250.

Then, as shown in FIG. 2D, a dielectric layer 270 is formed over the second capping material 250, and then the dielectric layer 270 is etched to form a trench 265 exposing the second conductive structure 195 to form a capacitor therein. Since the top of the dielectric structure 160B is protected by the cover layer at this time, the cover layer is a composite cover layer including the first cover layer 230 and the second cover layer 260, so it will not be exposed and undesirable leakage or The short-circuit path (as indicated by arrow B) can therefore improve the yield of the semiconductor device 2000.

In some embodiments, the material of the dielectric structure 270 may include doped or undoped dielectric materials, such as phosphosilicate glass, borosilicate glass, fluorine-doped silicate glass, boron-doped Phosphosilicate glass, undoped silicate glass, tetraethoxysilane oxide, low dielectric constant material, silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, silicon oxide, nitrogen Silicon dioxide, silicon oxynitride, a combination of the foregoing, or similar materials, and the dielectric structure 270 can be formed by a deposition process. In addition, the shape of the top of the second cap layer 260 is not limited to the substantially flat upper surface in the drawings, but may also be convex, concave, or other topography, and the shape of the side wall of the second cap layer 260 is not limited to the figure The inclined side wall in the formula may also be a substantially vertical side wall or other shapes.

Then, as shown in FIG. 2E, the lower electrode layer 282, the dielectric layer 284, and the upper electrode layer 286 of the capacitor 280 are sequentially formed, and then the remaining space of the trench 265 is filled to form the dielectric layer 290 covering the capacitor 280. The materials of the lower electrode layer 282 and the upper electrode layer 286 may include metal materials, such as titanium, tantalum, titanium nitride, and tantalum nitride. The material of the dielectric layer 284 may include a dielectric material having a high dielectric constant, such as zirconia, alumina, a combination of the foregoing, or similar dielectric materials. The material of the dielectric layer 290 may include silicon oxide, silicon nitride, silicon oxynitride, a combination of the foregoing, or similar materials, and the dielectric layer 290 may be formed by a deposition process.

As described above, the present invention provides a compound cap layer including the first cap layer 230 and the second cap layer 260 in the semiconductor device 2000, wherein the bottom of the first cap layer 230 and the bottom of the second cap layer 260 together form M The profile cross-sectional profile can thus protect the top of the dielectric structure 160B from being exposed in the subsequent etching process to form a path of leakage or short circuit, thereby improving the yield of the semiconductor device 2000.

It is worth mentioning that although the middle bottom of the M-shaped cross-sectional profile of the cap layer in FIGS. 2A-2E is lower than the bottom of the two sides (foot 255), the present invention is not limited to this. The present invention can also control the gap 240 to extend further downward during the process of etching a plurality of surrounding portions of the dielectric structure 160A to form the gap 240 in FIG. To ensure that the subsequently formed cap layer 255 can cover the dielectric structure 160C (as shown in FIG. 3), so that the dielectric structure 160C will not be exposed during the subsequent etching process and cause leakage or short-circuit paths, improving the semiconductor device 3000 Yield.

FIG. 4 is a schematic cross-sectional view of a semiconductor device 4000 according to yet other embodiments. Similarly, the manufacturing steps of the embodiment shown in FIG. 4 are substantially the same as those in FIGS. 2A-2E, the difference is that in the process of etching a plurality of surrounding portions of the dielectric structure 160A to form the gap 240 in FIG. 2B, the dielectric structure is etched 160A until the bottom of these gaps 240 passes through the dielectric structure 160A, and the etch stop layer 165 under the dielectric structure 160A is exposed. Among them, the dielectric structure after the above etching process is represented by 160D. Next, in the process of depositing the second capping material 250 in the gap 240 in FIG. 2C to form a pair of feet 255 extending toward the substrate 100, the feet 255 may be formed only in the upper half of the gap 240 to form air Clearance 275. In this embodiment, since the semiconductor device 4000 further has an air gap 275, the parasitic capacitance from bit line to bit line can be further reduced.

As described above, the present invention uses two etching processes and two deposition processes to form a capping layer with an M-shaped cross-sectional profile in the semiconductor device, thus preventing the dielectric structure from being exposed during subsequent etching processes and causing leakage or The short circuit path causes damage to the semiconductor device. Therefore, the present invention provides a compound cap layer including the first cap layer and the second cap layer in the semiconductor device to improve the yield of the semiconductor device. In addition, the cap layer with the M-shaped bottom profile can completely cover the dielectric structure, so the process margin can be improved.

Although the present invention has been described above with multiple embodiments, these embodiments are not intended to limit the present invention. Those of ordinary skill in the technical field to which the present invention belongs should understand that they can make various changes, substitutions, and replacements based on the embodiments of the present invention to achieve the same purpose as the multiple embodiments described herein And/or advantages. Those with ordinary knowledge in the technical field to which the present invention belongs can also understand that such modifications or designs do not depart from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be deemed as defined by the appended patent application scope.

100‧‧‧ base

110, 120‧‧‧ isolation structure

130‧‧‧ Barrier layer

140‧‧‧ character line

150、200‧‧‧Insulation structure

160B, 270‧‧‧dielectric structure

165‧‧‧Etching stop layer

170‧‧‧Protective layer

180‧‧‧The first conductive structure

185‧‧‧Silicide area

190‧‧‧lining

195‧‧‧Second conductive structure

230‧‧‧First cover

260‧‧‧Second cover

280‧‧‧Capacitor

282‧‧‧Lower electrode layer

284, 290‧‧‧ dielectric layer

286‧‧‧Upper electrode layer

2000‧‧‧Semiconductor device

Claims (13)

A semiconductor device includes: a substrate; a dielectric structure located above the substrate; and a cover layer located above the dielectric structure, wherein a bottom of the cover layer has an M-shaped cross-sectional profile, and the cover layer and The dielectric structure is formed of different materials. The semiconductor device as described in item 1 of the patent application range, wherein the cap layer is a composite cap layer, including: a first cap layer having a U-shaped cross-sectional profile; and a second cap layer located at the first On the cover layer, and the second cover layer has a pair of feet located on both sides of the first cover layer. The semiconductor device as described in item 2 of the patent application range, wherein the first capping layer includes a material having a different etching selectivity than the dielectric structure. The semiconductor device as described in item 2 of the scope of the patent application further includes a pair of air gaps between the pair of feet and the base. The semiconductor device as described in item 1 of the patent application range, wherein an edge of the cap layer and an edge of the dielectric structure form a common side wall. The semiconductor device as described in item 1 of the scope of the patent application further includes a pair of conductive structures located above the substrate, wherein the dielectric structure is located between the pair of conductive structures. The semiconductor device as described in item 1 of the patent application further includes a capacitor, wherein a bottom of the capacitor is adjacent to the cap layer. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a dielectric structure above the substrate; forming a first capping layer having a U-shaped cross-sectional profile above the dielectric structure; above the first capping layer Forming a second cover layer, wherein the second cover layer has a pair of feet extending toward the substrate on both sides of the first cover layer, so that a plurality of bottoms of the first cover layer and the second cover layer form a M-shaped profile. The method for manufacturing a semiconductor device as described in item 8 of the patent application range, wherein the formation of the first cap layer includes: etching the dielectric structure to form a U-shaped groove in a middle portion of the dielectric structure; Overfilling a first capping material in the U-shaped groove; and etching back the first capping material until a plurality of surrounding portions of the dielectric structure are exposed. The method for manufacturing a semiconductor device as described in item 9 of the patent application range, wherein the formation of the second capping layer includes: using the first capping layer as a mask, etching the surrounding portions exposed by the dielectric structure to A plurality of gaps are formed on both sides of the first cap layer; and the gaps are filled with a second cap layer material to form the pair of feet of the second cap layer. The method for manufacturing a semiconductor device as described in item 10 of the patent application range, wherein the second capping material fills the upper portions of the gaps to form a plurality of air gaps in the remaining portions of the gaps. The method for manufacturing a semiconductor device as described in item 8 of the scope of the patent application further includes forming a pair of conductive structures above the substrate, wherein the dielectric structure is located between the pair of conductive structures. The method of manufacturing a semiconductor device as described in item 12 of the scope of the patent application further includes forming a capacitor adjacent to the second cap layer above the pair of conductive structures.

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