TW202008503A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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TW202008503A
TW202008503A TW108121348A TW108121348A TW202008503A TW 202008503 A TW202008503 A TW 202008503A TW 108121348 A TW108121348 A TW 108121348A TW 108121348 A TW108121348 A TW 108121348A TW 202008503 A TW202008503 A TW 202008503A
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Taiwan
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opening
layer
source
gate
interlayer dielectric
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TW108121348A
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Chinese (zh)
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TWI709195B (en
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張博欽
林立德
林斌彥
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台灣積體電路製造股份有限公司
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Abstract

A method includes following steps. A semiconductor fin is formed on a substrate and extends in a first direction. A source/drain region is formed on the semiconductor fin and a first interlayer dielectric (ILD) layer over the source/drain region. A gate stack is formed across the semiconductor fin and extends in a second direction substantially perpendicular to the first direction. A patterned mask having a first opening is formed over the first ILD layer. A protective layer is formed in the first opening using a deposition process having a faster deposition rate in the first direction than in the second direction. After forming the protective layer, the first opening is elongated in the second direction. A second opening is formed in the first ILD layer and under the elongated first opening. A conductive material is formed in the second opening.

Description

延長的圖案及其形成方法 Extended pattern and its forming method

積體電路的製造受驅使於半導體裝置中積體電路(integrated circuit,IC)密度的增加。其實現是透過建置更積極的設計規則以允許形成更大密度的積體電路裝置。儘管如此,積體電路裝置(例如,電晶體)的密度增加也增加了處理具有減小的特徵尺寸的半導體裝置的複雜性。 The manufacture of integrated circuits is driven by an increase in the density of integrated circuits (ICs) in semiconductor devices. This is achieved by building more aggressive design rules to allow the formation of larger density integrated circuit devices. Nevertheless, the increased density of integrated circuit devices (eg, transistors) also increases the complexity of processing semiconductor devices with reduced feature sizes.

102‧‧‧基板 102‧‧‧ substrate

104‧‧‧半導體鰭片 104‧‧‧Semiconductor Fin

105‧‧‧隔離絕緣層 105‧‧‧Isolated insulating layer

106‧‧‧閘極堆疊 106‧‧‧Gate Stacking

108‧‧‧閘極間隔物 108‧‧‧Gate spacer

110‧‧‧源極/汲極區域 110‧‧‧ source/drain region

112‧‧‧第一層間介電層 112‧‧‧First dielectric layer

114‧‧‧第一蝕刻停止層 114‧‧‧First etch stop layer

116‧‧‧第二層間介電層 116‧‧‧second dielectric layer

118‧‧‧第二蝕刻停止層 118‧‧‧Second etching stop layer

118'‧‧‧第二蝕刻停止層 118'‧‧‧Second etching stop layer

120‧‧‧硬遮罩層 120‧‧‧hard mask layer

120'‧‧‧硬遮罩層 120'‧‧‧hard mask layer

122‧‧‧三層光阻遮罩 122‧‧‧Three-layer photoresist mask

124‧‧‧保護層 124‧‧‧Protective layer

126‧‧‧導電材料 126‧‧‧ conductive material

128‧‧‧源極/汲極接觸 128‧‧‧ source/drain contacts

202‧‧‧基板 202‧‧‧ substrate

204‧‧‧半導體鰭片 204‧‧‧Semiconductor Fin

205‧‧‧淺溝槽隔離 205‧‧‧Shallow trench isolation

206‧‧‧閘極堆疊 206‧‧‧Gate Stacking

208‧‧‧閘極間隔物 208‧‧‧Gate spacer

210‧‧‧源極/汲極區域 210‧‧‧ source/drain region

212‧‧‧第一層間介電層 212‧‧‧ First dielectric layer

214‧‧‧第一蝕刻停止層 214‧‧‧First etch stop layer

216‧‧‧第二層間介電層 216‧‧‧second dielectric layer

228‧‧‧源極/汲極接觸 228‧‧‧ source/drain contact

230‧‧‧蝕刻停止層 230‧‧‧Etching stop layer

232‧‧‧第三層間介電層 232‧‧‧The third interlayer dielectric layer

232'‧‧‧第三層間介電層 232'‧‧‧third dielectric layer

232"‧‧‧第三層間介電層 232"‧‧‧third dielectric layer

234‧‧‧光阻遮罩 234‧‧‧Photoresist mask

236‧‧‧保護層 236‧‧‧Protective layer

238‧‧‧第二三層光阻遮罩 238‧‧‧The second and third layers of photoresist mask

240‧‧‧保護層 240‧‧‧Protective layer

242‧‧‧閘極接觸 242‧‧‧Gate contact

244‧‧‧源極/汲極通孔 244‧‧‧Source/drain via

302‧‧‧基板 302‧‧‧ substrate

304‧‧‧半導體鰭片 304‧‧‧Semiconductor Fin

305‧‧‧淺溝槽隔離 305‧‧‧Shallow trench isolation

306‧‧‧閘極堆疊 306‧‧‧Gate Stacking

308‧‧‧閘極間隔物 308‧‧‧Gate spacer

310‧‧‧源極/汲極區域 310‧‧‧ source/drain region

312‧‧‧第一層間介電層 312‧‧‧Interlayer dielectric layer

314‧‧‧第一蝕刻停止層 314‧‧‧First etch stop layer

316‧‧‧第二層間介電層 316‧‧‧second dielectric layer

328‧‧‧源極/汲極接觸 328‧‧‧ source/drain contact

330‧‧‧蝕刻停止層 330‧‧‧Etching stop layer

332‧‧‧第三層間介電層 332‧‧‧The third interlayer dielectric layer

332'‧‧‧第三層間介電層 332'‧‧‧third dielectric layer

336‧‧‧保護層 336‧‧‧Protective layer

340‧‧‧三層光阻遮罩 340‧‧‧Three-layer photoresist mask

342‧‧‧保護層 342‧‧‧Protective layer

344‧‧‧導電通孔 344‧‧‧conductive through hole

402‧‧‧基板 402‧‧‧ substrate

404‧‧‧半導體鰭片 404‧‧‧Semiconductor Fin

405‧‧‧淺溝槽隔離 405‧‧‧Shallow trench isolation

406‧‧‧閘極堆疊 406‧‧‧Gate Stacking

406'‧‧‧短閘極堆疊 406'‧‧‧Short gate stack

408‧‧‧閘極間隔物 408‧‧‧Gate spacer

410‧‧‧源極/汲極區域 410‧‧‧ source/drain region

412‧‧‧層間介電層 412‧‧‧Interlayer dielectric layer

414‧‧‧蝕刻停止層 414‧‧‧Etching stop layer

416‧‧‧硬遮罩層 416‧‧‧hard mask layer

416'‧‧‧硬遮罩層 416'‧‧‧hard mask layer

418‧‧‧三層光阻遮罩 418‧‧‧Three-layer photoresist mask

420‧‧‧保護層 420‧‧‧Protective layer

422‧‧‧介電質結構 422‧‧‧dielectric structure

900‧‧‧電漿工具 900‧‧‧ plasma tool

902‧‧‧電漿源 902‧‧‧Plasma source

904‧‧‧電漿腔體 904‧‧‧Plasma cavity

906‧‧‧電漿 906‧‧‧Plasma

908‧‧‧電源 908‧‧‧Power

910‧‧‧外殼 910‧‧‧Housing

912‧‧‧射頻電感器 912‧‧‧RF Inductor

914‧‧‧氣體源 914‧‧‧gas source

916‧‧‧製程腔體 916‧‧‧Process cavity

917‧‧‧垂直線 917‧‧‧Vertical line

920‧‧‧提取板 920‧‧‧Extraction plate

921‧‧‧離子分佈 921‧‧‧Ion distribution

922a‧‧‧離子 922a‧‧‧ion

922b‧‧‧離子 922b‧‧‧ ion

923‧‧‧峰 923‧‧‧ Peak

925‧‧‧峰 925‧‧‧peak

926‧‧‧平臺 926‧‧‧platform

927‧‧‧驅動機構 927‧‧‧Drive mechanism

929‧‧‧軸 929‧‧‧axis

930‧‧‧提取孔 930‧‧‧Extraction hole

932‧‧‧電漿鞘邊界 932‧‧‧plasma sheath boundary

936‧‧‧平面 936‧‧‧plane

938‧‧‧直流電偏壓源 938‧‧‧DC bias source

1062‧‧‧閘極介電層 1062‧‧‧ Gate dielectric layer

1064‧‧‧金屬層 1064‧‧‧Metal layer

1222‧‧‧底層 1222‧‧‧Bottom

1222'‧‧‧圖案化的底層 1222'‧‧‧patterned bottom layer

1224‧‧‧中間層 1224‧‧‧ Middle layer

1226‧‧‧頂層 1226‧‧‧Top

1226'‧‧‧圖案化的頂層 1226'‧‧‧patterned top layer

2062‧‧‧閘極介電層 2062‧‧‧ Gate dielectric layer

2064‧‧‧閘極金屬層 2064‧‧‧Gate metal layer

2342‧‧‧底層 2342‧‧‧Bottom

2342'‧‧‧圖案化的底層 2342'‧‧‧patterned bottom layer

2344‧‧‧中間層 2344‧‧‧ Middle layer

2346‧‧‧頂層 2346‧‧‧Top

2382‧‧‧底層 2382‧‧‧Bottom

2382'‧‧‧圖案化的底層 2382'‧‧‧patterned bottom layer

2384‧‧‧中間層 2384‧‧‧ Middle layer

2386‧‧‧頂層 2386‧‧‧Top

2421‧‧‧第一側壁 2421‧‧‧First side wall

2422‧‧‧第二側壁 2422‧‧‧Second side wall

2441‧‧‧第一側壁 2441‧‧‧First side wall

2442‧‧‧第二側壁 2442‧‧‧Second side wall

3062‧‧‧閘極介電層 3062‧‧‧Gate dielectric layer

3064‧‧‧金屬層 3064‧‧‧Metal layer

3402‧‧‧底層 3402‧‧‧Bottom

3402'‧‧‧圖案化的底層 3402'‧‧‧patterned bottom layer

3404‧‧‧中間層 3404‧‧‧ Middle layer

3406‧‧‧頂層 3406‧‧‧Top

4062‧‧‧閘極介電層 4062‧‧‧ Gate dielectric layer

4062'‧‧‧閘極介電層 4062'‧‧‧Gate dielectric layer

4064‧‧‧金屬層 4064‧‧‧Metal layer

4064'‧‧‧閘極金屬層 4064'‧‧‧Gate metal layer

4182‧‧‧底層 4182‧‧‧Bottom

4182'‧‧‧圖案化的底層 4182'‧‧‧patterned bottom layer

4184‧‧‧中間層 4184‧‧‧ middle layer

4186‧‧‧頂層 4186‧‧‧Top

4186'‧‧‧圖案化的頂層 4186'‧‧‧patterned top layer

L11‧‧‧長度 L11‧‧‧Length

L12‧‧‧長度 L12‧‧‧Length

L12'‧‧‧長度 L12'‧‧‧Length

L12"‧‧‧長度 L12"‧‧‧Length

L13‧‧‧長度 L13‧‧‧Length

L14‧‧‧長度 L14‧‧‧Length

L21‧‧‧長度 L21‧‧‧Length

L22‧‧‧長度 L22‧‧‧Length

L22'‧‧‧長度 L22'‧‧‧Length

L22"‧‧‧長度 L22"‧‧‧Length

L23‧‧‧長度 L23‧‧‧Length

L24‧‧‧長度 L24‧‧‧Length

L31‧‧‧長度 L31‧‧‧Length

L32‧‧‧長度 L32‧‧‧Length

L32'‧‧‧長度 L32'‧‧‧Length

L32"‧‧‧長度 L32"‧‧‧Length

L33‧‧‧長度 L33‧‧‧Length

L34‧‧‧長度 L34‧‧‧Length

L51‧‧‧長度 L51‧‧‧Length

L52‧‧‧長度 L52‧‧‧Length

L52'‧‧‧長度 L52'‧‧‧Length

L52"‧‧‧長度 L52"‧‧‧Length

L53‧‧‧長度 L53‧‧‧Length

L61‧‧‧長度 L61‧‧‧Length

L62‧‧‧長度 L62‧‧‧Length

L62'‧‧‧長度 L62'‧‧‧Length

L62"‧‧‧長度 L62"‧‧‧Length

L63‧‧‧長度 L63‧‧‧Length

L64‧‧‧長度 L64‧‧‧Length

M1‧‧‧方法 M1‧‧‧Method

M2‧‧‧方法 M2‧‧‧Method

M3‧‧‧方法 M3‧‧‧Method

M4‧‧‧方法 M4‧‧‧Method

O11‧‧‧第一開口 O11‧‧‧First opening

O12‧‧‧第二開口 O12‧‧‧Second opening

012'‧‧‧第二開口 012'‧‧‧Second opening

O12"‧‧‧延長的開口 O12"‧‧‧Extended opening

O121‧‧‧第一側壁 O121‧‧‧First side wall

O122‧‧‧第二側壁 O122‧‧‧Second side wall

O13‧‧‧源極/汲極接觸開口 O13‧‧‧ source/drain contact opening

O21‧‧‧第一開口 O21‧‧‧First opening

O22‧‧‧第二開口 O22‧‧‧Second opening

O22'‧‧‧第二開口 O22'‧‧‧Second opening

O22"‧‧‧延長的開口 O22"‧‧‧Extended opening

O221‧‧‧第一側壁 O221‧‧‧First side wall

O222‧‧‧第二側壁 O222‧‧‧Second side wall

O23‧‧‧閘極接觸開口 O23‧‧‧Gate contact opening

O231‧‧‧第一側壁 O231‧‧‧First side wall

O232‧‧‧第二側壁 O232‧‧‧Second side wall

O31‧‧‧第三開口 O31‧‧‧The third opening

O32‧‧‧第四開口 O32‧‧‧The fourth opening

O32'‧‧‧第四開口 O32'‧‧‧The fourth opening

O32"‧‧‧延長的開口 O32"‧‧‧Extended opening

O321‧‧‧第一側壁 O321‧‧‧First side wall

O322‧‧‧第二側壁 O322‧‧‧Second side wall

O33‧‧‧源極/汲極通孔開口 O33‧‧‧Source/drain via opening

O331‧‧‧第一側壁 O331‧‧‧First side wall

O332‧‧‧第二側壁 O332‧‧‧Second side wall

O41‧‧‧閘極接觸開口 O41‧‧‧Gate contact opening

051‧‧‧第一開口 051‧‧‧First opening

O52‧‧‧第二開口 O52‧‧‧Second opening

O52'‧‧‧第二開口 O52'‧‧‧Second opening

O52"‧‧‧延長的開口 O52"‧‧‧Extended opening

O521‧‧‧第一側壁 O521‧‧‧First side wall

O522‧‧‧第二側壁 O522‧‧‧Second side wall

O53‧‧‧通孔開口 O53‧‧‧Through hole opening

O531‧‧‧第一側壁 O531‧‧‧First side wall

O532‧‧‧第二側壁 O532‧‧‧Second side wall

O61‧‧‧第一開口 O61‧‧‧First opening

O61'‧‧‧第二開口 O61'‧‧‧Second opening

O62‧‧‧第二開口 O62‧‧‧Second opening

O62'‧‧‧第二開口 O62'‧‧‧Second opening

O62"‧‧‧延長的開口 O62"‧‧‧Extended opening

O621‧‧‧第一側壁 O621‧‧‧First side wall

O622‧‧‧第二側壁 O622‧‧‧Second side wall

O63‧‧‧切割開口 O63‧‧‧cutting opening

O64‧‧‧開口 O64‧‧‧ opening

S101‧‧‧方框 S101‧‧‧Box

S102‧‧‧方框 S102‧‧‧Box

S103‧‧‧方框 S103‧‧‧Box

S104‧‧‧方框 S104‧‧‧Box

S105‧‧‧方框 S105‧‧‧Box

S106‧‧‧方框 S106‧‧‧Box

S107‧‧‧方框 S107‧‧‧Box

S108‧‧‧方框 S108‧‧‧Box

S109‧‧‧方框 S109‧‧‧Box

S201‧‧‧方框 S201‧‧‧Box

S202‧‧‧方框 S202‧‧‧Box

S203‧‧‧方框 S203‧‧‧Box

S204‧‧‧方框 S204‧‧‧Box

S205‧‧‧方框 S205‧‧‧Box

S206‧‧‧方框 S206‧‧‧Box

S207‧‧‧方框 S207‧‧‧Box

S208‧‧‧方框 S208‧‧‧Box

S209‧‧‧方框 S209‧‧‧Box

S210‧‧‧方框 S210‧‧‧Box

S211‧‧‧方框 S211‧‧‧Box

S212‧‧‧方框 S212‧‧‧Box

S213‧‧‧方框 S213‧‧‧Box

S214‧‧‧方框 S214‧‧‧Box

S301‧‧‧方框 S301‧‧‧Box

S302‧‧‧方框 S302‧‧‧Box

S303‧‧‧方框 S303‧‧‧Box

S304‧‧‧方框 S304‧‧‧Box

S305‧‧‧方框 S305‧‧‧Box

S306‧‧‧方框 S306‧‧‧Box

S307‧‧‧方框 S307‧‧‧Box

S401‧‧‧方框 S401‧‧‧Box

S402‧‧‧方框 S402‧‧‧Box

S403‧‧‧方框 S403‧‧‧Box

S404‧‧‧方框 S404‧‧‧Box

S405‧‧‧方框 S405‧‧‧Box

S406‧‧‧方框 S406‧‧‧Box

S407‧‧‧方框 S407‧‧‧Box

W11‧‧‧寬度 W11‧‧‧Width

W12‧‧‧寬度 W12‧‧‧Width

W12'‧‧‧寬度 W12'‧‧‧Width

W12"‧‧‧寬度 W12"‧‧‧Width

W13‧‧‧寬度 W13‧‧‧Width

W14‧‧‧寬度 W14‧‧‧Width

W21‧‧‧寬度 W21‧‧‧Width

W22‧‧‧寬度 W22‧‧‧Width

W22'‧‧‧寬度 W22'‧‧‧Width

W22"‧‧‧寬度 W22"‧‧‧Width

W23‧‧‧寬度 W23‧‧‧Width

W24‧‧‧寬度 W24‧‧‧Width

W31‧‧‧寬度 W31‧‧‧Width

W32‧‧‧寬度 W32‧‧‧Width

W32'‧‧‧寬度 W32'‧‧‧Width

W32"‧‧‧寬度 W32"‧‧‧Width

W33‧‧‧寬度 W33‧‧‧Width

W34‧‧‧寬度 W34‧‧‧Width

W51‧‧‧寬度 W51‧‧‧Width

W52‧‧‧寬度 W52‧‧‧Width

W52'‧‧‧寬度 W52'‧‧‧Width

W52"‧‧‧寬度 W52"‧‧‧Width

W53‧‧‧寬度 W53‧‧‧Width

W61‧‧‧寬度 W61‧‧‧Width

W62‧‧‧寬度 W62‧‧‧Width

W62'‧‧‧寬度 W62'‧‧‧Width

W62"‧‧‧寬度 W62"‧‧‧Width

W63‧‧‧寬度 W63‧‧‧Width

W64‧‧‧寬度 W64‧‧‧Width

WA‧‧‧晶圓 WA‧‧‧ Wafer

WA2‧‧‧晶圓 WA2‧‧‧ Wafer

WA3‧‧‧晶圓 WA3‧‧‧ Wafer

WA4‧‧‧晶圓 WA4‧‧‧ Wafer

WAP‧‧‧平面 WAP‧‧‧Plane

B-B‧‧‧線 B-B‧‧‧line

C-C‧‧‧線 C-C‧‧‧line

D-D‧‧‧線 D-D‧‧‧line

θ‧‧‧入射角 θ‧‧‧incidence angle

X‧‧‧方向 X‧‧‧ direction

Y‧‧‧方向 Y‧‧‧ direction

Z‧‧‧方向 Z‧‧‧ direction

當結合附圖閱讀時,從以下詳細描述中可以最好地理解本揭露的各方面。應注意,根據工業中的標準實踐,各種特徵未按比例繪製。實際上,為了清楚討論,可以任意增加或減少各種特徵的尺寸。 The aspects of the disclosure can be best understood from the following detailed description when read in conjunction with the drawings. It should be noted that according to standard practice in the industry, various features are not drawn to scale. In fact, for clear discussion, the size of various features can be arbitrarily increased or decreased.

第1圖是根據本揭露的一些實施例之形成半導體裝置的方法的流程圖;第2A圖和第3A圖繪示根據本揭露的一些實施例之處於第1圖之方法的各個階段中的半導體裝置的立體圖;第4A圖、第5A圖、第6A圖、第7A圖、第8A圖、第9A圖和第10A圖繪示根據本揭露的一些實施例之以第1圖之方法製作的各個階段中的半導體裝置的俯視圖; 第2B圖、第3B圖、第4B圖、第5B圖、第6B圖、第7B圖、第8B圖、第9B圖和第10B圖繪示根據本揭露的一些實施例之以第1圖之方法的各個階段中的半導體裝置的剖面圖;第2C圖、第3C圖、第4C圖、第5C圖、第6C圖、第7C圖、第8C圖、第9C圖和第10C圖繪示根據本揭露的一些實施例之以第1圖之方法製作的各個階段中的半導體裝置的另一剖面圖;第11A圖和第11B圖是根據本揭露的一些實施例中形成半導體裝置的方法的流程圖;第12A圖、第13A圖、第14A圖、第15A圖、第16A圖、第17A圖、第18A圖、第19A圖、第20A圖、第21A圖和第22A圖繪示根據本揭露的一些實施例之以第11A圖和第11B圖之方法製作的各個階段中的半導體裝置的俯視圖;第12B圖、第13B圖、第14B圖、第15B圖、第16B圖、第17B圖、第18B圖、第19B圖、第20B圖、第21B圖和第22B圖繪示根據本揭露的一些實施例之以第11A圖和第11B圖之方法製作的各個階段中的半導體裝置的剖面圖;第12C圖、第13C圖、第14C圖、第15C圖、第16C圖、第17C圖、第18C圖、第19C圖、第20C圖、第21C圖和第22C圖繪示根據本揭露的一些實施例之以第11A圖和第11B圖之方法製作的各個階段中的半導體裝置的另一剖面圖;第17D圖、第21D圖和第22D圖繪示根據本揭露的一些實施例之以第11A圖和第11B圖之方法製作的各個階段中的半導體裝置的另一剖面圖;第23圖是根據本揭露的一些實施例之形成半導體裝置的 方法的流程圖;第24A圖、第25A圖、第26A圖、第27A圖、第28A圖和第29A圖繪示根據本揭露的一些實施例以第23圖之方法製作的各個階段中的半導體裝置的剖面圖;第24B圖、第25B圖、第26B圖、第27B圖、第28B圖和第29B圖繪示根據本揭露的一些實施例之以第23圖之方法製作的各個階段中的半導體裝置的另一剖面圖;第30圖是根據本揭露的一些實施例中形成半導體裝置的方法的流程圖;第31A圖繪示根據本揭露的一些實施例中處於第30圖之方法的各個階段中的半導體裝置的立體圖;第32A圖、第33A圖、第34A圖、第35A圖、第36A圖和第37A圖繪示根據本揭露的一些實施例中以於第30圖之方法製作的各個階段中的半導體裝置的俯視圖;第31B圖、第32B圖、第33B圖、第34B圖、第35B圖、第36B圖和第37B圖繪示根據本揭露的一些實施例之以第30圖之方法製作的各個階段中的半導體裝置的剖面圖;第31C圖、第32C圖、第33C圖、第34C圖、第35C圖、第36C圖和第37C圖繪示根據本揭露的一些實施例之以第30圖之方法製作的各個階段中的半導體裝置的另一剖面圖;第36D圖和第37D圖繪示根據本揭露的一些實施例之以第30圖之方法製作的各個階段中的半導體裝置的另一剖面圖;第38圖繪示根據本揭露的一些實施例中電漿工具的示意性側視圖的;以及 第39圖繪示與第38圖的電漿工具產生的離子相關聯之示例性離子分佈圖。 FIG. 1 is a flowchart of a method of forming a semiconductor device according to some embodiments of the present disclosure; FIGS. 2A and 3A illustrate semiconductors at various stages of the method of FIG. 1 according to some embodiments of the present disclosure A perspective view of the device; Figure 4A, Figure 5A, Figure 6A, Figure 7A, Figure 8A, Figure 9A, and Figure 10A illustrate each of the methods made in Figure 1 according to some embodiments of the present disclosure Top view of the semiconductor device in the stage; Figures 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B show some according to the present disclosure Examples of the cross-sectional view of the semiconductor device at various stages of the method of FIG. 1; FIG. 2C, FIG. 3C, FIG. 4C, FIG. 5C, 6C, 7C, 8C, 9C FIGS. 10C and 10C illustrate another cross-sectional view of the semiconductor device in various stages of fabrication according to the method of FIG. 1 according to some embodiments of the present disclosure; FIGS. 11A and 11B are some embodiments according to the present disclosure A flowchart of a method of forming a semiconductor device in FIG. 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A and FIG. 22A illustrates a top view of a semiconductor device in various stages of fabrication according to the methods of FIGS. 11A and 11B according to some embodiments of the present disclosure; FIGS. 12B, 13B, 14B, and 15B, Figures 16B, 17B, 18B, 19B, 20B, 21B, and 22B illustrate each of the methods made in Figs. 11A and 11B according to some embodiments of the present disclosure. Cross-sectional views of the semiconductor device at the stage; Figures 12C, 13C, 14C, 15C, 16C, 17C, 18C, 19C, 20C, 21C and 22C illustrates another cross-sectional view of the semiconductor device in various stages of fabrication according to the methods of FIGS. 11A and 11B according to some embodiments of the present disclosure; FIGS. 17D, 21D, and 22D illustrate Some embodiments of the present disclosure are another cross-sectional view of the semiconductor device at various stages of fabrication by the methods of FIGS. 11A and 11B; FIG. 23 is a flow chart of a method of forming a semiconductor device according to some embodiments of the present disclosure Figures 24A, 25A, 26A, 27A, 28A, and 29A illustrate cross-sections of semiconductor devices at various stages of fabrication according to the method of FIG. 23 according to some embodiments of the disclosure Figures 24B, 25B, 26B, 27B, 28B, and 29B illustrate the semiconductor devices in various stages of fabrication according to the method of FIG. 23 according to some embodiments of the disclosure Another cross-sectional view; FIG. 30 is a flowchart of a method of forming a semiconductor device according to some embodiments of the present disclosure; FIG. 31A illustrates Perspective views of semiconductor devices in various stages of the method of FIG. 30 in some disclosed embodiments; FIGS. 32A, 33A, 34A, 35A, 36A, and 37A illustrate according to the present disclosure In some embodiments, the top view of the semiconductor device at various stages of fabrication by the method of FIG. 30; FIGS. 31B, 32B, 33B, 34B, 35B, 36B, and 37B Figures 31C, 32C, 33C, 34C, 35C, 36C are cross-sectional views of the semiconductor device at various stages of fabrication according to some embodiments of the disclosure; FIGS. 37C show another cross-sectional view of the semiconductor device in various stages of fabrication according to the method of FIG. 30 according to some embodiments of the present disclosure; FIGS. 36D and 37D show some implementations according to the present disclosure For example, another cross-sectional view of the semiconductor device in each stage manufactured by the method of FIG. 30; FIG. 38 shows a schematic side view of a plasma tool according to some embodiments of the present disclosure; and FIG. 39 An exemplary ion profile associated with the ions generated by the plasma tool of FIG. 38 is shown.

以下公開內容提供了用於實現所提供主題的不同特徵的許多不同實施例或示例。以下描述元件和配置的具體示例以簡化本揭露。當然,這些僅僅是示例,而不是限制性的。例如,在以下描述中在第二特徵之上或上方形成第一特徵可以包括其中第一特徵和第二特徵以直接接觸形成的實施例,並且還可以包括可以在第一特徵和第二特徵之間形成附加特徵,使得第一特徵和第二特徵可以不直接接觸的實施例。另外,本揭露可以在各種示例中重複參考數字及/或文字。此重複是為了簡單和清楚的目的,並且本身並不表示所討論的各種實施例及/或配置之間的關係。 The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not limiting. For example, forming the first feature on or above the second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include one that may be on the first feature and the second feature An embodiment in which additional features are formed so that the first feature and the second feature may not directly contact. In addition, the present disclosure may repeat reference numerals and/or text in various examples. This repetition is for simplicity and clarity, and does not in itself represent the relationship between the various embodiments and/or configurations discussed.

此外,本文可以使用空間相對術語,例如「在...下方」、「在...下面」、「低於」、「在...上方」、「高於」等,以便於描述一個元件或特徵與如圖所示的另一個元件或特徵的關係。除了圖中所示的取向之外,空間相對術語旨在涵蓋使用或操作中的裝置的不同取向。裝置可以以其他方式定向(旋轉90度或在其他方向上),並且同樣可以相應地解釋在此使用的空間相對描述符號。 In addition, this article can use spatial relative terms, such as "below", "below", "below", "above", "above", etc., in order to describe an element Or feature and another element or feature as shown. In addition to the orientations shown in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptive symbols used here can likewise be interpreted accordingly.

如下所討論的鰭式場效應電晶體的鰭片可以透過任何合適的方法圖案化。例如,可以使用一個或多個光微影製程(包括雙圖案化或多圖案化製程)來圖案化鰭片。通常,雙 圖案化或多圖案化製程組合光微影和自對準製程,以允許形成具有例如比使用單個、直接光微影製程可獲得的間距更小的間距的圖案。例如,在部分實施例中,在基板上形成犧牲層並使用光微影製程圖案化。使用自對準製程在圖案化的犧牲層旁邊形成間隔物。接著去除犧牲層,然後便可以使用剩餘的間隔物來圖案化鰭片。 The fins of the fin-type field effect transistors discussed below can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multi-patterning processes) can be used to pattern the fins. Generally, double patterning or multi-patterning processes combine photolithography and self-alignment processes to allow the formation of patterns with smaller pitches than those achievable using a single, direct photolithography process, for example. For example, in some embodiments, a sacrificial layer is formed on the substrate and patterned using a photolithography process. A self-aligned process is used to form spacers next to the patterned sacrificial layer. Then the sacrificial layer is removed, and then the remaining spacers can be used to pattern the fins.

第1圖繪示根據本揭露的一些實施例中形成半導體裝置的方法M1。第2A圖至第10C圖繪示根據本揭露的一些實施例之第1圖的方法M1的各個階段的各種製程。在各種視圖和說明性實施例中,相同的附圖標記用於表示相同的元件。在第2A圖至第3C圖中,「A」圖(例如,第2A圖和第3A圖)繪示立體圖,「B」圖(例如,第2B圖和第3B圖)繪示沿著與「A」圖中所示的線B-B對應的方向X的剖面圖,「C」圖(例如,第2C圖和第3C圖)繪示沿著與「A」圖中所示的線C-C對應的方向Y的剖面圖。在第4A圖至第10C圖中,「A」圖(例如,第4A圖、第5A圖等)繪示俯視圖,「B」圖(例如,第4B圖和第5B圖)繪示沿著與「A」圖中所示的線B-B對應的方向X的剖面圖,並且「C」圖(例如,第4C圖和第5C圖)繪示沿著與「A」圖中所示的線C-C對應的方向Y的剖面圖。應當理解,可以在第2A圖至第10C圖所示的製程之前、期間和之後提供額外的步驟,以作為此方法的其他實施例,並且可以替換或消除下面描述的一些步驟。步驟/製程的順序可以是可互換的。 FIG. 1 illustrates a method M1 of forming a semiconductor device according to some embodiments of the present disclosure. FIGS. 2A to 10C illustrate various processes at various stages of the method M1 of FIG. 1 according to some embodiments of the present disclosure. In various views and illustrative embodiments, the same reference numerals are used to represent the same elements. In Figures 2A to 3C, "A" (for example, Figures 2A and 3A) shows a perspective view, and "B" (for example, Figures 2B and 3B) shows along and " The cross-sectional view of the direction X corresponding to the line BB shown in the "A" figure, and the "C" figures (for example, figures 2C and 3C) are drawn along the direction corresponding to the line CC shown in the "A" figure Sectional view of Y. In FIGS. 4A to 10C, “A” (for example, FIGS. 4A, 5A, etc.) shows a top view, and “B” (for example, FIGS. 4B and 5B) shows along and A cross-sectional view in the direction X corresponding to the line BB shown in the "A" drawing, and the "C" drawing (for example, FIGS. 4C and 5C) is drawn along the line CC corresponding to the drawing in the "A" drawing Cross-sectional view in the direction Y. It should be understood that additional steps may be provided before, during, and after the processes shown in FIGS. 2A to 10C as other embodiments of this method, and some steps described below may be replaced or eliminated. The order of steps/processes can be interchangeable.

在方法M1的方框S101中,在基板上形成電晶體 (例如,鰭式場效應電晶體)和第一層間介電(interlayer dielectric,ILD)層。例如,如第2A圖至第2C所示,示出了具有基板102的半導體晶圓WA,基板102具有一個或多個半導體鰭片104和一個或多個閘極堆疊106。應當理解,出於說明的目的繪示四個半導體鰭片,然而其他實施例可以包括任意數量的半導體鰭片。半導體鰭片104在方向X上延伸並且在方向Z上從基板102突出,而閘極堆疊106在方向Y上延伸。閘極堆疊106延伸跨越半導體鰭片104,從而在基板102上形成鰭式場效應電晶體。 In block S101 of method M1, a transistor (e.g., fin field effect transistor) and a first interlayer dielectric (ILD) layer are formed on the substrate. For example, as shown in FIGS. 2A to 2C, a semiconductor wafer WA having a substrate 102 having one or more semiconductor fins 104 and one or more gate stacks 106 is shown. It should be understood that four semiconductor fins are shown for illustrative purposes, although other embodiments may include any number of semiconductor fins. The semiconductor fin 104 extends in the direction X and protrudes from the substrate 102 in the direction Z, while the gate stack 106 extends in the direction Y. The gate stack 106 extends across the semiconductor fin 104 to form a fin field effect transistor on the substrate 102.

基板102可以包括各種摻雜區域。在一些實施例中,摻雜區域可以摻雜有p型或n型摻雜物。例如,摻雜區域可以摻雜有p型摻雜物(例如,硼或二氟化硼(BF2));n型摻雜物(例如,磷或砷);及/或以上之組合。摻雜區域可以用於n型鰭式場效應電晶體,或者可用於p型鰭式場效應電晶體。 The substrate 102 may include various doped regions. In some embodiments, the doped region may be doped with p-type or n-type dopants. For example, the doped region may be doped with p-type dopants (eg, boron or boron difluoride (BF 2 )); n-type dopants (eg, phosphorus or arsenic); and/or a combination of the above. The doped region may be used for n-type fin field effect transistors, or may be used for p-type fin field effect transistors.

在一些實施例中,基板102可以由合適的元素半導體製成,例如矽、鑽石或鍺;合適的合金或化合物半導體,如IV族化合物半導體(矽鍺(SiGe)、碳化矽(SiC)、碳化矽鍺(SiGeC)、鍺錫(GeSn)、矽錫(SiSn)、矽鍺錫(SiGeSn))、III-V族化合物半導體(如,砷化鎵、砷化鎵銦(InGaAs)、砷化銦、磷化銦、銻化銦、砷磷化鎵或磷化鎵銦)或類似物。此外,基板102可以包括磊晶層(epi-layer),其可以是應變的以提高性能,及/或可以包括絕緣體上矽(silicon-on-insulator,SOI)結構。 In some embodiments, the substrate 102 may be made of a suitable element semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as a group IV compound semiconductor (silicon germanium (SiGe), silicon carbide (SiC), carbide Silicon germanium (SiGeC), germanium tin (GeSn), silicon tin (SiSn), silicon germanium tin (SiGeSn)), group III-V compound semiconductors (eg, gallium arsenide, indium gallium arsenide (InGaAs), indium arsenide , Indium phosphide, indium antimonide, gallium arsenide phosphide or indium gallium phosphide) or the like. In addition, the substrate 102 may include an epi-layer, which may be strained to improve performance, and/or may include a silicon-on-insulator (SOI) structure.

可以使用例如圖案化製程來形成半導體鰭片 104,以在基板102中形成溝槽,使得在相鄰的半導體鰭片104之間形成溝槽。隔離區域(例如,淺溝槽隔離(shallow trench isolations,STI)105)設置在基板102上方的溝槽中。在一些實施例中,隔離區域可以相當於隔離絕緣層。隔離絕緣層105可以由合適的介電材料製成,例如氧化矽、氮化矽、氮氧化矽、摻雜氟的矽酸鹽玻璃(fluorine-doped silicate glass,FSG)、低介電常數介電質(例如,摻雜碳的氧化物)、極低介電常數介電質(例如,摻雜多孔碳的二氧化矽)、聚合物(例如,聚醯亞胺)、以上之組合或類似物。在一些實施例中,隔離絕緣層105透過諸如化學氣相沉積(chemical vapor deposition,CVD)、可流動式化學氣相沉積(flowable chemical vapor deposition,FCVD)或旋塗玻璃製程的製程形成,然而亦可以使用任何可接受的製程。隨後,使用例如回蝕刻製程、化學機械平坦化(chemical mechanical polishing,CMP)等去除在半導體鰭片104的頂面上延伸之部分的隔離絕緣層105。 The semiconductor fins 104 may be formed using, for example, a patterning process to form trenches in the substrate 102 so that trenches are formed between adjacent semiconductor fins 104. An isolation region (for example, shallow trench isolations (STI) 105) is provided in the trench above the substrate 102. In some embodiments, the isolation region may correspond to an isolation insulating layer. The isolation insulating layer 105 may be made of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low dielectric constant dielectric Substances (for example, carbon-doped oxides), very low dielectric constant dielectrics (for example, porous carbon-doped silicon dioxide), polymers (for example, polyimide), combinations of the above, or the like . In some embodiments, the isolation insulating layer 105 is formed through a process such as chemical vapor deposition (CVD), flowable chemical vapor deposition (FCVD), or spin-on glass process, however, Any acceptable process can be used. Subsequently, the isolation insulating layer 105 extending on the top surface of the semiconductor fin 104 is removed using, for example, an etch-back process, chemical mechanical polishing (CMP), or the like.

在一些實施例中,凹陷隔離絕緣層105以暴露半導體鰭片104的頂部,如第2A圖至第2C圖所示。在一些實施例中,使用單蝕刻製程或多蝕刻製程來使隔離絕緣層105凹陷。在隔離絕緣層105由氧化矽製成的一些實施例中,蝕刻製程可以是例如乾式蝕刻、化學蝕刻或濕式清潔製程。例如,化學蝕刻可以使用含氟化學品,例如稀釋的氫氟酸。 In some embodiments, the isolation insulating layer 105 is recessed to expose the top of the semiconductor fin 104, as shown in FIGS. 2A to 2C. In some embodiments, a single etching process or a multiple etching process is used to recess the isolation insulating layer 105. In some embodiments where the isolation insulating layer 105 is made of silicon oxide, the etching process may be, for example, dry etching, chemical etching, or wet cleaning process. For example, chemical etching may use fluorine-containing chemicals, such as diluted hydrofluoric acid.

在形成半導體鰭片104之後,形成橫跨在半導體鰭片104上的虛設閘極結構(例如,多晶矽閘極結構),並且如下面進一步而言描述的將用閘極堆疊106替換虛設閘極結 構。在形成虛設閘極結構之後,沿著虛設閘極結構的側壁形成閘極間隔物108。接下來,在半導體鰭片104中形成源極/汲極區域110。源極/汲極區域110的形成包括例如使用合適的蝕刻技術使未被虛設閘極結構和閘極間隔物108覆蓋之部分的半導體鰭片104凹陷,並且從半導體鰭片104的凹陷部分磊晶生長源極/汲極區域110。 After forming the semiconductor fin 104, a dummy gate structure (eg, a polysilicon gate structure) is formed across the semiconductor fin 104, and the dummy gate structure will be replaced with the gate stack 106 as described further below . After forming the dummy gate structure, a gate spacer 108 is formed along the sidewall of the dummy gate structure. Next, the source/drain region 110 is formed in the semiconductor fin 104. The formation of the source/drain region 110 includes, for example, recessing a portion of the semiconductor fin 104 that is not covered by the dummy gate structure and the gate spacer 108 using an appropriate etching technique, and epitaxial from the recessed portion of the semiconductor fin 104 Growing source/drain region 110.

在一些實施例中,使半導體鰭片104凹陷可包括乾式蝕刻製程、濕式蝕刻製程或乾式和濕式蝕刻製程的組合。此蝕刻製程可以包括使用虛設閘極結構和閘極間隔物108作為遮罩的反應離子蝕刻(reactive ion etch,RIE),或者透過任何其他合適的去除製程。在蝕刻製程之後,在一些實施例中,可以執行預清潔製程以用氫氟酸或其他合適的溶液清潔半導體鰭片104中的凹槽。 In some embodiments, recessing the semiconductor fin 104 may include a dry etching process, a wet etching process, or a combination of dry and wet etching processes. This etching process may include reactive ion etch (RIE) using the dummy gate structure and the gate spacer 108 as a mask, or through any other suitable removal process. After the etching process, in some embodiments, a pre-cleaning process may be performed to clean the grooves in the semiconductor fin 104 with hydrofluoric acid or other suitable solutions.

在一些實施例中,源極/汲極區域110可以使用一個或多個磊晶製程形成,使得矽(Si)特徵、矽鍺(SiGe)特徵、磷酸矽(SiP)特徵、碳化矽(SiC)特徵及/或其他合適的特徵可以在半導體鰭片104上以結晶態形成。在一些實施例中,源極/汲極區域110的晶格常數不同於半導體鰭片104的晶格常數,因此源極/汲極區域110之間的通道區域可以被源極/汲極區域110應變或應力,以提升半導體裝置的載流子遷移率並增強裝置性能。 In some embodiments, the source/drain regions 110 may be formed using one or more epitaxial processes, such that silicon (Si) features, silicon germanium (SiGe) features, silicon phosphate (SiP) features, silicon carbide (SiC) The features and/or other suitable features may be formed on the semiconductor fin 104 in a crystalline state. In some embodiments, the lattice constant of the source/drain region 110 is different from the lattice constant of the semiconductor fin 104, so the channel region between the source/drain region 110 can be used by the source/drain region 110 Strain or stress to improve the carrier mobility of semiconductor devices and enhance device performance.

形成源極/汲極區域110的磊晶製程包括化學氣相沉積技術(例如,氣相磊晶(vapor-phase epitaxy,VPE)及/或超高真空化學氣相沉積(ultra-high vacuum chemical vapor deposition,UHV-CVD))、分子束磊晶及/或其他合適的製程。磊晶製程可以使用氣態及/或液態前驅物,其與半導體鰭片104的成分(例如,矽、矽鍺、磷酸矽或類似物)相互作用。磊晶源極/汲極區域110可以是原位(in-situ)摻雜的。摻雜物質包括p型摻雜物(例如,硼或二氟化硼(BF2));n型摻雜物(例如,磷或砷);及/或其他包括其組合的合適的摻雜物。如果磊晶源極/汲極區域110並未原位摻雜,則執行植入製程以摻雜磊晶源極/汲極區域110。可以執行一個或多個退火製程以活化磊晶源極/汲極區域110。退火製程包括快速熱退火(rapid thermal annealing,RTA)及/或雷射退火製程。 The epitaxial process for forming the source/drain regions 110 includes chemical vapor deposition techniques (for example, vapor-phase epitaxy (VPE) and/or ultra-high vacuum chemical vapor deposition (ultra-high vacuum chemical vapor deposition deposition, UHV-CVD)), molecular beam epitaxy and/or other suitable processes. The epitaxial process may use gaseous and/or liquid precursors that interact with the components of the semiconductor fin 104 (eg, silicon, silicon germanium, silicon phosphate, or the like). The epitaxial source/drain region 110 may be in-situ doped. Dopants include p-type dopants (eg, boron or boron difluoride (BF 2 )); n-type dopants (eg, phosphorus or arsenic); and/or other suitable dopants including combinations thereof . If the epitaxial source/drain region 110 is not doped in situ, an implantation process is performed to dope the epitaxial source/drain region 110. One or more annealing processes may be performed to activate the epitaxial source/drain regions 110. The annealing process includes rapid thermal annealing (RTA) and/or laser annealing processes.

在形成源極/汲極區域110之後,在源極/汲極區域110、虛設閘極結構和閘極間隔物108上方形成第一層間介電層112,然後執行化學機械平坦化製程以去除第一層間介電層112多餘的材料,以暴露虛設閘極結構。在一些實施例中,第一層間介電層112包括氧化矽、氮化矽、氮氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)、低介電常數介電材料及/或其他合適的介電材料。低介電常數介電材料的實例包括但不限於氟化二氧化矽玻璃(fluorinated silica glass,FSG)、摻雜碳的氧化矽、非晶氟化碳、聚對二甲苯、雙苯並環丁烯(bis-benzocyclobutenes,BCB)或聚醯亞胺。可以使用例如化學氣相沉積、原子層沉積、旋塗玻璃(spin-on-glass,SOG)或其他合適的技術來形成第一層間介電層112。在一些實施例中,在形成第一層間介電層112之前, 可選地在源極/汲極區域110上形成接觸蝕刻停止層(contact etch stop layer,CESL),然後在接觸蝕刻停止層上形成第一層間介電層112。接觸蝕刻停止層具有與第一層間介電層112不同的材料。舉例來說,接觸蝕刻停止層包括氮化矽、氮氧化矽或其他合適的材料。可以使用例如電漿增強化學氣相沉積、低壓化學氣相沉積、原子層沉積或其他合適的技術形成接觸蝕刻停止層。 After forming the source/drain region 110, a first interlayer dielectric layer 112 is formed over the source/drain region 110, the dummy gate structure, and the gate spacer 108, and then a chemical mechanical planarization process is performed to remove The first interlayer dielectric layer 112 has excess material to expose the dummy gate structure. In some embodiments, the first interlayer dielectric layer 112 includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) , Low dielectric constant dielectric materials and/or other suitable dielectric materials. Examples of low dielectric constant dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silica, amorphous carbon fluoride, parylene, dibenzocyclobutane Bis-benzocyclobutenes (BCB) or polyimide. The first interlayer dielectric layer 112 may be formed using, for example, chemical vapor deposition, atomic layer deposition, spin-on-glass (SOG), or other suitable techniques. In some embodiments, before forming the first interlayer dielectric layer 112, a contact etch stop layer (CESL) is optionally formed on the source/drain region 110, and then the contact etch stop layer is formed The first interlayer dielectric layer 112 is formed thereon. The contact etch stop layer has a different material from the first interlayer dielectric layer 112. For example, the contact etch stop layer includes silicon nitride, silicon oxynitride, or other suitable materials. The contact etch stop layer may be formed using, for example, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atomic layer deposition, or other suitable techniques.

此後,用閘極堆疊106替換虛設閘極結構。閘極替換製程包括例如移除虛設閘極結構以在閘極間隔物108之間形成閘極溝槽,以及在閘極溝槽中形成閘極堆疊106。形成閘極堆疊106的示例性方法可以包括在晶圓WA上方毯覆式形成閘極介電層1062,在毯覆式的閘極介電層1062上方形成一個或多個金屬層1064,以及執行化學機械平坦化製程以去除位於閘極溝槽外部的一個或多個金屬層1064和閘極介電層1062的多餘材料。閘極替換製程的結果為每個閘極堆疊106皆包括閘極介電層1062和由閘極介電層1062環繞的一個或多個金屬層1064。 Thereafter, the dummy gate structure is replaced with the gate stack 106. The gate replacement process includes, for example, removing the dummy gate structure to form a gate trench between the gate spacers 108, and forming a gate stack 106 in the gate trench. An exemplary method of forming the gate stack 106 may include blanket forming the gate dielectric layer 1062 over the wafer WA, forming one or more metal layers 1064 over the blanket gate dielectric layer 1062, and performing A chemical mechanical planarization process to remove excess material of one or more metal layers 1064 and gate dielectric layers 1062 located outside the gate trench. The result of the gate replacement process is that each gate stack 106 includes a gate dielectric layer 1062 and one or more metal layers 1064 surrounded by the gate dielectric layer 1062.

在一些實施例中,閘極介電層1062可包括例如高介電常數介電材料,例如金屬氧化物、金屬氮化物、金屬矽酸鹽、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽酸鹽、金屬氧氮化物、金屬鋁酸鹽、矽酸鋯、鋁酸鋯或以上之組合。在一些實施例中,閘極介電層1062可以包括二氧化鉿(HfO2)、氧化鉿矽(HfSiO)、氮氧化鉿矽(HfSiON)、氧化鉭鉿(HfTaO)、氧化鈦鉿(HfTiO)、氧化鋯鉿(HfZrO)、氧 化鑭(LaO)、氧化鋯(ZrO)、氧化鈦(TiO)、氧化鉭(Ta2O5)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3,STO)、氧化鋇鈦(BaTiO3,BTO)、氧化鋇鋯(BaZrO)、氧化鉿鑭(HfLaO)、氧化鑭矽(LaSiO)、氧化鋁矽(AlSiO)、氧化鋁(Al2O3)、氮化矽(Si3N4)、氧氮化物(SiON)及以上之組合。在一些實施例中,閘極介電層1062可以具有多層結構,例如一層氧化矽(例如,界面層)和另一層高介電常數材料。 In some embodiments, the gate dielectric layer 1062 may include, for example, a high dielectric constant dielectric material, such as metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal silicon Acid salt, metal oxynitride, metal aluminate, zirconium silicate, zirconium aluminate, or a combination thereof. In some embodiments, the gate dielectric layer 1062 may include hafnium dioxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), tantalum hafnium oxide (HfTaO), hafnium oxide titanium (HfTiO) , Hafnium zirconia (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), strontium titanate (SrTiO 3 , STO), barium titanium oxide (BaTiO 3 , BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum oxide silicon (LaSiO), aluminum oxide silicon (AlSiO), aluminum oxide (Al 2 O 3 ) , Silicon nitride (Si 3 N 4 ), oxynitride (SiON) and combinations thereof. In some embodiments, the gate dielectric layer 1062 may have a multi-layer structure, such as a layer of silicon oxide (eg, an interface layer) and another layer of high dielectric constant material.

在一些實施例中,金屬層1064是多層結構,包括一個或多個功函數金屬層和由一個或多個功函數金屬層環繞的填充金屬。一個或多個功函數金屬層可包括一種或多種n型功函數金屬及/或一種或多種p型功函數金屬。n型功函數金屬可示例性地包括,但不限於,鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、碳氮化鉭(TaCN)、鉿(Hf)、鋯(Zr)、鈦(Ti)、鉭(Ta)、鋁(Al)、金屬碳化物(例如,碳化鉿(HfC)、碳化鋯(ZrC)、碳化鈦(TiC)、碳化鋁(AlC))、鋁化物及/或其他合適的材料。p型功函數金屬可示例性地包括但不限於氮化鈦(TiN)、氮化鎢(WN)、鎢(W)、釕(Ru)、鈀(Pd)、鉑(Pt)、鈷(Co)、鎳(Ni)、導電金屬氧化物及/或其他合適的材料。填充金屬可以示例性地包括,但不限於,鎢、鋁、銅、鎳、鈷、鈦、鉭、氮化鈦、氮化鉭、矽化鎳、矽化鈷、碳化鉭(TaC)、氮矽化鉭(TaSiN)、氮碳化鉭(TaCN)、鈦鋁(TiAl)、氮化鈦鋁(TiAlN)或其他合適的材料。 In some embodiments, the metal layer 1064 is a multilayer structure including one or more work function metal layers and a filler metal surrounded by the one or more work function metal layers. The one or more work function metal layers may include one or more n-type work function metals and/or one or more p-type work function metals. The n-type work function metal may exemplarily include, but not limited to, titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti ), tantalum (Ta), aluminum (Al), metal carbides (eg, hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides and/or other suitable s material. The p-type work function metal may exemplarily include, but not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co ), nickel (Ni), conductive metal oxides and/or other suitable materials. Filler metals can exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tantalum carbide (TaC), tantalum silicon nitride ( TaSiN), tantalum nitride carbide (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN) or other suitable materials.

返回第1圖,方法M1接著進行到方框S102,在電晶體和第一層間介電層上形成第一蝕刻停止層(etch stop layer,ESL)、第二層間介電層、第二蝕刻停止層、硬遮罩層和三層光罩。參考第3A圖至第3C圖,在方框S102的一些實施例中,在第一層間介電層112和閘極堆疊106上依序形成第一蝕刻停止層114、第二層間介電層116、第二蝕刻停止層118、硬遮罩層120和三層光阻遮罩122。在一些實施例中,第一蝕刻停止層114可以包括氮化物材料,例如氮化矽、氮化鈦或類似物,並且可以使用諸如化學氣相沉積或物理氣相沉積的沉積製程來形成。在一些實施例中,第二層間介電層116可以包括與第一層間介電層112相同的材料,並且可以使用例如化學氣相沉積、原子層沉積、旋塗玻璃或其他合適的技術形成。例如,第二層間介電層116可以包括氧化矽、氮化矽、氮氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)、低介電常數介電材料及/或其他合適的介電材料。低介電常數介電材料的實例包括,但不限於,氟化二氧化矽玻璃(fluorinated silica glass,FSG)、碳摻雜氧化矽、非晶氟化碳、聚對二甲苯、雙苯並環丁烯(bis-benzocyclobutenes,BCB)或聚醯亞胺。第二層間介電層116具有比第一蝕刻停止層114更快的蝕刻速率,使得第一蝕刻停止層114可以減慢或甚至停止在第二層間介電層116上執行的蝕刻製程。 Returning to FIG. 1, the method M1 then proceeds to block S102 to form a first etch stop layer (ESL), a second interlayer dielectric layer, and a second etch on the transistor and the first interlayer dielectric layer Stop layer, hard mask layer and three-layer photomask. Referring to FIGS. 3A to 3C, in some embodiments of block S102, a first etch stop layer 114 and a second interlayer dielectric layer are sequentially formed on the first interlayer dielectric layer 112 and the gate stack 106 116. A second etch stop layer 118, a hard mask layer 120, and a three-layer photoresist mask 122. In some embodiments, the first etch stop layer 114 may include a nitride material, such as silicon nitride, titanium nitride, or the like, and may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition. In some embodiments, the second interlayer dielectric layer 116 may include the same material as the first interlayer dielectric layer 112, and may be formed using, for example, chemical vapor deposition, atomic layer deposition, spin on glass, or other suitable techniques . For example, the second interlayer dielectric layer 116 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric Constant dielectric materials and/or other suitable dielectric materials. Examples of low dielectric constant dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous carbon fluoride, parylene, dibenzo ring Butene (bis-benzocyclobutenes, BCB) or polyimide. The second interlayer dielectric layer 116 has a faster etch rate than the first etch stop layer 114, so that the first etch stop layer 114 can slow down or even stop the etching process performed on the second interlayer dielectric layer 116.

在一些實施例中,第二蝕刻停止層118可以包括碳化物材料(例如,碳化鎢)並且可以使用諸如化學氣相沉積或物理氣相沉積的沉積製程來形成。在一些實施例中,硬遮罩層120可以包括氧化物材料(例如,氧化矽),並且可以使用 諸如化學氣相沉積或物理氣相沉積的沉積製程來形成。三層光阻遮罩122包括位於硬遮罩層120上方的底層1222,位於底層1222上方的中間層1224,以及位於中間層1224上方的頂層1226。在一些實施例中,底層1222可包括有機材料(例如,旋塗碳(spin-on carbon,SOC)材料或類似物)並且可以使用旋轉塗佈(spin-on coating)、化學氣相沉積、原子層沉積或類似方法形成。中間層1224可以包括無機材料,其可以是氮化物(例如,氮化矽(SiN)、氮化鈦(TiN)、氮化鉭(TaN)或類似物)、氮氧化物(例如,氮氧化矽(SiON))、氧化物(例如,氧化矽)或類似物,且可以使用化學氣相沉積、原子層沉積或類似方法形成。頂層1226可以包括有機材料(例如,光阻材料)並且可以使用旋轉塗佈或類似方法形成。在一些實施例中,中間層1224具有比頂層1226更快的蝕刻速率,並且頂層1226可以做為用於圖案化中間層1224的蝕刻遮罩。在一些實施例中,底層1222具有比中間層1224更快的蝕刻速率,並且中間層1224可以做為用於圖案化底層1222的蝕刻遮罩。 In some embodiments, the second etch stop layer 118 may include a carbide material (eg, tungsten carbide) and may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition. In some embodiments, the hard mask layer 120 may include an oxide material (e.g., silicon oxide), and may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition. The three-layer photoresist mask 122 includes a bottom layer 1222 above the hard mask layer 120, an intermediate layer 1224 above the bottom layer 1222, and a top layer 1226 above the intermediate layer 1224. In some embodiments, the bottom layer 1222 may include an organic material (eg, spin-on carbon (SOC) material or the like) and may use spin-on coating, chemical vapor deposition, atomic Layer deposition or similar methods. The intermediate layer 1224 may include an inorganic material, which may be nitride (for example, silicon nitride (SiN), titanium nitride (TiN), tantalum nitride (TaN), or the like), oxynitride (for example, silicon oxynitride (SiON)), oxide (for example, silicon oxide), or the like, and can be formed using chemical vapor deposition, atomic layer deposition, or the like. The top layer 1226 may include an organic material (for example, a photoresist material) and may be formed using spin coating or the like. In some embodiments, the middle layer 1224 has a faster etch rate than the top layer 1226, and the top layer 1226 can be used as an etch mask for patterning the middle layer 1224. In some embodiments, the bottom layer 1222 has a faster etch rate than the middle layer 1224, and the middle layer 1224 can be used as an etch mask for patterning the bottom layer 1222.

返回第1圖,方法M1接著進行到方框S103,在三層光阻遮罩的頂層中並且在相應的源極/汲極區域上方形成第一開口。參考第4A圖至第4C圖,在方框S103的一些實施例中,使用合適的光微影技術將三層光阻遮罩122的頂層1226圖案化,以在圖案化的頂層1226'中並且在相應的源極/汲極區域110的垂直上方形成第一開口O11。在頂層1226包括光阻材料的一些實施例中,光阻材料被照射(曝光)並顯影以去除部分 的光阻材料。例如,光罩或倍縮式光罩(reticle)(未示出)可以設置在頂部光阻層1226上,然後可以將其暴露於輻射束,其可以是紫外線(ultraviolet,UV)或準分子雷射(excimer laser)(例如,氪氟化物(Krypton Fluoride,KrF)準分子雷射或氬氟化物(Argon Fluoride,ArF)準分子雷射)。可以使用浸潤式微影(immersion lithography)系統來執行頂部光阻層1226的曝光,以增加解析度並降低可實現的最小間距。可以執行烘烤或固化操作以硬化頂部光阻層1226,並且可以使用顯影劑並根據是使用正型或負型光阻來去除頂部光阻層1226的曝光或未曝光的部分。因此,可以在圖案化的頂部光阻層1226'中形成如第4A圖至第4C圖中所示的第一開口O11。 Returning to FIG. 1, the method M1 then proceeds to block S103, where a first opening is formed in the top layer of the three-layer photoresist mask and above the corresponding source/drain regions. Referring to FIGS. 4A to 4C, in some embodiments of block S103, the top layer 1226 of the three-layer photoresist mask 122 is patterned using a suitable photolithography technique to form in the patterned top layer 1226′ and A first opening O11 is formed vertically above the corresponding source/drain region 110. In some embodiments where the top layer 1226 includes photoresist material, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. For example, a reticle or reticle (not shown) may be disposed on the top photoresist layer 1226, and then it may be exposed to a radiation beam, which may be ultraviolet (UV) or excimer mine Excimer laser (for example, Krypton Fluoride (KrF) excimer laser or Argon Fluoride (ArF) excimer laser). An immersion lithography system can be used to perform the exposure of the top photoresist layer 1226 to increase resolution and reduce the minimum achievable pitch. A baking or curing operation may be performed to harden the top photoresist layer 1226, and a developer may be used to remove exposed or unexposed portions of the top photoresist layer 1226 depending on whether a positive or negative photoresist is used. Therefore, the first opening O11 as shown in FIGS. 4A to 4C may be formed in the patterned top photoresist layer 1226′.

圖案化的頂層1226'中的這些第一開口O11用於限定源極/汲極接觸開口的圖案,其將在以下步驟中形成在第一層間介電層112中。如第4A圖所示,每個第一開口O11在方向Y上具有長度L11並且在方向X上具有寬度W11,並且長度L11大於寬度W11。因此,隨後形成的源極/汲極接觸開口在方向Y上的長度將大於在方向X上的寬度,這將導致源極/汲極接觸面積增加,同時防止源極/汲極接觸接觸閘極堆疊106,其將在下面進一步而言討論。在一些實施例中,寬度W11大於約10奈米(nm)。如果寬度W11小於約10奈米,則後續使用定向離子的定向沉積及/或定向蝕刻的結果可能會不令人滿意。 These first openings O11 in the patterned top layer 1226' are used to define a pattern of source/drain contact openings, which will be formed in the first interlayer dielectric layer 112 in the following steps. As shown in FIG. 4A, each first opening O11 has a length L11 in the direction Y and a width W11 in the direction X, and the length L11 is greater than the width W11. Therefore, the length of the subsequently formed source/drain contact opening in direction Y will be greater than the width in direction X, which will result in an increase in the source/drain contact area while preventing the source/drain contact from contacting the gate Stack 106, which will be discussed further below. In some embodiments, the width W11 is greater than about 10 nanometers (nm). If the width W11 is less than about 10 nanometers, the result of subsequent directional deposition and/or directional etching using directional ions may be unsatisfactory.

返回第1圖,方法M1接著進行到方框S104,使用三層光阻遮罩作為蝕刻遮罩來圖案化硬遮罩層,以形成穿過硬 遮罩層和三層光阻遮罩的底層的第二開口。參考第5A圖至第5C圖,在方框S104的一些實施例中,對硬遮罩層120執行圖案化製程,以將圖案化的頂部光阻層1226'中的第一開口O11的圖案轉移到硬遮罩層120,從而產生在硬遮罩層120'中的第二開口O12。在一些實施例中,圖案化製程包括一個或多個蝕刻製程,其中三層光阻遮罩122用作蝕刻遮罩。一種或多種蝕刻製程可包括非等向性濕式蝕刻製程、非等向性乾式蝕刻製程或以上之組合。在圖案化製程期間,可能消耗三層光阻遮罩122之圖案化的頂層1226'和中間層1224,並且在圖案化製程之後可以保留部分的底層1222。如此一來,圖案化製程亦在圖案化的硬遮罩層120'上方產生圖案化的底層1222'。在一些實施例中,圖案化的底層1222'和圖案化的硬遮罩層120'的組合的厚度在約20奈米至約150奈米的範圍內。如果圖案化的底層1222'和圖案化的硬遮罩層120'的組合的厚度在此範圍之外,則後續使用定向沉積及/或定向蝕刻的結果可能會不令人滿意。 Returning to FIG. 1, method M1 then proceeds to block S104, using a three-layer photoresist mask as an etch mask to pattern the hard mask layer to form a bottom layer that passes through the hard mask layer and the bottom layer of the three-layer photoresist mask Second opening. Referring to FIGS. 5A to 5C, in some embodiments of block S104, a patterning process is performed on the hard mask layer 120 to transfer the pattern of the first opening O11 in the patterned top photoresist layer 1226′ To the hard mask layer 120, thereby creating a second opening O12 in the hard mask layer 120'. In some embodiments, the patterning process includes one or more etching processes, wherein the three-layer photoresist mask 122 is used as an etching mask. The one or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof. During the patterning process, the patterned top layer 1226' and the middle layer 1224 of the three photoresist masks 122 may be consumed, and a portion of the bottom layer 1222 may be retained after the patterning process. As such, the patterning process also generates a patterned bottom layer 1222' above the patterned hard mask layer 120'. In some embodiments, the combined thickness of the patterned bottom layer 1222' and the patterned hard mask layer 120' is in the range of about 20 nanometers to about 150 nanometers. If the combined thickness of the patterned bottom layer 1222' and the patterned hard mask layer 120' is outside this range, the results of subsequent use of directional deposition and/or directional etching may be unsatisfactory.

因為使用圖案化的頂部光阻層1226'(如第4A圖所示)作為蝕刻遮罩執行圖案化製程,所以圖案化的底層1222'和圖案化的硬遮罩層120'繼承頂部光阻層1226中的圖案。如此一來,延伸穿過圖案化的底層1222'和圖案化的硬遮罩層120的第二開口O12可以具有與相應之圖案化的頂部光阻層1226'中的第一開口O11實質上相同的形狀、尺寸和間隔。例如,每個第二開口O12在方向Y上具有長度L12並且在方向X上具有寬度W12,並且長度L12大於寬度W12。垂直地在相應的源極 /汲極區域110上方的第二開口O12的圖案可以在以下步驟中轉移到下面的第一層間介電層112,因此第二開口O12可以用於限定在第一層間介電層112中的源極/汲極接觸開口的圖案。如此一來,隨後形成的源極/汲極接觸開口在方向Y上的長度將大於在方向X上的寬度。 Because the patterned process is performed using the patterned top photoresist layer 1226' (as shown in FIG. 4A) as an etch mask, the patterned bottom layer 1222' and the patterned hard mask layer 120' inherit the top photoresist layer The pattern in 1226. As such, the second opening O12 extending through the patterned bottom layer 1222' and the patterned hard mask layer 120 may have substantially the same as the first opening O11 in the corresponding patterned top photoresist layer 1226' Shape, size and spacing. For example, each second opening O12 has a length L12 in the direction Y and a width W12 in the direction X, and the length L12 is greater than the width W12. The pattern of the second opening O12 vertically above the corresponding source/drain region 110 can be transferred to the underlying first interlayer dielectric layer 112 in the following steps, so the second opening O12 can be used to define the first opening The pattern of source/drain contact openings in the interlayer dielectric layer 112. As a result, the length of the subsequently formed source/drain contact opening in direction Y will be greater than the width in direction X.

第二開口O12在方向Y上的長度L12與源極/汲極接觸面積正相關。換句話說,第二開口O12的長度L12越長,源極/汲極接觸面積越大。因此,可以使用一個或多個橫向蝕刻製程來在方向Y上延長第二開口O12。然而,如果圖案化的底層1222'和圖案化的硬遮罩層120'經歷一個或多個橫向蝕刻製程,則第二開口O12將在方向X和方向Y上不可避免地延長,這將導致第二開口O12的寬度W12增加,也可能在將延長的第二開口O12的圖案轉移到第一層間介電層112期間對沿方向X配置的閘極堆疊106造成損壞。因此,在本揭露的一些實施例中,在晶圓WA上進行在方向X上比在方向Y上具有更快沉積速率的定向沉積製程(方法M1的方框S105),接著是進行在方向Y上比在方向X上具有更快蝕刻速率的定向蝕刻製程(方法M1的方框S106)。以這種方式,第二開口O12可以在方向Y上延長但實質上不在方向X上延長(請參考以下更詳細的描述)。 The length L12 of the second opening O12 in the direction Y is positively related to the source/drain contact area. In other words, the longer the length L12 of the second opening O12, the larger the source/drain contact area. Therefore, one or more lateral etching processes may be used to extend the second opening O12 in the direction Y. However, if the patterned bottom layer 1222' and the patterned hard mask layer 120' undergo one or more lateral etching processes, the second opening O12 will inevitably extend in the direction X and the direction Y, which will cause the first The increase in the width W12 of the two openings O12 may also cause damage to the gate stack 106 disposed along the direction X during the transfer of the pattern of the extended second opening O12 to the first interlayer dielectric layer 112. Therefore, in some embodiments of the present disclosure, a directional deposition process having a faster deposition rate in the direction X than in the direction Y is performed on the wafer WA (block S105 of method M1), followed by the direction Y A directional etching process with a faster etching rate than in the direction X (block S106 of method M1). In this way, the second opening O12 may be extended in the direction Y but not substantially extended in the direction X (please refer to the more detailed description below).

返回第1圖,方法M1接著進行到方框S105,在第二開口的第一側壁上形成保護層。參考第6A圖至第6C圖,在方框S105的一些實施例中,執行定向沉積製程以在沿方向Y上延伸之第二開口O12'的第一側壁O121上形成保護層124,並 且實質上不在沿方向X延伸之第二開口O12'的第二側壁O122上形成保護層124。使用從電漿提取的定向離子執行定向沉積製程,並且相對於晶片表面的垂線以非零角度引導到晶圓WA(請參考以下更詳細的描述)。 Returning to FIG. 1, the method M1 then proceeds to block S105 to form a protective layer on the first sidewall of the second opening. Referring to FIGS. 6A to 6C, in some embodiments of block S105, a directional deposition process is performed to form a protective layer 124 on the first sidewall O121 of the second opening O12′ extending in the direction Y, and substantially The protective layer 124 is not formed on the second sidewall O122 of the second opening O12' extending in the direction X. The directional deposition process is performed using directional ions extracted from the plasma, and is directed to the wafer WA at a non-zero angle relative to the perpendicular to the wafer surface (please refer to the more detailed description below).

第38圖繪示根據本揭露的一些實施例中能夠執行定向沉積製程和定向蝕刻製程的電漿工具900的示意性側視圖的。電漿工具900包括電漿源902,電漿源902包括電漿腔體904以容納電漿906。電漿腔體904可以產生電漿906,然而應當理解,當提供給電漿腔體904電源和適當的氣態物質時,會產生電漿906。氣體源914連接到電漿源902,更具體地連接到電漿腔體904,以提供用於產生電漿906的氣態物質。在一些實施例中,氣體源914可代表多個獨立的氣體源。 FIG. 38 shows a schematic side view of a plasma tool 900 capable of performing a directional deposition process and a directional etching process according to some embodiments of the present disclosure. The plasma tool 900 includes a plasma source 902 that includes a plasma cavity 904 to accommodate the plasma 906. Plasma cavity 904 may generate plasma 906, however, it should be understood that when power is supplied to plasma cavity 904 and an appropriate gaseous substance, plasma 906 is generated. The gas source 914 is connected to the plasma source 902, more specifically to the plasma cavity 904, to provide a gaseous substance for generating the plasma 906. In some embodiments, the gas source 914 may represent multiple independent gas sources.

電漿源902或電漿工具900的其他元件也可以連接到幫浦(未示出),例如渦輪幫浦。產生電漿906的電漿源902可以是例如射頻電漿源、感應耦合電漿(inductively-coupled plasma,ICP)源、電容耦合電漿(capacitively-coupled plasma,CCP)源、間接加熱陰極(indirectly heated cathode,IHC)或其他合適的電漿源。在一些實施例中,電漿源902是射頻電漿源,其具有電源908和射頻電感器912以產生感應耦合電漿。在一些實施例中,外殼910包圍電漿源902。 The plasma source 902 or other elements of the plasma tool 900 may also be connected to a pump (not shown), such as a turbo pump. The plasma source 902 generating the plasma 906 may be, for example, a radio frequency plasma source, an inductively-coupled plasma (ICP) source, a capacitively-coupled plasma (CCP) source, or an indirectly heated cathode (indirectly heated) heated cathode, IHC) or other suitable plasma source. In some embodiments, the plasma source 902 is a radio frequency plasma source with a power source 908 and a radio frequency inductor 912 to generate inductively coupled plasma. In some embodiments, the housing 910 surrounds the plasma source 902.

與電漿腔體904相鄰的是製程腔體916,其在基板處理期間容納晶圓WA。提供提取板920以從電漿906提取離子922a和離子922b並將離子922a和離子922b引導到晶圓WA, 其中離子922a和離子922b具有不同的軌跡。進一步而言,提取板920具有提取孔930,其產生相對於晶圓WA的平面WAP(即,晶圓WA的頂面)的垂直線917形成入射角θ的離子922a和離子922b。以這種方式,提取板920可以產生離子分佈921(如第39圖所示),其具有以零度為中心的入射角的雙峰分佈(bimodal distribution),其中兩個峰(峰923和峰925)位於零度之相對的兩側。製程腔體916包括平臺926,平臺926被配置為支撐晶圓WA。平臺926可以連接到驅動機構927,使得平臺926可以沿方向X、方向Y和方向Z中的一個或多個方向移動,並且繞支撐平臺926的在方向Z上延伸的軸929旋轉。在一些實施例中,平臺926可以在方向X及/或方向Y上移動,使得晶圓WA相對於提取孔930進行掃描。在一些實施例中,提取孔930可以是延伸的提取孔,其在相對於方向X的方向Y上具有較長的尺寸。在此配置中,可以沿著方向X掃描晶圓WA,以便將整個晶圓WA暴露於從電漿906提取的離子922a和離子922b。在其他實施例中,提取孔可以具有不同的形狀,或者提取板可包括多個提取孔。 Adjacent to the plasma cavity 904 is a process cavity 916, which accommodates the wafer WA during substrate processing. An extraction plate 920 is provided to extract ions 922a and 922b from the plasma 906 and guide the ions 922a and 922b to the wafer WA, where the ions 922a and 922b have different trajectories. Further, the extraction plate 920 has an extraction hole 930 that generates ions 922a and 922b that form an incident angle θ with respect to a vertical line 917 of the plane WAP of the wafer WA (ie, the top surface of the wafer WA). In this way, the extraction plate 920 can produce an ion distribution 921 (as shown in FIG. 39), which has a bimodal distribution with an incident angle centered at zero degrees, of which two peaks (peak 923 and peak 925 ) Are located on opposite sides of zero degrees. The process cavity 916 includes a platform 926 that is configured to support the wafer WA. The platform 926 may be connected to the driving mechanism 927 so that the platform 926 can move in one or more of the direction X, the direction Y, and the direction Z, and rotate about an axis 929 that supports the platform 926 extending in the direction Z. In some embodiments, the platform 926 can be moved in the direction X and/or the direction Y so that the wafer WA is scanned relative to the extraction hole 930. In some embodiments, the extraction hole 930 may be an extended extraction hole, which has a longer dimension in the direction Y relative to the direction X. In this configuration, the wafer WA may be scanned along the direction X in order to expose the entire wafer WA to the ions 922a and 922b extracted from the plasma 906. In other embodiments, the extraction holes may have different shapes, or the extraction plate may include a plurality of extraction holes.

如第38圖所示,提取板920與提取孔930的定位可以產生具有曲率的電漿鞘邊界(plasma sheath boundary)932。在所描繪的實施例中,電漿鞘邊界932具有相對於晶圓WA的平面WAP(即,晶圓WA的頂面)與相對於提取板920的平面936的凹形形狀。此曲率導致在電漿鞘邊界932處從電漿906提取離子922a和離子922b,其中離子軌跡可能偏離相對於晶圓WA的平面WAP之垂直入射。透過改變電漿工具900的 電漿製程條件,可以改變電漿鞘邊界932的形狀和曲率,從而導致對離子軌跡的控制。這可以允許控制離子相對於待處理之晶圓WA上的特徵(例如,第5A圖至第5C圖所示之圖案化的硬遮罩層120'和圖案化的底層1222'中的第二開口O12)的方向性或入射角。 As shown in FIG. 38, the positioning of the extraction plate 920 and the extraction hole 930 can produce a plasma sheath boundary 932 having a curvature. In the depicted embodiment, the plasma sheath boundary 932 has a concave shape relative to the plane WAP of the wafer WA (ie, the top surface of the wafer WA) and the plane 936 relative to the extraction plate 920. This curvature results in the extraction of ions 922a and 922b from the plasma 906 at the plasma sheath boundary 932, where the ion trajectory may deviate from normal incidence of the plane WAP relative to the wafer WA. By changing the plasma process conditions of the plasma tool 900, the shape and curvature of the plasma sheath boundary 932 can be changed, resulting in control of the ion trajectory. This may allow control of ions relative to features on the wafer WA to be processed (eg, the second opening in the patterned hard mask layer 120' and the patterned bottom layer 1222' shown in FIGS. 5A-5C O12) directivity or angle of incidence.

如第38圖所示,可以向從電漿906提取的離子922a和離子922b提供特定的離子方向。離子922a和離子922b的方向性(例如,離子922a和離子922b相對於參考方向(例如,晶圓WA的垂直線)的入射角)可以透過使用諸如提取孔930的寬度、來自電漿源的射頻功率(即,電源908和射頻電感器912的組合)、來自氣體源914之氣體的氣體壓力、在電漿腔體904和晶圓WA之間施加的擷取電壓(例如,來自脈衝直流電偏壓源938的電壓)等等的參數來控制。離子可以以這樣的方式控制,使得離子軌跡在第38圖的方向X和方向Z上延伸,而實質上不在方向Y上延伸。這種離子方向性的控制因此有助於選擇性地處理(例如,形成聚合物或者蝕刻)晶圓WA上所需處理的表面,而實質上不處理其他表面。 As shown in FIG. 38, the ion 922a and the ion 922b extracted from the plasma 906 may be provided with a specific ion direction. The directivity of the ion 922a and the ion 922b (for example, the angle of incidence of the ion 922a and the ion 922b with respect to the reference direction (for example, the vertical line of the wafer WA)) can be transmitted using radio frequency from the plasma source such as the width of the extraction hole 930 Power (ie, the combination of power supply 908 and RF inductor 912), gas pressure of gas from gas source 914, extraction voltage applied between plasma chamber 904 and wafer WA (eg, from pulsed DC bias) The voltage of the source 938) and so on. The ions can be controlled in such a way that the ion trajectory extends in the direction X and the direction Z of FIG. 38, but does not substantially extend in the direction Y. This control of ion directivity therefore helps to selectively process (eg, form a polymer or etch) the surface on the wafer WA that needs to be processed, while not substantially processing other surfaces.

返回到第6A圖至第6C圖,可以使用定向離子(例如,如第38圖中所示的離子922a和離子922b)來執行定向沉積製程,從而導致在方向X上比在方向Y上具有更快的沉積速率,使得如第6A圖所示,方向Y側壁O121可以比方向X側壁O122有更多的聚合物沉積。進一步而言,離子可以被引導到第二開口O12'的第一側壁O121,而實質上不被引導到第二開口O12'的第二側壁O122。例如,方向X上的沉積速率與方向Y 上的沉積速率的比例在約10:1至約30:1的範圍內。在一些實施例中,選擇製程條件使得由離子產生的聚合現象較由離子引起的蝕刻現象佔主導性,使得離子922a和離子922b指向第二開口O12'的第一側壁O121但實質上不指向第二開口O12'的第二側壁O122處,這將導致聚合物沉積在第一側壁O121上,但實質上不沉積在第二側壁O122上。這些沉積的聚合物可稱為保護層(或聚合物層)124。 Returning to FIGS. 6A to 6C, directional ions (for example, ions 922a and 922b as shown in FIG. 38) may be used to perform a directional deposition process, resulting in a more directional X direction than a Y direction. The fast deposition rate allows the side wall O121 in direction Y to have more polymer deposited than the side wall O122 in direction X, as shown in FIG. 6A. Further, ions may be guided to the first side wall O121 of the second opening O12', but not substantially to the second side wall O122 of the second opening O12'. For example, the ratio of the deposition rate in direction X to the deposition rate in direction Y is in the range of about 10:1 to about 30:1. In some embodiments, the process conditions are selected so that the polymerization phenomenon caused by ions is more dominant than the etching phenomenon caused by ions, so that ions 922a and 922b are directed toward the first sidewall O121 of the second opening O12' but are not substantially directed toward the first At the second side wall O122 of the two openings O12', this will cause the polymer to be deposited on the first side wall O121, but not substantially deposited on the second side wall O122. These deposited polymers may be referred to as protective layers (or polymer layers) 124.

在一些實施例中,定向沉積製程的執行可以使用包括甲烷(CH4)、四氯化矽(SiCl4)、氧氣(O2)、氮氣(N2)、溴化氫(HBr)、三氯化硼(BCl3)或以上之組合的氣體,其中使用的製程氣體其壓力在約0.1mTorr至約20mTorr的範圍內,射頻功率在約100W至約2000W的範圍內,偏壓為約0至約5kV,體積流速在約1sccm至約100sccm範圍內。如果製程條件超出上述選定範圍,則定向沉積現象可能會不令人滿意。在使用包括甲烷(CH4)的氣體進行定向沉積製程的一些實施例中,所得的保護層124包括含碳聚合物。在使用包括四氯化矽(SiCl4)、三氯化硼(BCl3)或以上之組合的氣體進行定向沉積製程的一些實施例中,所得的保護層124包括含氯聚合物。在使用包括溴化氫(HBr)的氣體進行定向沉積製程的一些實施例中,所得的保護層124包括含溴聚合物。 In some embodiments, the directional deposition process may be performed using methane (CH 4 ), silicon tetrachloride (SiCl 4 ), oxygen (O 2 ), nitrogen (N 2 ), hydrogen bromide (HBr), trichloro Boron trioxide (BCl 3 ) or a combination of the above, wherein the process gas used has a pressure in the range of about 0.1 mTorr to about 20 mTorr, RF power in the range of about 100 W to about 2000 W, and a bias voltage of about 0 to about 5 kV, the volume flow rate is in the range of about 1 sccm to about 100 sccm. If the process conditions exceed the above-mentioned selected range, the directional deposition phenomenon may be unsatisfactory. In some embodiments where a gas including methane (CH 4 ) is used for the directional deposition process, the resulting protective layer 124 includes a carbon-containing polymer. In some embodiments where a gas including silicon tetrachloride (SiCl 4 ), boron trichloride (BCl 3 ), or a combination thereof is used for the directional deposition process, the resulting protective layer 124 includes a chlorine-containing polymer. In some embodiments where a gas including hydrogen bromide (HBr) is used for the directional deposition process, the resulting protective layer 124 includes a bromine-containing polymer.

由於定向沉積,第二開口O12'在方向Y上的長度L12'保持與第二開口O12的長度L12實質上相同(如第5A圖所示),但第二開口O12'在方向X上的寬度W12'小於第二開口O12的寬度W12。定向沉積之後第二開口O12'的寬度W12'與 定向沉積之前第二開口O12的寬度W12之間的差異實質上是保護層124的厚度的兩倍。在一些實施例中,定向沉積導致在圖案化的底層1222'的頂面上方沉積聚合物,使得保護層124在圖案化的底層1222'的頂面上延伸。在一些實施例中,由於定向離子的傾斜軌跡造成的遮蔽效應(shadowing effect),第二開口O12'底部的第二蝕刻停止層118可能不受保護層124(即,聚合物)的覆蓋。 Due to the directional deposition, the length L12' of the second opening O12' in the direction Y remains substantially the same as the length L12 of the second opening O12 (as shown in FIG. 5A), but the width of the second opening O12' in the direction X W12' is smaller than the width W12 of the second opening O12. The difference between the width W12' of the second opening O12' after directional deposition and the width W12 of the second opening O12 before directional deposition is substantially twice the thickness of the protective layer 124. In some embodiments, directional deposition results in the deposition of polymer above the top surface of the patterned bottom layer 1222', such that the protective layer 124 extends on the top surface of the patterned bottom layer 1222'. In some embodiments, the second etch stop layer 118 at the bottom of the second opening O12' may not be covered by the protective layer 124 (ie, polymer) due to the shadowing effect caused by the inclined trajectories of directional ions.

返回第1圖,方法M1然後進行到方框S106,蝕刻第二開口的第二側壁以延長第二開口。在方框S106的一些實施例中,在第二開口O12'的第二側壁O122上執行定向蝕刻製程,從而產生如第7A圖至第7C圖所示之延長的開口O12"。使用定向離子執行定向蝕刻製程。例如,可以使用如第38圖所示的電漿工具900來執行定向蝕刻製程(請參考下面詳細的描述)。 Returning to FIG. 1, the method M1 then proceeds to block S106, and the second sidewall of the second opening is etched to extend the second opening. In some embodiments of block S106, a directional etching process is performed on the second sidewall O122 of the second opening O12', resulting in an elongated opening O12" as shown in FIGS. 7A to 7C. Performed using directional ions Directional etching process. For example, the plasma tool 900 shown in FIG. 38 may be used to perform the directional etching process (please refer to the detailed description below).

在電漿工具900中對晶圓WA執行定向沉積製程之後,晶圓WA可繞方向Z軸929旋轉約88度至約92度(例如,約90度)。以這種方式,第二開口O12'的第二側壁O122可以在第38圖中的方向X上排列。在旋轉晶圓WA之後,可以提取離子922a和離子922b並將其引導到晶圓WA。因為離子922a和離子922b的軌跡在第38圖中沿方向X和方向Z延伸但實質上不沿方向Y延伸,所以離子922a和離子922b可以指向第二開口O12'的第二側壁O122,而實質上不指向沿著第二開口O12'的第一側壁O121的保護層124。在一些實施例中,選擇製程條件使得由離子引起的蝕刻現象較由離子引起的聚合現象佔主 導性。因此,離子922a和離子922b可用於執行定向蝕刻製程,此定向蝕刻製程在第38圖中在方向X上具有比在方向Y上更快的蝕刻速率。例如,在方向X上的蝕刻速率與在方向Y上的蝕刻速率的比例在約10:1至約30:1的範圍內。因此,離子922a和離子922b可以指向第二開口O12'的第二側壁O122,但實質上不指向第二開口O12'的第一側壁O121,因此導致蝕刻第二側壁O122,但實質上不蝕刻沿著第一側壁O121的保護層124。以這種方式,定向蝕刻製程可以透過蝕刻第二側壁O122而實質上不蝕刻第一側壁O121來延長第二開口O12',從而產生如第7A圖至第7C圖所示之延長的開口O12"。 After performing the directional deposition process on the wafer WA in the plasma tool 900, the wafer WA may be rotated about the direction Z axis 929 by about 88 degrees to about 92 degrees (for example, about 90 degrees). In this way, the second side wall O122 of the second opening O12' may be arranged in the direction X in FIG. 38. After rotating the wafer WA, the ions 922a and 922b may be extracted and guided to the wafer WA. Since the trajectories of the ions 922a and 922b extend in the direction X and the direction Z in FIG. 38 but do not substantially extend in the direction Y, the ions 922a and 922b may point to the second side wall O122 of the second opening O12' The top does not point to the protective layer 124 along the first sidewall O121 of the second opening O12'. In some embodiments, the process conditions are selected so that the ion-induced etching phenomenon is more dominant than the ion-induced polymerization phenomenon. Therefore, ion 922a and ion 922b can be used to perform a directional etching process that has a faster etching rate in direction X than in direction Y in FIG. 38. For example, the ratio of the etching rate in the direction X to the etching rate in the direction Y is in the range of about 10:1 to about 30:1. Therefore, the ions 922a and 922b may point to the second side wall O122 of the second opening O12', but do not substantially point to the first side wall O121 of the second opening O12', thus causing the second side wall O122 to be etched, but not substantially along the edge The protective layer 124 of the first side wall O121. In this way, the directional etching process can extend the second opening O12' by etching the second side wall O122 without substantially etching the first side wall O121, resulting in an extended opening O12" as shown in FIGS. 7A to 7C .

在一些實施例中,保護層124對定向蝕刻製程的抗蝕刻性高於圖案化的底層1222'和圖案化的硬遮罩層120'的抗蝕刻性,使得保護層124可以保護第一側壁O121免受定向蝕刻製程。在一些實施例中,可以使用包括氟甲烷(CH3F)、三氟甲烷(CHF3)、甲烷(CH4)、四氟化碳(CF4)、二氟乙炔(C2F2)、二氧化硫(SO2)、六氟化硫(SF6)、氧氣(O2)、氮氣(N2)、三氟化氮(NF3)、氯氣(Cl2)、三氯化硼(BCl3)、四氯化矽(SiCl4)、溴化氫(HBr)、氦(He)、氬(Ar)、氪(Kr)或以上之組合的氣體來執行定向蝕刻製程,其中使用的製程氣體其壓力在約0.1mTorr至約10mTorr的範圍內,射頻功率在約100W至約2000W的範圍內,偏壓在約0至約10kV的範圍內,氣體流速在約1sccm至約100sccm的範圍內。如果製程條件超出所選範圍,則定向蝕刻現象可能會不令人滿意。定向蝕刻製程的製程氣體及/或其他 製程條件不同於定向沉積製程的製程氣體及/或其他製程條件。 In some embodiments, the etch resistance of the protection layer 124 to the directional etching process is higher than that of the patterned bottom layer 1222' and the patterned hard mask layer 120', so that the protection layer 124 can protect the first sidewall O121 Free from directional etching process. In some embodiments, fluoromethane (CH 3 F), trifluoromethane (CHF 3 ), methane (CH 4 ), carbon tetrafluoride (CF 4 ), difluoroacetylene (C 2 F 2 ), Sulfur dioxide (SO 2 ), sulfur hexafluoride (SF 6 ), oxygen (O 2 ), nitrogen (N 2 ), nitrogen trifluoride (NF 3 ), chlorine (Cl 2 ), boron trichloride (BCl 3 ) , Silicon tetrachloride (SiCl 4 ), hydrogen bromide (HBr), helium (He), argon (Ar), krypton (Kr) or a combination of the above gases to perform a directional etching process, wherein the pressure of the process gas used In the range of about 0.1 mTorr to about 10 mTorr, the RF power is in the range of about 100 W to about 2000 W, the bias voltage is in the range of about 0 to about 10 kV, and the gas flow rate is in the range of about 1 sccm to about 100 sccm. If the process conditions exceed the selected range, the directional etching phenomenon may be unsatisfactory. The process gas and/or other process conditions of the directional etching process are different from the process gas and/or other process conditions of the directional deposition process.

參照第7A圖,由於定向蝕刻,延長的開口O12'的長度L12"大於第二開口O12'的長度L12'(如第6A圖所示),但是延長的開口O12"的寬度W12"保持與第二開口O12'的寬度W12'實質上相同。因為延長的開口O12"具有增加的長度,所以隨後形成之繼承延長的開口O12"的圖案的源極/汲極接觸可以在方向Y上具有增加的長度,從而導致提升的源極/汲極接觸面積。此外,因為延長製程不會增加開口O12'的寬度,所以隨後形成之繼承延長的開口O12"的圖案的源極/汲極接觸將與閘極堆疊106分離,從而防止源極/汲極接觸和閘極堆疊106之間不想要的短路。所得的長度L12"與所得的寬度W12"的示例性比例在約2.7:1至約4.6:1的範圍內,其高於第4A圖所示之圖案化的光阻層1226'的長度L11和寬度W11的比例。 7A, due to directional etching, the length L12" of the extended opening O12' is greater than the length L12' of the second opening O12' (as shown in FIG. 6A), but the width W12" of the extended opening O12" remains the same as the first The width W12' of the two openings O12' is substantially the same. Because the extended opening O12" has an increased length, the subsequently formed source/drain contacts inheriting the pattern of the extended opening O12" may have an increased in direction Y Length, which results in an increased source/drain contact area. In addition, since the extension process does not increase the width of the opening O12', the source/drain contact that is subsequently formed to inherit the pattern of the extended opening O12" will be in contact with the gate The electrode stack 106 is separated, thereby preventing an unwanted short circuit between the source/drain contact and the gate stack 106. An exemplary ratio of the resulting length L12" to the resulting width W12" is in the range of about 2.7:1 to about 4.6:1, which is higher than the length L11 of the patterned photoresist layer 1226' shown in FIG. 4A and The ratio of the width W11.

在一些實施例中,可以利用方框S105的定向沉積製程原位執行方框S106的定向蝕刻製程,這將防止晶圓WA的污染。如本文所用,術語「原位」用於描述在裝置或基板仍保留在製程系統(例如,包括晶片裝載/卸載腔體(load lock chamber)、晶片傳送腔體(transfer chamber)、處理腔體或任何其他流體耦合腔體(fluidly coupled chamber))內時執行的製程,例如,製程系統允許基板保持在真空條件下。因此,術語「原位」通常也可用於表示在不暴露於外部環境(例如,製程系統外部)的情況下處理裝置或基板的製程。例如, 如第38圖所示,在電漿工具900中進行方框S105的定向沉積製成,然後使用驅動機構927使電漿工具900中的晶圓WA繞軸929旋轉。之後,在電漿工具900中執行方框S106的定向蝕刻製程。以這種方式,從方框S105到方框S106便不會發生破真空。 In some embodiments, the directional etching process of block S106 may be performed in situ using the directional deposition process of block S105, which will prevent contamination of the wafer WA. As used herein, the term "in situ" is used to describe a device or substrate that remains in the process system (eg, including a wafer load/unload chamber, a transfer chamber, a processing chamber, or Any other process performed in a fluidly coupled chamber, for example, the process system allows the substrate to be kept under vacuum. Therefore, the term "in situ" can also be used to refer to the process of processing a device or substrate without being exposed to an external environment (eg, outside the process system). For example, as shown in FIG. 38, the directional deposition of block S105 is performed in the plasma tool 900, and then the wafer WA in the plasma tool 900 is rotated around the axis 929 using the driving mechanism 927. Thereafter, the directional etching process of block S106 is performed in the plasma tool 900. In this way, no vacuum break occurs from block S105 to block S106.

返回第1圖,方法M1然後進行到方框S107,將延長的第二開口的圖案轉移到下面的層以形成源極/汲極接觸開口。參考第8A圖至第8C圖,在方框S104的一些實施例中,對在第二蝕刻停止層118、第二層間介電層116、第一蝕刻停止層114和第一層間介電層112執行圖案化製程,以將延長的開口O12"的圖案轉移到這些層,以在這些層中形成源極/汲極接觸開口O13並暴露源極/汲極區域110。在一些實施例中,圖案化製程包括一個或多個蝕刻製程,其中保護層124、圖案化的底層1222'和圖案化的硬遮罩層120'的組合作為蝕刻遮罩。一種或多種蝕刻製程可包括非等向性濕式蝕刻製程、非等向性乾式蝕刻製程或以上之組合。在圖案化製程期間,可能會消耗保護層124、圖案化的底層1222'和圖案化的硬遮罩層120'。在一些實施例中,可以使用合適的蝕刻劑去除保護層124、圖案化的底層1222'和圖案化的硬遮罩層120'的剩餘部分。 Returning to FIG. 1, the method M1 then proceeds to block S107, transferring the pattern of the extended second opening to the underlying layer to form the source/drain contact opening. Referring to FIGS. 8A to 8C, in some embodiments of block S104, for the second etch stop layer 118, the second interlayer dielectric layer 116, the first etch stop layer 114, and the first interlayer dielectric layer 112 performs a patterning process to transfer the pattern of elongated openings O12" to these layers to form source/drain contact openings O13 and expose source/drain regions 110. In some embodiments, The patterning process includes one or more etching processes, wherein the combination of the protective layer 124, the patterned bottom layer 1222', and the patterned hard mask layer 120' serves as an etching mask. One or more etching processes may include anisotropy Wet etching process, anisotropic dry etching process or a combination of the above. During the patterning process, the protective layer 124, the patterned bottom layer 1222' and the patterned hard mask layer 120' may be consumed. In some implementations For example, a suitable etchant may be used to remove the remaining portion of the protective layer 124, the patterned bottom layer 1222', and the patterned hard mask layer 120'.

由於圖案化製程,源極/汲極接觸開口O13繼承了延長的開口O12"的圖案(如第7A圖至第7C圖所示)。進一步而言,源極/汲極接觸開口O13的長度L13與延長的開口O12的長度L12"實質上相同,並且源極/汲極接觸開口O13的寬度W13與延長的開口O12"的寬度W12"實質上相同。如第8B圖 所示,控制源極/汲極接觸開口O13的寬度W13,使得沿著方向X配置在源極/汲極接觸開口O13的相對側上的閘極堆疊106不會被源極/汲極接觸開口O13暴露。這將有利於防止由圖案化製程中使用的蝕刻劑造成的閘極堆疊106的損壞。 Due to the patterning process, the source/drain contact opening O13 inherits the extended opening O12" pattern (as shown in FIGS. 7A to 7C). Further, the length L13 of the source/drain contact opening O13 The length L12" of the extended opening O12 is substantially the same, and the width W13 of the source/drain contact opening O13 is substantially the same as the width W12" of the extended opening O12". As shown in FIG. 8B, the width W13 of the source/drain contact opening O13 is controlled so that the gate stack 106 disposed on the opposite side of the source/drain contact opening O13 along the direction X is not affected by the source/ The drain contact opening O13 is exposed. This will help prevent damage to the gate stack 106 caused by the etchant used in the patterning process.

返回第1圖,方法M1然後進行到方框S108,其中使用導電材料填滿源極/汲極接觸開口。參考第9A圖至第9C圖,在方框S108的一些實施例中,一個或多個導電材料126沉積在晶圓WA上並且過填充源極/汲極接觸開口O13。一種或多種導電材料126包括,例如,任何合適的金屬(例如,鈷(Co)、鎢(W)、鈦(Ti)、鉭(Ta)、銅(Cu)、鋁(Al)及/或鎳(Ni)及/或鈦(Ti)或鉭(Ta)的氮化物)。 Returning to FIG. 1, the method M1 then proceeds to block S108, where the source/drain contact opening is filled with conductive material. Referring to FIGS. 9A to 9C, in some embodiments of block S108, one or more conductive materials 126 are deposited on the wafer WA and overfill the source/drain contact opening O13. The one or more conductive materials 126 include, for example, any suitable metal (eg, cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), and/or nickel (Ni) and/or titanium (Ti) or tantalum (Ta) nitride).

返回第1圖,方法M1然後進行到方框S109,其中平坦化導電材料以形成源極/汲極接觸。參考第10A圖至第10C圖,在方框S109的一些實施例中,執行化學機械平坦化製程以去除源極/汲極接觸開口O13外部的多餘導電材料126,直到到達第二層間介電層116。源極/汲極接觸開口O13中剩餘的導電材料126可以作為與相應的源極/汲極區域110接觸的源極/汲極接觸128。 Returning to FIG. 1, method M1 then proceeds to block S109, where the conductive material is planarized to form source/drain contacts. Referring to FIGS. 10A to 10C, in some embodiments of block S109, a chemical mechanical planarization process is performed to remove excess conductive material 126 outside the source/drain contact opening O13 until reaching the second interlayer dielectric layer 116. The conductive material 126 remaining in the source/drain contact opening O13 may serve as the source/drain contact 128 in contact with the corresponding source/drain region 110.

因為源極/汲極接觸開口O13填充有源極/汲極接觸128,所以源極/汲極接觸128繼承源極/汲極接觸開口O13的圖案(如第8A圖至第8C圖所示)。進一步而言,源極/汲極接觸128的長度L14與源極/汲極接觸開口O13的長度L13實質上相同,並且源極/汲極接觸128的寬度W14與源極/汲極接觸開口O13的寬度W13實質上相同。控制源極/汲極接觸128的寬度 W14,使得源極/汲極接觸128與閘極堆疊106分離,並且控制源極/汲極接觸128的長度L14,使得源極/汲極接觸128和源極/汲極區域110之間的接觸面積可以增加。 Since the source/drain contact opening O13 fills the source/drain contact 128, the source/drain contact 128 inherits the pattern of the source/drain contact opening O13 (as shown in FIGS. 8A to 8C) . Further, the length L14 of the source/drain contact 128 is substantially the same as the length L13 of the source/drain contact opening O13, and the width W14 of the source/drain contact 128 and the source/drain contact opening O13 The width W13 is substantially the same. The width W14 of the source/drain contact 128 is controlled so that the source/drain contact 128 is separated from the gate stack 106, and the length L14 of the source/drain contact 128 is controlled so that the source/drain contact 128 and the source The contact area between the pole/drain regions 110 can be increased.

用於形成延長的源極/汲極接觸所使用之如上所述的定向沉積製程和定向蝕刻製程亦可用於形成其他延長的特徵。例如,請參考第11A圖和第11B圖,其繪示方法M2,其中包括使用如上所述的定向沉積製程和定向蝕刻製程形成延長的閘極接觸和延長的源極/汲極通孔。第12A圖至第22D圖繪示根據本揭露的一些實施例之第11A圖和第11B圖的方法M2的各個階段的各種製程。在各種視圖和說明性實施例中,相同的附圖標記用於表示相同的元件。在第12A圖至第22D圖中,「A」圖(例如,第12A圖、第13A圖等)繪示俯視圖,「B」圖(例如,第12B圖、第13B圖等)繪示沿著對應於「A」圖中所示的線B-B的方向X的剖面圖,「C」圖(例如,第12C圖、第13C圖等)繪示沿著對應於「A」中所示的線C-C的方向Y的剖面圖,「D」圖(例如,第17D圖、第21D圖等)繪示沿著對應於「A」圖中所示的線D-D的方向Y的剖面圖。應當理解,可以在第12A圖至第22D圖所示的製程之前、期間和之後提供額外的步驟,並且可以替換或消除下面描述的一些步驟以作為對於此方法的其他實施例。步驟/製程的順序可以是可互換的。 The directional deposition process and directional etching process described above used to form the extended source/drain contacts can also be used to form other extended features. For example, please refer to FIGS. 11A and 11B, which illustrates a method M2, which includes using the directional deposition process and the directional etching process as described above to form an extended gate contact and an extended source/drain via. FIGS. 12A to 22D illustrate various processes at various stages of the method M2 of FIGS. 11A and 11B according to some embodiments of the present disclosure. In various views and illustrative embodiments, the same reference numerals are used to represent the same elements. In Figures 12A to 22D, "A" (eg, 12A, 13A, etc.) shows a top view, "B" (eg, 12B, 13B, etc.) shows along A cross-sectional view corresponding to the direction X of the line BB shown in the "A" drawing, and the "C" drawing (eg, FIG. 12C, FIG. 13C, etc.) is drawn along the line CC corresponding to the "A" The cross-sectional view in the direction Y of FIG. 3, the "D" drawing (for example, FIG. 17D, FIG. 21D, etc.) shows a cross-sectional view along the direction Y corresponding to the line DD shown in the "A" drawing. It should be understood that additional steps may be provided before, during, and after the processes shown in FIGS. 12A to 22D, and some of the steps described below may be replaced or eliminated as other embodiments for this method. The order of steps/processes can be interchangeable.

如第12A圖至第12C圖所示,半導體晶圓WA2在許多方面實質上類似於半導體晶圓WA,並且包括基板202、半導體鰭片204、淺溝槽隔離205、具有閘極介電層2062和金 屬層2064的閘極堆疊206、閘極間隔物208、源極/汲極區域210、第一層間介電層212、第一蝕刻停止層214和第二層間介電層216,每個實質上如上所述相對於基板102、半導體鰭片104、淺溝槽隔離105、具有閘極介電層1062和金屬層1064的閘極堆疊106、閘極間隔物108、源極/汲極區域110、第一層間介電層112、第一蝕刻停止層114和第二層間介電層116。半導體晶圓WA2還包括源極/汲極接觸228。在一些實施例中,使用如上關於源極/汲極接觸128所述之涉及定向沉積製程和定向蝕刻製程的延長製程形成源極/汲極接觸228。在一些其他實施例中,在不使用定向沉積製程和定向蝕刻製程的情況下形成源極/汲極接觸228,因此可以具有與源極/汲極接觸128不同的形狀。 As shown in FIGS. 12A to 12C, the semiconductor wafer WA2 is substantially similar to the semiconductor wafer WA in many respects, and includes a substrate 202, a semiconductor fin 204, a shallow trench isolation 205, and a gate dielectric layer 2062 And the gate stack 206 of the metal layer 2064, the gate spacer 208, the source/drain region 210, the first interlayer dielectric layer 212, the first etch stop layer 214, and the second interlayer dielectric layer 216, each Substantially as described above with respect to substrate 102, semiconductor fins 104, shallow trench isolation 105, gate stack 106 with gate dielectric layer 1062 and metal layer 1064, gate spacer 108, source/drain regions 110, a first interlayer dielectric layer 112, a first etch stop layer 114, and a second interlayer dielectric layer 116. The semiconductor wafer WA2 also includes source/drain contacts 228. In some embodiments, the source/drain contact 228 is formed using an extended process involving the directional deposition process and the directional etching process as described above with respect to the source/drain contact 128. In some other embodiments, the source/drain contact 228 is formed without using a directional deposition process and a directional etching process, and thus may have a different shape from the source/drain contact 128.

在方框S201中,使用合適的沉積技術依序在源極/汲極接觸228和第二層間介電層216上形成蝕刻停止層230和第三層間介電層232以及第一三層光阻遮罩234。在一些實施例中,蝕刻停止層230可以包括氮化物材料(例如,氮化矽、氮化鈦或類似物)並且可以使用諸如化學氣相沉積或物理氣相沉積的沉積製程來形成。第三層間介電層232可以使用例如化學氣相沉積、原子層沉積、旋塗玻璃(spin-on-glass,SOG)或其他合適的技術形成,並且包括與第一層間介電層212及/或第二層間介電層216相同的材料,因此,為簡潔起見,在此不再重複關於第三層間介電層232的描述。第一三層光阻遮罩234包括底層2342、中間層2344和頂層2346,分別類似於先前關於第3A圖至第3C圖討論之三層光阻遮罩122的底層 1222、中間層1224和頂層1226。因此,為了簡潔起見,在此不再重複關於底層2342、中間層2344和頂層2346的描述。 In block S201, an appropriate deposition technique is used to sequentially form an etch stop layer 230 and a third interlayer dielectric layer 232 and a first three-layer photoresist on the source/drain contact 228 and the second interlayer dielectric layer 216 Mask 234. In some embodiments, the etch stop layer 230 may include a nitride material (eg, silicon nitride, titanium nitride, or the like) and may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition. The third interlayer dielectric layer 232 can be formed using, for example, chemical vapor deposition, atomic layer deposition, spin-on-glass (SOG), or other suitable techniques, and includes the first interlayer dielectric layer 212 and /Or the second interlayer dielectric layer 216 is the same material, therefore, for the sake of brevity, the description about the third interlayer dielectric layer 232 will not be repeated here. The first three-layer photoresist mask 234 includes a bottom layer 2342, an intermediate layer 2344, and a top layer 2346, respectively similar to the bottom layer 1222, the middle layer 1224, and the top layer of the three-layer photoresist mask 122 previously discussed with respect to FIGS. 3A to 3C. 1226. Therefore, for the sake of brevity, the description about the bottom layer 2342, the middle layer 2344, and the top layer 2346 will not be repeated here.

在方框S202中,在頂層2346中和在閘極堆疊206上方形成第一開口O21。第一開口O21的形成包括曝光頂層2346並顯影頂層2346以移除部分的頂層(如前面參考第4A圖至第4C圖所討論的)。頂部光阻層2346中的第一開口O21用於限定在以下步驟中將形成在第二層間介電層216中的閘極接觸開口的圖案。如第12A圖所示,第一開口O21在方向Y上具有長度L21並且在方向X上具有寬度W21,並且長度L21大於寬度W21。因此,隨後形成的閘極接觸開口在方向Y上的長度將大於在方向X上的寬度,這將導致閘極接觸面積的增加,同時防止閘極接觸接觸源極/汲極接觸228,這將在下面進行更詳細地討論。 In block S202, a first opening O21 is formed in the top layer 2346 and above the gate stack 206. The formation of the first opening O21 includes exposing the top layer 2346 and developing the top layer 2346 to remove part of the top layer (as previously discussed with reference to FIGS. 4A to 4C). The first opening O21 in the top photoresist layer 2346 is used to define the pattern of the gate contact opening to be formed in the second interlayer dielectric layer 216 in the following steps. As shown in FIG. 12A, the first opening O21 has a length L21 in the direction Y and a width W21 in the direction X, and the length L21 is greater than the width W21. Therefore, the length of the subsequently formed gate contact opening in direction Y will be greater than the width in direction X, which will result in an increase in the gate contact area while preventing the gate contact from contacting the source/drain contact 228, which will This is discussed in more detail below.

返回第11A圖,方法M2接著進行到方框S203,使用第一三層光阻遮罩作為蝕刻遮罩來圖案化第三層間介電層以形成第二開口。參考第13A圖至第13C圖,在方框S203的一些實施例中,對第三層間介電層232執行圖案化製程,以將圖案化的頂部光阻層2346中的第一開口O21的圖案轉移至第三層間介電層232,從而產生在第三層間介電層232'中的第二開口O22。在一些實施例中,圖案化製程包括一個或多個蝕刻製程,其中三層光阻遮罩234作為蝕刻遮罩。一個或多個蝕刻製程可包括非等向性濕式蝕刻製程、非等向性乾式蝕刻製程或以上之組合。在圖案化製程期間,可能消耗光阻遮罩234之圖案化的頂層2346和中間層2344,並且在圖案化製程之後可以 保留部分的底層2342。以這種方式,圖案化製程也在圖案化的層間介電層232'上產生圖案化的底層2342'。 Returning to FIG. 11A, method M2 then proceeds to block S203, using the first three-layer photoresist mask as an etch mask to pattern the third interlayer dielectric layer to form a second opening. Referring to FIGS. 13A to 13C, in some embodiments of block S203, a patterning process is performed on the third interlayer dielectric layer 232 to pattern the first opening O21 in the patterned top photoresist layer 2346 Transferred to the third interlayer dielectric layer 232, thereby creating a second opening O22 in the third interlayer dielectric layer 232'. In some embodiments, the patterning process includes one or more etching processes, wherein the three-layer photoresist mask 234 serves as an etching mask. The one or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof. During the patterning process, the patterned top layer 2346 and the middle layer 2344 of the photoresist mask 234 may be consumed, and a portion of the bottom layer 2342 may be retained after the patterning process. In this way, the patterning process also creates a patterned bottom layer 2342' on the patterned interlayer dielectric layer 232'.

圖案化的底層2342'和圖案化的層間介電層232'繼承頂部光阻層2346中的圖案,因此第二開口O22具有與在圖案化的頂部光阻層2346中的第一開口O21實質上相同的形狀、尺寸和位置。例如,第二開口O22在方向Y上具有長度L22,在方向X上具有寬度W22,並且長度L22大於寬度W22。垂直在閘極堆疊206上方的第二開口O22的圖案可以在以下步驟中轉移到下面的第二層間介電層216,因此第二開口O22可以用於限定第二層間介電層216中的閘極接觸開口的圖案。以這種方式,隨後形成之閘極接觸開口在方向Y上的長度將大於在方向X上的寬度。 The patterned bottom layer 2342' and the patterned interlayer dielectric layer 232' inherit the pattern in the top photoresist layer 2346, so the second opening O22 has substantially the same as the first opening O21 in the patterned top photoresist layer 2346 Same shape, size and location. For example, the second opening O22 has a length L22 in the direction Y, a width W22 in the direction X, and the length L22 is greater than the width W22. The pattern of the second opening O22 perpendicular to the gate stack 206 can be transferred to the underlying second interlayer dielectric layer 216 in the following steps, so the second opening O22 can be used to define the gate in the second interlayer dielectric layer 216 The pattern of the pole contact opening. In this way, the length of the subsequently formed gate contact opening in direction Y will be greater than the width in direction X.

第二開口O22在方向Y上的長度L22與閘極接觸面積正相關。換句話說,第二開口O22的長度L22越大,閘極接觸面積越大。因此,可以使用一個或多個橫向蝕刻製程來在方向Y上延長第二開口O22。然而,如果圖案化的底層2342'和第三層間介電層232'經歷一個或多個橫向蝕刻製程,則第二開口O22在方向X和方向Y上將不可避免地皆延長,這將導致第二開口O22的寬度W22的增加,其在將延長的第二開口O22的圖案轉移到第二層間介電層216的製程中,可能會對沿方向X配置的源極/汲極接觸228造成損壞。因此,在本揭露的一些實施例中,在晶圓WA2上執行在方向X上具有比在方向Y上更快的沉積速率的定向沉積製程(方法M2的方框S204),接著執行在方向Y上具有比在方向X上更快的蝕刻速率的定向蝕刻 製程(方法M2的方框S205)。以這種方式,第二開口O22可以在方向Y上延長但實質上不在方向X上延長(請參考以下更詳細的描述)。 The length L22 of the second opening O22 in the direction Y is positively related to the gate contact area. In other words, the greater the length L22 of the second opening O22, the greater the gate contact area. Therefore, one or more lateral etching processes may be used to extend the second opening O22 in the direction Y. However, if the patterned bottom layer 2342' and the third interlayer dielectric layer 232' undergo one or more lateral etching processes, the second opening O22 will inevitably extend in both the direction X and the direction Y, which will cause the first The increase in the width W22 of the two openings O22 may cause damage to the source/drain contacts 228 arranged along the direction X during the process of transferring the pattern of the extended second opening O22 to the second interlayer dielectric layer 216 . Therefore, in some embodiments of the present disclosure, a directional deposition process having a faster deposition rate in direction X than in direction Y is performed on wafer WA2 (block S204 of method M2), and then performed in direction Y A directional etching process with a faster etching rate than in the direction X (block S205 of method M2). In this way, the second opening O22 may be extended in the direction Y but not substantially extended in the direction X (please refer to the more detailed description below).

參考第14A圖至第14C圖,在方框S204的一些實施例中,執行定向沉積製程以在沿方向Y延伸之第二開口O22'的第一側壁O221上形成保護層236,並且實質上不在沿方向X延伸之第二開口O22'的第二側壁O222上形成保護層236。使用定向離子進行定向沉積製程,從而在方向X上產生比在方向Y上更快的沉積速率,使得如第14A圖中所示的方向Y側壁O221可以比如第14A圖中所示的方向X側壁O222沉積更多聚合物(例如,含碳聚合物、含氯聚合物及/或含溴聚合物)。在一些實施例中,方向X上的沉積速率與方向Y上的沉積速率的比例在約10:1至約30:1的範圍內。 Referring to FIGS. 14A to 14C, in some embodiments of block S204, a directional deposition process is performed to form a protective layer 236 on the first sidewall O221 of the second opening O22′ extending in the direction Y, and is not substantially in A protective layer 236 is formed on the second sidewall O222 of the second opening O22' extending in the direction X. The directional deposition process using directional ions produces a faster deposition rate in direction X than in direction Y, so that the side wall O221 of direction Y as shown in FIG. 14A can be the side wall of direction X shown in FIG. 14A O222 deposits more polymers (eg, carbon-containing polymers, chlorine-containing polymers, and/or bromine-containing polymers). In some embodiments, the ratio of the deposition rate in direction X to the deposition rate in direction Y is in the range of about 10:1 to about 30:1.

可以使用例如如第38圖所示的電漿工具900來執行定向沉積製程。進一步而言,可以提取離子922a和離子922b並將其引導到晶圓WA2。如前所述,在第38圖中,因為離子922a和離子922b的軌跡可以被控制為在方向X和方向Z上延伸,而實質上不在方向Y上延伸,所以離子922a和離子922b可以指向第一側壁O221,而實質上不指向第二側壁O222。在一些實施例中,選擇製程條件使得由離子引起的聚合現象較由離子引起的蝕刻現象佔主導性,使得離子922a和離子922b指向第二開口O22'的第一側壁O221而實質上不指向第二開口O22'的第二側壁O222,因而導致聚合物沉積在第一側壁O221上,但實質上不會沉積在第二側壁O222上。這些沉積的聚合 物可以稱為保護層(或聚合物層)236。在一些實施例中,定向沉積製程的製程條件類似於先前關於第6A圖至第6C圖所討論的定向沉積製程的製程條件,因此,為簡潔起見,在此不再重複。 For example, the plasma tool 900 shown in FIG. 38 may be used to perform the directional deposition process. Further, the ions 922a and 922b can be extracted and guided to the wafer WA2. As described above, in FIG. 38, since the trajectories of the ion 922a and the ion 922b can be controlled to extend in the direction X and the direction Z, but not substantially extend in the direction Y, the ion 922a and the ion 922b can point to the One side wall O221 does not substantially point to the second side wall O222. In some embodiments, the process conditions are selected so that the polymerization phenomenon caused by ions is more dominant than the etching phenomenon caused by ions, so that ions 922a and 922b are directed toward the first sidewall O221 of the second opening O22' and are not substantially directed toward the first The second side wall O222 of the two openings O22' thus causes the polymer to be deposited on the first side wall O221, but is not substantially deposited on the second side wall O222. These deposited polymers may be referred to as protective layers (or polymer layers) 236. In some embodiments, the process conditions of the directional deposition process are similar to the process conditions of the directional deposition process previously discussed with respect to FIGS. 6A to 6C, so for the sake of brevity, they are not repeated here.

由於定向沉積,第二開口O22'在方向Y上的長度L22'保持與第二開口O22的長度L22(如第13A圖所示)實質上相同,並且第二開口O22'在方向X上的寬度W22'小於第二開口O22的寬度W22。定向沉積之後第二開口O22'的寬度W22'與定向沉積之前第二開口O22的寬度W22之間的差異實質上是保護層236的厚度的兩倍。在一些實施例中,定向沉積導致聚合物沉積在圖案化的底層2342'的頂面上方,使得保護層236在圖案化的底層2342'的頂面上延伸。在一些實施例中,由於定向離子的傾斜軌跡導致的遮蔽效應,第二開口O22'底部的蝕刻停止層230可能不受保護層236(即,聚合物)的覆蓋。 Due to the directional deposition, the length L22' of the second opening O22' in the direction Y remains substantially the same as the length L22 of the second opening O22 (as shown in FIG. 13A), and the width of the second opening O22' in the direction X W22' is smaller than the width W22 of the second opening O22. The difference between the width W22' of the second opening O22' after directional deposition and the width W22 of the second opening O22 before directional deposition is substantially twice the thickness of the protective layer 236. In some embodiments, the directional deposition results in the polymer being deposited over the top surface of the patterned bottom layer 2342' such that the protective layer 236 extends on the top surface of the patterned bottom layer 2342'. In some embodiments, the etch stop layer 230 at the bottom of the second opening O22' may not be covered by the protective layer 236 (ie, polymer) due to the shadowing effect caused by the inclined trajectory of directional ions.

返回第11A圖,方法M2接著進行到方框S205,蝕刻第二開口的第二側壁以延長第二開口。在方框S205的一些實施例中,在第二開口O22'的第二側壁O222上執行定向蝕刻製程,從而產生如第15A圖至第15C圖所示之延長的開口O12"。使用定向離子執行定向蝕刻製程。例如,如下面詳細描述的,可以使用如第38圖所示的電漿工具900來執行定向蝕刻製程。 Returning to FIG. 11A, method M2 then proceeds to block S205, where the second sidewall of the second opening is etched to extend the second opening. In some embodiments of block S205, a directional etching process is performed on the second sidewall O222 of the second opening O22', resulting in an extended opening O12" as shown in FIGS. 15A to 15C. Performed using directional ions Directional etching process. For example, as described in detail below, the plasma tool 900 shown in FIG. 38 may be used to perform the directional etching process.

在電漿工具900中對晶圓WA2執行定向沉積製程之後,晶圓WA2可繞方向Z軸929旋轉約88度至約92度(例如,約90度)。以這種方式,第二開口O22'的第二側壁O222 可以在第38圖中的方向X上排列。在旋轉晶圓WA之後,可以提取離子922a和離子922b並將其引導到晶圓WA2。因為離子922a和離子922b的軌跡在第38圖中沿方向X和方向Z延伸但實質上不沿方向Y延伸,所以離子922a和離子922b可以指向第二開口O22'的第二側壁O222,而實質上不指向沿第二開口O22'的第一側壁O221的保護層236。在一些實施例中,選擇製程條件使得由離子引起的蝕刻現象較由離子引起的聚合現象佔主導性。因此,離子922a和離子922b可用於執行定向蝕刻製程,此定向蝕刻製程在第38圖中在方向X上具有比在方向Y上更快的蝕刻速率。例如,在方向X上的蝕刻速率與在方向Y上的蝕刻速率的比例在約10:1至約30:1的範圍內。進一步而言,離子922a和離子922b可以指向第二開口O12'的第二側壁O222但是實質上不指向第二開口O12'的第一側壁O221,因此導致蝕刻第二側壁O222,而實質上不蝕刻沿第一側壁O221的保護層236。以這種方式,定向蝕刻製程可以透過蝕刻第二側壁O222而實質上不蝕刻第一側壁O221來延長第二開口O22',從而產生如第15A圖至第15C圖所示之延長的開口O12"。在一些實施例中,定向蝕刻製程的製程條件類似於先前關於第7A圖至第7C圖討論的定向蝕刻製程的製程條件,因此,為簡潔起見,在此不再重複。 After performing the directional deposition process on the wafer WA2 in the plasma tool 900, the wafer WA2 may be rotated about the direction Z axis 929 by about 88 degrees to about 92 degrees (for example, about 90 degrees). In this way, the second sidewall O222 of the second opening O22' may be arranged in the direction X in FIG. 38. After rotating the wafer WA, the ions 922a and 922b may be extracted and guided to the wafer WA2. Since the trajectories of the ions 922a and 922b extend in the direction X and the direction Z in FIG. 38 but do not substantially extend in the direction Y, the ions 922a and 922b may point to the second sidewall O222 of the second opening O22' The top does not point to the protective layer 236 along the first sidewall O221 of the second opening O22'. In some embodiments, the process conditions are selected so that the ion-induced etching phenomenon is more dominant than the ion-induced polymerization phenomenon. Therefore, ion 922a and ion 922b can be used to perform a directional etching process that has a faster etching rate in direction X than in direction Y in FIG. 38. For example, the ratio of the etching rate in the direction X to the etching rate in the direction Y is in the range of about 10:1 to about 30:1. Further, the ions 922a and 922b may point to the second side wall O222 of the second opening O12' but not substantially point to the first side wall O221 of the second opening O12', thus causing the second side wall O222 to be etched without being substantially etched The protective layer 236 along the first sidewall O221. In this way, the directional etching process can extend the second opening O22' by etching the second side wall O222 without substantially etching the first side wall O221, thereby creating an extended opening O12" as shown in FIGS. 15A to 15C In some embodiments, the process conditions of the directional etching process are similar to the process conditions of the directional etching process previously discussed with respect to FIGS. 7A to 7C, so for the sake of brevity, they are not repeated here.

參見第15A圖,作為定向蝕刻的結果,延長的開口O22"的長度L22"大於第二開口O22'的長度L22'(如第14A圖所示),並且,延長的開口O22"的寬度W22"與第二開口O22'的寬度W22'實質上相同。因為延長的開口O22"具有增加 的長度,所以隨後形成之繼承延長的開口O22"的圖案的閘極接觸可以在方向Y上具有增加的長度,從而導致閘極接觸面積的提升。此外,因為延長製程不會增加開口O22'的寬度,所以隨後形成之繼承延長的開口O22"的圖案的閘極接觸將與源極/汲極接觸228分離,從而防止閘極接觸和源極/汲極接觸228之間不希望的短路。所得的長度L22"與所得的寬度W22"的示例比例在約2.7:1至約4.6:1的範圍內。在一些實施例中,可以利用方框S204的定向沉積製程原位執行方框S205的定向蝕刻製程,以防止晶圓WA2的污染。 Referring to Fig. 15A, as a result of directional etching, the length L22" of the extended opening O22" is greater than the length L22' of the second opening O22' (as shown in Fig. 14A), and the width W22" of the extended opening O22" The width W22' of the second opening O22' is substantially the same. Because the extended opening O22" has an increased length, the gate contact formed subsequently to inherit the pattern of the extended opening O22" may have an increased length in the direction Y, resulting in an increase in the gate contact area. In addition, because the extension process does not increase the width of the opening O22', the gate contact formed subsequently to inherit the pattern of the extended opening O22" will be separated from the source/drain contact 228, thereby preventing the gate contact and the source/ An undesirable short circuit between drain contacts 228. An example ratio of the resulting length L22" to the resulting width W22" is in the range of about 2.7:1 to about 4.6:1. In some embodiments, block S204 may be utilized The directional deposition process of the in-situ process performs the directional etching process of block S205 to prevent contamination of the wafer WA2.

返回第11A圖,方法M2然後進行到方框S206,將延長的開口的圖案轉移到下面的層以形成閘極接觸開口。參考第16A圖至第16C圖,在方框S206的一些實施例中,對蝕刻停止層230、第二層間介電層216和第一蝕刻停止層114執行圖案化製程,以將延長的開口O22"的圖案轉移到這些層,以在這些層中產生閘極接觸開口O23並暴露閘極金屬層2064。在一些實施例中,圖案化製程包括一個或多個蝕刻製程,其中使用保護層236、圖案化的底層2342'和圖案化的層間介電層232'的組合作為蝕刻遮罩。一種或多種蝕刻製程可包括非等向性濕式蝕刻製程、非等向性乾式蝕刻製程或以上之組合。在圖案化製程期間,可能消耗圖案化的底層2342'。在一些實施例中,可以使用合適的蝕刻劑去除圖案化的底層2342'的剩餘部分。 Returning to FIG. 11A, method M2 then proceeds to block S206, transferring the pattern of the elongated opening to the underlying layer to form the gate contact opening. Referring to FIGS. 16A to 16C, in some embodiments of block S206, a patterning process is performed on the etch stop layer 230, the second interlayer dielectric layer 216, and the first etch stop layer 114 to extend the extended opening O22 The pattern of "is transferred to these layers to create gate contact openings O23 in these layers and expose the gate metal layer 2064. In some embodiments, the patterning process includes one or more etching processes, in which the protective layer 236, The combination of the patterned bottom layer 2342' and the patterned interlayer dielectric layer 232' serves as an etching mask. One or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof During the patterning process, the patterned bottom layer 2342' may be consumed. In some embodiments, a suitable etchant may be used to remove the remaining portion of the patterned bottom layer 2342'.

作為圖案化製程的結果,閘極接觸開口O23繼承了延長的開口O22"的圖案(如第15A圖至第15C圖所示)。進一步而言,閘極接觸開口O23的長度L23與延長的開口O22" 的長度L22"實質上相同,並且閘極接觸開口O23的寬度W23與延長的開口O22"的寬度W22"實質上相同。如第16B圖所示,控制閘極接觸開口O23的寬度W23,使得沿方向X配置在閘極接觸開口O23的相對側上的源極/汲極接觸228不會被閘極接觸開口O23暴露。這將防止源極/汲極接觸228免於受到由圖案化製程中使用的蝕刻劑而引起的損壞。 As a result of the patterning process, the gate contact opening O23 inherits the pattern of the extended opening O22" (as shown in FIGS. 15A to 15C). Further, the length L23 of the gate contact opening O23 and the extended opening The length L22" of O22" is substantially the same, and the width W23 of the gate contact opening O23 is substantially the same as the width W22" of the extended opening O22". As shown in FIG. 16B, the width W23 of the gate contact opening O23 is controlled, The source/drain contacts 228 arranged on opposite sides of the gate contact opening O23 in the direction X will not be exposed by the gate contact opening O23. This will prevent the source/drain contacts 228 from being subjected to the patterning process Damage caused by the etchant used.

在一些實施例中,圖案化的第三層間介電層232'保留在蝕刻停止層230上方,部分的保護層236保留在沿方向Y延伸之閘極接觸開口O23的第一側壁O231,並且沿方向X延伸的閘極接觸開口O23的第二側壁O232並沒有被保護層236覆蓋。 In some embodiments, the patterned third interlayer dielectric layer 232' remains above the etch stop layer 230, and a portion of the protective layer 236 remains on the first sidewall O231 of the gate contact opening O23 extending in the direction Y, and along The second sidewall O232 of the gate contact opening O23 extending in the direction X is not covered by the protective layer 236.

返回第11B圖,方法M2接著進行到方框S207,形成第二三層光阻遮罩以過填充閘極接觸開口。參考第17A圖至第17D圖,在晶圓WA2上形成第二三層光阻遮罩238,使得閘極接觸開口O23被第二三層光阻遮罩238的底層2382過填充。第二三層光阻遮罩238包括底層2382、中間層2384和頂層2386,其分別類似於先前關於第3A圖至第3C圖所討論的三層光阻遮罩122的底層1222、中間層1224和頂層1226。因此,為了簡潔起見,不再重複關於底層2382、中間層2384和頂層2386的描述。 Returning to FIG. 11B, method M2 then proceeds to block S207, forming a second three-layer photoresist mask to overfill the gate contact opening. Referring to FIGS. 17A to 17D, a second three-layer photoresist mask 238 is formed on the wafer WA2 so that the gate contact opening O23 is overfilled with the bottom layer 2382 of the second three-layer photoresist mask 238. The second three-layer photoresist mask 238 includes a bottom layer 2382, an intermediate layer 2384, and a top layer 2386, which are respectively similar to the bottom layer 1222 and the middle layer 1224 of the three-layer photoresist mask 122 previously discussed with respect to FIGS. 3A to 3C. And the top floor 1226. Therefore, for the sake of brevity, the description about the bottom layer 2382, the middle layer 2384, and the top layer 2386 is not repeated.

在方框S208中,在頂層2386中並且在源極/汲極接觸228上方形成第三開口O31。第三開口O31的形成包括曝光頂層2386並使頂層2386顯影以移除部分的頂層2386,如先前關於第4A圖至第4C圖所討論。在頂部光阻層2386中的第三 開口O31用於定義在後續步驟中將在圖案化的第三層間介電層232'中形成之源極/汲極通孔開口的圖案。如第17A圖所示,每個第三開口O31在方向Y上具有長度L31並且在方向X上具有寬度W31,並且長度L31大於寬度W31。因此,隨後形成的源極/汲極通孔開口在方向Y上的長度將大於在方向X上的寬度,這將導致源極/汲極通孔與源極/汲極接觸之間的接觸面積增加,同時防止接觸隨後將形成在閘極接觸開口O23中的閘極接觸,這將在下面更詳細地討論。 In block S208, a third opening O31 is formed in the top layer 2386 and above the source/drain contacts 228. The formation of the third opening O31 includes exposing the top layer 2386 and developing the top layer 2386 to remove a portion of the top layer 2386, as previously discussed with respect to FIGS. 4A to 4C. The third opening O31 in the top photoresist layer 2386 is used to define a pattern of source/drain via openings to be formed in the patterned third interlayer dielectric layer 232' in the subsequent steps. As shown in FIG. 17A, each third opening O31 has a length L31 in the direction Y and a width W31 in the direction X, and the length L31 is greater than the width W31. Therefore, the length of the subsequently formed source/drain via opening in direction Y will be greater than the width in direction X, which will result in the contact area between the source/drain via and the source/drain contact The increase, while preventing contact, will then form the gate contact in the gate contact opening O23, which will be discussed in more detail below.

返回第11B圖,方法M2接著進行到方框S209,使用第二三層光阻遮罩作為蝕刻遮罩來圖案化第三層間介電層以形成第四開口。參考第18A圖至第18C圖,在方框S203的一些實施例中,對第三層間介電層232'執行圖案化製程,以將圖案化的頂部光阻層2386中的第三開口O31的圖案轉移到第三層間介電層232'中,從而在第三層間介電層232"中產生第四開口O32。值得注意的是,第三層間介電層232'經歷兩個各別的圖案化製程,其中先前的圖案化製程用於形成閘極接觸開口,並且後面的圖案化製程用於形成源極/汲極通孔開口。在一些實施例中,圖案化製程包括一個或多個蝕刻製程,其中第二三層光阻遮罩238用作蝕刻遮罩。一種或多種蝕刻製程可包括非等向性濕式蝕刻製程、非等向性乾式蝕刻製程或以上之組合。在圖案化製程期間,可以消耗圖案化的頂層2386、光阻遮罩238的中間層2384,並且在圖案化製程之後可以保留部分的底層2382。以這種方式,圖案化製程還在圖案化的層間介電層232"上方產生圖案化的底層2382'。 Returning to FIG. 11B, method M2 then proceeds to block S209, using the second three-layer photoresist mask as an etch mask to pattern the third interlayer dielectric layer to form a fourth opening. Referring to FIGS. 18A to 18C, in some embodiments of block S203, a patterning process is performed on the third interlayer dielectric layer 232′ to remove the third opening O31 in the patterned top photoresist layer 2386 The pattern is transferred into the third interlayer dielectric layer 232', thereby creating a fourth opening O32 in the third interlayer dielectric layer 232". It is worth noting that the third interlayer dielectric layer 232' undergoes two separate patterns Process, where the previous patterning process is used to form the gate contact opening, and the subsequent patterning process is used to form the source/drain via opening. In some embodiments, the patterning process includes one or more etchings Process, in which the second and third photoresist masks 238 are used as etching masks. One or more etching processes may include anisotropic wet etching process, anisotropic dry etching process or a combination of the above. In the patterning process During this period, the patterned top layer 2386, the middle layer 2384 of the photoresist mask 238 can be consumed, and a portion of the bottom layer 2382 can be retained after the patterning process. In this way, the patterning process is still in the patterned interlayer dielectric layer A patterned bottom layer 2382' is created above 232".

圖案化的底層2382'和圖案化的層間介電層232"繼承頂部光阻層2386中的圖案,因此第四開口O32與在圖案化的頂部光阻層2386中的第三開口O31實質上具有相同的形狀、尺寸和位置。例如,第四開口O32在方向Y上具有長度L32並且在方向X上具有寬度W32,並且長度L32大於寬度W32。垂直在源極/汲極接觸228上方的第四開口O32的圖案可以在以下步驟中轉移到下面的蝕刻停止層230,因此第四開口O32可以用於定義源極/汲極通孔開口的圖案。以這種方式,隨後形成的源極/汲極通孔開口在方向Y上的長度將大於在方向X上的寬度。 The patterned bottom layer 2382' and the patterned interlayer dielectric layer 232" inherit the pattern in the top photoresist layer 2386, so the fourth opening O32 and the third opening O31 in the patterned top photoresist layer 2386 substantially have The same shape, size and position. For example, the fourth opening O32 has a length L32 in the direction Y and a width W32 in the direction X, and the length L32 is greater than the width W32. The fourth perpendicular to the source/drain contact 228 The pattern of the opening O32 can be transferred to the underlying etch stop layer 230 in the following steps, so the fourth opening O32 can be used to define the pattern of the source/drain via opening. In this way, the subsequently formed source/drain The length of the pole via opening in direction Y will be greater than the width in direction X.

第四開口O32在方向Y上的長度L32與隨後形成的源極/汲極通孔與源極/汲極接觸228之間的接觸面積成正相關。換句話說,第四開口O32的長度L32越大,隨後形成的源極/汲極通孔與源極/汲極接觸228之間的接觸面積也越大。因此,可以使用一個或多個橫向蝕刻製程以在方向Y上延長第四開口O32。然而,如果圖案化的底層2382'和圖案化的第三層間介電層232"經歷一個或多個橫向蝕刻製程,則第四開口O32將不可避免地在方向X和方向Y上延長,這將導致第四開口O32的寬度W32增加,這又可能導致隨後形成在閘極接觸開口O23中的源極/汲極通孔和閘極接觸之間的不希望的短路。因此,在本揭露的一些實施例中,對晶圓WA2執行在方向X上具有比在方向Y上更快的沉積速率的定向沉積製程(方法M2的方框S210),接著是執行在方向Y上具有比在方向X上更快的蝕刻速率的定向蝕刻製程(方法M2的方框S211)。以這種方 式,第四開口O32可以在方向Y上延長但實質上不在方向X上延長(請參考以下更詳細的描述)。 The length L32 of the fourth opening O32 in the direction Y is positively related to the contact area between the subsequently formed source/drain via and source/drain contact 228. In other words, the greater the length L32 of the fourth opening O32, the greater the contact area between the source/drain via and the source/drain contact 228 that are subsequently formed. Therefore, one or more lateral etching processes may be used to extend the fourth opening O32 in the direction Y. However, if the patterned bottom layer 2382' and the patterned third interlayer dielectric layer 232" undergo one or more lateral etching processes, the fourth opening O32 will inevitably extend in direction X and direction Y, which will This results in an increase in the width W32 of the fourth opening O32, which in turn may lead to an undesirable short circuit between the source/drain via and the gate contact subsequently formed in the gate contact opening O23. Therefore, some of the disclosure In an embodiment, a directional deposition process with a faster deposition rate in the direction X than in the direction Y is performed on the wafer WA2 (block S210 of the method M2), followed by performing in the direction Y with a faster deposition rate than in the direction X A faster etch rate directional etching process (block S211 of method M2). In this way, the fourth opening O32 can extend in the direction Y but not substantially extend in the direction X (please refer to the more detailed description below) .

參考第19A圖至第19C圖,在方框S210的一些實施例中,執行定向沉積製程以在沿方向Y延伸之第四開口O32'的第一側壁O321上形成保護層240,並且實質上不在沿方向X延伸之第四開口O32'的第二側壁O322上形成保護層240。使用定向離子進行定向沉積製程,因此導致在方向X上的沉積速率高於在方向Y上的沉積速率,使得如第19A圖所示之方向Y的側壁O321可以比如第19A圖所示之方向X的側壁O322沉積更多的聚合物(例如,含碳聚合物、含氯聚合物及/或含溴聚合物)。在一些實施例中,方向X上的沉積速率與方向Y上的沉積速率的比例在約10:1至約30:1的範圍內。 Referring to FIGS. 19A to 19C, in some embodiments of block S210, a directional deposition process is performed to form a protective layer 240 on the first sidewall O321 of the fourth opening O32′ extending in the direction Y, and is not substantially in A protective layer 240 is formed on the second sidewall O322 of the fourth opening O32' extending in the direction X. The use of directional ions for the directional deposition process results in a deposition rate in direction X that is higher than the deposition rate in direction Y, so that the side wall O321 in direction Y as shown in FIG. 19A can be like the direction X shown in FIG. 19A The side wall O322 deposits more polymer (eg, carbon-containing polymer, chlorine-containing polymer, and/or bromine-containing polymer). In some embodiments, the ratio of the deposition rate in direction X to the deposition rate in direction Y is in the range of about 10:1 to about 30:1.

可以使用例如如第38圖所示的電漿工具900來執行定向沉積製程。進一步而言,可以提取離子922a和離子922b並將其引導到晶圓WA2。因為如前所述,離子922a和離子922b的軌跡可以被控制為在第38圖中的方向X和方向Z上延伸但實質上不在方向Y上延伸,所以離子922a和離子922b可以指向第一側壁O321,而實質上不指向第二側壁O322。在一些實施例中,選擇製程條件使得由離子引起的聚合現象較由離子引起的蝕刻現象更佔主導性,使得離子922a和離子922b指向第四開口O32'的第一側壁O321,但實質上不指向第四開口O32'的第二側壁O322,這可以導致聚合物沉積在第一側壁O321上,但實質上不會沉積在第二側壁O322上。這些沉積的聚合物可以稱為保護層(或聚合物層)240。在一些實施例中,定向沉積 製程的製程條件類似於先前關於第6A圖至第6C圖所討論的定向沉積製程的製程條件,因此,為簡潔起見,在此不再重複。 For example, the plasma tool 900 shown in FIG. 38 may be used to perform the directional deposition process. Further, the ions 922a and 922b can be extracted and guided to the wafer WA2. Since the trajectory of the ion 922a and the ion 922b can be controlled to extend in the direction X and the direction Z in FIG. 38 but not substantially extend in the direction Y as described above, the ion 922a and the ion 922b can point to the first side wall O321, but does not substantially point to the second side wall O322. In some embodiments, the process conditions are selected so that the polymerization phenomenon caused by ions is more dominant than the etching phenomenon caused by ions, so that ions 922a and 922b are directed to the first sidewall O321 of the fourth opening O32', but are not substantially Pointing to the second side wall O322 of the fourth opening O32', this may cause the polymer to be deposited on the first side wall O321, but not substantially deposited on the second side wall O322. These deposited polymers may be referred to as protective layers (or polymer layers) 240. In some embodiments, the process conditions of the directional deposition process are similar to the process conditions of the directional deposition process previously discussed with respect to FIGS. 6A to 6C, so for the sake of brevity, they are not repeated here.

作為定向沉積的結果,第四開口O32'在方向Y上的長度L32'保持與第四開口O32的長度L32(如第18A圖所示)實質上相同,並且第四開口O32'在方向X上的寬度W32'小於第四開口O32的寬度W32。定向沉積之後第四開口O32'的寬度W32'與定向沉積之前第四開口O22的寬度W22之間的差異實質上是保護層240厚度的兩倍。在一些實施例中,定向沉積導致聚合物沉積在圖案化的底層2382'的頂面上方,使得保護層240在圖案化的底層2382'的頂面上延伸。在一些實施例中,由於定向離子的傾斜軌跡導致的遮蔽效應,第四開口O32'底部的蝕刻停止層230可能不受保護層240(即,聚合物)的覆蓋。 As a result of directional deposition, the length L32' of the fourth opening O32' in the direction Y remains substantially the same as the length L32 of the fourth opening O32 (as shown in FIG. 18A), and the fourth opening O32' in the direction X The width W32' is smaller than the width W32 of the fourth opening O32. The difference between the width W32' of the fourth opening O32' after directional deposition and the width W22 of the fourth opening O22 before directional deposition is substantially twice the thickness of the protective layer 240. In some embodiments, directional deposition causes polymer to be deposited over the top surface of the patterned bottom layer 2382', such that the protective layer 240 extends on the top surface of the patterned bottom layer 2382'. In some embodiments, the etch stop layer 230 at the bottom of the fourth opening O32' may not be covered by the protective layer 240 (ie, polymer) due to the shadowing effect caused by the inclined trajectory of the directional ions.

返回第11B圖,方法M2接著進行到方框S211,蝕刻第四開口的第二側壁以延長第四開口。在方框S211的一些實施例中,對第四開口O32'的第二側壁O322執行定向蝕刻製程,從而產生如第20A圖至第20C圖所示之延長的開口O32"。使用定向離子執行定向蝕刻製程。例如,可以使用如第38圖所示的電漿工具900來執行定向蝕刻製程(請參閱下面詳細的描述)。 Returning to FIG. 11B, the method M2 then proceeds to block S211, etching the second sidewall of the fourth opening to extend the fourth opening. In some embodiments of block S211, a directional etching process is performed on the second sidewall O322 of the fourth opening O32', resulting in an extended opening O32" as shown in FIGS. 20A to 20C. Orientation is performed using directional ions Etching process. For example, a plasma tool 900 as shown in FIG. 38 may be used to perform a directional etching process (please refer to the detailed description below).

在電漿工具900中對晶圓WA2執行定向沉積製程之後,晶圓WA2可繞方向Z軸929旋轉約88度至約92度(例如,約90度)。以這種方式,第四開口O32'的第二側壁O322可以在第38圖中的方向X上排列。在旋轉晶圓WA2之後,離子922a和離子922b可以被提取並被引導到晶圓WA2。因為離子 922a和離子922b的軌跡在第38圖中沿方向X和方向Z延伸但實質上不沿方向Y延伸,所以離子922a和離子922b可以指向第四開口O32'的第二側壁O322,而實質上不指向沿第四開口O32'的第一側壁O321的保護層240。在一些實施例中,選擇製程條件使得由離子引起的蝕刻現象較由離子引起的聚合現象更佔主導性。因此,離子922a和離子922b可用於執行定向蝕刻製程,此製程在第38圖中在方向X上具有比在方向Y上更快的蝕刻速率。例如,在方向X上的蝕刻速率與在方向Y上的蝕刻速率的比例在約10:1至約30:1的範圍內。進一步而言,離子922a和離子922b可以指向第四開口O32'的第二側壁O322,但實質上不指向第四開口O32'的第一側壁O321,因此導致蝕刻第二側壁O322但實質上不蝕刻沿第一側壁O321的保護層240。以這種方式,定向蝕刻製程可以透過蝕刻第二側壁O322而實質上不蝕刻第一側壁O321來延長第二開口O32',從而產生如第20A圖至第20C圖所示之延長的開口O32"。在一些實施例中,定向蝕刻製程的製程條件類似於先前關於第7A圖至第7C圖所討論的定向蝕刻製程的製程條件,因此,為簡潔起見,在此不再重複。 After performing the directional deposition process on the wafer WA2 in the plasma tool 900, the wafer WA2 may be rotated about the direction Z axis 929 by about 88 degrees to about 92 degrees (for example, about 90 degrees). In this way, the second side wall O322 of the fourth opening O32' may be arranged in the direction X in FIG. 38. After rotating the wafer WA2, the ions 922a and 922b may be extracted and guided to the wafer WA2. Since the trajectories of the ions 922a and 922b extend in the direction X and the direction Z in FIG. 38 but do not substantially extend in the direction Y, the ions 922a and 922b may point to the second side wall O322 of the fourth opening O32' The top does not point to the protective layer 240 along the first sidewall O321 of the fourth opening O32'. In some embodiments, the process conditions are selected so that the ion-induced etching phenomenon is more dominant than the ion-induced polymerization phenomenon. Therefore, ions 922a and 922b can be used to perform a directional etching process, which has a faster etching rate in direction X than in direction Y in FIG. 38. For example, the ratio of the etching rate in the direction X to the etching rate in the direction Y is in the range of about 10:1 to about 30:1. Further, the ions 922a and 922b may point to the second sidewall O322 of the fourth opening O32', but do not substantially point to the first sidewall O321 of the fourth opening O32', thus causing the second sidewall O322 to be etched but not substantially etched The protective layer 240 along the first sidewall O321. In this way, the directional etching process can extend the second opening O32' by etching the second side wall O322 without substantially etching the first side wall O321, thereby creating an extended opening O32" as shown in FIGS. 20A to 20C In some embodiments, the process conditions of the directional etching process are similar to the process conditions of the directional etching process previously discussed with respect to FIGS. 7A to 7C, so for the sake of brevity, they are not repeated here.

參照第20A圖,作為定向蝕刻的結果,延長的開口O32"的長度L32"大於第二開口O32'的長度L32'(如第14A圖所示),但是,延長的開口O32"的寬度W32"與第二開口O32'的寬度W32'實質上相同。因為延長的開口O32"具有增加的長度,所以隨後形成之繼承延長的開口O32"的圖案的源極/汲極通孔可以在方向Y上具有增加的長度,從而導致在隨後形 成的源極/汲極通孔和源極/汲極接觸228之間的接觸面積的提升。此外,因為延長製程不會增加開口O32'的寬度,所以隨後形成之繼承延長的開口O32"的圖案的源極/汲極通孔將與隨後形成在閘極接觸開口中的閘極接觸分開,從而防止閘極接觸和源極/汲極通孔之間不希望的短路。所得的長度L32"與所得的寬度W32"的示例比例在約2.7:1至約4.6:1的範圍內。在一些實施例中,可以利用方框S210的定向沉積製程原位執行方框S211的定向蝕刻製程,這將防止晶圓WA2的污染。 Referring to Fig. 20A, as a result of directional etching, the length L32" of the extended opening O32" is greater than the length L32' of the second opening O32' (as shown in Fig. 14A), but the width W32" of the extended opening O32" The width W32' of the second opening O32' is substantially the same. Because the extended opening O32" has an increased length, the subsequently formed source/drain vias that inherit the pattern of the extended opening O32" may have an increased length in the direction Y, resulting in the source/drain formed subsequently The contact area between the drain via and the source/drain contact 228 is increased. In addition, since the extension process does not increase the width of the opening O32', the subsequently formed source/drain vias inheriting the pattern of the extended opening O32" will be separated from the gate contact subsequently formed in the gate contact opening, This prevents an undesirable short circuit between the gate contact and the source/drain via. An example ratio of the resulting length L32" to the resulting width W32" is in the range of about 2.7:1 to about 4.6:1. In some In an embodiment, the directional deposition process of block S211 may be performed in situ using the directional deposition process of block S210, which will prevent contamination of the wafer WA2.

返回第11B圖,方法M2接著進行到方框S212,延長的開口的圖案被轉移到下面的層以形成源極/汲極通孔開口。參考第21A圖至第21D圖,在方框S212的一些實施例中,對蝕刻停止層230執行圖案化製程以將延長的開口O32"的圖案轉移到蝕刻停止層230,從而穿過蝕刻停止層230產生源極/汲極通孔開口O33,並且暴露源極/汲極接觸228。在一些實施例中,圖案化製程包括一個或多個蝕刻製程,其中保護層236、圖案化的底層2382'和圖案化的層間介電層232"的組合作為蝕刻遮罩。一種或多種蝕刻製程可包括非等向性濕式蝕刻製程、非等向性乾式蝕刻製程或以上之組合。在圖案化製程期間,可能消耗圖案化的底層2382'。在一些實施例中,可以使用合適的蝕刻劑去除圖案化的底層2382'的殘留物,使得閘極接觸開口O23和源極/汲極通孔開口O33皆被暴露。 Returning to FIG. 11B, method M2 then proceeds to block S212, and the pattern of the extended opening is transferred to the underlying layer to form the source/drain via opening. Referring to FIGS. 21A to 21D, in some embodiments of block S212, a patterning process is performed on the etch stop layer 230 to transfer the pattern of the extended opening O32″ to the etch stop layer 230, thereby passing through the etch stop layer 230 produces source/drain via openings O33 and exposes source/drain contacts 228. In some embodiments, the patterning process includes one or more etching processes, wherein the protective layer 236, the patterned bottom layer 2382' The combination with the patterned interlayer dielectric layer 232" acts as an etch mask. The one or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof. During the patterning process, the patterned bottom layer 2382' may be consumed. In some embodiments, a suitable etchant may be used to remove the residue of the patterned bottom layer 2382' so that both the gate contact opening O23 and the source/drain via opening O33 are exposed.

作為圖案化製程的結果,源極/汲極通孔開口O33繼承了延長的開口O32"的圖案(如第20A圖至第20C圖所示)。進一步而言,源極/汲極通孔開口O33的長度L33與延長 的開口O32"的長度L32"實質上相同,並且源極/汲極通孔開口O33的寬度W33實質上與延長的開口O32"的寬度W32"相同。如第21B圖所示,控制源極/汲極通孔開口O33的寬度W33和閘極接觸開口O23的寬度W23,使得源極/汲極通孔開口O33和閘極接觸開口O23透過圖案化的層間介電層232"彼此分開。這有利於防止隨後形成的源極/汲極通孔和閘極接觸之間的短路。 As a result of the patterning process, the source/drain via opening O33 inherits the extended opening O32" pattern (as shown in FIGS. 20A to 20C). Further, the source/drain via opening The length L33 of O33 is substantially the same as the length L32" of the extended opening O32", and the width W33 of the source/drain via opening O33 is substantially the same as the width W32" of the extended opening O32". As shown in FIG. 21B As shown, the width W33 of the source/drain via opening O33 and the width W23 of the gate contact opening O23 are controlled so that the source/drain via opening O33 and the gate contact opening O23 pass through the patterned interlayer dielectric layer 232 "Apart from each other. This helps prevent short circuits between the source/drain vias and gate contacts that are subsequently formed.

在一些實施例中,圖案化的第三層間介電層232"保留在蝕刻停止層230上方,部分的保護層240保留在沿方向Y延伸的源極/汲極通孔開口O33的第一側壁O331上,並且在方向X上延伸之源極/汲極通孔開口O33的第二側壁O332沒有被保護層240覆蓋。 In some embodiments, the patterned third interlayer dielectric layer 232" remains above the etch stop layer 230, and a portion of the protective layer 240 remains on the first sidewall of the source/drain via opening O33 extending in the direction Y On O331, and the second sidewall O332 of the source/drain via opening O33 extending in the direction X is not covered by the protective layer 240.

在方法M2的方框S213中(如第11B圖所示),使用合適的沉積技術,用導電材料填充閘極接觸開口O23和源極/汲極通孔開口O33。此後,在方框S214中,平坦化導電材料以在閘極接觸開口O23中形成閘極接觸242,並在源極/汲極通孔開口O33中形成源極/汲極通孔244。所得到的結構如第22A圖至第22D圖所示。閘極接觸242和源極/汲極通孔244的導電材料包括,例如,任何合適的金屬(例如,鈷(Co)、鎢(W)、鈦(Ti)、鉭(Ta)、銅(Cu)、鋁(Al)及/或鎳(Ni)及/或鈦(Ti)或鉭(Ta)的氮化物)。 In block S213 of method M2 (as shown in FIG. 11B), the gate contact opening O23 and the source/drain via opening O33 are filled with a conductive material using a suitable deposition technique. Thereafter, in block S214, the conductive material is planarized to form the gate contact 242 in the gate contact opening O23, and the source/drain via 244 is formed in the source/drain via opening O33. The resulting structure is shown in Figures 22A to 22D. The conductive material of the gate contact 242 and the source/drain via 244 includes, for example, any suitable metal (eg, cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu ), aluminum (Al) and/or nickel (Ni) and/or titanium (Ti) or tantalum (Ta) nitride).

閘極接觸242和源極/汲極通孔244分別繼承閘極接觸開口O23和源極/汲極通孔開口O33的圖案(如第21A圖至第21D圖所示)。因此,閘極接觸242的長度L24與閘極接觸 開口O23的長度L23實質上相同,閘極接觸242的寬度W24與閘極接觸開口O23的寬度W23實質上相同,源極/汲極通孔244的長度L34與源極/汲極通孔開口O33的長度L33實質上相同,源極/汲極通孔244的寬度W34與源極/汲極通孔開口O33的寬度W33實質上相同。控制閘極接觸242的寬度W24和源極/汲極通孔244的寬度W34,使得閘極接觸242與源極/汲極通孔244分離。控制閘極接觸242的長度L24,使得閘極接觸242和閘極金屬層2064之間的接觸面積增加。控制源極/汲極通孔244的長度L34,使得源極/汲極通孔244與源極/汲極接觸228之間的接觸面積增加。 The gate contact 242 and the source/drain via 244 inherit the patterns of the gate contact opening O23 and the source/drain via opening O33, respectively (as shown in FIGS. 21A to 21D). Therefore, the length L24 of the gate contact 242 is substantially the same as the length L23 of the gate contact opening O23, the width W24 of the gate contact 242 is substantially the same as the width W23 of the gate contact opening O23, and the source/drain via 244 The length L34 is substantially the same as the length L33 of the source/drain via opening O33, and the width W34 of the source/drain via 244 is substantially the same as the width W33 of the source/drain via opening O33. The width W24 of the gate contact 242 and the width W34 of the source/drain via 244 are controlled so that the gate contact 242 is separated from the source/drain via 244. The length L24 of the gate contact 242 is controlled so that the contact area between the gate contact 242 and the gate metal layer 2064 increases. The length L34 of the source/drain via 244 is controlled so that the contact area between the source/drain via 244 and the source/drain contact 228 increases.

在一些實施例中,閘極接觸242包括實質上沿方向Y延伸之相對的第一側壁2421和實質上沿方向X延伸之相對的第二側壁2422。保護層236(例如,聚合物層)保留在第一側壁2421上並與第二側壁2422分離。類似地,源極/汲極通孔244包括實質上沿方向Y延伸之相對的第一側壁2441和實質上沿方向X上延伸之相對的第二側壁2442。保護層240(例如,聚合物層)保留在第一側壁2441上並與第二側壁2442分離。更具體地,閘極接觸242和源極/汲極通孔244在方向Y上的側壁部分地被聚合物覆蓋,但是閘極接觸242和源極/汲極通孔244在方向X上的側壁則沒有被聚合物覆蓋。 In some embodiments, the gate contact 242 includes opposing first side walls 2421 extending substantially in the direction Y and opposing second side walls 2422 extending substantially in the direction X. The protective layer 236 (eg, polymer layer) remains on the first side wall 2421 and is separated from the second side wall 2422. Similarly, the source/drain via 244 includes opposing first side walls 2441 extending substantially in the direction Y and opposing second side walls 2442 extending substantially in the direction X. The protective layer 240 (eg, polymer layer) remains on the first side wall 2441 and is separated from the second side wall 2442. More specifically, the sidewalls of the gate contact 242 and the source/drain via 244 in direction Y are partially covered by the polymer, but the sidewalls of the gate contact 242 and the source/drain via 244 in direction X Is not covered by polymer.

第23圖繪示方法M3,其包括形成延長的通孔,此延長的通孔用於使閘極堆疊和源極/汲極接觸短路。第24A圖至第29B圖繪示根據本揭露的一些實施例中,第23圖的方法M3的各個階段的各種製程。在各種視圖和說明性實施例中, 相同的附圖標記用於表示相同的元件。在第24A圖至第29B圖中,「A」圖(例如,第24A圖、第25A圖等)繪示沿方向X的剖面圖,並且「B」圖(例如,第24B圖、第25B圖等)繪示沿方向Y的另一剖面圖。應當理解,可以在第24A圖至第29B圖所示的製程之前、期間和之後提供額外步驟,並且對於此方法的其他實施例,可以替換或消除下面描述的一些步驟。步驟/製程的順序可以是可互換的。 FIG. 23 illustrates a method M3, which includes forming an elongated through hole for shorting the gate stack and source/drain contacts. FIGS. 24A to 29B illustrate various processes at various stages of the method M3 of FIG. 23 according to some embodiments of the present disclosure. In various views and illustrative embodiments, the same reference numerals are used to represent the same elements. In FIGS. 24A to 29B, “A” (for example, FIGS. 24A, 25A, etc.) shows a cross-sectional view along the direction X, and “B” (for example, FIGS. 24B, 25B Etc.) shows another cross-sectional view along the direction Y. It should be understood that additional steps may be provided before, during, and after the process shown in FIGS. 24A to 29B, and for other embodiments of this method, some steps described below may be replaced or eliminated. The order of steps/processes can be interchangeable.

如第24A圖至第24B圖所示,半導體晶圓WA3實質上在許多方面類似於第17B圖和第17C圖中所示的半導體晶圓WA2,並且包括基板302、半導體鰭片304、淺溝槽隔離305、具有閘極介電層3062和金屬層3064的閘極堆疊306、閘極間隔物308、源極/汲極區域310、第一層間介電層312、第一蝕刻停止層314、第二層間介電層316、源極/汲極接觸328、蝕刻停止層330和第三層間介電層332,每個實質上如上所述相對於基板202、半導體鰭片204、淺溝槽隔離205、具有閘極介電層2062和金屬層2064的閘極堆疊206、閘極間隔物208、源極/汲極區域210、第一層間介電層212、第一蝕刻停止層214、第二層間介電層216、源極/汲極接觸228、蝕刻停止層230和第三層間介電層332。半導體晶圓WA2還包括閘極接觸開口O41,其可以使用例如如上面關於閘極接觸開口O23所述之涉及定向沉積製程和定向蝕刻製程的延長製程所形成。因此,由定向沉積製程產生的聚合物保留在閘極接觸開口O41的特定側壁上,並且可以稱為保護層(或聚合物層)336。在一些其他實施例中,閘極接觸開口O41在不使用定向沉積製程和定向 蝕刻製程的情況下形成,因此保護層336可能不存在於閘極接觸開口O41中。 As shown in FIGS. 24A to 24B, the semiconductor wafer WA3 is substantially similar to the semiconductor wafer WA2 shown in FIGS. 17B and 17C in many respects, and includes a substrate 302, a semiconductor fin 304, and a shallow trench Trench isolation 305, gate stack 306 with gate dielectric layer 3062 and metal layer 3064, gate spacer 308, source/drain region 310, first interlayer dielectric layer 312, first etch stop layer 314 , The second interlayer dielectric layer 316, the source/drain contact 328, the etch stop layer 330, and the third interlayer dielectric layer 332, each substantially relative to the substrate 202, the semiconductor fin 204, and the shallow trench as described above Isolation 205, gate stack 206 with gate dielectric layer 2062 and metal layer 2064, gate spacer 208, source/drain region 210, first interlayer dielectric layer 212, first etch stop layer 214, The second interlayer dielectric layer 216, the source/drain contact 228, the etch stop layer 230, and the third interlayer dielectric layer 332. The semiconductor wafer WA2 further includes a gate contact opening O41, which can be formed using, for example, an extended process involving the directional deposition process and the directional etching process as described above with respect to the gate contact opening O23. Therefore, the polymer produced by the directional deposition process remains on the specific sidewall of the gate contact opening O41, and may be referred to as a protective layer (or polymer layer) 336. In some other embodiments, the gate contact opening O41 is formed without using the directional deposition process and the directional etching process, so the protective layer 336 may not be present in the gate contact opening O41.

在方框S301中,在第三層間介電層332上和在閘極接觸開口O41中形成三層光阻遮罩340。三層光阻遮罩340包括底層3402、中間層3404和頂層3406,分別類似於先前關於第3A圖至第3C圖所述之三層光阻遮罩122的底層1222、中間層1224和頂層1226。因此,為了簡潔起見,不再重複關於底層3402、中間層3404和頂層3406的描述。閘極接觸開口O41以三層光阻遮罩340的底層3402過填充。 In block S301, a three-layer photoresist mask 340 is formed on the third interlayer dielectric layer 332 and in the gate contact opening O41. The three-layer photoresist mask 340 includes a bottom layer 3402, an intermediate layer 3404, and a top layer 3406, respectively similar to the bottom layer 1222, the middle layer 1224, and the top layer 1226 of the three-layer photoresist mask 122 previously described with respect to FIGS. 3A to 3C. . Therefore, for the sake of brevity, the description about the bottom layer 3402, the middle layer 3404, and the top layer 3406 will not be repeated. The gate contact opening O41 is overfilled with the bottom layer 3402 of the three-layer photoresist mask 340.

在方框S302中,在頂層3406中並且在源極/汲極接觸328和閘極接觸開口O41上方形成第一開口O51。第一開口O51的形成包括曝光頂層3406和顯影頂層3406以去除部分的頂層3406。第一開口O51在方向X上具有長度L51,在方向Y上具有寬度W51,並且長度L51大於寬度W51。 In block S302, a first opening O51 is formed in the top layer 3406 and above the source/drain contact 328 and the gate contact opening O41. The formation of the first opening O51 includes exposing the top layer 3406 and developing the top layer 3406 to remove a portion of the top layer 3406. The first opening O51 has a length L51 in the direction X, a width W51 in the direction Y, and the length L51 is greater than the width W51.

返回第23圖,方法M3接著進行到方框S303,其中使用三層光阻遮罩作為蝕刻遮罩來圖案化第三層間介電層以形成第二開口。參考第25A圖至第25B圖,在方框S303的一些實施例中,對第三層間介電層332執行圖案化製程,以將圖案化的頂部光阻層3406中的第一開口O51的圖案轉移到第三層間介電層332,從而在第三層間介電層332'中產生第二開口O52。在一些實施例中,圖案化製程包括一個或多個蝕刻製程,其中三層光阻遮罩340作為蝕刻遮罩。一個或多個蝕刻製程可包括非等向性濕式蝕刻製程,非等向性乾式蝕刻製程或以上之組合。在圖案化製程期間,可能消耗光阻遮罩234之圖案 化的頂層3406和中間層3404,並且在圖案化製程之後可以保留部分的底層3402。以這種方式,圖案化製程還在圖案化的層間介電層332'上產生圖案化的底層3402'。 Returning to FIG. 23, method M3 then proceeds to block S303, in which a third interlayer dielectric layer is patterned to form a second opening using a three-layer photoresist mask as an etch mask. Referring to FIGS. 25A to 25B, in some embodiments of block S303, a patterning process is performed on the third interlayer dielectric layer 332 to pattern the first opening O51 in the patterned top photoresist layer 3406 Transferred to the third interlayer dielectric layer 332, thereby creating a second opening O52 in the third interlayer dielectric layer 332'. In some embodiments, the patterning process includes one or more etching processes, wherein the three-layer photoresist mask 340 serves as an etching mask. The one or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof. During the patterning process, the patterned top layer 3406 and the middle layer 3404 of the photoresist mask 234 may be consumed, and a portion of the bottom layer 3402 may remain after the patterning process. In this way, the patterning process also creates a patterned bottom layer 3402' on the patterned interlayer dielectric layer 332'.

圖案化的底層3402'和圖案化的層間介電層332'繼承頂部光阻層3406中的圖案,因此第二開口O52與在圖案化的頂部光阻層3406中的第一開口O51具有實質上相同的形狀、尺寸和位置。例如,第二開口O52在方向X上具有長度L52並且在方向Y上具有寬度W52,並且長度L52大於寬度W52。 The patterned bottom layer 3402' and the patterned interlayer dielectric layer 332' inherit the pattern in the top photoresist layer 3406, so the second opening O52 and the first opening O51 in the patterned top photoresist layer 3406 have substantially Same shape, size and location. For example, the second opening O52 has a length L52 in the direction X and a width W52 in the direction Y, and the length L52 is greater than the width W52.

參考第26A圖至第26B圖,在方框S304的一些實施例中,執行定向沉積製程以在沿方向X上延伸(即,延伸進出第26B圖的頁面的平面的方向)的第二開口O52'的第二側壁O522上形成保護層342,並且實質上不在沿方向Y上延伸(即,延伸進出第26A圖的頁面的平面的方向)的第二開口O52'的第一側壁O521上形成保護層342。可以使用定向離子執行定向蝕刻製程,從而導致在方向Y上的沉積速率高於在方向X上的沉積速率,使得第二側壁O522可以比第一側壁O521沉積更多的聚合物(例如,含碳聚合物、含氯聚合物及/或含溴聚合物)。例如,方向Y上的沉積速率與方向X上的沉積速率的比例在約10:1至約30:1的範圍內。 Referring to FIGS. 26A to 26B, in some embodiments of block S304, a directional deposition process is performed to extend in the second opening O52 in the direction X (ie, extending in and out of the plane of the page of FIG. 26B) A protective layer 342 is formed on the second side wall O522 of the', and substantially does not form a protection on the first side wall O521 of the second opening O52' extending in the direction Y (ie, extending in and out of the plane of the page of Fig. 26A) Floor 342. The directional etching process may be performed using directional ions, resulting in a deposition rate in direction Y that is higher than the deposition rate in direction X, so that the second sidewall O522 may deposit more polymer (eg, carbon-containing) than the first sidewall O521 Polymers, chlorine-containing polymers and/or bromine-containing polymers). For example, the ratio of the deposition rate in direction Y to the deposition rate in direction X is in the range of about 10:1 to about 30:1.

可以使用例如如第38圖所示的電漿工具900來執行定向沉積製程。進一步而言,可以提取離子922a和離子922b並將其引導到晶圓WA2。如前所述,可以控制離子922a和離子922b的軌跡使其在第38圖的方向X和方向Z上延伸,但實質上不在方向Y上延伸。因此,晶圓WA3可以被定向成使得離子 922a和離子922b可以指向第二側壁O522,而實質上不指向第一側壁O521。在一些實施例中,選擇製程條件使得由離子引起的聚合現象較由離子引起的蝕刻現象更具主導性,使得指向第二側壁O522但實質上不指向第一側壁O521的離子922a和離子922b可導致聚合物沉積在第二側壁O522上,但實質上不沉積在第一側壁O521上。這些沉積的聚合物可以稱為保護層(或聚合物層)342。在一些實施例中,定向沉積製程的製程條件類似於先前關於6A圖至第6C圖所討論的定向沉積製程的製程條件,因此,為簡潔起見,在此不再重複。 For example, the plasma tool 900 shown in FIG. 38 may be used to perform the directional deposition process. Further, the ions 922a and 922b can be extracted and guided to the wafer WA2. As described above, the trajectories of ions 922a and 922b can be controlled to extend in the direction X and the direction Z in FIG. 38, but they do not substantially extend in the direction Y. Therefore, the wafer WA3 may be oriented so that the ions 922a and 922b can be directed toward the second side wall O522, but not substantially toward the first side wall O521. In some embodiments, the process conditions are selected so that the polymerization phenomenon caused by ions is more dominant than the etching phenomenon caused by ions, so that ions 922a and 922b directed to the second sidewall O522 but not substantially directed to the first sidewall O521 may As a result, the polymer is deposited on the second side wall O522, but is not substantially deposited on the first side wall O521. These deposited polymers may be referred to as protective layers (or polymer layers) 342. In some embodiments, the process conditions of the directional deposition process are similar to the process conditions of the directional deposition process previously discussed with respect to FIGS. 6A to 6C, so for the sake of brevity, they are not repeated here.

作為定向沉積的結果,第二開口O52'在方向X上的長度L52'保持與第二開口O52的長度L52(如第24A圖所示)實質上相同,並且第二開口O52'在方向Y上的寬度W52'小於第二開口O52的寬度W52。定向沉積之後第二開口O52'的寬度W52'與定向沉積之前第二開口O52的寬度W52之間的差異實質上是保護層342厚度的兩倍。在一些實施例中,定向沉積導致聚合物沉積在圖案化的底層3402'的頂面上方,使得保護層342在圖案化的底層3402'的頂面上延伸。在一些實施例中,由於定向離子產生的遮蔽效應,第二開口O52'底部的蝕刻停止層330可能不受保護層342(即聚合物)的覆蓋。 As a result of directional deposition, the length L52' of the second opening O52' in the direction X remains substantially the same as the length L52 of the second opening O52 (as shown in FIG. 24A), and the second opening O52' in the direction Y The width W52' is smaller than the width W52 of the second opening O52. The difference between the width W52' of the second opening O52' after directional deposition and the width W52 of the second opening O52 before directional deposition is substantially twice the thickness of the protective layer 342. In some embodiments, the directional deposition causes the polymer to be deposited over the top surface of the patterned bottom layer 3402' such that the protective layer 342 extends on the top surface of the patterned bottom layer 3402'. In some embodiments, due to the shadowing effect generated by the directional ions, the etch stop layer 330 at the bottom of the second opening O52' may not be covered by the protective layer 342 (ie, polymer).

返回第23圖,方法M2接著進行到方框S305,其中蝕刻第二開口的第一側壁以延長第二開口。在方框S205的一些實施例中,對第二開口O52'的第一側壁O521執行定向蝕刻製程,從而產生延長的開口O52",如第27A圖至第27B圖所示。使用定向離子執行定向蝕刻製程。例如,如下面詳細描述 的,可以使用如第38圖所示的電漿工具900來執行定向蝕刻製程。 Returning to FIG. 23, the method M2 then proceeds to block S305, where the first sidewall of the second opening is etched to extend the second opening. In some embodiments of block S205, a directional etching process is performed on the first sidewall O521 of the second opening O52', resulting in an elongated opening O52", as shown in FIGS. 27A to 27B. Orientation is performed using directional ions Etching process. For example, as described in detail below, a plasma tool 900 as shown in FIG. 38 may be used to perform a directional etching process.

在對電漿工具900中的晶圓WA3執行定向沉積製程之後,晶圓WA3可以繞方向Z軸929旋轉大約88度至約92度(例如,大約90度)。此後,離子922a和離子922b可被提取並指向第二開口O52'的第一側壁O521,而實質上不指向沿第二開口O52'的第二側壁O522的保護層342。在一些實施例中,選擇製程條件使得由離子引起的蝕刻現象較由離子引起的聚合現象更佔主導性。因此,離子922a和離子922b可導致蝕刻第一側壁O521,但實質上不蝕刻沿第二側壁O522的保護層342。以這種方式,定向蝕刻製程可以透過蝕刻第一側壁O521而實質上不蝕刻第二側壁O522來延長第二開口O52',從而產生如第27A圖至第27B圖所示之延長的開口O52"。在一些實施例中,定向蝕刻製程的製程條件類似於先前關於第7A圖至第7C圖所討論的定向蝕刻製程的製程條件,因此,為簡潔起見,在此不再重複。 After performing the directional deposition process on the wafer WA3 in the plasma tool 900, the wafer WA3 may be rotated about the direction Z axis 929 by about 88 degrees to about 92 degrees (for example, about 90 degrees). Thereafter, the ions 922a and 922b may be extracted and directed toward the first sidewall O521 of the second opening O52', but not substantially directed toward the protective layer 342 along the second sidewall O522 of the second opening O52'. In some embodiments, the process conditions are selected so that the ion-induced etching phenomenon is more dominant than the ion-induced polymerization phenomenon. Therefore, the ions 922a and 922b may cause the first sidewall O521 to be etched, but the protective layer 342 along the second sidewall O522 is not substantially etched. In this way, the directional etching process can extend the second opening O52' by etching the first side wall O521 without substantially etching the second side wall O522, resulting in an extended opening O52" as shown in FIGS. 27A to 27B In some embodiments, the process conditions of the directional etching process are similar to the process conditions of the directional etching process previously discussed with respect to FIGS. 7A to 7C, so for the sake of brevity, they are not repeated here.

作為定向蝕刻的結果,延長的開口O52"的長度L52"大於第二開口O52'的長度L52'(如第26A圖所示),並且延長的開口O52"的寬度W52"與第二開口O52'的寬度W52'實質上相同。在一些實施例中,使用如前面第12A圖至第16C圖所討論的延長製程形成閘極接觸開口O41,閘極接觸開口O41的長度方向將平行於方向Y(即,延伸進出第27A圖的頁面的平面的方向),並因此垂直於延長的開口O52"的長度方向。所得的長度L52"與所得的寬度W52"的示例性比例在約 2.7:1至約4.6:1的範圍內。在一些實施例中,可以利用方框S304的定向沉積製程原位執行方框S305的定向蝕刻製程,這將防止晶圓WA3的污染。 As a result of directional etching, the length L52" of the extended opening O52" is greater than the length L52' of the second opening O52' (as shown in FIG. 26A), and the width W52" of the extended opening O52" and the second opening O52' The width W52' is substantially the same. In some embodiments, the gate contact opening O41 is formed using an extended process as previously discussed in FIGS. 12A to 16C. The length of the gate contact opening O41 will be parallel to the direction Y (ie, extending into and out of FIG. 27A The direction of the plane of the page), and therefore perpendicular to the length of the elongated opening O52". An exemplary ratio of the resulting length L52" to the resulting width W52" is in the range of about 2.7:1 to about 4.6:1. In some embodiments, the directional deposition process of block S305 may be performed in situ using the directional deposition process of block S304, which will prevent contamination of the wafer WA3.

返回第23圖,方法M2接著進行到方框S306,其中將延長的開口的圖案轉移到下面的層以形成通孔開口。參考第28A圖至第28B圖,在方框S306的一些實施例中,對蝕刻停止層330執行圖案化製程以將延長的開口O52"的圖案轉移到蝕刻停止層330,從而導致穿過蝕刻停止層330的通孔開口O53並暴露源極/汲極接觸328。在一些實施例中,圖案化製程包括一個或多個蝕刻製程,其中保護層342、圖案化的底層3402'和圖案化的層間介電層332的組合作為蝕刻遮罩。一種或多種蝕刻製程可包括非等向性濕式蝕刻製程、非等向性乾式蝕刻製程或以上之組合。在圖案化製程期間,可能消耗圖案化的底層3402'。在一些實施例中,可以使用合適的蝕刻劑去除圖案化的底層3402'的殘留物,使得閘極接觸開口O41和通孔開口O53都被暴露。閘極接觸開口O41從通孔開口O53的底部延伸到閘極金屬層3604。 Returning to FIG. 23, the method M2 then proceeds to block S306, where the pattern of the elongated opening is transferred to the underlying layer to form the via opening. Referring to FIGS. 28A to 28B, in some embodiments of block S306, a patterning process is performed on the etch stop layer 330 to transfer the pattern of the elongated opening O52″ to the etch stop layer 330, thereby causing the stop through the etch The via opening of the layer 330 is O53 and exposes the source/drain contact 328. In some embodiments, the patterning process includes one or more etching processes, wherein the protective layer 342, the patterned bottom layer 3402', and the patterned interlayer The combination of the dielectric layer 332 serves as an etching mask. One or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination of the above. During the patterning process, the patterned may be consumed The bottom layer 3402'. In some embodiments, a suitable etchant may be used to remove the residue of the patterned bottom layer 3402' so that both the gate contact opening O41 and the via opening O53 are exposed. The gate contact opening O41 is removed from the via The bottom of the opening O53 extends to the gate metal layer 3604.

作為圖案化製程的結果,通孔開口O53繼承了延長的開口O52"的圖案(如第27A圖至第27B圖所示)。進一步而言,通孔開口O53的長度L53與延長的開口O52"的長度L52"實質上相同,並且通孔開口O53的寬度W53與延長的開口O52"的寬度W52"實質上相同。 As a result of the patterning process, the via opening O53 inherits the pattern of the extended opening O52" (as shown in FIGS. 27A to 27B). Further, the length L53 of the via opening O53 and the extended opening O52" The length L52" is substantially the same, and the width W53 of the through-hole opening O53 is substantially the same as the width W52" of the elongated opening O52".

在一些實施例中,圖案化的第三層間介電層332'保留在蝕刻停止層330上方,部分的保護層342保留在沿方向X 上延伸(即,延伸進出第28B圖的頁面的平面的方向)的通孔開口O53的第二側壁O532上,並且在沿方向Y上延伸(即,延伸進出第28A圖的頁面的平面的方向)的通孔開口O53的第一側壁O531並未受到保護層342的覆蓋。 In some embodiments, the patterned third interlayer dielectric layer 332' remains above the etch stop layer 330, and a portion of the protective layer 342 remains extending in the direction X (ie, extending into and out of the plane of the page of FIG. 28B Direction) of the through-hole opening O53 on the second side wall O532, and the first side wall O531 of the through-hole opening O53 extending in the direction Y (ie, the direction extending into and out of the plane of the page of FIG. 28A) is not protected Coverage of layer 342.

此後,在方法M3(第23圖中所示)的方框S307中,在閘極接觸開口O41和通孔開口O53中形成導電通孔344,如第29A圖和第29B圖所示。導電通孔344的形成包括例如用導電材料過填充閘極接觸開口O41和通孔開口O53,然後執行化學機械平坦化製程以去除閘極接觸開口O41和通孔開口O53外部之多餘的導電材料。導電通孔344的導電材料包括,例如,任何合適的金屬(例如,鈷(Co)、鎢(W)、鈦(Ti)、鉭(Ta)、銅(Cu)、鋁(Al)及/或鎳(Ni)及/或鈦(Ti)或鉭(Ta)的氮化物)。 Thereafter, in block S307 of the method M3 (shown in FIG. 23), conductive vias 344 are formed in the gate contact opening O41 and the via opening O53, as shown in FIGS. 29A and 29B. The formation of the conductive via 344 includes, for example, overfilling the gate contact opening O41 and the via opening O53 with a conductive material, and then performing a chemical mechanical planarization process to remove excess conductive material outside the gate contact opening O41 and the via opening O53. The conductive material of the conductive via 344 includes, for example, any suitable metal (eg, cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), and/or Nickel (Ni) and/or titanium (Ti) or tantalum (Ta) nitride).

第30圖繪示方法M4,其包括閘極切割製程(或稱為切割金屬閘極製程),其涉及如前所述的定向沉積和定向蝕刻。第31A圖至第37D圖繪示根據本揭露的一些實施例中第30圖的方法M4的各個階段的各種製程。在各種視圖和說明性實施例中,相同的附圖標記用於表示相同的元件。第31A圖繪示立體圖,第31B圖繪示對應於第31A圖中的線B-B沿方向X的剖面圖,第31C圖繪示對應於第31A圖中的線C-C沿方向Y的剖面圖。在第32A圖至第37D圖中,「A」圖(例如,第32A圖、第33A圖等)繪示俯視圖,「B」圖(例如,第32B圖、第33B圖等)繪示對應於「A」圖中所示的線B-B沿方向X的剖面圖,「C」圖(例如,第32C圖、第33C圖等)繪示對應於 「A」中所示的線C-C沿著方向Y的剖面圖。「D」圖(例如,第36D圖、第37D圖)繪示對應於「A」圖中所示的線D-D沿方向Y的剖面圖。應當理解,可以在第31A圖至第37D圖所示的製程之前、期間和之後提供額外步驟,並且可以替換或消除下面描述的一些步驟以作為對於此方法的其他實施例。步驟/製程的順序可以是可互換的。 FIG. 30 illustrates a method M4, which includes a gate cutting process (or referred to as a cut metal gate process), which involves directional deposition and directional etching as described above. FIGS. 31A to 37D illustrate various processes at various stages of the method M4 of FIG. 30 in some embodiments of the present disclosure. In various views and illustrative embodiments, the same reference numerals are used to represent the same elements. FIG. 31A shows a perspective view, FIG. 31B shows a cross-sectional view corresponding to line B-B in FIG. 31A along direction X, and FIG. 31C shows a cross-sectional view corresponding to line C-C in FIG. 31A along direction Y. FIG. In Figures 32A to 37D, "A" (eg, 32A, 33A, etc.) shows a top view, and "B" (eg, 32B, 33B, etc.) shows the corresponding to A cross-sectional view of the line BB shown in the "A" diagram along the direction X, and a "C" figure (for example, FIG. 32C, FIG. 33C, etc.) plots corresponding to the line CC shown in "A" along the direction Y Section view. The "D" diagram (for example, the 36D and 37D diagrams) shows a cross-sectional view along the direction Y corresponding to the line D-D shown in the "A" diagram. It should be understood that additional steps may be provided before, during and after the processes shown in FIGS. 31A to 37D, and some steps described below may be replaced or eliminated as other embodiments for this method. The order of steps/processes can be interchangeable.

如第31A圖至第31C圖所示,半導體晶圓WA4在許多方面實質上類似於半導體晶圓WA,並且包括基板402、半導體鰭片404、淺溝槽隔離405、具有閘極介電層4062和金屬層4064的閘極堆疊406、閘極間隔物408、源極/汲極區域410和層間介電層412,每個實質上如上所述相對於基板102、半導體鰭片104、淺溝槽隔離105、具有閘極介電層1062和金屬層1064的閘極堆疊106、閘極間隔物108、源極/汲極區域110和第一層間介電層112。 As shown in FIGS. 31A to 31C, the semiconductor wafer WA4 is substantially similar to the semiconductor wafer WA in many respects, and includes a substrate 402, a semiconductor fin 404, a shallow trench isolation 405, and a gate dielectric layer 4062 And the metal layer 4064, the gate stack 406, the gate spacer 408, the source/drain region 410, and the interlayer dielectric layer 412, each substantially relative to the substrate 102, the semiconductor fin 104, and the shallow trench as described above Isolation 105, gate stack 106 with gate dielectric layer 1062 and metal layer 1064, gate spacer 108, source/drain region 110, and first interlayer dielectric layer 112.

在方框S401中,在閘極堆疊406和第一層間介電層112上依序形成蝕刻停止層414、硬遮罩層416和三層光阻遮罩418。在一些實施例中,蝕刻停止層414可以包括氮化鈦或類似物,並且可以使用諸如化學氣相沉積或物理氣相沉積的沉積製程來形成。在一些實施例中,硬遮罩層416可以包括氮化矽或類似物,並且可以使用諸如化學氣相沉積或物理氣相沉積的沉積製程來形成。三層光阻遮罩418包括底層4182、中間層4184和頂層4186,分別類似於先前關於第3A圖至第3C圖所討論的三層光阻遮罩122的底層1222、中間層1224和頂層1226。因此,為了簡潔起見,不再重複關於底層4182、中間 層4184和頂層4186的描述。 In block S401, an etch stop layer 414, a hard mask layer 416, and three photoresist masks 418 are sequentially formed on the gate stack 406 and the first interlayer dielectric layer 112. In some embodiments, the etch stop layer 414 may include titanium nitride or the like, and may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition. In some embodiments, the hard mask layer 416 may include silicon nitride or the like, and may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition. The three-layer photoresist mask 418 includes a bottom layer 4182, an intermediate layer 4184, and a top layer 4186, respectively similar to the bottom layer 1222, intermediate layer 1224, and top layer 1226 of the three-layer photoresist mask 122 previously discussed with respect to FIGS. 3A to 3C. . Therefore, for the sake of brevity, the description about the bottom layer 4182, the middle layer 4184, and the top layer 4186 will not be repeated.

方法M4接著進行到方框S402,其中第一開口形成在三層光阻遮罩的頂層中並橫跨一個或多個第一閘極堆疊。參考第32A圖至第32C圖所示,在方框S402的一些實施例中,第一開口O61形成在圖案化的頂層4186'中並跨越閘極堆疊406。第一開口O61的形成包括曝光頂層4186並顯影頂層4186以移除頂層4186的一部分,因此產生圖案化的頂層4186'。圖案化的頂部光阻層4186'中的第一開口O61用於定義閘極切割圖案(或閘極切割開口),這將在下面更詳細地描述。如第32A圖所示,第一開口O61在方向X上具有長度L61並且在方向Y上具有寬度W61,並且長度L61大於寬度W61。因此,隨後形成的閘極切割圖案將具有在方向X上的長度大於在方向Y上的寬度,這可以導致切割閘極的數量增加,同時防止在閘極切割製程期間損壞源極/汲極區域410,這將在下面進一步而言討論。 Method M4 then proceeds to block S402, where a first opening is formed in the top layer of the three-layer photoresist mask and spans one or more first gate stacks. Referring to FIGS. 32A to 32C, in some embodiments of block S402, a first opening O61 is formed in the patterned top layer 4186′ and spans the gate stack 406. The formation of the first opening O61 includes exposing the top layer 4186 and developing the top layer 4186 to remove a portion of the top layer 4186, thus creating a patterned top layer 4186'. The first opening O61 in the patterned top photoresist layer 4186' is used to define a gate cutting pattern (or gate cutting opening), which will be described in more detail below. As shown in FIG. 32A, the first opening O61 has a length L61 in the direction X and a width W61 in the direction Y, and the length L61 is greater than the width W61. Therefore, the subsequently formed gate cutting pattern will have a length in direction X greater than the width in direction Y, which may result in an increase in the number of cut gates while preventing damage to the source/drain regions during the gate cutting process 410, which will be discussed further below.

返回第30圖,方法M4接著進行到方框S403,其中使用三層光阻遮罩作為蝕刻遮罩來圖案化硬遮罩層以形成第二開口。參考第33A圖至第33C圖,在方框S403的一些實施例中,對硬遮罩層416執行圖案化製程,以將圖案化的頂部光阻層4186'中的第一開口O61的圖案轉移到硬遮罩層416中,從而在硬遮罩層416'中產生第二開口O62。在一些實施例中,圖案化製程包括一個或多個蝕刻製程,其中三層光阻遮罩418用作蝕刻遮罩。一種或多種蝕刻製程可包括非等向性濕式蝕刻製程、非等向性乾式蝕刻製程或以上之組合。在圖案化製程期 間,可以消耗光阻遮罩418的圖案化的頂層4186'和中間層4184,並且可以在圖案化製程之後保留部分的底層4182。以這種方式,圖案化製程還在圖案化的硬遮罩層416'上產生圖案化的底層4182'。 Returning to FIG. 30, method M4 then proceeds to block S403, where a three-layer photoresist mask is used as an etch mask to pattern the hard mask layer to form a second opening. Referring to FIGS. 33A to 33C, in some embodiments of block S403, a patterning process is performed on the hard mask layer 416 to transfer the pattern of the first opening O61 in the patterned top photoresist layer 4186′ Into the hard mask layer 416, thereby creating a second opening O62 in the hard mask layer 416'. In some embodiments, the patterning process includes one or more etching processes, in which the three-layer photoresist mask 418 is used as an etching mask. The one or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof. During the patterning process, the patterned top layer 4186' and the intermediate layer 4184 of the photoresist mask 418 may be consumed, and a portion of the bottom layer 4182 may remain after the patterning process. In this way, the patterning process also creates a patterned bottom layer 4182' on the patterned hard mask layer 416'.

圖案化的底層4182'和圖案化的硬遮罩層416'繼承頂部光阻層4186'中的圖案。如此一來,第二開口O62與圖案化的頂部光阻層4186'中的第一開口O61可以具有實質上相同的形狀、尺寸和位置。例如,第二開口O62在方向X上具有長度L62並且在方向Y上具有寬度W62,並且長度L62大於寬度W62。跨越閘極堆疊406的第二開口O62的圖案可用於定義在後續步驟中用於劃分閘極堆疊406的閘極切割圖案。 The patterned bottom layer 4182' and the patterned hard mask layer 416' inherit the pattern in the top photoresist layer 4186'. As such, the second opening O62 and the first opening O61 in the patterned top photoresist layer 4186' may have substantially the same shape, size, and position. For example, the second opening O62 has a length L62 in the direction X and a width W62 in the direction Y, and the length L62 is greater than the width W62. The pattern across the second opening O62 of the gate stack 406 may be used to define a gate cutting pattern for dividing the gate stack 406 in a subsequent step.

因為閘極堆疊406沿方向X配置,所以第二開口O62在方向X上的長度L62與待切割的多個閘極堆疊406成正相關。換句話說,第二開口O62的長度L62越大,則待切割的閘極堆疊406越多。因此,可以使用一個或多個橫向蝕刻製程來在方向X上延長第二開口O62。然而,如果圖案化的底層4182'和硬遮罩層416'經歷一個或多個橫向蝕刻製程,則第二開口O62將在方向X和方向Y上不可避免地延長,這將導致第二開口O62的寬度W62增加,其又可能在閘極切割製程期間對沿方向Y配置的源極/汲極區域410造成損壞。因此,在本揭露的一些實施例中,在晶圓WA4上執行在方向Y上的沉積速率快於在方向X上的沉積速率的定向沉積製程(方法M4的方框S404),接著是執行具有在方向X上的蝕刻速率高於在方向Y上的蝕刻速率(方法M4的方框S405)的定向蝕刻製程。以這 種方式,第二開口O62可以在方向X上延長但實質上不在方向Y上延長(請參閱下面更詳細的描述)。 Because the gate stack 406 is arranged in the direction X, the length L62 of the second opening O62 in the direction X is positively related to the plurality of gate stacks 406 to be cut. In other words, the greater the length L62 of the second opening O62, the more gate stacks 406 to be cut. Therefore, one or more lateral etching processes may be used to extend the second opening O62 in the direction X. However, if the patterned bottom layer 4182' and the hard mask layer 416' undergo one or more lateral etching processes, the second opening O62 will inevitably extend in direction X and direction Y, which will result in the second opening O62 The width W62 increases, which in turn may cause damage to the source/drain regions 410 arranged along the direction Y during the gate cutting process. Therefore, in some embodiments of the present disclosure, a directional deposition process is performed on the wafer WA4 with a deposition rate in the direction Y faster than the deposition rate in the direction X (block S404 of method M4), followed by performing A directional etching process in which the etching rate in direction X is higher than the etching rate in direction Y (block S405 of method M4). In this way, the second opening O62 may be extended in the direction X but not substantially extended in the direction Y (see the more detailed description below).

參考第34A圖至第34C圖,在方框S404的一些實施例中,執行定向沉積製程以在沿方向X延伸之第二開口O62'的第二側壁O622上形成保護層420,並且實質上不在沿方向Y延伸之第二開口O62'的第一側壁O621上形成保護層420。使用定向離子進行定向沉積製程,從而產生在方向Y上比在方向X上更快的沉積速率,使得方向X的側壁O622可以比方向Y的側壁O621沉積更多聚合物(例如,含碳聚合物、含氯聚合物及/或含溴聚合物)。在一些實施例中,方向Y上的沉積速率與方向X上的沉積速率的比例在約10:1至約30:1的範圍內。 Referring to FIGS. 34A to 34C, in some embodiments of block S404, a directional deposition process is performed to form a protective layer 420 on the second sidewall O622 of the second opening O62′ extending in the direction X, and is not substantially in A protective layer 420 is formed on the first sidewall O621 of the second opening O62' extending in the direction Y. The directional deposition process using directional ions results in a faster deposition rate in direction Y than in direction X, so that the side wall O622 in direction X can deposit more polymer (eg, carbon-containing polymer) than the side wall O621 in direction Y , Chlorine-containing polymers and/or bromine-containing polymers). In some embodiments, the ratio of the deposition rate in direction Y to the deposition rate in direction X is in the range of about 10:1 to about 30:1.

可以使用例如如第38圖所示的電漿工具900來執行定向沉積製程。進一步而言,可以提取離子922a和離子922b並將其引導到晶圓WA4。如前所述,可以控制離子922a和離子922b的軌跡使其在第38圖中的方向X和方向Z上延伸,但在實質上不在方向Y上延伸。因此,晶圓WA4可以被定向成使得離子922a和離子922b可以指向第二側壁O622,而實質上不指向第一側壁O621。在一些實施例中,選擇製程條件使得由離子產生的聚合現象較由離子引起的蝕刻現象更具主導性,使得離子922a和離子922b指向第二側壁O622但實質上不指向第一側壁O621,因而導致聚合物在第二側壁O622上沉積,但實質上不在第一側壁O621上沉積。這些沉積的聚合物可以稱為保護層(或聚合物層)420。在一些實施例中,定向沉積製程的製程條件類似於先前關於第6A圖至第6C圖所討論的定向沉 積製程的製程條件,因此,為簡潔起見,在此不再重複。 For example, the plasma tool 900 shown in FIG. 38 may be used to perform the directional deposition process. Further, the ions 922a and 922b can be extracted and guided to the wafer WA4. As described above, the trajectories of ions 922a and 922b can be controlled to extend in the direction X and the direction Z in FIG. 38, but they do not substantially extend in the direction Y. Therefore, the wafer WA4 may be oriented so that the ions 922a and 922b can be directed toward the second side wall O622, but not substantially toward the first side wall O621. In some embodiments, the process conditions are selected so that the polymerization phenomenon caused by ions is more dominant than the etching phenomenon caused by ions, so that ions 922a and 922b are directed toward the second side wall O622 but not substantially toward the first side wall O621, thus As a result, the polymer is deposited on the second sidewall O622, but is not substantially deposited on the first sidewall O621. These deposited polymers may be referred to as protective layers (or polymer layers) 420. In some embodiments, the process conditions of the directional deposition process are similar to the process conditions of the directional deposition process previously discussed with respect to FIGS. 6A to 6C, so for the sake of brevity, they are not repeated here.

作為定向沉積的結果,第二開口O62'在方向X上的長度L62'保持與第二開口O62的長度L62(如第33A圖所示)實質上相同,並且第二開口O62'在方向Y上的寬度W62'小於第二開口O62的寬度W62。定向沉積之後第二開口O62'的寬度W62'與定向沉積之前第二開口O62的寬度W62之間的差異實質上是保護層420厚度的兩倍。在一些實施例中,定向沉積導致在圖案化的底層4182'的頂面上方沉積聚合物,使得保護層420在圖案化的底層4182'的頂面上延伸。在一些實施例中,由於定向離子產生的遮蔽效應,位於第二開口O62'底部的蝕刻停止層414可能不受保護層420(即,聚合物)的覆蓋。 As a result of the directional deposition, the length L62' of the second opening O62' in the direction X remains substantially the same as the length L62 of the second opening O62 (as shown in FIG. 33A), and the second opening O62' in the direction Y The width W62' is smaller than the width W62 of the second opening O62. The difference between the width W62' of the second opening O62' after directional deposition and the width W62 of the second opening O62 before directional deposition is substantially twice the thickness of the protective layer 420. In some embodiments, directional deposition results in the deposition of polymer over the top surface of the patterned bottom layer 4182' such that the protective layer 420 extends on the top surface of the patterned bottom layer 4182'. In some embodiments, due to the shadowing effect generated by the directional ions, the etch stop layer 414 at the bottom of the second opening O62' may not be covered by the protective layer 420 (ie, polymer).

返回第30圖,方法M2接著進行到方框S405,其中蝕刻第二開口的第一側壁以延長第二開口。在方框S405的一些實施例中,對第二開口O62'的第一側壁O621執行定向蝕刻製程,從而產生如第35A圖至第35C圖所示之延長的開口O62"。使用定向離子執行定向蝕刻製程。例如,可以使用如下面詳細描述之如第38圖所示的電漿工具900來執行定向蝕刻製程。 Returning to FIG. 30, the method M2 then proceeds to block S405, where the first sidewall of the second opening is etched to extend the second opening. In some embodiments of block S405, a directional etching process is performed on the first sidewall O621 of the second opening O62', resulting in an extended opening O62" as shown in FIGS. 35A to 35C. Orientation is performed using directional ions Etching process. For example, a plasma tool 900 as shown in FIG. 38 as described in detail below may be used to perform a directional etching process.

在對電漿工具900中的晶圓WA4執行定向沉積製程之後,晶圓WA4可繞方向Z軸929旋轉大約88度至約92度(例如,大約90度)。此後,離子922a和離子922b可被提取並指向第二開口O62'的第一側壁O621,而實質上不指向沿第二開口O62’的第二側壁O622的保護層420。在一些實施例中,選擇製程條件使得由離子引起的蝕刻現象較由離子引起的 聚合現象更具主導性。因此,離子922a和離子922b可導致蝕刻第一側壁O621,但實質上不蝕刻沿第二側壁O622的保護層420。例如,蝕刻第一側壁O621的蝕刻速率與沿第二側壁O622蝕刻保護層420的蝕刻速率的比例在約10:1至約30:1的範圍內。以這種方式,定向蝕刻製程可以透過蝕刻第一側壁O621而實質上不蝕刻第二側壁O622來延長第二開口O62',從而產生如第35A圖至第35C圖所示之延長的開口O62"。在一些實施例中,定向蝕刻製程的製程條件類似於先前關於第7A圖至第7C圖所討論的定向蝕刻製程的製程條件,因此,為簡潔起見,在此不再重複。 After performing the directional deposition process on the wafer WA4 in the plasma tool 900, the wafer WA4 may be rotated about the direction Z axis 929 by about 88 degrees to about 92 degrees (for example, about 90 degrees). Thereafter, the ions 922a and 922b may be extracted and directed toward the first sidewall O621 of the second opening O62', but not substantially directed toward the protective layer 420 along the second sidewall O622 of the second opening O62'. In some embodiments, the process conditions are selected so that the ion-induced etching phenomenon is more dominant than the ion-induced polymerization phenomenon. Therefore, the ions 922a and 922b may cause the first sidewall O621 to be etched, but the protective layer 420 along the second sidewall O622 is not substantially etched. For example, the ratio of the etching rate of the first sidewall O621 to the etching rate of the protective layer 420 along the second sidewall O622 is in the range of about 10:1 to about 30:1. In this way, the directional etching process can extend the second opening O62' by etching the first side wall O621 without substantially etching the second side wall O622, resulting in an extended opening O62" as shown in FIGS. 35A to 35C In some embodiments, the process conditions of the directional etching process are similar to the process conditions of the directional etching process previously discussed with respect to FIGS. 7A to 7C, so for the sake of brevity, they are not repeated here.

作為定向蝕刻的結果,延長的開口O62"的長度L62"大於第二開口O62'的長度L62'(如第34A圖所示),並且延長的開口O62"的寬度W62"與第二開口O62'的寬度W62'實質上相同。因為延長的開口O62"在方向X上具有增加的長度,所以可以增加將經歷閘極切割製程的閘極堆疊406的數量。此外,因為延長製程不會增加開口O62"在方向Y上的寬度,所以可以防止由閘極切割製程引起的源極/汲極區域410的損壞。所得的長度L62"與所得的寬度W62"的示例性比例在約2.7:1至約4.6:1的範圍內。在一些實施例中,可以利用方框S404的定向沉積製程原位執行方框S405的定向蝕刻製程,這將防止晶圓WA4的污染。 As a result of directional etching, the length L62" of the extended opening O62" is greater than the length L62' of the second opening O62' (as shown in FIG. 34A), and the width W62" of the extended opening O62" and the second opening O62' The width W62' is substantially the same. Because the extended opening O62" has an increased length in the direction X, the number of gate stacks 406 that will undergo the gate cutting process can be increased. In addition, because the extended process does not increase the width of the opening O62" in the direction Y, Therefore, damage to the source/drain region 410 caused by the gate cutting process can be prevented. An exemplary ratio of the resulting length L62" to the resulting width W62" is in the range of about 2.7:1 to about 4.6:1. In some embodiments, the directional deposition process of block S405 may be performed in situ using the directional deposition process of block S404, which will prevent contamination of the wafer WA4.

返回第30圖,方法M2接著進行到方框S406,其中使用硬遮罩層作為蝕刻遮罩蝕刻蝕刻停止層和一個或多個第一閘極堆疊,以將一個或多個第一閘極堆疊分成多個第二閘 極堆疊。參考第36A圖至第36D圖,在方框S406的一些實施例中,使用保護層420、圖案化的底層4182'和圖案化的硬遮罩層416'的組合作為蝕刻遮罩,對晶圓WA4執行一個或多個蝕刻製程,導致切割開口O63將一個或多個長閘極堆疊406分成多個短閘極堆疊406',每個短閘極堆疊406'包括閘極介電層4062'和在閘極介電層4062'上方的閘極金屬層4064'。因此,一個或多個蝕刻製程可以稱為閘極切割製程。一個或多個蝕刻製程可包括非等向性濕式蝕刻製程、非等向性乾式蝕刻製程或以上之組合。在圖案化製程期間,可能消耗圖案化的底層4182'。在一些實施例中,可以使用合適的蝕刻劑去除圖案化的底層4182'的殘留物。 Returning to FIG. 30, method M2 then proceeds to block S406, where the hard mask layer is used as an etch mask to etch the etch stop layer and the one or more first gate stacks to stack the one or more first gates Divided into multiple second gate stacks. Referring to FIGS. 36A to 36D, in some embodiments of block S406, using a combination of the protective layer 420, the patterned bottom layer 4182' and the patterned hard mask layer 416' as an etch mask, the wafer WA4 performs one or more etching processes, resulting in the cutting opening O63 dividing one or more long gate stacks 406 into a plurality of short gate stacks 406', each short gate stack 406' includes a gate dielectric layer 4062' and A gate metal layer 4064' above the gate dielectric layer 4062'. Therefore, one or more etching processes may be referred to as gate cutting processes. The one or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof. During the patterning process, the patterned bottom layer 4182' may be consumed. In some embodiments, a suitable etchant may be used to remove residues of the patterned bottom layer 4182'.

作為圖案化製程的結果,切割開口O63繼承了延長的開口O62"的圖案(如第35A圖至第35C圖所示)。進一步而言,切割開口O63的長度L63與延長的開口O62"的長度L62"實質上相同,切割開口O63的寬度W63與延長的開口O62"的寬度W62"實質上相同。如第36C圖所示,控制切割開口O63的寬度W63,使得沿方向X配置在切割開口O63的相對側上的源極/汲極區域410不會被閘極接觸開口O23暴露。這有利於防止由在圖案化製程中使用的蝕刻劑造成的源極/汲極區域410的損壞。 As a result of the patterning process, the cut opening O63 inherits the pattern of the extended opening O62" (as shown in FIGS. 35A to 35C). Further, the length L63 of the cut opening O63 and the length of the extended opening O62" L62" is substantially the same, and the width W63 of the cutting opening O63 is substantially the same as the width W62" of the extended opening O62". As shown in FIG. 36C, the width W63 of the cutting opening O63 is controlled so that it is arranged along the direction X at the cutting opening O63 The source/drain region 410 on the opposite side of is not exposed by the gate contact opening O23. This helps prevent damage to the source/drain region 410 caused by the etchant used in the patterning process.

此後,在方法M4的方框S407的一些實施例中(如第30圖所示),沉積介電質結構422以過填充切割開口O63,隨後進行化學機械平坦化製程以去除介電質結構422的多餘材料直到達到例如蝕刻停止層414。所得到的結構如第37A圖至 第37D圖所示。介電質結構422可以包括合適的介電材料,例如氧化矽、氮化矽、氮氧化矽、低介電常數介電質(例如,摻雜碳的氧化物)、極低介電常數介電質(例如,摻雜多孔碳的二氧化矽)、這些的組合或者類似物。在一些實施例中,蝕刻停止層414也可以透過化學機械平坦化製程去除。 Thereafter, in some embodiments of block S407 of method M4 (as shown in FIG. 30), a dielectric structure 422 is deposited to overfill the cut opening O63, followed by a chemical mechanical planarization process to remove the dielectric structure 422 Of excess material until reaching the etch stop layer 414, for example. The resulting structure is shown in Figures 37A to 37D. The dielectric structure 422 may include suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant dielectrics (eg, carbon-doped oxides), very low dielectric constant dielectrics Materials (eg, silicon dioxide doped with porous carbon), combinations of these, or the like. In some embodiments, the etch stop layer 414 can also be removed through a chemical mechanical planarization process.

介電質結構422繼承切割開口O63的圖案(如第36A圖至第36D圖所示),使得介電質結構422可以與相鄰的短閘極堆疊406'分離並且因而與相鄰的短閘極堆疊406'絕緣。此外,介電質結構422的長度L64與切割開口O63的長度L63實質上相同,並且介電質結構422的寬度W64與切割開口O63的寬度W63實質上相同。控制介電質結構422的寬度W64,使得介電質結構422在源極/汲極區域410之間並且與源極/汲極區域410分離。 The dielectric structure 422 inherits the pattern of the cutting opening O63 (as shown in FIGS. 36A to 36D), so that the dielectric structure 422 can be separated from the adjacent short gate stack 406' and thus from the adjacent short gate The pole stack 406' is insulated. In addition, the length L64 of the dielectric structure 422 is substantially the same as the length L63 of the cutting opening O63, and the width W64 of the dielectric structure 422 is substantially the same as the width W63 of the cutting opening O63. The width W64 of the dielectric structure 422 is controlled so that the dielectric structure 422 is between the source/drain regions 410 and separated from the source/drain regions 410.

基於以上討論,可以看出本揭露提供了益處。然而,應理解,其他實施例可提供額外的益處,並且並非所有益處都必須在本文中揭露,並且並非所有實施例都需要特定的益處。其中一個益處是當開口經歷蝕刻製程以延長開口時,開口的寬度可以保持實質上不變,因為執行定向沉積製程以覆蓋開口的第一側壁但暴露開口的第二側壁。另一個益處是可以使用相同的工具(例如,相同的電漿工具)執行用於形成延長的圖案的定向沉積製程和定向蝕刻製程,從而防止晶片上的污染。 Based on the above discussion, it can be seen that this disclosure provides benefits. However, it should be understood that other embodiments may provide additional benefits, and not all benefits must be disclosed herein, and not all embodiments require specific benefits. One of the benefits is that when the opening undergoes an etching process to extend the opening, the width of the opening can be kept substantially unchanged because the directional deposition process is performed to cover the first sidewall of the opening but expose the second sidewall of the opening. Another benefit is that the same tool (eg, the same plasma tool) can be used to perform the directional deposition process and the directional etching process for forming extended patterns, thereby preventing contamination on the wafer.

在一些實施例中,一種方法包括在基板上形成沿第一方向延伸的半導體鰭片。在半導體鰭片上形成源極/汲極區域,在源極/汲極區域上方形成第一層間介電層。閘極堆疊 橫跨地形成在半導體鰭片上並且在實質上垂直於第一方向的第二方向上延伸。在第一層間介電層上形成具有第一開口的圖案化遮罩。使用在第一方向上比在第二方向上具有更快沉積速率的沉積製程在第一開口中形成保護層。在形成保護層之後,第一開口在第二方向上延長。第二開口形成在第一層間介電層中並且在延長的第一開口下方。在第二開口中形成導電材料。 In some embodiments, a method includes forming a semiconductor fin extending in a first direction on a substrate. A source/drain region is formed on the semiconductor fin, and a first interlayer dielectric layer is formed above the source/drain region. The gate stack is formed across the semiconductor fins and extends in a second direction that is substantially perpendicular to the first direction. A patterned mask having a first opening is formed on the first interlayer dielectric layer. A deposition process having a faster deposition rate in the first direction than in the second direction is used to form the protective layer in the first opening. After the protective layer is formed, the first opening is extended in the second direction. The second opening is formed in the first interlayer dielectric layer and below the elongated first opening. A conductive material is formed in the second opening.

在一些實施例中,一種方法包括形成突出於基板並沿第一方向延伸的鰭片。形成橫跨鰭片的第一閘極堆疊,並且其沿實質上垂直於第一方向的第二方向延伸。在第一閘極結構上形成具有開口的圖案化遮罩。使用在第二方向上比在第一方向上具有更快沉積速率的沉積製程在圖案化遮罩的開口中形成保護層。在形成保護層之後,在第一方向上延伸開口。蝕刻在延長的開口下方的第一閘極堆疊以將第一閘極堆疊分成成多個第二閘極堆疊。在第二閘極結構之間形成介電質結構。 In some embodiments, a method includes forming fins that protrude from the substrate and extend in the first direction. A first gate stack is formed across the fins, and it extends in a second direction that is substantially perpendicular to the first direction. A patterned mask with openings is formed on the first gate structure. A deposition process having a faster deposition rate in the second direction than in the first direction is used to form a protective layer in the opening of the patterned mask. After the protective layer is formed, the opening is extended in the first direction. The first gate stack is etched under the elongated opening to divide the first gate stack into a plurality of second gate stacks. A dielectric structure is formed between the second gate structures.

在一些實施例中,半導體裝置包括半導體基板、源極/汲極區域、源極/汲極接觸、導電通孔和第一聚合物層。源極/汲極區域位於半導體基板中。源極/汲極接觸位於源極/汲極區域上方。源極/汲極通孔位於源極/汲極接觸之上。第一聚合物層沿著導電通孔的第一側壁延伸,並且與實質上垂直於導電通孔的第一側壁之導電通孔的第二側壁分開。 In some embodiments, the semiconductor device includes a semiconductor substrate, source/drain regions, source/drain contacts, conductive vias, and the first polymer layer. The source/drain regions are located in the semiconductor substrate. The source/drain contact is located above the source/drain region. The source/drain via is located above the source/drain contact. The first polymer layer extends along the first sidewall of the conductive via and is separated from the second sidewall of the conductive via substantially perpendicular to the first sidewall of the conductive via.

以上概述了若干實施例的特徵,使得本領域技術人員可以更好地理解本揭露的各方面。本領域技術人員應當理解,他們可以容易地使用本揭露作為設計或修改其他過程和結構的基礎,以實現相同的目的及/或實現本文介紹的實施例的 相同益處。本領域技術人員還應該認識到,這樣的等同構造不脫離本揭露的精神和範圍,並且在不脫離本揭露的精神和範圍的情況下,它們可以在本文中進行各種改變,替換和變更。 The above outlines the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or to achieve the same benefits of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

M1‧‧‧方法 M1‧‧‧Method

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Claims (20)

一種方法,包括:形成一半導體鰭片於一基板上,該半導體鰭片沿一第一方向延伸;形成一源極/汲極區域於該半導體鰭片上並且形成一第一層間介電層於該源極/汲極區域上;形成一閘極堆疊橫跨於該半導體鰭片上,該閘極堆疊沿實質上垂直於該第一方向的一第二方向延伸;形成一圖案化遮罩,該圖案化遮罩在該第一層間介電層上具有一第一開口;使用在該第一方向上比在該第二方向上具有更快沉積速率的一沉積製程在該第一開口中形成一保護層;在形成該保護層之後,在該第二方向延長該第一開口;形成一第二開口於該第一層間介電層中並於延長的該第一開口下;以及形成一導電材料於該第二開口中。 A method includes: forming a semiconductor fin on a substrate, the semiconductor fin extending in a first direction; forming a source/drain region on the semiconductor fin and forming a first interlayer dielectric layer on On the source/drain region; forming a gate stack across the semiconductor fin, the gate stack extending in a second direction substantially perpendicular to the first direction; forming a patterned mask, the The patterned mask has a first opening in the first interlayer dielectric layer; it is formed in the first opening using a deposition process that has a faster deposition rate in the first direction than in the second direction A protective layer; after forming the protective layer, extending the first opening in the second direction; forming a second opening in the first interlayer dielectric layer and under the extended first opening; and forming a The conductive material is in the second opening. 如請求項1所述的方法,其中延長該第一開口包含一蝕刻製程,並且該蝕刻製程在該第二方向上具有比在該第一方向上更快的一蝕刻速率。 The method of claim 1, wherein extending the first opening includes an etching process, and the etching process has a faster etching rate in the second direction than in the first direction. 如請求項1所述的方法,其中該保護層由一聚合物製成。 The method of claim 1, wherein the protective layer is made of a polymer. 如請求項1所述的方法,其中在相同的一電 漿工具中執行該保護層的形成和該第一開口的延長。 The method according to claim 1, wherein the formation of the protective layer and the extension of the first opening are performed in the same plasma tool. 如請求項4所述的方法,更包含:在形成該保護層之後並在延長該第一開口之前,在該電漿工具中旋轉該基板。 The method according to claim 4, further comprising: after forming the protective layer and before extending the first opening, rotating the substrate in the plasma tool. 如請求項1所述的方法,更包含:在形成該圖案化遮罩之前,形成一蝕刻停止層以覆蓋該第一層間介電層。 The method of claim 1, further comprising: before forming the patterned mask, forming an etch stop layer to cover the first interlayer dielectric layer. 如請求項6所述的方法,其中在延長該第一開口之後,該蝕刻停止層仍保持覆蓋該第一層間介電層。 The method of claim 6, wherein after extending the first opening, the etch stop layer still covers the first interlayer dielectric layer. 如請求項1所述的方法,其中在該第一層間介電層中形成該第二開口,使得該第二開口暴露該源極/汲極區域。 The method of claim 1, wherein the second opening is formed in the first interlayer dielectric layer such that the second opening exposes the source/drain region. 如請求項1所述的方法,其中在該第一層間介電層中形成該第二開口,使得該第二開口暴露該閘極堆疊。 The method of claim 1, wherein the second opening is formed in the first interlayer dielectric layer such that the second opening exposes the gate stack. 如請求項1所述的方法,更包含:在形成該第一層間介電層之前,在該源極/汲極區域上形成一第二層間介電層;以及在形成該第一層間介電層之前,在該第二層間介電層中形成一源極/汲極接觸,其中在該第一層間介電層中形成該第 二開口,使得該源極/汲極接觸被暴露。 The method of claim 1, further comprising: forming a second interlayer dielectric layer on the source/drain region before forming the first interlayer dielectric layer; and forming the first interlayer Before the dielectric layer, a source/drain contact is formed in the second interlayer dielectric layer, wherein the second opening is formed in the first interlayer dielectric layer so that the source/drain contact is exposed . 一種方法,包含:形成一鰭片,該鰭片從一基板突出並沿一第一方向延伸;形成一第一閘極堆疊橫跨於該鰭片上並沿實質上垂直於該第一方向的一第二方向延伸;形成一圖案化遮罩,該圖案化遮罩在該第一閘極堆疊上具有一開口;使用在該第二方向上比在該第一方向上具有更快沉積速率的一沉積製程在該圖案化遮罩的該開口中形成一保護層;在形成該保護層之後,在該第一方向上延長該開口;蝕刻延長的該開口下方的該第一閘極堆疊,以將該第一閘極堆疊分成複數第二閘極堆疊;以及形成一介電質結構於該些第二閘極堆疊之間。 A method includes: forming a fin that protrudes from a substrate and extending in a first direction; forming a first gate stack across the fin and along a substantially perpendicular to the first direction Extending in the second direction; forming a patterned mask with an opening in the first gate stack; using a faster deposition rate in the second direction than in the first direction The deposition process forms a protective layer in the opening of the patterned mask; after forming the protective layer, the opening is extended in the first direction; the first gate stack under the extended opening is etched to remove The first gate stack is divided into a plurality of second gate stacks; and a dielectric structure is formed between the second gate stacks. 如請求項11所述的方法,其中在該圖案化遮罩中延長該開口包含一蝕刻製程,並且該蝕刻製程在該第一方向上具有比在該第二方向上更快的一蝕刻速率。 The method of claim 11, wherein extending the opening in the patterned mask includes an etching process, and the etching process has a faster etching rate in the first direction than in the second direction. 如請求項11所述的方法,更包含:在形成該圖案化遮罩之前,形成一蝕刻停止層以覆蓋該第一閘極堆疊。 The method of claim 11, further comprising: before forming the patterned mask, forming an etch stop layer to cover the first gate stack. 如請求項13所述的方法,其中在延長該開口之後,該蝕刻停止層仍保持覆蓋該第一閘極堆疊。 The method of claim 13, wherein after extending the opening, the etch stop layer still covers the first gate stack. 如請求項11所述的方法,其中使用離子執行該保護層的形成和該開口的延長。 The method according to claim 11, wherein the formation of the protective layer and the extension of the opening are performed using ions. 如請求項11所述的方法,更包含:旋轉該基板於該保護層的形成和該開口的延長之間。 The method of claim 11, further comprising: rotating the substrate between the formation of the protective layer and the extension of the opening. 一種半導體裝置,包含:一半導體基板;一源極/汲極區域,位於該半導體基板中;一源極/汲極接觸,位於該源極/汲極區域上;一導電通孔,位於該源極/汲極接觸上;以及一第一聚合物層,沿該導電通孔的一第一側壁延伸,並與實質上垂直於該導電通孔的該第一側壁之該導電通孔的一第二側壁分開。 A semiconductor device includes: a semiconductor substrate; a source/drain region located in the semiconductor substrate; a source/drain contact located on the source/drain region; and a conductive via located in the source A pole/drain contact; and a first polymer layer extending along a first side wall of the conductive via, and a first layer of the conductive via substantially perpendicular to the first side wall of the conductive via The two side walls are separated. 如請求項17所述的半導體裝置,更包含:一蝕刻停止層,圍繞該導電通孔,其中該第一聚合物層具有透過該蝕刻停止層與該源極/汲極接觸隔開的一底部。 The semiconductor device of claim 17, further comprising: an etch stop layer surrounding the conductive via, wherein the first polymer layer has a bottom spaced from the source/drain contact through the etch stop layer . 如請求項17所述的半導體裝置,更包含:一閘極堆疊,於該半導體基板上;一閘極接觸,於該閘極堆疊上;以及一第二聚合物層,沿著該閘極接觸的一第一側壁延伸,並與實質上垂直於該閘極堆疊的該第一側壁之該閘極接觸的 一第二側壁分離。 The semiconductor device of claim 17, further comprising: a gate stack on the semiconductor substrate; a gate contact on the gate stack; and a second polymer layer in contact along the gate A first side wall extends and is separated from a second side wall that is substantially perpendicular to the gate contact of the first side wall of the gate stack. 如請求項19所述的半導體裝置,更包含:一蝕刻停止層,圍繞該閘極接觸,其中該蝕刻停止層位於該第二聚合物層和該閘極堆疊之間。 The semiconductor device of claim 19, further comprising: an etch stop layer surrounding the gate contact, wherein the etch stop layer is located between the second polymer layer and the gate stack.
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US20200043795A1 (en) 2020-02-06
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US20210013103A1 (en) 2021-01-14
TWI709195B (en) 2020-11-01

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