TW202008503A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A method includes following steps. A semiconductor fin is formed on a substrate and extends in a first direction. A source/drain region is formed on the semiconductor fin and a first interlayer dielectric (ILD) layer over the source/drain region. A gate stack is formed across the semiconductor fin and extends in a second direction substantially perpendicular to the first direction. A patterned mask having a first opening is formed over the first ILD layer. A protective layer is formed in the first opening using a deposition process having a faster deposition rate in the first direction than in the second direction. After forming the protective layer, the first opening is elongated in the second direction. A second opening is formed in the first ILD layer and under the elongated first opening. A conductive material is formed in the second opening.

Description

Extended pattern and its forming method

The manufacture of integrated circuits is driven by an increase in the density of integrated circuits (ICs) in semiconductor devices. This is achieved by building more aggressive design rules to allow the formation of larger density integrated circuit devices. Nevertheless, the increased density of integrated circuit devices (eg, transistors) also increases the complexity of processing semiconductor devices with reduced feature sizes.

102‧‧‧ substrate

104‧‧‧Semiconductor Fin

105‧‧‧Isolated insulating layer

106‧‧‧Gate Stacking

108‧‧‧Gate spacer

110‧‧‧ source/drain region

112‧‧‧First dielectric layer

114‧‧‧First etch stop layer

116‧‧‧second dielectric layer

118‧‧‧Second etching stop layer

118'‧‧‧Second etching stop layer

120‧‧‧hard mask layer

120'‧‧‧hard mask layer

122‧‧‧Three-layer photoresist mask

124‧‧‧Protective layer

126‧‧‧ conductive material

128‧‧‧ source/drain contacts

202‧‧‧ substrate

204‧‧‧Semiconductor Fin

205‧‧‧Shallow trench isolation

206‧‧‧Gate Stacking

208‧‧‧Gate spacer

210‧‧‧ source/drain region

212‧‧‧ First dielectric layer

214‧‧‧First etch stop layer

216‧‧‧second dielectric layer

228‧‧‧ source/drain contact

230‧‧‧Etching stop layer

232‧‧‧The third interlayer dielectric layer

232'‧‧‧third dielectric layer

232"‧‧‧third dielectric layer

234‧‧‧Photoresist mask

236‧‧‧Protective layer

238‧‧‧The second and third layers of photoresist mask

240‧‧‧Protective layer

242‧‧‧Gate contact

244‧‧‧Source/drain via

302‧‧‧ substrate

304‧‧‧Semiconductor Fin

305‧‧‧Shallow trench isolation

306‧‧‧Gate Stacking

308‧‧‧Gate spacer

310‧‧‧ source/drain region

312‧‧‧Interlayer dielectric layer

314‧‧‧First etch stop layer

316‧‧‧second dielectric layer

328‧‧‧ source/drain contact

330‧‧‧Etching stop layer

332‧‧‧The third interlayer dielectric layer

332'‧‧‧third dielectric layer

336‧‧‧Protective layer

340‧‧‧Three-layer photoresist mask

342‧‧‧Protective layer

344‧‧‧conductive through hole

402‧‧‧ substrate

404‧‧‧Semiconductor Fin

405‧‧‧Shallow trench isolation

406‧‧‧Gate Stacking

406'‧‧‧Short gate stack

408‧‧‧Gate spacer

410‧‧‧ source/drain region

412‧‧‧Interlayer dielectric layer

414‧‧‧Etching stop layer

416‧‧‧hard mask layer

416'‧‧‧hard mask layer

418‧‧‧Three-layer photoresist mask

420‧‧‧Protective layer

422‧‧‧dielectric structure

900‧‧‧ plasma tool

902‧‧‧Plasma source

904‧‧‧Plasma cavity

906‧‧‧Plasma

908‧‧‧Power

910‧‧‧Housing

912‧‧‧RF Inductor

914‧‧‧gas source

916‧‧‧Process cavity

917‧‧‧Vertical line

920‧‧‧Extraction plate

921‧‧‧Ion distribution

922a‧‧‧ion

922b‧‧‧ ion

923‧‧‧ Peak

925‧‧‧peak

926‧‧‧platform

927‧‧‧Drive mechanism

929‧‧‧axis

930‧‧‧Extraction hole

932‧‧‧plasma sheath boundary

936‧‧‧plane

938‧‧‧DC bias source

1062‧‧‧ Gate dielectric layer

1064‧‧‧Metal layer

1222‧‧‧Bottom

1222'‧‧‧patterned bottom layer

1224‧‧‧ Middle layer

1226‧‧‧Top

1226'‧‧‧patterned top layer

2062‧‧‧ Gate dielectric layer

2064‧‧‧Gate metal layer

2342‧‧‧Bottom

2342'‧‧‧patterned bottom layer

2344‧‧‧ Middle layer

2346‧‧‧Top

2382‧‧‧Bottom

2382'‧‧‧patterned bottom layer

2384‧‧‧ Middle layer

2386‧‧‧Top

2421‧‧‧First side wall

2422‧‧‧Second side wall

2441‧‧‧First side wall

2442‧‧‧Second side wall

3062‧‧‧Gate dielectric layer

3064‧‧‧Metal layer

3402‧‧‧Bottom

3402'‧‧‧patterned bottom layer

3404‧‧‧ Middle layer

3406‧‧‧Top

4062‧‧‧ Gate dielectric layer

4062'‧‧‧Gate dielectric layer

4064‧‧‧Metal layer

4064'‧‧‧Gate metal layer

4182‧‧‧Bottom

4182'‧‧‧patterned bottom layer

4184‧‧‧ middle layer

4186‧‧‧Top

4186'‧‧‧patterned top layer

L11‧‧‧Length

L12‧‧‧Length

L12'‧‧‧Length

L12"‧‧‧Length

L13‧‧‧Length

L14‧‧‧Length

L21‧‧‧Length

L22‧‧‧Length

L22'‧‧‧Length

L22"‧‧‧Length

L23‧‧‧Length

L24‧‧‧Length

L31‧‧‧Length

L32‧‧‧Length

L32'‧‧‧Length

L32"‧‧‧Length

L33‧‧‧Length

L34‧‧‧Length

L51‧‧‧Length

L52‧‧‧Length

L52'‧‧‧Length

L52"‧‧‧Length

L53‧‧‧Length

L61‧‧‧Length

L62‧‧‧Length

L62'‧‧‧Length

L62"‧‧‧Length

L63‧‧‧Length

L64‧‧‧Length

M1‧‧‧Method

M2‧‧‧Method

M3‧‧‧Method

M4‧‧‧Method

O11‧‧‧First opening

O12‧‧‧Second opening

012'‧‧‧Second opening

O12"‧‧‧Extended opening

O121‧‧‧First side wall

O122‧‧‧Second side wall

O13‧‧‧ source/drain contact opening

O21‧‧‧First opening

O22‧‧‧Second opening

O22'‧‧‧Second opening

O22"‧‧‧Extended opening

O221‧‧‧First side wall

O222‧‧‧Second side wall

O23‧‧‧Gate contact opening

O231‧‧‧First side wall

O232‧‧‧Second side wall

O31‧‧‧The third opening

O32‧‧‧The fourth opening

O32'‧‧‧The fourth opening

O32"‧‧‧Extended opening

O321‧‧‧First side wall

O322‧‧‧Second side wall

O33‧‧‧Source/drain via opening

O331‧‧‧First side wall

O332‧‧‧Second side wall

O41‧‧‧Gate contact opening

051‧‧‧First opening

O52‧‧‧Second opening

O52'‧‧‧Second opening

O52"‧‧‧Extended opening

O521‧‧‧First side wall

O522‧‧‧Second side wall

O53‧‧‧Through hole opening

O531‧‧‧First side wall

O532‧‧‧Second side wall

O61‧‧‧First opening

O61'‧‧‧Second opening

O62‧‧‧Second opening

O62'‧‧‧Second opening

O62"‧‧‧Extended opening

O621‧‧‧First side wall

O622‧‧‧Second side wall

O63‧‧‧cutting opening

O64‧‧‧ opening

S101‧‧‧Box

S102‧‧‧Box

S103‧‧‧Box

S104‧‧‧Box

S105‧‧‧Box

S106‧‧‧Box

S107‧‧‧Box

S108‧‧‧Box

S109‧‧‧Box

S201‧‧‧Box

S202‧‧‧Box

S203‧‧‧Box

S204‧‧‧Box

S205‧‧‧Box

S206‧‧‧Box

S207‧‧‧Box

S208‧‧‧Box

S209‧‧‧Box

S210‧‧‧Box

S211‧‧‧Box

S212‧‧‧Box

S213‧‧‧Box

S214‧‧‧Box

S301‧‧‧Box

S302‧‧‧Box

S303‧‧‧Box

S304‧‧‧Box

S305‧‧‧Box

S306‧‧‧Box

S307‧‧‧Box

S401‧‧‧Box

S402‧‧‧Box

S403‧‧‧Box

S404‧‧‧Box

S405‧‧‧Box

S406‧‧‧Box

S407‧‧‧Box

W11‧‧‧Width

W12‧‧‧Width

W12'‧‧‧Width

W12"‧‧‧Width

W13‧‧‧Width

W14‧‧‧Width

W21‧‧‧Width

W22‧‧‧Width

W22'‧‧‧Width

W22"‧‧‧Width

W23‧‧‧Width

W24‧‧‧Width

W31‧‧‧Width

W32‧‧‧Width

W32'‧‧‧Width

W32"‧‧‧Width

W33‧‧‧Width

W34‧‧‧Width

W51‧‧‧Width

W52‧‧‧Width

W52'‧‧‧Width

W52"‧‧‧Width

W53‧‧‧Width

W61‧‧‧Width

W62‧‧‧Width

W62'‧‧‧Width

W62"‧‧‧Width

W63‧‧‧Width

W64‧‧‧Width

WA‧‧‧ Wafer

WA2‧‧‧ Wafer

WA3‧‧‧ Wafer

WA4‧‧‧ Wafer

WAP‧‧‧Plane

B-B‧‧‧line

C-C‧‧‧line

D-D‧‧‧line

θ‧‧‧incidence angle

X‧‧‧ direction

Y‧‧‧ direction

Z‧‧‧ direction

The aspects of the disclosure can be best understood from the following detailed description when read in conjunction with the drawings. It should be noted that according to standard practice in the industry, various features are not drawn to scale. In fact, for clear discussion, the size of various features can be arbitrarily increased or decreased.

FIG. 1 is a flowchart of a method of forming a semiconductor device according to some embodiments of the present disclosure; FIGS. 2A and 3A illustrate semiconductors at various stages of the method of FIG. 1 according to some embodiments of the present disclosure A perspective view of the device; Figure 4A, Figure 5A, Figure 6A, Figure 7A, Figure 8A, Figure 9A, and Figure 10A illustrate each of the methods made in Figure 1 according to some embodiments of the present disclosure Top view of the semiconductor device in the stage; Figures 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B show some according to the present disclosure Examples of the cross-sectional view of the semiconductor device at various stages of the method of FIG. 1; FIG. 2C, FIG. 3C, FIG. 4C, FIG. 5C, 6C, 7C, 8C, 9C FIGS. 10C and 10C illustrate another cross-sectional view of the semiconductor device in various stages of fabrication according to the method of FIG. 1 according to some embodiments of the present disclosure; FIGS. 11A and 11B are some embodiments according to the present disclosure A flowchart of a method of forming a semiconductor device in FIG. 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A and FIG. 22A illustrates a top view of a semiconductor device in various stages of fabrication according to the methods of FIGS. 11A and 11B according to some embodiments of the present disclosure; FIGS. 12B, 13B, 14B, and 15B, Figures 16B, 17B, 18B, 19B, 20B, 21B, and 22B illustrate each of the methods made in Figs. 11A and 11B according to some embodiments of the present disclosure. Cross-sectional views of the semiconductor device at the stage; Figures 12C, 13C, 14C, 15C, 16C, 17C, 18C, 19C, 20C, 21C and 22C illustrates another cross-sectional view of the semiconductor device in various stages of fabrication according to the methods of FIGS. 11A and 11B according to some embodiments of the present disclosure; FIGS. 17D, 21D, and 22D illustrate Some embodiments of the present disclosure are another cross-sectional view of the semiconductor device at various stages of fabrication by the methods of FIGS. 11A and 11B; FIG. 23 is a flow chart of a method of forming a semiconductor device according to some embodiments of the present disclosure Figures 24A, 25A, 26A, 27A, 28A, and 29A illustrate cross-sections of semiconductor devices at various stages of fabrication according to the method of FIG. 23 according to some embodiments of the disclosure Figures 24B, 25B, 26B, 27B, 28B, and 29B illustrate the semiconductor devices in various stages of fabrication according to the method of FIG. 23 according to some embodiments of the disclosure Another cross-sectional view; FIG. 30 is a flowchart of a method of forming a semiconductor device according to some embodiments of the present disclosure; FIG. 31A illustrates Perspective views of semiconductor devices in various stages of the method of FIG. 30 in some disclosed embodiments; FIGS. 32A, 33A, 34A, 35A, 36A, and 37A illustrate according to the present disclosure In some embodiments, the top view of the semiconductor device at various stages of fabrication by the method of FIG. 30; FIGS. 31B, 32B, 33B, 34B, 35B, 36B, and 37B Figures 31C, 32C, 33C, 34C, 35C, 36C are cross-sectional views of the semiconductor device at various stages of fabrication according to some embodiments of the disclosure; FIGS. 37C show another cross-sectional view of the semiconductor device in various stages of fabrication according to the method of FIG. 30 according to some embodiments of the present disclosure; FIGS. 36D and 37D show some implementations according to the present disclosure For example, another cross-sectional view of the semiconductor device in each stage manufactured by the method of FIG. 30; FIG. 38 shows a schematic side view of a plasma tool according to some embodiments of the present disclosure; and FIG. 39 An exemplary ion profile associated with the ions generated by the plasma tool of FIG. 38 is shown.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not limiting. For example, forming the first feature on or above the second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include one that may be on the first feature and the second feature An embodiment in which additional features are formed so that the first feature and the second feature may not directly contact. In addition, the present disclosure may repeat reference numerals and/or text in various examples. This repetition is for simplicity and clarity, and does not in itself represent the relationship between the various embodiments and/or configurations discussed.

In addition, this article can use spatial relative terms, such as "below", "below", "below", "above", "above", etc., in order to describe an element Or feature and another element or feature as shown. In addition to the orientations shown in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptive symbols used here can likewise be interpreted accordingly.

The fins of the fin-type field effect transistors discussed below can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multi-patterning processes) can be used to pattern the fins. Generally, double patterning or multi-patterning processes combine photolithography and self-alignment processes to allow the formation of patterns with smaller pitches than those achievable using a single, direct photolithography process, for example. For example, in some embodiments, a sacrificial layer is formed on the substrate and patterned using a photolithography process. A self-aligned process is used to form spacers next to the patterned sacrificial layer. Then the sacrificial layer is removed, and then the remaining spacers can be used to pattern the fins.

FIG. 1 illustrates a method M1 of forming a semiconductor device according to some embodiments of the present disclosure. FIGS. 2A to 10C illustrate various processes at various stages of the method M1 of FIG. 1 according to some embodiments of the present disclosure. In various views and illustrative embodiments, the same reference numerals are used to represent the same elements. In Figures 2A to 3C, "A" (for example, Figures 2A and 3A) shows a perspective view, and "B" (for example, Figures 2B and 3B) shows along and " The cross-sectional view of the direction X corresponding to the line BB shown in the "A" figure, and the "C" figures (for example, figures 2C and 3C) are drawn along the direction corresponding to the line CC shown in the "A" figure Sectional view of Y. In FIGS. 4A to 10C, “A” (for example, FIGS. 4A, 5A, etc.) shows a top view, and “B” (for example, FIGS. 4B and 5B) shows along and A cross-sectional view in the direction X corresponding to the line BB shown in the "A" drawing, and the "C" drawing (for example, FIGS. 4C and 5C) is drawn along the line CC corresponding to the drawing in the "A" drawing Cross-sectional view in the direction Y. It should be understood that additional steps may be provided before, during, and after the processes shown in FIGS. 2A to 10C as other embodiments of this method, and some steps described below may be replaced or eliminated. The order of steps/processes can be interchangeable.

In block S101 of method M1, a transistor (e.g., fin field effect transistor) and a first interlayer dielectric (ILD) layer are formed on the substrate. For example, as shown in FIGS. 2A to 2C, a semiconductor wafer WA having a substrate 102 having one or more semiconductor fins 104 and one or more gate stacks 106 is shown. It should be understood that four semiconductor fins are shown for illustrative purposes, although other embodiments may include any number of semiconductor fins. The semiconductor fin 104 extends in the direction X and protrudes from the substrate 102 in the direction Z, while the gate stack 106 extends in the direction Y. The gate stack 106 extends across the semiconductor fin 104 to form a fin field effect transistor on the substrate 102.

The substrate 102 may include various doped regions. In some embodiments, the doped region may be doped with p-type or n-type dopants. For example, the doped region may be doped with p-type dopants (eg, boron or boron difluoride (BF ₂ )); n-type dopants (eg, phosphorus or arsenic); and/or a combination of the above. The doped region may be used for n-type fin field effect transistors, or may be used for p-type fin field effect transistors.

In some embodiments, the substrate 102 may be made of a suitable element semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as a group IV compound semiconductor (silicon germanium (SiGe), silicon carbide (SiC), carbide Silicon germanium (SiGeC), germanium tin (GeSn), silicon tin (SiSn), silicon germanium tin (SiGeSn)), group III-V compound semiconductors (eg, gallium arsenide, indium gallium arsenide (InGaAs), indium arsenide , Indium phosphide, indium antimonide, gallium arsenide phosphide or indium gallium phosphide) or the like. In addition, the substrate 102 may include an epi-layer, which may be strained to improve performance, and/or may include a silicon-on-insulator (SOI) structure.

The semiconductor fins 104 may be formed using, for example, a patterning process to form trenches in the substrate 102 so that trenches are formed between adjacent semiconductor fins 104. An isolation region (for example, shallow trench isolations (STI) 105) is provided in the trench above the substrate 102. In some embodiments, the isolation region may correspond to an isolation insulating layer. The isolation insulating layer 105 may be made of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low dielectric constant dielectric Substances (for example, carbon-doped oxides), very low dielectric constant dielectrics (for example, porous carbon-doped silicon dioxide), polymers (for example, polyimide), combinations of the above, or the like . In some embodiments, the isolation insulating layer 105 is formed through a process such as chemical vapor deposition (CVD), flowable chemical vapor deposition (FCVD), or spin-on glass process, however, Any acceptable process can be used. Subsequently, the isolation insulating layer 105 extending on the top surface of the semiconductor fin 104 is removed using, for example, an etch-back process, chemical mechanical polishing (CMP), or the like.

In some embodiments, the isolation insulating layer 105 is recessed to expose the top of the semiconductor fin 104, as shown in FIGS. 2A to 2C. In some embodiments, a single etching process or a multiple etching process is used to recess the isolation insulating layer 105. In some embodiments where the isolation insulating layer 105 is made of silicon oxide, the etching process may be, for example, dry etching, chemical etching, or wet cleaning process. For example, chemical etching may use fluorine-containing chemicals, such as diluted hydrofluoric acid.

After forming the semiconductor fin 104, a dummy gate structure (eg, a polysilicon gate structure) is formed across the semiconductor fin 104, and the dummy gate structure will be replaced with the gate stack 106 as described further below . After forming the dummy gate structure, a gate spacer 108 is formed along the sidewall of the dummy gate structure. Next, the source/drain region 110 is formed in the semiconductor fin 104. The formation of the source/drain region 110 includes, for example, recessing a portion of the semiconductor fin 104 that is not covered by the dummy gate structure and the gate spacer 108 using an appropriate etching technique, and epitaxial from the recessed portion of the semiconductor fin 104 Growing source/drain region 110.

In some embodiments, recessing the semiconductor fin 104 may include a dry etching process, a wet etching process, or a combination of dry and wet etching processes. This etching process may include reactive ion etch (RIE) using the dummy gate structure and the gate spacer 108 as a mask, or through any other suitable removal process. After the etching process, in some embodiments, a pre-cleaning process may be performed to clean the grooves in the semiconductor fin 104 with hydrofluoric acid or other suitable solutions.

In some embodiments, the source/drain regions 110 may be formed using one or more epitaxial processes, such that silicon (Si) features, silicon germanium (SiGe) features, silicon phosphate (SiP) features, silicon carbide (SiC) The features and/or other suitable features may be formed on the semiconductor fin 104 in a crystalline state. In some embodiments, the lattice constant of the source/drain region 110 is different from the lattice constant of the semiconductor fin 104, so the channel region between the source/drain region 110 can be used by the source/drain region 110 Strain or stress to improve the carrier mobility of semiconductor devices and enhance device performance.

The epitaxial process for forming the source/drain regions 110 includes chemical vapor deposition techniques (for example, vapor-phase epitaxy (VPE) and/or ultra-high vacuum chemical vapor deposition (ultra-high vacuum chemical vapor deposition deposition, UHV-CVD)), molecular beam epitaxy and/or other suitable processes. The epitaxial process may use gaseous and/or liquid precursors that interact with the components of the semiconductor fin 104 (eg, silicon, silicon germanium, silicon phosphate, or the like). The epitaxial source/drain region 110 may be in-situ doped. Dopants include p-type dopants (eg, boron or boron difluoride (BF ₂ )); n-type dopants (eg, phosphorus or arsenic); and/or other suitable dopants including combinations thereof . If the epitaxial source/drain region 110 is not doped in situ, an implantation process is performed to dope the epitaxial source/drain region 110. One or more annealing processes may be performed to activate the epitaxial source/drain regions 110. The annealing process includes rapid thermal annealing (RTA) and/or laser annealing processes.

After forming the source/drain region 110, a first interlayer dielectric layer 112 is formed over the source/drain region 110, the dummy gate structure, and the gate spacer 108, and then a chemical mechanical planarization process is performed to remove The first interlayer dielectric layer 112 has excess material to expose the dummy gate structure. In some embodiments, the first interlayer dielectric layer 112 includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) , Low dielectric constant dielectric materials and/or other suitable dielectric materials. Examples of low dielectric constant dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silica, amorphous carbon fluoride, parylene, dibenzocyclobutane Bis-benzocyclobutenes (BCB) or polyimide. The first interlayer dielectric layer 112 may be formed using, for example, chemical vapor deposition, atomic layer deposition, spin-on-glass (SOG), or other suitable techniques. In some embodiments, before forming the first interlayer dielectric layer 112, a contact etch stop layer (CESL) is optionally formed on the source/drain region 110, and then the contact etch stop layer is formed The first interlayer dielectric layer 112 is formed thereon. The contact etch stop layer has a different material from the first interlayer dielectric layer 112. For example, the contact etch stop layer includes silicon nitride, silicon oxynitride, or other suitable materials. The contact etch stop layer may be formed using, for example, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atomic layer deposition, or other suitable techniques.

Thereafter, the dummy gate structure is replaced with the gate stack 106. The gate replacement process includes, for example, removing the dummy gate structure to form a gate trench between the gate spacers 108, and forming a gate stack 106 in the gate trench. An exemplary method of forming the gate stack 106 may include blanket forming the gate dielectric layer 1062 over the wafer WA, forming one or more metal layers 1064 over the blanket gate dielectric layer 1062, and performing A chemical mechanical planarization process to remove excess material of one or more metal layers 1064 and gate dielectric layers 1062 located outside the gate trench. The result of the gate replacement process is that each gate stack 106 includes a gate dielectric layer 1062 and one or more metal layers 1064 surrounded by the gate dielectric layer 1062.

In some embodiments, the gate dielectric layer 1062 may include, for example, a high dielectric constant dielectric material, such as metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal silicon Acid salt, metal oxynitride, metal aluminate, zirconium silicate, zirconium aluminate, or a combination thereof. In some embodiments, the gate dielectric layer 1062 may include hafnium dioxide (HfO ₂ ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), tantalum hafnium oxide (HfTaO), hafnium oxide titanium (HfTiO) , Hafnium zirconia (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), strontium titanate (SrTiO ₃ , STO), barium titanium oxide (BaTiO ₃ , BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum oxide silicon (LaSiO), aluminum oxide silicon (AlSiO), aluminum oxide (Al ₂ O ₃ ) , Silicon nitride (Si ₃ N ₄ ), oxynitride (SiON) and combinations thereof. In some embodiments, the gate dielectric layer 1062 may have a multi-layer structure, such as a layer of silicon oxide (eg, an interface layer) and another layer of high dielectric constant material.

In some embodiments, the metal layer 1064 is a multilayer structure including one or more work function metal layers and a filler metal surrounded by the one or more work function metal layers. The one or more work function metal layers may include one or more n-type work function metals and/or one or more p-type work function metals. The n-type work function metal may exemplarily include, but not limited to, titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti ), tantalum (Ta), aluminum (Al), metal carbides (eg, hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides and/or other suitable s material. The p-type work function metal may exemplarily include, but not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co ), nickel (Ni), conductive metal oxides and/or other suitable materials. Filler metals can exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tantalum carbide (TaC), tantalum silicon nitride ( TaSiN), tantalum nitride carbide (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN) or other suitable materials.

Returning to FIG. 1, the method M1 then proceeds to block S102 to form a first etch stop layer (ESL), a second interlayer dielectric layer, and a second etch on the transistor and the first interlayer dielectric layer Stop layer, hard mask layer and three-layer photomask. Referring to FIGS. 3A to 3C, in some embodiments of block S102, a first etch stop layer 114 and a second interlayer dielectric layer are sequentially formed on the first interlayer dielectric layer 112 and the gate stack 106 116. A second etch stop layer 118, a hard mask layer 120, and a three-layer photoresist mask 122. In some embodiments, the first etch stop layer 114 may include a nitride material, such as silicon nitride, titanium nitride, or the like, and may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition. In some embodiments, the second interlayer dielectric layer 116 may include the same material as the first interlayer dielectric layer 112, and may be formed using, for example, chemical vapor deposition, atomic layer deposition, spin on glass, or other suitable techniques . For example, the second interlayer dielectric layer 116 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric Constant dielectric materials and/or other suitable dielectric materials. Examples of low dielectric constant dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous carbon fluoride, parylene, dibenzo ring Butene (bis-benzocyclobutenes, BCB) or polyimide. The second interlayer dielectric layer 116 has a faster etch rate than the first etch stop layer 114, so that the first etch stop layer 114 can slow down or even stop the etching process performed on the second interlayer dielectric layer 116.

In some embodiments, the second etch stop layer 118 may include a carbide material (eg, tungsten carbide) and may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition. In some embodiments, the hard mask layer 120 may include an oxide material (e.g., silicon oxide), and may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition. The three-layer photoresist mask 122 includes a bottom layer 1222 above the hard mask layer 120, an intermediate layer 1224 above the bottom layer 1222, and a top layer 1226 above the intermediate layer 1224. In some embodiments, the bottom layer 1222 may include an organic material (eg, spin-on carbon (SOC) material or the like) and may use spin-on coating, chemical vapor deposition, atomic Layer deposition or similar methods. The intermediate layer 1224 may include an inorganic material, which may be nitride (for example, silicon nitride (SiN), titanium nitride (TiN), tantalum nitride (TaN), or the like), oxynitride (for example, silicon oxynitride (SiON)), oxide (for example, silicon oxide), or the like, and can be formed using chemical vapor deposition, atomic layer deposition, or the like. The top layer 1226 may include an organic material (for example, a photoresist material) and may be formed using spin coating or the like. In some embodiments, the middle layer 1224 has a faster etch rate than the top layer 1226, and the top layer 1226 can be used as an etch mask for patterning the middle layer 1224. In some embodiments, the bottom layer 1222 has a faster etch rate than the middle layer 1224, and the middle layer 1224 can be used as an etch mask for patterning the bottom layer 1222.

Returning to FIG. 1, the method M1 then proceeds to block S103, where a first opening is formed in the top layer of the three-layer photoresist mask and above the corresponding source/drain regions. Referring to FIGS. 4A to 4C, in some embodiments of block S103, the top layer 1226 of the three-layer photoresist mask 122 is patterned using a suitable photolithography technique to form in the patterned top layer 1226′ and A first opening O11 is formed vertically above the corresponding source/drain region 110. In some embodiments where the top layer 1226 includes photoresist material, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. For example, a reticle or reticle (not shown) may be disposed on the top photoresist layer 1226, and then it may be exposed to a radiation beam, which may be ultraviolet (UV) or excimer mine Excimer laser (for example, Krypton Fluoride (KrF) excimer laser or Argon Fluoride (ArF) excimer laser). An immersion lithography system can be used to perform the exposure of the top photoresist layer 1226 to increase resolution and reduce the minimum achievable pitch. A baking or curing operation may be performed to harden the top photoresist layer 1226, and a developer may be used to remove exposed or unexposed portions of the top photoresist layer 1226 depending on whether a positive or negative photoresist is used. Therefore, the first opening O11 as shown in FIGS. 4A to 4C may be formed in the patterned top photoresist layer 1226′.

These first openings O11 in the patterned top layer 1226' are used to define a pattern of source/drain contact openings, which will be formed in the first interlayer dielectric layer 112 in the following steps. As shown in FIG. 4A, each first opening O11 has a length L11 in the direction Y and a width W11 in the direction X, and the length L11 is greater than the width W11. Therefore, the length of the subsequently formed source/drain contact opening in direction Y will be greater than the width in direction X, which will result in an increase in the source/drain contact area while preventing the source/drain contact from contacting the gate Stack 106, which will be discussed further below. In some embodiments, the width W11 is greater than about 10 nanometers (nm). If the width W11 is less than about 10 nanometers, the result of subsequent directional deposition and/or directional etching using directional ions may be unsatisfactory.

Returning to FIG. 1, method M1 then proceeds to block S104, using a three-layer photoresist mask as an etch mask to pattern the hard mask layer to form a bottom layer that passes through the hard mask layer and the bottom layer of the three-layer photoresist mask Second opening. Referring to FIGS. 5A to 5C, in some embodiments of block S104, a patterning process is performed on the hard mask layer 120 to transfer the pattern of the first opening O11 in the patterned top photoresist layer 1226′ To the hard mask layer 120, thereby creating a second opening O12 in the hard mask layer 120'. In some embodiments, the patterning process includes one or more etching processes, wherein the three-layer photoresist mask 122 is used as an etching mask. The one or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof. During the patterning process, the patterned top layer 1226' and the middle layer 1224 of the three photoresist masks 122 may be consumed, and a portion of the bottom layer 1222 may be retained after the patterning process. As such, the patterning process also generates a patterned bottom layer 1222' above the patterned hard mask layer 120'. In some embodiments, the combined thickness of the patterned bottom layer 1222' and the patterned hard mask layer 120' is in the range of about 20 nanometers to about 150 nanometers. If the combined thickness of the patterned bottom layer 1222' and the patterned hard mask layer 120' is outside this range, the results of subsequent use of directional deposition and/or directional etching may be unsatisfactory.

Because the patterned process is performed using the patterned top photoresist layer 1226' (as shown in FIG. 4A) as an etch mask, the patterned bottom layer 1222' and the patterned hard mask layer 120' inherit the top photoresist layer The pattern in 1226. As such, the second opening O12 extending through the patterned bottom layer 1222' and the patterned hard mask layer 120 may have substantially the same as the first opening O11 in the corresponding patterned top photoresist layer 1226' Shape, size and spacing. For example, each second opening O12 has a length L12 in the direction Y and a width W12 in the direction X, and the length L12 is greater than the width W12. The pattern of the second opening O12 vertically above the corresponding source/drain region 110 can be transferred to the underlying first interlayer dielectric layer 112 in the following steps, so the second opening O12 can be used to define the first opening The pattern of source/drain contact openings in the interlayer dielectric layer 112. As a result, the length of the subsequently formed source/drain contact opening in direction Y will be greater than the width in direction X.

The length L12 of the second opening O12 in the direction Y is positively related to the source/drain contact area. In other words, the longer the length L12 of the second opening O12, the larger the source/drain contact area. Therefore, one or more lateral etching processes may be used to extend the second opening O12 in the direction Y. However, if the patterned bottom layer 1222' and the patterned hard mask layer 120' undergo one or more lateral etching processes, the second opening O12 will inevitably extend in the direction X and the direction Y, which will cause the first The increase in the width W12 of the two openings O12 may also cause damage to the gate stack 106 disposed along the direction X during the transfer of the pattern of the extended second opening O12 to the first interlayer dielectric layer 112. Therefore, in some embodiments of the present disclosure, a directional deposition process having a faster deposition rate in the direction X than in the direction Y is performed on the wafer WA (block S105 of method M1), followed by the direction Y A directional etching process with a faster etching rate than in the direction X (block S106 of method M1). In this way, the second opening O12 may be extended in the direction Y but not substantially extended in the direction X (please refer to the more detailed description below).

Returning to FIG. 1, the method M1 then proceeds to block S105 to form a protective layer on the first sidewall of the second opening. Referring to FIGS. 6A to 6C, in some embodiments of block S105, a directional deposition process is performed to form a protective layer 124 on the first sidewall O121 of the second opening O12′ extending in the direction Y, and substantially The protective layer 124 is not formed on the second sidewall O122 of the second opening O12' extending in the direction X. The directional deposition process is performed using directional ions extracted from the plasma, and is directed to the wafer WA at a non-zero angle relative to the perpendicular to the wafer surface (please refer to the more detailed description below).

FIG. 38 shows a schematic side view of a plasma tool 900 capable of performing a directional deposition process and a directional etching process according to some embodiments of the present disclosure. The plasma tool 900 includes a plasma source 902 that includes a plasma cavity 904 to accommodate the plasma 906. Plasma cavity 904 may generate plasma 906, however, it should be understood that when power is supplied to plasma cavity 904 and an appropriate gaseous substance, plasma 906 is generated. The gas source 914 is connected to the plasma source 902, more specifically to the plasma cavity 904, to provide a gaseous substance for generating the plasma 906. In some embodiments, the gas source 914 may represent multiple independent gas sources.

The plasma source 902 or other elements of the plasma tool 900 may also be connected to a pump (not shown), such as a turbo pump. The plasma source 902 generating the plasma 906 may be, for example, a radio frequency plasma source, an inductively-coupled plasma (ICP) source, a capacitively-coupled plasma (CCP) source, or an indirectly heated cathode (indirectly heated) heated cathode, IHC) or other suitable plasma source. In some embodiments, the plasma source 902 is a radio frequency plasma source with a power source 908 and a radio frequency inductor 912 to generate inductively coupled plasma. In some embodiments, the housing 910 surrounds the plasma source 902.

Adjacent to the plasma cavity 904 is a process cavity 916, which accommodates the wafer WA during substrate processing. An extraction plate 920 is provided to extract ions 922a and 922b from the plasma 906 and guide the ions 922a and 922b to the wafer WA, where the ions 922a and 922b have different trajectories. Further, the extraction plate 920 has an extraction hole 930 that generates ions 922a and 922b that form an incident angle θ with respect to a vertical line 917 of the plane WAP of the wafer WA (ie, the top surface of the wafer WA). In this way, the extraction plate 920 can produce an ion distribution 921 (as shown in FIG. 39), which has a bimodal distribution with an incident angle centered at zero degrees, of which two peaks (peak 923 and peak 925 ) Are located on opposite sides of zero degrees. The process cavity 916 includes a platform 926 that is configured to support the wafer WA. The platform 926 may be connected to the driving mechanism 927 so that the platform 926 can move in one or more of the direction X, the direction Y, and the direction Z, and rotate about an axis 929 that supports the platform 926 extending in the direction Z. In some embodiments, the platform 926 can be moved in the direction X and/or the direction Y so that the wafer WA is scanned relative to the extraction hole 930. In some embodiments, the extraction hole 930 may be an extended extraction hole, which has a longer dimension in the direction Y relative to the direction X. In this configuration, the wafer WA may be scanned along the direction X in order to expose the entire wafer WA to the ions 922a and 922b extracted from the plasma 906. In other embodiments, the extraction holes may have different shapes, or the extraction plate may include a plurality of extraction holes.

As shown in FIG. 38, the positioning of the extraction plate 920 and the extraction hole 930 can produce a plasma sheath boundary 932 having a curvature. In the depicted embodiment, the plasma sheath boundary 932 has a concave shape relative to the plane WAP of the wafer WA (ie, the top surface of the wafer WA) and the plane 936 relative to the extraction plate 920. This curvature results in the extraction of ions 922a and 922b from the plasma 906 at the plasma sheath boundary 932, where the ion trajectory may deviate from normal incidence of the plane WAP relative to the wafer WA. By changing the plasma process conditions of the plasma tool 900, the shape and curvature of the plasma sheath boundary 932 can be changed, resulting in control of the ion trajectory. This may allow control of ions relative to features on the wafer WA to be processed (eg, the second opening in the patterned hard mask layer 120' and the patterned bottom layer 1222' shown in FIGS. 5A-5C O12) directivity or angle of incidence.

As shown in FIG. 38, the ion 922a and the ion 922b extracted from the plasma 906 may be provided with a specific ion direction. The directivity of the ion 922a and the ion 922b (for example, the angle of incidence of the ion 922a and the ion 922b with respect to the reference direction (for example, the vertical line of the wafer WA)) can be transmitted using radio frequency from the plasma source such as the width of the extraction hole 930 Power (ie, the combination of power supply 908 and RF inductor 912), gas pressure of gas from gas source 914, extraction voltage applied between plasma chamber 904 and wafer WA (eg, from pulsed DC bias) The voltage of the source 938) and so on. The ions can be controlled in such a way that the ion trajectory extends in the direction X and the direction Z of FIG. 38, but does not substantially extend in the direction Y. This control of ion directivity therefore helps to selectively process (eg, form a polymer or etch) the surface on the wafer WA that needs to be processed, while not substantially processing other surfaces.

Returning to FIGS. 6A to 6C, directional ions (for example, ions 922a and 922b as shown in FIG. 38) may be used to perform a directional deposition process, resulting in a more directional X direction than a Y direction. The fast deposition rate allows the side wall O121 in direction Y to have more polymer deposited than the side wall O122 in direction X, as shown in FIG. 6A. Further, ions may be guided to the first side wall O121 of the second opening O12', but not substantially to the second side wall O122 of the second opening O12'. For example, the ratio of the deposition rate in direction X to the deposition rate in direction Y is in the range of about 10:1 to about 30:1. In some embodiments, the process conditions are selected so that the polymerization phenomenon caused by ions is more dominant than the etching phenomenon caused by ions, so that ions 922a and 922b are directed toward the first sidewall O121 of the second opening O12' but are not substantially directed toward the first At the second side wall O122 of the two openings O12', this will cause the polymer to be deposited on the first side wall O121, but not substantially deposited on the second side wall O122. These deposited polymers may be referred to as protective layers (or polymer layers) 124.

In some embodiments, the directional deposition process may be performed using methane (CH ₄ ), silicon tetrachloride (SiCl ₄ ), oxygen (O ₂ ), nitrogen (N ₂ ), hydrogen bromide (HBr), trichloro Boron trioxide (BCl ₃ ) or a combination of the above, wherein the process gas used has a pressure in the range of about 0.1 mTorr to about 20 mTorr, RF power in the range of about 100 W to about 2000 W, and a bias voltage of about 0 to about 5 kV, the volume flow rate is in the range of about 1 sccm to about 100 sccm. If the process conditions exceed the above-mentioned selected range, the directional deposition phenomenon may be unsatisfactory. In some embodiments where a gas including methane (CH ₄ ) is used for the directional deposition process, the resulting protective layer 124 includes a carbon-containing polymer. In some embodiments where a gas including silicon tetrachloride (SiCl ₄ ), boron trichloride (BCl ₃ ), or a combination thereof is used for the directional deposition process, the resulting protective layer 124 includes a chlorine-containing polymer. In some embodiments where a gas including hydrogen bromide (HBr) is used for the directional deposition process, the resulting protective layer 124 includes a bromine-containing polymer.

Due to the directional deposition, the length L12' of the second opening O12' in the direction Y remains substantially the same as the length L12 of the second opening O12 (as shown in FIG. 5A), but the width of the second opening O12' in the direction X W12' is smaller than the width W12 of the second opening O12. The difference between the width W12' of the second opening O12' after directional deposition and the width W12 of the second opening O12 before directional deposition is substantially twice the thickness of the protective layer 124. In some embodiments, directional deposition results in the deposition of polymer above the top surface of the patterned bottom layer 1222', such that the protective layer 124 extends on the top surface of the patterned bottom layer 1222'. In some embodiments, the second etch stop layer 118 at the bottom of the second opening O12' may not be covered by the protective layer 124 (ie, polymer) due to the shadowing effect caused by the inclined trajectories of directional ions.

Returning to FIG. 1, the method M1 then proceeds to block S106, and the second sidewall of the second opening is etched to extend the second opening. In some embodiments of block S106, a directional etching process is performed on the second sidewall O122 of the second opening O12', resulting in an elongated opening O12" as shown in FIGS. 7A to 7C. Performed using directional ions Directional etching process. For example, the plasma tool 900 shown in FIG. 38 may be used to perform the directional etching process (please refer to the detailed description below).

After performing the directional deposition process on the wafer WA in the plasma tool 900, the wafer WA may be rotated about the direction Z axis 929 by about 88 degrees to about 92 degrees (for example, about 90 degrees). In this way, the second side wall O122 of the second opening O12' may be arranged in the direction X in FIG. 38. After rotating the wafer WA, the ions 922a and 922b may be extracted and guided to the wafer WA. Since the trajectories of the ions 922a and 922b extend in the direction X and the direction Z in FIG. 38 but do not substantially extend in the direction Y, the ions 922a and 922b may point to the second side wall O122 of the second opening O12' The top does not point to the protective layer 124 along the first sidewall O121 of the second opening O12'. In some embodiments, the process conditions are selected so that the ion-induced etching phenomenon is more dominant than the ion-induced polymerization phenomenon. Therefore, ion 922a and ion 922b can be used to perform a directional etching process that has a faster etching rate in direction X than in direction Y in FIG. 38. For example, the ratio of the etching rate in the direction X to the etching rate in the direction Y is in the range of about 10:1 to about 30:1. Therefore, the ions 922a and 922b may point to the second side wall O122 of the second opening O12', but do not substantially point to the first side wall O121 of the second opening O12', thus causing the second side wall O122 to be etched, but not substantially along the edge The protective layer 124 of the first side wall O121. In this way, the directional etching process can extend the second opening O12' by etching the second side wall O122 without substantially etching the first side wall O121, resulting in an extended opening O12" as shown in FIGS. 7A to 7C .

In some embodiments, the etch resistance of the protection layer 124 to the directional etching process is higher than that of the patterned bottom layer 1222' and the patterned hard mask layer 120', so that the protection layer 124 can protect the first sidewall O121 Free from directional etching process. In some embodiments, fluoromethane (CH ₃ F), trifluoromethane (CHF ₃ ), methane (CH ₄ ), carbon tetrafluoride (CF ₄ ), difluoroacetylene (C ₂ F ₂ ), Sulfur dioxide (SO ₂ ), sulfur hexafluoride (SF ₆ ), oxygen (O ₂ ), nitrogen (N ₂ ), nitrogen trifluoride (NF ₃ ), chlorine (Cl ₂ ), boron trichloride (BCl ₃ ) , Silicon tetrachloride (SiCl ₄ ), hydrogen bromide (HBr), helium (He), argon (Ar), krypton (Kr) or a combination of the above gases to perform a directional etching process, wherein the pressure of the process gas used In the range of about 0.1 mTorr to about 10 mTorr, the RF power is in the range of about 100 W to about 2000 W, the bias voltage is in the range of about 0 to about 10 kV, and the gas flow rate is in the range of about 1 sccm to about 100 sccm. If the process conditions exceed the selected range, the directional etching phenomenon may be unsatisfactory. The process gas and/or other process conditions of the directional etching process are different from the process gas and/or other process conditions of the directional deposition process.

7A, due to directional etching, the length L12" of the extended opening O12' is greater than the length L12' of the second opening O12' (as shown in FIG. 6A), but the width W12" of the extended opening O12" remains the same as the first The width W12' of the two openings O12' is substantially the same. Because the extended opening O12" has an increased length, the subsequently formed source/drain contacts inheriting the pattern of the extended opening O12" may have an increased in direction Y Length, which results in an increased source/drain contact area. In addition, since the extension process does not increase the width of the opening O12', the source/drain contact that is subsequently formed to inherit the pattern of the extended opening O12" will be in contact with the gate The electrode stack 106 is separated, thereby preventing an unwanted short circuit between the source/drain contact and the gate stack 106. An exemplary ratio of the resulting length L12" to the resulting width W12" is in the range of about 2.7:1 to about 4.6:1, which is higher than the length L11 of the patterned photoresist layer 1226' shown in FIG. 4A and The ratio of the width W11.

In some embodiments, the directional etching process of block S106 may be performed in situ using the directional deposition process of block S105, which will prevent contamination of the wafer WA. As used herein, the term "in situ" is used to describe a device or substrate that remains in the process system (eg, including a wafer load/unload chamber, a transfer chamber, a processing chamber, or Any other process performed in a fluidly coupled chamber, for example, the process system allows the substrate to be kept under vacuum. Therefore, the term "in situ" can also be used to refer to the process of processing a device or substrate without being exposed to an external environment (eg, outside the process system). For example, as shown in FIG. 38, the directional deposition of block S105 is performed in the plasma tool 900, and then the wafer WA in the plasma tool 900 is rotated around the axis 929 using the driving mechanism 927. Thereafter, the directional etching process of block S106 is performed in the plasma tool 900. In this way, no vacuum break occurs from block S105 to block S106.

Returning to FIG. 1, the method M1 then proceeds to block S107, transferring the pattern of the extended second opening to the underlying layer to form the source/drain contact opening. Referring to FIGS. 8A to 8C, in some embodiments of block S104, for the second etch stop layer 118, the second interlayer dielectric layer 116, the first etch stop layer 114, and the first interlayer dielectric layer 112 performs a patterning process to transfer the pattern of elongated openings O12" to these layers to form source/drain contact openings O13 and expose source/drain regions 110. In some embodiments, The patterning process includes one or more etching processes, wherein the combination of the protective layer 124, the patterned bottom layer 1222', and the patterned hard mask layer 120' serves as an etching mask. One or more etching processes may include anisotropy Wet etching process, anisotropic dry etching process or a combination of the above. During the patterning process, the protective layer 124, the patterned bottom layer 1222' and the patterned hard mask layer 120' may be consumed. In some implementations For example, a suitable etchant may be used to remove the remaining portion of the protective layer 124, the patterned bottom layer 1222', and the patterned hard mask layer 120'.

Due to the patterning process, the source/drain contact opening O13 inherits the extended opening O12" pattern (as shown in FIGS. 7A to 7C). Further, the length L13 of the source/drain contact opening O13 The length L12" of the extended opening O12 is substantially the same, and the width W13 of the source/drain contact opening O13 is substantially the same as the width W12" of the extended opening O12". As shown in FIG. 8B, the width W13 of the source/drain contact opening O13 is controlled so that the gate stack 106 disposed on the opposite side of the source/drain contact opening O13 along the direction X is not affected by the source/ The drain contact opening O13 is exposed. This will help prevent damage to the gate stack 106 caused by the etchant used in the patterning process.

Returning to FIG. 1, the method M1 then proceeds to block S108, where the source/drain contact opening is filled with conductive material. Referring to FIGS. 9A to 9C, in some embodiments of block S108, one or more conductive materials 126 are deposited on the wafer WA and overfill the source/drain contact opening O13. The one or more conductive materials 126 include, for example, any suitable metal (eg, cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), and/or nickel (Ni) and/or titanium (Ti) or tantalum (Ta) nitride).

Returning to FIG. 1, method M1 then proceeds to block S109, where the conductive material is planarized to form source/drain contacts. Referring to FIGS. 10A to 10C, in some embodiments of block S109, a chemical mechanical planarization process is performed to remove excess conductive material 126 outside the source/drain contact opening O13 until reaching the second interlayer dielectric layer 116. The conductive material 126 remaining in the source/drain contact opening O13 may serve as the source/drain contact 128 in contact with the corresponding source/drain region 110.

Since the source/drain contact opening O13 fills the source/drain contact 128, the source/drain contact 128 inherits the pattern of the source/drain contact opening O13 (as shown in FIGS. 8A to 8C) . Further, the length L14 of the source/drain contact 128 is substantially the same as the length L13 of the source/drain contact opening O13, and the width W14 of the source/drain contact 128 and the source/drain contact opening O13 The width W13 is substantially the same. The width W14 of the source/drain contact 128 is controlled so that the source/drain contact 128 is separated from the gate stack 106, and the length L14 of the source/drain contact 128 is controlled so that the source/drain contact 128 and the source The contact area between the pole/drain regions 110 can be increased.

The directional deposition process and directional etching process described above used to form the extended source/drain contacts can also be used to form other extended features. For example, please refer to FIGS. 11A and 11B, which illustrates a method M2, which includes using the directional deposition process and the directional etching process as described above to form an extended gate contact and an extended source/drain via. FIGS. 12A to 22D illustrate various processes at various stages of the method M2 of FIGS. 11A and 11B according to some embodiments of the present disclosure. In various views and illustrative embodiments, the same reference numerals are used to represent the same elements. In Figures 12A to 22D, "A" (eg, 12A, 13A, etc.) shows a top view, "B" (eg, 12B, 13B, etc.) shows along A cross-sectional view corresponding to the direction X of the line BB shown in the "A" drawing, and the "C" drawing (eg, FIG. 12C, FIG. 13C, etc.) is drawn along the line CC corresponding to the "A" The cross-sectional view in the direction Y of FIG. 3, the "D" drawing (for example, FIG. 17D, FIG. 21D, etc.) shows a cross-sectional view along the direction Y corresponding to the line DD shown in the "A" drawing. It should be understood that additional steps may be provided before, during, and after the processes shown in FIGS. 12A to 22D, and some of the steps described below may be replaced or eliminated as other embodiments for this method. The order of steps/processes can be interchangeable.

As shown in FIGS. 12A to 12C, the semiconductor wafer WA2 is substantially similar to the semiconductor wafer WA in many respects, and includes a substrate 202, a semiconductor fin 204, a shallow trench isolation 205, and a gate dielectric layer 2062 And the gate stack 206 of the metal layer 2064, the gate spacer 208, the source/drain region 210, the first interlayer dielectric layer 212, the first etch stop layer 214, and the second interlayer dielectric layer 216, each Substantially as described above with respect to substrate 102, semiconductor fins 104, shallow trench isolation 105, gate stack 106 with gate dielectric layer 1062 and metal layer 1064, gate spacer 108, source/drain regions 110, a first interlayer dielectric layer 112, a first etch stop layer 114, and a second interlayer dielectric layer 116. The semiconductor wafer WA2 also includes source/drain contacts 228. In some embodiments, the source/drain contact 228 is formed using an extended process involving the directional deposition process and the directional etching process as described above with respect to the source/drain contact 128. In some other embodiments, the source/drain contact 228 is formed without using a directional deposition process and a directional etching process, and thus may have a different shape from the source/drain contact 128.

In block S201, an appropriate deposition technique is used to sequentially form an etch stop layer 230 and a third interlayer dielectric layer 232 and a first three-layer photoresist on the source/drain contact 228 and the second interlayer dielectric layer 216 Mask 234. In some embodiments, the etch stop layer 230 may include a nitride material (eg, silicon nitride, titanium nitride, or the like) and may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition. The third interlayer dielectric layer 232 can be formed using, for example, chemical vapor deposition, atomic layer deposition, spin-on-glass (SOG), or other suitable techniques, and includes the first interlayer dielectric layer 212 and /Or the second interlayer dielectric layer 216 is the same material, therefore, for the sake of brevity, the description about the third interlayer dielectric layer 232 will not be repeated here. The first three-layer photoresist mask 234 includes a bottom layer 2342, an intermediate layer 2344, and a top layer 2346, respectively similar to the bottom layer 1222, the middle layer 1224, and the top layer of the three-layer photoresist mask 122 previously discussed with respect to FIGS. 3A to 3C. 1226. Therefore, for the sake of brevity, the description about the bottom layer 2342, the middle layer 2344, and the top layer 2346 will not be repeated here.

In block S202, a first opening O21 is formed in the top layer 2346 and above the gate stack 206. The formation of the first opening O21 includes exposing the top layer 2346 and developing the top layer 2346 to remove part of the top layer (as previously discussed with reference to FIGS. 4A to 4C). The first opening O21 in the top photoresist layer 2346 is used to define the pattern of the gate contact opening to be formed in the second interlayer dielectric layer 216 in the following steps. As shown in FIG. 12A, the first opening O21 has a length L21 in the direction Y and a width W21 in the direction X, and the length L21 is greater than the width W21. Therefore, the length of the subsequently formed gate contact opening in direction Y will be greater than the width in direction X, which will result in an increase in the gate contact area while preventing the gate contact from contacting the source/drain contact 228, which will This is discussed in more detail below.

Returning to FIG. 11A, method M2 then proceeds to block S203, using the first three-layer photoresist mask as an etch mask to pattern the third interlayer dielectric layer to form a second opening. Referring to FIGS. 13A to 13C, in some embodiments of block S203, a patterning process is performed on the third interlayer dielectric layer 232 to pattern the first opening O21 in the patterned top photoresist layer 2346 Transferred to the third interlayer dielectric layer 232, thereby creating a second opening O22 in the third interlayer dielectric layer 232'. In some embodiments, the patterning process includes one or more etching processes, wherein the three-layer photoresist mask 234 serves as an etching mask. The one or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof. During the patterning process, the patterned top layer 2346 and the middle layer 2344 of the photoresist mask 234 may be consumed, and a portion of the bottom layer 2342 may be retained after the patterning process. In this way, the patterning process also creates a patterned bottom layer 2342' on the patterned interlayer dielectric layer 232'.

The patterned bottom layer 2342' and the patterned interlayer dielectric layer 232' inherit the pattern in the top photoresist layer 2346, so the second opening O22 has substantially the same as the first opening O21 in the patterned top photoresist layer 2346 Same shape, size and location. For example, the second opening O22 has a length L22 in the direction Y, a width W22 in the direction X, and the length L22 is greater than the width W22. The pattern of the second opening O22 perpendicular to the gate stack 206 can be transferred to the underlying second interlayer dielectric layer 216 in the following steps, so the second opening O22 can be used to define the gate in the second interlayer dielectric layer 216 The pattern of the pole contact opening. In this way, the length of the subsequently formed gate contact opening in direction Y will be greater than the width in direction X.

The length L22 of the second opening O22 in the direction Y is positively related to the gate contact area. In other words, the greater the length L22 of the second opening O22, the greater the gate contact area. Therefore, one or more lateral etching processes may be used to extend the second opening O22 in the direction Y. However, if the patterned bottom layer 2342' and the third interlayer dielectric layer 232' undergo one or more lateral etching processes, the second opening O22 will inevitably extend in both the direction X and the direction Y, which will cause the first The increase in the width W22 of the two openings O22 may cause damage to the source/drain contacts 228 arranged along the direction X during the process of transferring the pattern of the extended second opening O22 to the second interlayer dielectric layer 216 . Therefore, in some embodiments of the present disclosure, a directional deposition process having a faster deposition rate in direction X than in direction Y is performed on wafer WA2 (block S204 of method M2), and then performed in direction Y A directional etching process with a faster etching rate than in the direction X (block S205 of method M2). In this way, the second opening O22 may be extended in the direction Y but not substantially extended in the direction X (please refer to the more detailed description below).

Referring to FIGS. 14A to 14C, in some embodiments of block S204, a directional deposition process is performed to form a protective layer 236 on the first sidewall O221 of the second opening O22′ extending in the direction Y, and is not substantially in A protective layer 236 is formed on the second sidewall O222 of the second opening O22' extending in the direction X. The directional deposition process using directional ions produces a faster deposition rate in direction X than in direction Y, so that the side wall O221 of direction Y as shown in FIG. 14A can be the side wall of direction X shown in FIG. 14A O222 deposits more polymers (eg, carbon-containing polymers, chlorine-containing polymers, and/or bromine-containing polymers). In some embodiments, the ratio of the deposition rate in direction X to the deposition rate in direction Y is in the range of about 10:1 to about 30:1.

For example, the plasma tool 900 shown in FIG. 38 may be used to perform the directional deposition process. Further, the ions 922a and 922b can be extracted and guided to the wafer WA2. As described above, in FIG. 38, since the trajectories of the ion 922a and the ion 922b can be controlled to extend in the direction X and the direction Z, but not substantially extend in the direction Y, the ion 922a and the ion 922b can point to the One side wall O221 does not substantially point to the second side wall O222. In some embodiments, the process conditions are selected so that the polymerization phenomenon caused by ions is more dominant than the etching phenomenon caused by ions, so that ions 922a and 922b are directed toward the first sidewall O221 of the second opening O22' and are not substantially directed toward the first The second side wall O222 of the two openings O22' thus causes the polymer to be deposited on the first side wall O221, but is not substantially deposited on the second side wall O222. These deposited polymers may be referred to as protective layers (or polymer layers) 236. In some embodiments, the process conditions of the directional deposition process are similar to the process conditions of the directional deposition process previously discussed with respect to FIGS. 6A to 6C, so for the sake of brevity, they are not repeated here.

Due to the directional deposition, the length L22' of the second opening O22' in the direction Y remains substantially the same as the length L22 of the second opening O22 (as shown in FIG. 13A), and the width of the second opening O22' in the direction X W22' is smaller than the width W22 of the second opening O22. The difference between the width W22' of the second opening O22' after directional deposition and the width W22 of the second opening O22 before directional deposition is substantially twice the thickness of the protective layer 236. In some embodiments, the directional deposition results in the polymer being deposited over the top surface of the patterned bottom layer 2342' such that the protective layer 236 extends on the top surface of the patterned bottom layer 2342'. In some embodiments, the etch stop layer 230 at the bottom of the second opening O22' may not be covered by the protective layer 236 (ie, polymer) due to the shadowing effect caused by the inclined trajectory of directional ions.

Returning to FIG. 11A, method M2 then proceeds to block S205, where the second sidewall of the second opening is etched to extend the second opening. In some embodiments of block S205, a directional etching process is performed on the second sidewall O222 of the second opening O22', resulting in an extended opening O12" as shown in FIGS. 15A to 15C. Performed using directional ions Directional etching process. For example, as described in detail below, the plasma tool 900 shown in FIG. 38 may be used to perform the directional etching process.

After performing the directional deposition process on the wafer WA2 in the plasma tool 900, the wafer WA2 may be rotated about the direction Z axis 929 by about 88 degrees to about 92 degrees (for example, about 90 degrees). In this way, the second sidewall O222 of the second opening O22' may be arranged in the direction X in FIG. 38. After rotating the wafer WA, the ions 922a and 922b may be extracted and guided to the wafer WA2. Since the trajectories of the ions 922a and 922b extend in the direction X and the direction Z in FIG. 38 but do not substantially extend in the direction Y, the ions 922a and 922b may point to the second sidewall O222 of the second opening O22' The top does not point to the protective layer 236 along the first sidewall O221 of the second opening O22'. In some embodiments, the process conditions are selected so that the ion-induced etching phenomenon is more dominant than the ion-induced polymerization phenomenon. Therefore, ion 922a and ion 922b can be used to perform a directional etching process that has a faster etching rate in direction X than in direction Y in FIG. 38. For example, the ratio of the etching rate in the direction X to the etching rate in the direction Y is in the range of about 10:1 to about 30:1. Further, the ions 922a and 922b may point to the second side wall O222 of the second opening O12' but not substantially point to the first side wall O221 of the second opening O12', thus causing the second side wall O222 to be etched without being substantially etched The protective layer 236 along the first sidewall O221. In this way, the directional etching process can extend the second opening O22' by etching the second side wall O222 without substantially etching the first side wall O221, thereby creating an extended opening O12" as shown in FIGS. 15A to 15C In some embodiments, the process conditions of the directional etching process are similar to the process conditions of the directional etching process previously discussed with respect to FIGS. 7A to 7C, so for the sake of brevity, they are not repeated here.

Referring to Fig. 15A, as a result of directional etching, the length L22" of the extended opening O22" is greater than the length L22' of the second opening O22' (as shown in Fig. 14A), and the width W22" of the extended opening O22" The width W22' of the second opening O22' is substantially the same. Because the extended opening O22" has an increased length, the gate contact formed subsequently to inherit the pattern of the extended opening O22" may have an increased length in the direction Y, resulting in an increase in the gate contact area. In addition, because the extension process does not increase the width of the opening O22', the gate contact formed subsequently to inherit the pattern of the extended opening O22" will be separated from the source/drain contact 228, thereby preventing the gate contact and the source/ An undesirable short circuit between drain contacts 228. An example ratio of the resulting length L22" to the resulting width W22" is in the range of about 2.7:1 to about 4.6:1. In some embodiments, block S204 may be utilized The directional deposition process of the in-situ process performs the directional etching process of block S205 to prevent contamination of the wafer WA2.

Returning to FIG. 11A, method M2 then proceeds to block S206, transferring the pattern of the elongated opening to the underlying layer to form the gate contact opening. Referring to FIGS. 16A to 16C, in some embodiments of block S206, a patterning process is performed on the etch stop layer 230, the second interlayer dielectric layer 216, and the first etch stop layer 114 to extend the extended opening O22 The pattern of "is transferred to these layers to create gate contact openings O23 in these layers and expose the gate metal layer 2064. In some embodiments, the patterning process includes one or more etching processes, in which the protective layer 236, The combination of the patterned bottom layer 2342' and the patterned interlayer dielectric layer 232' serves as an etching mask. One or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof During the patterning process, the patterned bottom layer 2342' may be consumed. In some embodiments, a suitable etchant may be used to remove the remaining portion of the patterned bottom layer 2342'.

As a result of the patterning process, the gate contact opening O23 inherits the pattern of the extended opening O22" (as shown in FIGS. 15A to 15C). Further, the length L23 of the gate contact opening O23 and the extended opening The length L22" of O22" is substantially the same, and the width W23 of the gate contact opening O23 is substantially the same as the width W22" of the extended opening O22". As shown in FIG. 16B, the width W23 of the gate contact opening O23 is controlled, The source/drain contacts 228 arranged on opposite sides of the gate contact opening O23 in the direction X will not be exposed by the gate contact opening O23. This will prevent the source/drain contacts 228 from being subjected to the patterning process Damage caused by the etchant used.

In some embodiments, the patterned third interlayer dielectric layer 232' remains above the etch stop layer 230, and a portion of the protective layer 236 remains on the first sidewall O231 of the gate contact opening O23 extending in the direction Y, and along The second sidewall O232 of the gate contact opening O23 extending in the direction X is not covered by the protective layer 236.

Returning to FIG. 11B, method M2 then proceeds to block S207, forming a second three-layer photoresist mask to overfill the gate contact opening. Referring to FIGS. 17A to 17D, a second three-layer photoresist mask 238 is formed on the wafer WA2 so that the gate contact opening O23 is overfilled with the bottom layer 2382 of the second three-layer photoresist mask 238. The second three-layer photoresist mask 238 includes a bottom layer 2382, an intermediate layer 2384, and a top layer 2386, which are respectively similar to the bottom layer 1222 and the middle layer 1224 of the three-layer photoresist mask 122 previously discussed with respect to FIGS. 3A to 3C. And the top floor 1226. Therefore, for the sake of brevity, the description about the bottom layer 2382, the middle layer 2384, and the top layer 2386 is not repeated.

In block S208, a third opening O31 is formed in the top layer 2386 and above the source/drain contacts 228. The formation of the third opening O31 includes exposing the top layer 2386 and developing the top layer 2386 to remove a portion of the top layer 2386, as previously discussed with respect to FIGS. 4A to 4C. The third opening O31 in the top photoresist layer 2386 is used to define a pattern of source/drain via openings to be formed in the patterned third interlayer dielectric layer 232' in the subsequent steps. As shown in FIG. 17A, each third opening O31 has a length L31 in the direction Y and a width W31 in the direction X, and the length L31 is greater than the width W31. Therefore, the length of the subsequently formed source/drain via opening in direction Y will be greater than the width in direction X, which will result in the contact area between the source/drain via and the source/drain contact The increase, while preventing contact, will then form the gate contact in the gate contact opening O23, which will be discussed in more detail below.

Returning to FIG. 11B, method M2 then proceeds to block S209, using the second three-layer photoresist mask as an etch mask to pattern the third interlayer dielectric layer to form a fourth opening. Referring to FIGS. 18A to 18C, in some embodiments of block S203, a patterning process is performed on the third interlayer dielectric layer 232′ to remove the third opening O31 in the patterned top photoresist layer 2386 The pattern is transferred into the third interlayer dielectric layer 232', thereby creating a fourth opening O32 in the third interlayer dielectric layer 232". It is worth noting that the third interlayer dielectric layer 232' undergoes two separate patterns Process, where the previous patterning process is used to form the gate contact opening, and the subsequent patterning process is used to form the source/drain via opening. In some embodiments, the patterning process includes one or more etchings Process, in which the second and third photoresist masks 238 are used as etching masks. One or more etching processes may include anisotropic wet etching process, anisotropic dry etching process or a combination of the above. In the patterning process During this period, the patterned top layer 2386, the middle layer 2384 of the photoresist mask 238 can be consumed, and a portion of the bottom layer 2382 can be retained after the patterning process. In this way, the patterning process is still in the patterned interlayer dielectric layer A patterned bottom layer 2382' is created above 232".

The patterned bottom layer 2382' and the patterned interlayer dielectric layer 232" inherit the pattern in the top photoresist layer 2386, so the fourth opening O32 and the third opening O31 in the patterned top photoresist layer 2386 substantially have The same shape, size and position. For example, the fourth opening O32 has a length L32 in the direction Y and a width W32 in the direction X, and the length L32 is greater than the width W32. The fourth perpendicular to the source/drain contact 228 The pattern of the opening O32 can be transferred to the underlying etch stop layer 230 in the following steps, so the fourth opening O32 can be used to define the pattern of the source/drain via opening. In this way, the subsequently formed source/drain The length of the pole via opening in direction Y will be greater than the width in direction X.

The length L32 of the fourth opening O32 in the direction Y is positively related to the contact area between the subsequently formed source/drain via and source/drain contact 228. In other words, the greater the length L32 of the fourth opening O32, the greater the contact area between the source/drain via and the source/drain contact 228 that are subsequently formed. Therefore, one or more lateral etching processes may be used to extend the fourth opening O32 in the direction Y. However, if the patterned bottom layer 2382' and the patterned third interlayer dielectric layer 232" undergo one or more lateral etching processes, the fourth opening O32 will inevitably extend in direction X and direction Y, which will This results in an increase in the width W32 of the fourth opening O32, which in turn may lead to an undesirable short circuit between the source/drain via and the gate contact subsequently formed in the gate contact opening O23. Therefore, some of the disclosure In an embodiment, a directional deposition process with a faster deposition rate in the direction X than in the direction Y is performed on the wafer WA2 (block S210 of the method M2), followed by performing in the direction Y with a faster deposition rate than in the direction X A faster etch rate directional etching process (block S211 of method M2). In this way, the fourth opening O32 can extend in the direction Y but not substantially extend in the direction X (please refer to the more detailed description below) .

Referring to FIGS. 19A to 19C, in some embodiments of block S210, a directional deposition process is performed to form a protective layer 240 on the first sidewall O321 of the fourth opening O32′ extending in the direction Y, and is not substantially in A protective layer 240 is formed on the second sidewall O322 of the fourth opening O32' extending in the direction X. The use of directional ions for the directional deposition process results in a deposition rate in direction X that is higher than the deposition rate in direction Y, so that the side wall O321 in direction Y as shown in FIG. 19A can be like the direction X shown in FIG. 19A The side wall O322 deposits more polymer (eg, carbon-containing polymer, chlorine-containing polymer, and/or bromine-containing polymer). In some embodiments, the ratio of the deposition rate in direction X to the deposition rate in direction Y is in the range of about 10:1 to about 30:1.

For example, the plasma tool 900 shown in FIG. 38 may be used to perform the directional deposition process. Further, the ions 922a and 922b can be extracted and guided to the wafer WA2. Since the trajectory of the ion 922a and the ion 922b can be controlled to extend in the direction X and the direction Z in FIG. 38 but not substantially extend in the direction Y as described above, the ion 922a and the ion 922b can point to the first side wall O321, but does not substantially point to the second side wall O322. In some embodiments, the process conditions are selected so that the polymerization phenomenon caused by ions is more dominant than the etching phenomenon caused by ions, so that ions 922a and 922b are directed to the first sidewall O321 of the fourth opening O32', but are not substantially Pointing to the second side wall O322 of the fourth opening O32', this may cause the polymer to be deposited on the first side wall O321, but not substantially deposited on the second side wall O322. These deposited polymers may be referred to as protective layers (or polymer layers) 240. In some embodiments, the process conditions of the directional deposition process are similar to the process conditions of the directional deposition process previously discussed with respect to FIGS. 6A to 6C, so for the sake of brevity, they are not repeated here.

As a result of directional deposition, the length L32' of the fourth opening O32' in the direction Y remains substantially the same as the length L32 of the fourth opening O32 (as shown in FIG. 18A), and the fourth opening O32' in the direction X The width W32' is smaller than the width W32 of the fourth opening O32. The difference between the width W32' of the fourth opening O32' after directional deposition and the width W22 of the fourth opening O22 before directional deposition is substantially twice the thickness of the protective layer 240. In some embodiments, directional deposition causes polymer to be deposited over the top surface of the patterned bottom layer 2382', such that the protective layer 240 extends on the top surface of the patterned bottom layer 2382'. In some embodiments, the etch stop layer 230 at the bottom of the fourth opening O32' may not be covered by the protective layer 240 (ie, polymer) due to the shadowing effect caused by the inclined trajectory of the directional ions.

Returning to FIG. 11B, the method M2 then proceeds to block S211, etching the second sidewall of the fourth opening to extend the fourth opening. In some embodiments of block S211, a directional etching process is performed on the second sidewall O322 of the fourth opening O32', resulting in an extended opening O32" as shown in FIGS. 20A to 20C. Orientation is performed using directional ions Etching process. For example, a plasma tool 900 as shown in FIG. 38 may be used to perform a directional etching process (please refer to the detailed description below).

After performing the directional deposition process on the wafer WA2 in the plasma tool 900, the wafer WA2 may be rotated about the direction Z axis 929 by about 88 degrees to about 92 degrees (for example, about 90 degrees). In this way, the second side wall O322 of the fourth opening O32' may be arranged in the direction X in FIG. 38. After rotating the wafer WA2, the ions 922a and 922b may be extracted and guided to the wafer WA2. Since the trajectories of the ions 922a and 922b extend in the direction X and the direction Z in FIG. 38 but do not substantially extend in the direction Y, the ions 922a and 922b may point to the second side wall O322 of the fourth opening O32' The top does not point to the protective layer 240 along the first sidewall O321 of the fourth opening O32'. In some embodiments, the process conditions are selected so that the ion-induced etching phenomenon is more dominant than the ion-induced polymerization phenomenon. Therefore, ions 922a and 922b can be used to perform a directional etching process, which has a faster etching rate in direction X than in direction Y in FIG. 38. For example, the ratio of the etching rate in the direction X to the etching rate in the direction Y is in the range of about 10:1 to about 30:1. Further, the ions 922a and 922b may point to the second sidewall O322 of the fourth opening O32', but do not substantially point to the first sidewall O321 of the fourth opening O32', thus causing the second sidewall O322 to be etched but not substantially etched The protective layer 240 along the first sidewall O321. In this way, the directional etching process can extend the second opening O32' by etching the second side wall O322 without substantially etching the first side wall O321, thereby creating an extended opening O32" as shown in FIGS. 20A to 20C In some embodiments, the process conditions of the directional etching process are similar to the process conditions of the directional etching process previously discussed with respect to FIGS. 7A to 7C, so for the sake of brevity, they are not repeated here.

Referring to Fig. 20A, as a result of directional etching, the length L32" of the extended opening O32" is greater than the length L32' of the second opening O32' (as shown in Fig. 14A), but the width W32" of the extended opening O32" The width W32' of the second opening O32' is substantially the same. Because the extended opening O32" has an increased length, the subsequently formed source/drain vias that inherit the pattern of the extended opening O32" may have an increased length in the direction Y, resulting in the source/drain formed subsequently The contact area between the drain via and the source/drain contact 228 is increased. In addition, since the extension process does not increase the width of the opening O32', the subsequently formed source/drain vias inheriting the pattern of the extended opening O32" will be separated from the gate contact subsequently formed in the gate contact opening, This prevents an undesirable short circuit between the gate contact and the source/drain via. An example ratio of the resulting length L32" to the resulting width W32" is in the range of about 2.7:1 to about 4.6:1. In some In an embodiment, the directional deposition process of block S211 may be performed in situ using the directional deposition process of block S210, which will prevent contamination of the wafer WA2.

Returning to FIG. 11B, method M2 then proceeds to block S212, and the pattern of the extended opening is transferred to the underlying layer to form the source/drain via opening. Referring to FIGS. 21A to 21D, in some embodiments of block S212, a patterning process is performed on the etch stop layer 230 to transfer the pattern of the extended opening O32″ to the etch stop layer 230, thereby passing through the etch stop layer 230 produces source/drain via openings O33 and exposes source/drain contacts 228. In some embodiments, the patterning process includes one or more etching processes, wherein the protective layer 236, the patterned bottom layer 2382' The combination with the patterned interlayer dielectric layer 232" acts as an etch mask. The one or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof. During the patterning process, the patterned bottom layer 2382' may be consumed. In some embodiments, a suitable etchant may be used to remove the residue of the patterned bottom layer 2382' so that both the gate contact opening O23 and the source/drain via opening O33 are exposed.

As a result of the patterning process, the source/drain via opening O33 inherits the extended opening O32" pattern (as shown in FIGS. 20A to 20C). Further, the source/drain via opening The length L33 of O33 is substantially the same as the length L32" of the extended opening O32", and the width W33 of the source/drain via opening O33 is substantially the same as the width W32" of the extended opening O32". As shown in FIG. 21B As shown, the width W33 of the source/drain via opening O33 and the width W23 of the gate contact opening O23 are controlled so that the source/drain via opening O33 and the gate contact opening O23 pass through the patterned interlayer dielectric layer 232 "Apart from each other. This helps prevent short circuits between the source/drain vias and gate contacts that are subsequently formed.

In some embodiments, the patterned third interlayer dielectric layer 232" remains above the etch stop layer 230, and a portion of the protective layer 240 remains on the first sidewall of the source/drain via opening O33 extending in the direction Y On O331, and the second sidewall O332 of the source/drain via opening O33 extending in the direction X is not covered by the protective layer 240.

In block S213 of method M2 (as shown in FIG. 11B), the gate contact opening O23 and the source/drain via opening O33 are filled with a conductive material using a suitable deposition technique. Thereafter, in block S214, the conductive material is planarized to form the gate contact 242 in the gate contact opening O23, and the source/drain via 244 is formed in the source/drain via opening O33. The resulting structure is shown in Figures 22A to 22D. The conductive material of the gate contact 242 and the source/drain via 244 includes, for example, any suitable metal (eg, cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu ), aluminum (Al) and/or nickel (Ni) and/or titanium (Ti) or tantalum (Ta) nitride).

The gate contact 242 and the source/drain via 244 inherit the patterns of the gate contact opening O23 and the source/drain via opening O33, respectively (as shown in FIGS. 21A to 21D). Therefore, the length L24 of the gate contact 242 is substantially the same as the length L23 of the gate contact opening O23, the width W24 of the gate contact 242 is substantially the same as the width W23 of the gate contact opening O23, and the source/drain via 244 The length L34 is substantially the same as the length L33 of the source/drain via opening O33, and the width W34 of the source/drain via 244 is substantially the same as the width W33 of the source/drain via opening O33. The width W24 of the gate contact 242 and the width W34 of the source/drain via 244 are controlled so that the gate contact 242 is separated from the source/drain via 244. The length L24 of the gate contact 242 is controlled so that the contact area between the gate contact 242 and the gate metal layer 2064 increases. The length L34 of the source/drain via 244 is controlled so that the contact area between the source/drain via 244 and the source/drain contact 228 increases.

In some embodiments, the gate contact 242 includes opposing first side walls 2421 extending substantially in the direction Y and opposing second side walls 2422 extending substantially in the direction X. The protective layer 236 (eg, polymer layer) remains on the first side wall 2421 and is separated from the second side wall 2422. Similarly, the source/drain via 244 includes opposing first side walls 2441 extending substantially in the direction Y and opposing second side walls 2442 extending substantially in the direction X. The protective layer 240 (eg, polymer layer) remains on the first side wall 2441 and is separated from the second side wall 2442. More specifically, the sidewalls of the gate contact 242 and the source/drain via 244 in direction Y are partially covered by the polymer, but the sidewalls of the gate contact 242 and the source/drain via 244 in direction X Is not covered by polymer.

FIG. 23 illustrates a method M3, which includes forming an elongated through hole for shorting the gate stack and source/drain contacts. FIGS. 24A to 29B illustrate various processes at various stages of the method M3 of FIG. 23 according to some embodiments of the present disclosure. In various views and illustrative embodiments, the same reference numerals are used to represent the same elements. In FIGS. 24A to 29B, “A” (for example, FIGS. 24A, 25A, etc.) shows a cross-sectional view along the direction X, and “B” (for example, FIGS. 24B, 25B Etc.) shows another cross-sectional view along the direction Y. It should be understood that additional steps may be provided before, during, and after the process shown in FIGS. 24A to 29B, and for other embodiments of this method, some steps described below may be replaced or eliminated. The order of steps/processes can be interchangeable.

As shown in FIGS. 24A to 24B, the semiconductor wafer WA3 is substantially similar to the semiconductor wafer WA2 shown in FIGS. 17B and 17C in many respects, and includes a substrate 302, a semiconductor fin 304, and a shallow trench Trench isolation 305, gate stack 306 with gate dielectric layer 3062 and metal layer 3064, gate spacer 308, source/drain region 310, first interlayer dielectric layer 312, first etch stop layer 314 , The second interlayer dielectric layer 316, the source/drain contact 328, the etch stop layer 330, and the third interlayer dielectric layer 332, each substantially relative to the substrate 202, the semiconductor fin 204, and the shallow trench as described above Isolation 205, gate stack 206 with gate dielectric layer 2062 and metal layer 2064, gate spacer 208, source/drain region 210, first interlayer dielectric layer 212, first etch stop layer 214, The second interlayer dielectric layer 216, the source/drain contact 228, the etch stop layer 230, and the third interlayer dielectric layer 332. The semiconductor wafer WA2 further includes a gate contact opening O41, which can be formed using, for example, an extended process involving the directional deposition process and the directional etching process as described above with respect to the gate contact opening O23. Therefore, the polymer produced by the directional deposition process remains on the specific sidewall of the gate contact opening O41, and may be referred to as a protective layer (or polymer layer) 336. In some other embodiments, the gate contact opening O41 is formed without using the directional deposition process and the directional etching process, so the protective layer 336 may not be present in the gate contact opening O41.

In block S301, a three-layer photoresist mask 340 is formed on the third interlayer dielectric layer 332 and in the gate contact opening O41. The three-layer photoresist mask 340 includes a bottom layer 3402, an intermediate layer 3404, and a top layer 3406, respectively similar to the bottom layer 1222, the middle layer 1224, and the top layer 1226 of the three-layer photoresist mask 122 previously described with respect to FIGS. 3A to 3C. . Therefore, for the sake of brevity, the description about the bottom layer 3402, the middle layer 3404, and the top layer 3406 will not be repeated. The gate contact opening O41 is overfilled with the bottom layer 3402 of the three-layer photoresist mask 340.

In block S302, a first opening O51 is formed in the top layer 3406 and above the source/drain contact 328 and the gate contact opening O41. The formation of the first opening O51 includes exposing the top layer 3406 and developing the top layer 3406 to remove a portion of the top layer 3406. The first opening O51 has a length L51 in the direction X, a width W51 in the direction Y, and the length L51 is greater than the width W51.

Returning to FIG. 23, method M3 then proceeds to block S303, in which a third interlayer dielectric layer is patterned to form a second opening using a three-layer photoresist mask as an etch mask. Referring to FIGS. 25A to 25B, in some embodiments of block S303, a patterning process is performed on the third interlayer dielectric layer 332 to pattern the first opening O51 in the patterned top photoresist layer 3406 Transferred to the third interlayer dielectric layer 332, thereby creating a second opening O52 in the third interlayer dielectric layer 332'. In some embodiments, the patterning process includes one or more etching processes, wherein the three-layer photoresist mask 340 serves as an etching mask. The one or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof. During the patterning process, the patterned top layer 3406 and the middle layer 3404 of the photoresist mask 234 may be consumed, and a portion of the bottom layer 3402 may remain after the patterning process. In this way, the patterning process also creates a patterned bottom layer 3402' on the patterned interlayer dielectric layer 332'.

The patterned bottom layer 3402' and the patterned interlayer dielectric layer 332' inherit the pattern in the top photoresist layer 3406, so the second opening O52 and the first opening O51 in the patterned top photoresist layer 3406 have substantially Same shape, size and location. For example, the second opening O52 has a length L52 in the direction X and a width W52 in the direction Y, and the length L52 is greater than the width W52.

Referring to FIGS. 26A to 26B, in some embodiments of block S304, a directional deposition process is performed to extend in the second opening O52 in the direction X (ie, extending in and out of the plane of the page of FIG. 26B) A protective layer 342 is formed on the second side wall O522 of the', and substantially does not form a protection on the first side wall O521 of the second opening O52' extending in the direction Y (ie, extending in and out of the plane of the page of Fig. 26A) Floor 342. The directional etching process may be performed using directional ions, resulting in a deposition rate in direction Y that is higher than the deposition rate in direction X, so that the second sidewall O522 may deposit more polymer (eg, carbon-containing) than the first sidewall O521 Polymers, chlorine-containing polymers and/or bromine-containing polymers). For example, the ratio of the deposition rate in direction Y to the deposition rate in direction X is in the range of about 10:1 to about 30:1.

For example, the plasma tool 900 shown in FIG. 38 may be used to perform the directional deposition process. Further, the ions 922a and 922b can be extracted and guided to the wafer WA2. As described above, the trajectories of ions 922a and 922b can be controlled to extend in the direction X and the direction Z in FIG. 38, but they do not substantially extend in the direction Y. Therefore, the wafer WA3 may be oriented so that the ions 922a and 922b can be directed toward the second side wall O522, but not substantially toward the first side wall O521. In some embodiments, the process conditions are selected so that the polymerization phenomenon caused by ions is more dominant than the etching phenomenon caused by ions, so that ions 922a and 922b directed to the second sidewall O522 but not substantially directed to the first sidewall O521 may As a result, the polymer is deposited on the second side wall O522, but is not substantially deposited on the first side wall O521. These deposited polymers may be referred to as protective layers (or polymer layers) 342. In some embodiments, the process conditions of the directional deposition process are similar to the process conditions of the directional deposition process previously discussed with respect to FIGS. 6A to 6C, so for the sake of brevity, they are not repeated here.

As a result of directional deposition, the length L52' of the second opening O52' in the direction X remains substantially the same as the length L52 of the second opening O52 (as shown in FIG. 24A), and the second opening O52' in the direction Y The width W52' is smaller than the width W52 of the second opening O52. The difference between the width W52' of the second opening O52' after directional deposition and the width W52 of the second opening O52 before directional deposition is substantially twice the thickness of the protective layer 342. In some embodiments, the directional deposition causes the polymer to be deposited over the top surface of the patterned bottom layer 3402' such that the protective layer 342 extends on the top surface of the patterned bottom layer 3402'. In some embodiments, due to the shadowing effect generated by the directional ions, the etch stop layer 330 at the bottom of the second opening O52' may not be covered by the protective layer 342 (ie, polymer).

Returning to FIG. 23, the method M2 then proceeds to block S305, where the first sidewall of the second opening is etched to extend the second opening. In some embodiments of block S205, a directional etching process is performed on the first sidewall O521 of the second opening O52', resulting in an elongated opening O52", as shown in FIGS. 27A to 27B. Orientation is performed using directional ions Etching process. For example, as described in detail below, a plasma tool 900 as shown in FIG. 38 may be used to perform a directional etching process.

After performing the directional deposition process on the wafer WA3 in the plasma tool 900, the wafer WA3 may be rotated about the direction Z axis 929 by about 88 degrees to about 92 degrees (for example, about 90 degrees). Thereafter, the ions 922a and 922b may be extracted and directed toward the first sidewall O521 of the second opening O52', but not substantially directed toward the protective layer 342 along the second sidewall O522 of the second opening O52'. In some embodiments, the process conditions are selected so that the ion-induced etching phenomenon is more dominant than the ion-induced polymerization phenomenon. Therefore, the ions 922a and 922b may cause the first sidewall O521 to be etched, but the protective layer 342 along the second sidewall O522 is not substantially etched. In this way, the directional etching process can extend the second opening O52' by etching the first side wall O521 without substantially etching the second side wall O522, resulting in an extended opening O52" as shown in FIGS. 27A to 27B In some embodiments, the process conditions of the directional etching process are similar to the process conditions of the directional etching process previously discussed with respect to FIGS. 7A to 7C, so for the sake of brevity, they are not repeated here.

As a result of directional etching, the length L52" of the extended opening O52" is greater than the length L52' of the second opening O52' (as shown in FIG. 26A), and the width W52" of the extended opening O52" and the second opening O52' The width W52' is substantially the same. In some embodiments, the gate contact opening O41 is formed using an extended process as previously discussed in FIGS. 12A to 16C. The length of the gate contact opening O41 will be parallel to the direction Y (ie, extending into and out of FIG. 27A The direction of the plane of the page), and therefore perpendicular to the length of the elongated opening O52". An exemplary ratio of the resulting length L52" to the resulting width W52" is in the range of about 2.7:1 to about 4.6:1. In some embodiments, the directional deposition process of block S305 may be performed in situ using the directional deposition process of block S304, which will prevent contamination of the wafer WA3.

Returning to FIG. 23, the method M2 then proceeds to block S306, where the pattern of the elongated opening is transferred to the underlying layer to form the via opening. Referring to FIGS. 28A to 28B, in some embodiments of block S306, a patterning process is performed on the etch stop layer 330 to transfer the pattern of the elongated opening O52″ to the etch stop layer 330, thereby causing the stop through the etch The via opening of the layer 330 is O53 and exposes the source/drain contact 328. In some embodiments, the patterning process includes one or more etching processes, wherein the protective layer 342, the patterned bottom layer 3402', and the patterned interlayer The combination of the dielectric layer 332 serves as an etching mask. One or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination of the above. During the patterning process, the patterned may be consumed The bottom layer 3402'. In some embodiments, a suitable etchant may be used to remove the residue of the patterned bottom layer 3402' so that both the gate contact opening O41 and the via opening O53 are exposed. The gate contact opening O41 is removed from the via The bottom of the opening O53 extends to the gate metal layer 3604.

As a result of the patterning process, the via opening O53 inherits the pattern of the extended opening O52" (as shown in FIGS. 27A to 27B). Further, the length L53 of the via opening O53 and the extended opening O52" The length L52" is substantially the same, and the width W53 of the through-hole opening O53 is substantially the same as the width W52" of the elongated opening O52".

In some embodiments, the patterned third interlayer dielectric layer 332' remains above the etch stop layer 330, and a portion of the protective layer 342 remains extending in the direction X (ie, extending into and out of the plane of the page of FIG. 28B Direction) of the through-hole opening O53 on the second side wall O532, and the first side wall O531 of the through-hole opening O53 extending in the direction Y (ie, the direction extending into and out of the plane of the page of FIG. 28A) is not protected Coverage of layer 342.

Thereafter, in block S307 of the method M3 (shown in FIG. 23), conductive vias 344 are formed in the gate contact opening O41 and the via opening O53, as shown in FIGS. 29A and 29B. The formation of the conductive via 344 includes, for example, overfilling the gate contact opening O41 and the via opening O53 with a conductive material, and then performing a chemical mechanical planarization process to remove excess conductive material outside the gate contact opening O41 and the via opening O53. The conductive material of the conductive via 344 includes, for example, any suitable metal (eg, cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), and/or Nickel (Ni) and/or titanium (Ti) or tantalum (Ta) nitride).

FIG. 30 illustrates a method M4, which includes a gate cutting process (or referred to as a cut metal gate process), which involves directional deposition and directional etching as described above. FIGS. 31A to 37D illustrate various processes at various stages of the method M4 of FIG. 30 in some embodiments of the present disclosure. In various views and illustrative embodiments, the same reference numerals are used to represent the same elements. FIG. 31A shows a perspective view, FIG. 31B shows a cross-sectional view corresponding to line B-B in FIG. 31A along direction X, and FIG. 31C shows a cross-sectional view corresponding to line C-C in FIG. 31A along direction Y. FIG. In Figures 32A to 37D, "A" (eg, 32A, 33A, etc.) shows a top view, and "B" (eg, 32B, 33B, etc.) shows the corresponding to A cross-sectional view of the line BB shown in the "A" diagram along the direction X, and a "C" figure (for example, FIG. 32C, FIG. 33C, etc.) plots corresponding to the line CC shown in "A" along the direction Y Section view. The "D" diagram (for example, the 36D and 37D diagrams) shows a cross-sectional view along the direction Y corresponding to the line D-D shown in the "A" diagram. It should be understood that additional steps may be provided before, during and after the processes shown in FIGS. 31A to 37D, and some steps described below may be replaced or eliminated as other embodiments for this method. The order of steps/processes can be interchangeable.

As shown in FIGS. 31A to 31C, the semiconductor wafer WA4 is substantially similar to the semiconductor wafer WA in many respects, and includes a substrate 402, a semiconductor fin 404, a shallow trench isolation 405, and a gate dielectric layer 4062 And the metal layer 4064, the gate stack 406, the gate spacer 408, the source/drain region 410, and the interlayer dielectric layer 412, each substantially relative to the substrate 102, the semiconductor fin 104, and the shallow trench as described above Isolation 105, gate stack 106 with gate dielectric layer 1062 and metal layer 1064, gate spacer 108, source/drain region 110, and first interlayer dielectric layer 112.

In block S401, an etch stop layer 414, a hard mask layer 416, and three photoresist masks 418 are sequentially formed on the gate stack 406 and the first interlayer dielectric layer 112. In some embodiments, the etch stop layer 414 may include titanium nitride or the like, and may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition. In some embodiments, the hard mask layer 416 may include silicon nitride or the like, and may be formed using a deposition process such as chemical vapor deposition or physical vapor deposition. The three-layer photoresist mask 418 includes a bottom layer 4182, an intermediate layer 4184, and a top layer 4186, respectively similar to the bottom layer 1222, intermediate layer 1224, and top layer 1226 of the three-layer photoresist mask 122 previously discussed with respect to FIGS. 3A to 3C. . Therefore, for the sake of brevity, the description about the bottom layer 4182, the middle layer 4184, and the top layer 4186 will not be repeated.

Method M4 then proceeds to block S402, where a first opening is formed in the top layer of the three-layer photoresist mask and spans one or more first gate stacks. Referring to FIGS. 32A to 32C, in some embodiments of block S402, a first opening O61 is formed in the patterned top layer 4186′ and spans the gate stack 406. The formation of the first opening O61 includes exposing the top layer 4186 and developing the top layer 4186 to remove a portion of the top layer 4186, thus creating a patterned top layer 4186'. The first opening O61 in the patterned top photoresist layer 4186' is used to define a gate cutting pattern (or gate cutting opening), which will be described in more detail below. As shown in FIG. 32A, the first opening O61 has a length L61 in the direction X and a width W61 in the direction Y, and the length L61 is greater than the width W61. Therefore, the subsequently formed gate cutting pattern will have a length in direction X greater than the width in direction Y, which may result in an increase in the number of cut gates while preventing damage to the source/drain regions during the gate cutting process 410, which will be discussed further below.

Returning to FIG. 30, method M4 then proceeds to block S403, where a three-layer photoresist mask is used as an etch mask to pattern the hard mask layer to form a second opening. Referring to FIGS. 33A to 33C, in some embodiments of block S403, a patterning process is performed on the hard mask layer 416 to transfer the pattern of the first opening O61 in the patterned top photoresist layer 4186′ Into the hard mask layer 416, thereby creating a second opening O62 in the hard mask layer 416'. In some embodiments, the patterning process includes one or more etching processes, in which the three-layer photoresist mask 418 is used as an etching mask. The one or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof. During the patterning process, the patterned top layer 4186' and the intermediate layer 4184 of the photoresist mask 418 may be consumed, and a portion of the bottom layer 4182 may remain after the patterning process. In this way, the patterning process also creates a patterned bottom layer 4182' on the patterned hard mask layer 416'.

The patterned bottom layer 4182' and the patterned hard mask layer 416' inherit the pattern in the top photoresist layer 4186'. As such, the second opening O62 and the first opening O61 in the patterned top photoresist layer 4186' may have substantially the same shape, size, and position. For example, the second opening O62 has a length L62 in the direction X and a width W62 in the direction Y, and the length L62 is greater than the width W62. The pattern across the second opening O62 of the gate stack 406 may be used to define a gate cutting pattern for dividing the gate stack 406 in a subsequent step.

Because the gate stack 406 is arranged in the direction X, the length L62 of the second opening O62 in the direction X is positively related to the plurality of gate stacks 406 to be cut. In other words, the greater the length L62 of the second opening O62, the more gate stacks 406 to be cut. Therefore, one or more lateral etching processes may be used to extend the second opening O62 in the direction X. However, if the patterned bottom layer 4182' and the hard mask layer 416' undergo one or more lateral etching processes, the second opening O62 will inevitably extend in direction X and direction Y, which will result in the second opening O62 The width W62 increases, which in turn may cause damage to the source/drain regions 410 arranged along the direction Y during the gate cutting process. Therefore, in some embodiments of the present disclosure, a directional deposition process is performed on the wafer WA4 with a deposition rate in the direction Y faster than the deposition rate in the direction X (block S404 of method M4), followed by performing A directional etching process in which the etching rate in direction X is higher than the etching rate in direction Y (block S405 of method M4). In this way, the second opening O62 may be extended in the direction X but not substantially extended in the direction Y (see the more detailed description below).

Referring to FIGS. 34A to 34C, in some embodiments of block S404, a directional deposition process is performed to form a protective layer 420 on the second sidewall O622 of the second opening O62′ extending in the direction X, and is not substantially in A protective layer 420 is formed on the first sidewall O621 of the second opening O62' extending in the direction Y. The directional deposition process using directional ions results in a faster deposition rate in direction Y than in direction X, so that the side wall O622 in direction X can deposit more polymer (eg, carbon-containing polymer) than the side wall O621 in direction Y , Chlorine-containing polymers and/or bromine-containing polymers). In some embodiments, the ratio of the deposition rate in direction Y to the deposition rate in direction X is in the range of about 10:1 to about 30:1.

For example, the plasma tool 900 shown in FIG. 38 may be used to perform the directional deposition process. Further, the ions 922a and 922b can be extracted and guided to the wafer WA4. As described above, the trajectories of ions 922a and 922b can be controlled to extend in the direction X and the direction Z in FIG. 38, but they do not substantially extend in the direction Y. Therefore, the wafer WA4 may be oriented so that the ions 922a and 922b can be directed toward the second side wall O622, but not substantially toward the first side wall O621. In some embodiments, the process conditions are selected so that the polymerization phenomenon caused by ions is more dominant than the etching phenomenon caused by ions, so that ions 922a and 922b are directed toward the second side wall O622 but not substantially toward the first side wall O621, thus As a result, the polymer is deposited on the second sidewall O622, but is not substantially deposited on the first sidewall O621. These deposited polymers may be referred to as protective layers (or polymer layers) 420. In some embodiments, the process conditions of the directional deposition process are similar to the process conditions of the directional deposition process previously discussed with respect to FIGS. 6A to 6C, so for the sake of brevity, they are not repeated here.

As a result of the directional deposition, the length L62' of the second opening O62' in the direction X remains substantially the same as the length L62 of the second opening O62 (as shown in FIG. 33A), and the second opening O62' in the direction Y The width W62' is smaller than the width W62 of the second opening O62. The difference between the width W62' of the second opening O62' after directional deposition and the width W62 of the second opening O62 before directional deposition is substantially twice the thickness of the protective layer 420. In some embodiments, directional deposition results in the deposition of polymer over the top surface of the patterned bottom layer 4182' such that the protective layer 420 extends on the top surface of the patterned bottom layer 4182'. In some embodiments, due to the shadowing effect generated by the directional ions, the etch stop layer 414 at the bottom of the second opening O62' may not be covered by the protective layer 420 (ie, polymer).

Returning to FIG. 30, the method M2 then proceeds to block S405, where the first sidewall of the second opening is etched to extend the second opening. In some embodiments of block S405, a directional etching process is performed on the first sidewall O621 of the second opening O62', resulting in an extended opening O62" as shown in FIGS. 35A to 35C. Orientation is performed using directional ions Etching process. For example, a plasma tool 900 as shown in FIG. 38 as described in detail below may be used to perform a directional etching process.

After performing the directional deposition process on the wafer WA4 in the plasma tool 900, the wafer WA4 may be rotated about the direction Z axis 929 by about 88 degrees to about 92 degrees (for example, about 90 degrees). Thereafter, the ions 922a and 922b may be extracted and directed toward the first sidewall O621 of the second opening O62', but not substantially directed toward the protective layer 420 along the second sidewall O622 of the second opening O62'. In some embodiments, the process conditions are selected so that the ion-induced etching phenomenon is more dominant than the ion-induced polymerization phenomenon. Therefore, the ions 922a and 922b may cause the first sidewall O621 to be etched, but the protective layer 420 along the second sidewall O622 is not substantially etched. For example, the ratio of the etching rate of the first sidewall O621 to the etching rate of the protective layer 420 along the second sidewall O622 is in the range of about 10:1 to about 30:1. In this way, the directional etching process can extend the second opening O62' by etching the first side wall O621 without substantially etching the second side wall O622, resulting in an extended opening O62" as shown in FIGS. 35A to 35C In some embodiments, the process conditions of the directional etching process are similar to the process conditions of the directional etching process previously discussed with respect to FIGS. 7A to 7C, so for the sake of brevity, they are not repeated here.

As a result of directional etching, the length L62" of the extended opening O62" is greater than the length L62' of the second opening O62' (as shown in FIG. 34A), and the width W62" of the extended opening O62" and the second opening O62' The width W62' is substantially the same. Because the extended opening O62" has an increased length in the direction X, the number of gate stacks 406 that will undergo the gate cutting process can be increased. In addition, because the extended process does not increase the width of the opening O62" in the direction Y, Therefore, damage to the source/drain region 410 caused by the gate cutting process can be prevented. An exemplary ratio of the resulting length L62" to the resulting width W62" is in the range of about 2.7:1 to about 4.6:1. In some embodiments, the directional deposition process of block S405 may be performed in situ using the directional deposition process of block S404, which will prevent contamination of the wafer WA4.

Returning to FIG. 30, method M2 then proceeds to block S406, where the hard mask layer is used as an etch mask to etch the etch stop layer and the one or more first gate stacks to stack the one or more first gates Divided into multiple second gate stacks. Referring to FIGS. 36A to 36D, in some embodiments of block S406, using a combination of the protective layer 420, the patterned bottom layer 4182' and the patterned hard mask layer 416' as an etch mask, the wafer WA4 performs one or more etching processes, resulting in the cutting opening O63 dividing one or more long gate stacks 406 into a plurality of short gate stacks 406', each short gate stack 406' includes a gate dielectric layer 4062' and A gate metal layer 4064' above the gate dielectric layer 4062'. Therefore, one or more etching processes may be referred to as gate cutting processes. The one or more etching processes may include an anisotropic wet etching process, an anisotropic dry etching process, or a combination thereof. During the patterning process, the patterned bottom layer 4182' may be consumed. In some embodiments, a suitable etchant may be used to remove residues of the patterned bottom layer 4182'.

As a result of the patterning process, the cut opening O63 inherits the pattern of the extended opening O62" (as shown in FIGS. 35A to 35C). Further, the length L63 of the cut opening O63 and the length of the extended opening O62" L62" is substantially the same, and the width W63 of the cutting opening O63 is substantially the same as the width W62" of the extended opening O62". As shown in FIG. 36C, the width W63 of the cutting opening O63 is controlled so that it is arranged along the direction X at the cutting opening O63 The source/drain region 410 on the opposite side of is not exposed by the gate contact opening O23. This helps prevent damage to the source/drain region 410 caused by the etchant used in the patterning process.

Thereafter, in some embodiments of block S407 of method M4 (as shown in FIG. 30), a dielectric structure 422 is deposited to overfill the cut opening O63, followed by a chemical mechanical planarization process to remove the dielectric structure 422 Of excess material until reaching the etch stop layer 414, for example. The resulting structure is shown in Figures 37A to 37D. The dielectric structure 422 may include suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant dielectrics (eg, carbon-doped oxides), very low dielectric constant dielectrics Materials (eg, silicon dioxide doped with porous carbon), combinations of these, or the like. In some embodiments, the etch stop layer 414 can also be removed through a chemical mechanical planarization process.

The dielectric structure 422 inherits the pattern of the cutting opening O63 (as shown in FIGS. 36A to 36D), so that the dielectric structure 422 can be separated from the adjacent short gate stack 406' and thus from the adjacent short gate The pole stack 406' is insulated. In addition, the length L64 of the dielectric structure 422 is substantially the same as the length L63 of the cutting opening O63, and the width W64 of the dielectric structure 422 is substantially the same as the width W63 of the cutting opening O63. The width W64 of the dielectric structure 422 is controlled so that the dielectric structure 422 is between the source/drain regions 410 and separated from the source/drain regions 410.

Based on the above discussion, it can be seen that this disclosure provides benefits. However, it should be understood that other embodiments may provide additional benefits, and not all benefits must be disclosed herein, and not all embodiments require specific benefits. One of the benefits is that when the opening undergoes an etching process to extend the opening, the width of the opening can be kept substantially unchanged because the directional deposition process is performed to cover the first sidewall of the opening but expose the second sidewall of the opening. Another benefit is that the same tool (eg, the same plasma tool) can be used to perform the directional deposition process and the directional etching process for forming extended patterns, thereby preventing contamination on the wafer.

In some embodiments, a method includes forming a semiconductor fin extending in a first direction on a substrate. A source/drain region is formed on the semiconductor fin, and a first interlayer dielectric layer is formed above the source/drain region. The gate stack is formed across the semiconductor fins and extends in a second direction that is substantially perpendicular to the first direction. A patterned mask having a first opening is formed on the first interlayer dielectric layer. A deposition process having a faster deposition rate in the first direction than in the second direction is used to form the protective layer in the first opening. After the protective layer is formed, the first opening is extended in the second direction. The second opening is formed in the first interlayer dielectric layer and below the elongated first opening. A conductive material is formed in the second opening.

In some embodiments, a method includes forming fins that protrude from the substrate and extend in the first direction. A first gate stack is formed across the fins, and it extends in a second direction that is substantially perpendicular to the first direction. A patterned mask with openings is formed on the first gate structure. A deposition process having a faster deposition rate in the second direction than in the first direction is used to form a protective layer in the opening of the patterned mask. After the protective layer is formed, the opening is extended in the first direction. The first gate stack is etched under the elongated opening to divide the first gate stack into a plurality of second gate stacks. A dielectric structure is formed between the second gate structures.

In some embodiments, the semiconductor device includes a semiconductor substrate, source/drain regions, source/drain contacts, conductive vias, and the first polymer layer. The source/drain regions are located in the semiconductor substrate. The source/drain contact is located above the source/drain region. The source/drain via is located above the source/drain contact. The first polymer layer extends along the first sidewall of the conductive via and is separated from the second sidewall of the conductive via substantially perpendicular to the first sidewall of the conductive via.

The above outlines the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or to achieve the same benefits of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

M1‧‧‧Method

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Claims (20)

A method includes: forming a semiconductor fin on a substrate, the semiconductor fin extending in a first direction; forming a source/drain region on the semiconductor fin and forming a first interlayer dielectric layer on On the source/drain region; forming a gate stack across the semiconductor fin, the gate stack extending in a second direction substantially perpendicular to the first direction; forming a patterned mask, the The patterned mask has a first opening in the first interlayer dielectric layer; it is formed in the first opening using a deposition process that has a faster deposition rate in the first direction than in the second direction A protective layer; after forming the protective layer, extending the first opening in the second direction; forming a second opening in the first interlayer dielectric layer and under the extended first opening; and forming a The conductive material is in the second opening. The method of claim 1, wherein extending the first opening includes an etching process, and the etching process has a faster etching rate in the second direction than in the first direction. The method of claim 1, wherein the protective layer is made of a polymer. The method according to claim 1, wherein the formation of the protective layer and the extension of the first opening are performed in the same plasma tool. The method according to claim 4, further comprising: after forming the protective layer and before extending the first opening, rotating the substrate in the plasma tool. The method of claim 1, further comprising: before forming the patterned mask, forming an etch stop layer to cover the first interlayer dielectric layer. The method of claim 6, wherein after extending the first opening, the etch stop layer still covers the first interlayer dielectric layer. The method of claim 1, wherein the second opening is formed in the first interlayer dielectric layer such that the second opening exposes the source/drain region. The method of claim 1, wherein the second opening is formed in the first interlayer dielectric layer such that the second opening exposes the gate stack. The method of claim 1, further comprising: forming a second interlayer dielectric layer on the source/drain region before forming the first interlayer dielectric layer; and forming the first interlayer Before the dielectric layer, a source/drain contact is formed in the second interlayer dielectric layer, wherein the second opening is formed in the first interlayer dielectric layer so that the source/drain contact is exposed . A method includes: forming a fin that protrudes from a substrate and extending in a first direction; forming a first gate stack across the fin and along a substantially perpendicular to the first direction Extending in the second direction; forming a patterned mask with an opening in the first gate stack; using a faster deposition rate in the second direction than in the first direction The deposition process forms a protective layer in the opening of the patterned mask; after forming the protective layer, the opening is extended in the first direction; the first gate stack under the extended opening is etched to remove The first gate stack is divided into a plurality of second gate stacks; and a dielectric structure is formed between the second gate stacks. The method of claim 11, wherein extending the opening in the patterned mask includes an etching process, and the etching process has a faster etching rate in the first direction than in the second direction. The method of claim 11, further comprising: before forming the patterned mask, forming an etch stop layer to cover the first gate stack. The method of claim 13, wherein after extending the opening, the etch stop layer still covers the first gate stack. The method according to claim 11, wherein the formation of the protective layer and the extension of the opening are performed using ions. The method of claim 11, further comprising: rotating the substrate between the formation of the protective layer and the extension of the opening. A semiconductor device includes: a semiconductor substrate; a source/drain region located in the semiconductor substrate; a source/drain contact located on the source/drain region; and a conductive via located in the source A pole/drain contact; and a first polymer layer extending along a first side wall of the conductive via, and a first layer of the conductive via substantially perpendicular to the first side wall of the conductive via The two side walls are separated. The semiconductor device of claim 17, further comprising: an etch stop layer surrounding the conductive via, wherein the first polymer layer has a bottom spaced from the source/drain contact through the etch stop layer . The semiconductor device of claim 17, further comprising: a gate stack on the semiconductor substrate; a gate contact on the gate stack; and a second polymer layer in contact along the gate A first side wall extends and is separated from a second side wall that is substantially perpendicular to the gate contact of the first side wall of the gate stack. The semiconductor device of claim 19, further comprising: an etch stop layer surrounding the gate contact, wherein the etch stop layer is located between the second polymer layer and the gate stack.

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