TW202004714A - Gate driver circuit - Google Patents

Abstract

The present invention discloses a gate driver circuit including multiple stages of single stage gate driver circuits. Each stage of the single stage gate driver circuits includes a dual-scan control unit, a scan signal output unit, a voltage stabilizer unit a first voltage lifting unit and a second voltage lifting unit. The scan signal output unit is coupled to the dual-scan control unit, and is configured to output a scan signal. The voltage stabilizer unit is coupled to the dual-scan control unit and the scan signal output unit, and stabilizes the scan signal according to a first clock signal and a second clock signal. The first voltage lifting unit is coupled to the dual-scan control unit, and adjusts the scan signal according to a first reference voltage of a previous two stage of single stage gate driver circuit and a second reference voltage of a previous one stage of single stage gate driver circuit. The second voltage lifting unit is coupled to the dual-scan control unit, and adjusts the scan signal according to a third reference voltage of a next two stage of single stage gate driver circuit and a fourth reference voltage of a next one stage of single stage gate driver circuit.

Description

Gate drive circuit

The present invention relates to a gate driving circuit, in particular to a gate driving circuit for a display device.

In the prior art, the display panel usually includes multiple gate lines and multiple data lines. The gate lines and the data lines are alternately arranged in a manner perpendicular to each other. One or more pixels are provided at the position where each gate line and data line intersect. By controlling the switch of the gate transistor on the gate line with the scanning signal to select whether the signal on the data line should be written into the pixel, the purpose of displaying the pixel is achieved.

As people's requirements for the resolution of display devices become higher and higher, the number of gate lines and data lines in the display device is bound to increase, and the scanning time between the gate lines and the gate lines is shortened. The shortening of the scanning time will make the rising time and falling time of the scanning signal output by the gate driving circuit to the gate line become more important. If the rise time/fall time is too long, it will make the switching transistor coupled to the gate line too late to turn on/off, so that the pixels cannot be written to the correct data, which will affect the picture quality of the display device.

Therefore, how to shorten the rise time and fall time of the scan signal output by the gate drive circuit has become one of the goals of the industry.

The purpose of the present invention is to propose a gate drive circuit that can shorten the rise time and fall time of the output scan signal.

The embodiment of the invention discloses a gate driving circuit, which includes a plurality of single-stage gate driving circuits. Each single-stage gate drive circuit includes a bidirectional scanning control unit, a scanning signal output unit, a voltage stabilizing unit with a first voltage raising unit and a second voltage raising unit. The bidirectional scanning control unit is used to receive a first scanning control signal and a second scanning control signal. The scan signal output unit is coupled to the bidirectional scan control unit, and is used to output a scan signal. The voltage stabilizing unit is coupled to the bidirectional scanning control unit and the scanning signal output unit. The voltage stabilizing unit stabilizes the scanning signal according to a first clock signal and a second clock signal. The first voltage raising unit is coupled to the bidirectional scanning control unit. The first voltage raising unit is based on a first reference voltage of a previous two-stage single-stage gate drive circuit and a second reference of a previous one-stage single-stage gate drive circuit Voltage adjustment scan signal. The second voltage boosting unit is coupled to the bidirectional scanning control unit. The second voltage boosting unit is based on a third reference voltage of a second-stage single-stage gate drive circuit and a fourth reference of a second-stage single-stage gate drive circuit Voltage adjustment scan signal.

According to an embodiment of the present invention, the gate driving circuit can output a scan signal with a short rise time and a fall time, so that the gate transistor on the gate line can be turned on or off correctly within the scan time, thereby allowing the display The pixels in the device can be correctly written or not written to achieve the effect of improving the picture quality of the display device.

In order to have a better understanding of the above and other aspects of the present invention, the following examples are specifically described in conjunction with the accompanying drawings as follows:

Please refer to FIG. 1, which illustrates a block diagram of a gate driving circuit according to an embodiment of the invention. The gate driving circuit 1 includes a plurality of single-stage gate driving circuits 10_1~10_K, where K is the number of single-stage gate driving circuits, and K is a positive integer. The gate driving circuit 1 can be disposed in a display device (not shown). The display device may include multiple gate lines (not shown) and multiple data lines (not shown), and the gate lines and the data lines are alternately arranged. The gate driving circuit 1 can be coupled to these gate lines. Further, the single-stage gate drive circuits 10_1~10_K of the gate drive circuit 1 are respectively coupled to one of the gate lines to provide a scanning signal G[1]~G[K] to the gate of the gate line Transistor (not shown).

Each level of single-stage gate drive circuits 10_1~10_K includes a bidirectional scanning control unit 102, a scanning signal output unit 104, a voltage stabilizing unit 106, a first voltage boosting unit 108a, and a second voltage boosting unit 108b. It should be understood that since the single-stage gate drive circuits 10_1 to 10_K of each stage have a similar circuit structure, the single-stage gate drive circuit 10_N is taken as a representative example for description below.

The bidirectional scanning control unit 102 is used to receive a first scanning control signal U2D and a second scanning control signal D2U. For example, when the first scan control signal U2D is at a high level and the second scan control signal D2U is at a low level, the display device performs a scan in a first direction; otherwise, when the first scan control signal U2D is at a low level, When the second scanning control signal D2U is at a high level, the display device performs scanning in a second direction. Generally speaking, the first direction is opposite to the second direction, for example, the first direction is from top to bottom, and the second direction is from bottom to top.

The scan signal output unit 104 is coupled to the bidirectional scan control unit 102 for outputting the scan signal G[N]. The scanning signal G[N] can be output to the gate transistor of the gate line, so that the gate transistor can be controlled by the scanning signal G[N] turning on or off.

The voltage stabilizing unit 106 is coupled to the bidirectional scanning control unit 102 and the scanning signal output unit 104, and stabilizes the scanning signal G[N] according to a first clock signal and a second clock signal. The first clock signal is different from the second clock signal. In this embodiment, the first clock signal and the second clock signal are substantially opposite. For example, when the first clock signal is at a high level, the second clock signal is at a low level; conversely, when the first clock signal is at a low level, the second clock signal is at a high level. However, considering the needs of the actual circuit, the first clock signal and the second clock signal are not limited to the above limitations.

The first voltage raising unit 108a is coupled to the bidirectional scanning control unit 102, and is based on a first reference voltage Vr1 of a front-stage single-stage gate drive circuit 10_N-2 and a previous-stage single-stage gate drive circuit 10_N-1 A second reference voltage Vr2 adjusts the scanning signal G[N].

The second voltage raising unit 108b is coupled to the bidirectional scanning control unit 102, and is based on a third reference voltage Vr3 of a second-stage single-stage gate drive circuit 10_N+2 and a second-stage single-stage gate drive circuit 10_N+1 A fourth reference voltage Vr4 adjusts the scanning signal G[N].

The detailed structure of the single-stage gate drive circuits 10_1~10_K will be further described below.

Please refer to FIG. 2, which illustrates a block diagram of one-stage single-stage gate driving circuit in the gate driving circuit according to an embodiment of the present invention. Since the single-stage gate drive circuits 10_1 to 10_K have similar circuit structures, this embodiment will be described by taking the single-stage gate drive circuit 10_N as a representative example.

The bidirectional scan control unit 102 includes a first scan control transistor Msc1 and a second scan transistor Msc2.

The first scan control transistor Msc1 is coupled to the scan signal output unit 104, the first voltage boosting unit 108a, and the voltage stabilizing unit 106. The first scan control transistor Msc1 can be used to receive the first scan control signal U2D.

The second scan control transistor Msc2 is coupled to the scan signal output unit 104, the second voltage boosting unit 108b, the voltage stabilizing unit 106, and the first scan control transistor Msc1. The second scan control transistor Msc2 can be used to receive the second scan control signal D2U.

The scan signal output unit 104 includes a driving transistor Md1 and a driving capacitor Cd. A gate of the driving transistor Md1 is coupled to the bidirectional scanning control unit 102. The other end of the driving transistor Md1 except the gate receives the first clock signal CK. The other end of the driving transistor Md1 except the gate is used to output the scan signal G[N]. One end of the driving capacitor Cd is coupled to the gate of the driving transistor Md1 and the bidirectional scanning control unit 102. The other end of the driving capacitor Cd is coupled to the driving transistor Md1 and used to output the scan signal G[N].

The voltage stabilizing unit 106 includes a first voltage stabilizing transistor Mst1, a second voltage stabilizing transistor Mst2, a third voltage stabilizing transistor Mst3, a fourth voltage stabilizing transistor Mst4, and a voltage stabilizing capacitor Cst.

The first voltage stabilizing transistor Mst1 is coupled to the scanning signal output unit 104, and is turned on or off according to the second clock signal XCK. The second voltage stabilizing transistor Mst2 is coupled to the scan signal output unit 104 and the first voltage stabilizing transistor Mst1. The third voltage stabilizing transistor Mst3 is coupled to the first voltage stabilizing transistor Mst1, the second voltage stabilizing transistor Mst2, and the bidirectional scanning control unit 102. The fourth stabilized transistor Mst4 is coupled to the first stabilized transistor Mst1, the second stabilized transistor Mst2, the third stabilized transistor Mst3, and the bidirectional scanning control unit 102. One end of the voltage stabilizing capacitor Cst is coupled to the first voltage stabilizing transistor Mst1, the second voltage stabilizing transistor Mst2, the third voltage stabilizing transistor Mst3 and the fourth voltage stabilizing transistor Mst4. The other end of the voltage stabilizing capacitor Cst is coupled to the first clock signal CK.

The first voltage boosting unit 108a includes a first transistor M1, a second transistor M2, and a first capacitor C1.

The first transistor M1 is turned on or off according to the first reference voltage Vr1. The second transistor M2 is coupled to the first transistor M1. The second transistor M2 is turned on or off according to the first clock signal CK.

One end of the first capacitor C1 is coupled to the first transistor M1, the second transistor M2, and the first scan control transistor Msc1 of the bidirectional scanning control unit 102, and is used to output a first operating voltage A[N], so that A scan control transistor Msc1 can be turned on or off according to the first scan control signal U2D and the first operating voltage A[N]. The other end of the first capacitor C1 is coupled to the second reference voltage Vr2.

In this embodiment, the first reference voltage Vr1 is the scan signal G[N-2] output by the first-stage single-stage gate drive circuit 10_N-2, and the second reference voltage Vr2 is the previous-stage single-stage gate drive circuit 10_N -1 Scanning signal G[N-1] output.

The second voltage boosting unit 108b includes a third transistor M3, a fourth transistor M4, and a second capacitor C2.

The third transistor M3 is turned on or off according to the third reference voltage Vr3. The fourth transistor M4 is coupled to the third transistor M3. The fourth transistor M4 is turned on or off according to the first clock signal CK.

One end of the second capacitor C2 is coupled to the third transistor M3, the fourth transistor M4, and the second scan control transistor Msc2 of the bidirectional scanning control unit 102, and is used to output a second operating voltage B[N], so that The two scan control transistor Msc2 can be turned on or off according to the second scan control signal D2U and the second operating voltage B[N]. The other end of the second capacitor C2 is coupled to the fourth reference voltage Vr4.

In this embodiment, the third reference voltage Vr3 is the scan signal G[N+2] output by the second-stage single-stage gate drive circuit 10_N+2, and the fourth reference voltage Vr4 is the latter-stage single-stage gate drive circuit 10_N +1 output scan signal G[N+1].

In one embodiment, during the scan in the first direction, the (node) gate voltage Q[N] is mainly charged by the first voltage raising unit 108a, and the scan signal G[N] is adjusted; otherwise, the During the scan in the second direction, the (node) gate voltage Q[N]Q[N] is mainly charged by the second voltage boosting unit 108b, and the scan signal G[N] is adjusted.

Please refer to FIG. 3, which illustrates an operation timing diagram of one stage of the single-stage gate driving circuit in the gate driving circuit according to an embodiment of the present invention. In this embodiment, for example, the single-stage gate drive circuit 10_N shown in FIG. 2 is in the period of performing the scan in the first direction (ie, the first scan signal U2D is at a high level and the second scan signal D2U is at a low level) Operation timing diagram.

In a first stage S1, the scanning signal G[N-2] of the first-stage single-stage gate drive circuit 10_N-2 is at a high level, and the scanning signal G[N of the previous-stage single-stage gate drive circuit 10_N-1 -1] is a low level, the first clock signal CK is a low level, and the second clock signal XCK is a high level. CK1 and XCK1 are another set of clock signals, which are 90 degrees out of phase with the first clock signal CK and the second clock signal XCK, respectively. In this embodiment, they can be used to control the previous stage of the single-stage gate drive circuit 10_N The operation timing of the single-stage gate drive circuit 10_N-1 and the subsequent single-stage gate drive circuit 10_N+1. In one embodiment, one set of clock signals CK, XCK is used to control odd-level single-stage gate drive circuits 10_1, 10_3, etc., and the other set of clock signals CK1, XCK1 is used to control even-level single-stage Gate drive circuits 10_2, 10_4, etc. In another embodiment, one set of clock signals CK, XCK is used to control even-level single-stage gate drive circuits 10_2, 10_4, etc., and the other set of clock signals CK1, XCK1 is used to control odd-level single-stage Level gate drive circuits 10_1, 10_3, etc. The first scan control transistor Msc1, the first transistor M1, the driving transistor Md1, the first voltage stabilizing transistor Mst1 and the fourth voltage stabilizing transistor Mst4 are turned on. The second scanning transistor Msc2, the second transistor M2, the third transistor M3, the fourth transistor M4, the second voltage stabilizing transistor Mst2, and the third voltage stabilizing transistor Mst3 are turned off. The first operating voltage A[N] is raised from an initial level V0 to a first level by charging the first capacitor C1 with the scanning signal G[N-2] of the previous two-stage single-stage gate drive circuit 10_N-2 Operation level V1'. The gate voltage Q[N] of the driving transistor Md1 is raised from the initial level V0 to the first level V1 by charging the driving capacitor Cd with the first scan signal U2D, and the first level is lower than The first operation level V1' (the difference is approximately equal to the threshold voltage of the first scan control transistor Msc1).

In a second stage S2, the scanning signal G[N-2] of the first-stage single-stage gate drive circuit 10_N-2 is reduced from the high level to the low-level. The scanning signal G[N-1] is at a high level, the first clock signal CK is at a low level, and the second clock signal XCK is reduced from a high level to a low level. The first scan control transistor Msc1, the driving transistor Md1, the first voltage stabilizing transistor Mst1 and the fourth voltage stabilizing transistor Mst4 are turned on. The second scanning transistor Msc2, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the second voltage stabilizing transistor Mst2 and the third voltage stabilizing transistor Mst3 are turned off. The first operating voltage A[N] is raised from the first operating level V1' to a first level by charging the first capacitor C1 with the scanning signal G[N-1] of the previous single-stage gate drive circuit 10_N-1 Two operation level V2'. As the voltage of the gate terminal of the first scan control transistor Msc1 rises, the voltage higher than a high gate level Vgh applied by the first scan control signal U2D can pass through the first scan control transistor Msc1, thereby driving The gate voltage Q[N] of the transistor Md1 rises from the first step level V1 to a second step level V2.

In a third stage S3, the scanning signal G[N-2] of the first-stage single-stage gate drive circuit 10_N-2 is at a low level, and the scanning signal G[N of the previous-stage single-stage gate drive circuit 10_N-1 -1] From the high level to the low level, the first clock signal CK is the high level, and the second clock signal XCK is the low level. The second transistor M2, the fourth transistor M4, the driving transistor Md1 and the fourth voltage stabilizing transistor Mst4 are turned on. First scan control transistor Msc1, second scan transistor Msc2, first transistor M1, third transistor M3, first stabilized transistor Mst1, second stabilized transistor Mst2 and third stabilized transistor Mst3 shut down. Since the first capacitor C1 is discharged through the second transistor M2, the first operating voltage A[N] drops to the initial level V0. The gate voltage Q[N] of the driving transistor Md1 is raised from the second step level V2 to a third step level V3 by charging the driving capacitor Cd with the first clock signal CK. The scanning signal G[N] of the single-stage gate drive circuit 10_N is output in the third stage. After the first stage S1 and the second stage S2, the gate voltage (waveform) of the driving transistor Md1 will be raised to a higher voltage (third stage level V3) in the third stage S3 to adjust Scanning the waveform of the signal G[N] makes the rise time and fall time of the waveform of the scanning signal G[N] shorter.

In a fourth stage S4, the scanning signal G[N-2] of the first-stage single-stage gate drive circuit 10_N-2 is at a low level, and the scanning signal G[N of the previous-stage single-stage gate drive circuit 10_N-1 -1] is a low level, the first clock signal CK is a low level, and the second clock signal XCK is a low level. The driving transistor Md1 and the fourth voltage stabilizing transistor Mst4 are turned on. The first scan control transistor Msc1, the second scan transistor Msc2, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the first voltage stabilizing transistor Mst1, the second stable The piezoelectric crystal Mst2 and the third voltage stabilizing transistor Mst3 are turned off. The gate voltage Q[N] of the driving transistor Md1 will be pulled down from the third step level V3 to a fourth step level V4 due to the first clock signal CK falling to a low level. In some embodiments, the fourth step level V4 may be equal to or slightly lower than the second step level V2.

In a fifth stage S5, the scanning signal G[N-2] of the first-stage single-stage gate drive circuit 10_N-2 is at a low level, and the scanning signal G[N of the previous-stage single-stage gate drive circuit 10_N-1 -1] is a low level, the first clock signal CK is a low level, and the second clock signal XCK is reduced from a high level to a low level. The second scanning transistor Msc2, the third transistor M3 and the first voltage stabilizing transistor Mst1 are turned on. The first scan control transistor Msc1, the first transistor M1, the second transistor M2, the fourth transistor M4, the driving transistor Md1, the second stabilized transistor Mst2, the third stabilized transistor Mst3 and the fourth stable The piezoelectric crystal Mst4 is turned off. The driving capacitor Cd is discharged through the first voltage stabilizing transistor Mst1, and the first capacitor C1 is discharged through the second scanning transistor Msc2, so that the gate voltage Q[N] of the driving transistor Md1 is pulled down by the fourth step level V4 To the initial level V0.

In a sixth stage S6, the scanning signal G[N-2] of the first-stage single-stage gate drive circuit 10_N-2 is at a low level, and the scanning signal G[N of the previous-stage single-stage gate drive circuit 10_N-1 -1] is low level. The second transistor M2, the fourth transistor M4, the second voltage stabilizing transistor Mst2 and the third voltage stabilizing transistor Mst3 are turned on. The first scanning control transistor Msc1, the second scanning transistor Msc2, the first transistor M1, the second transistor M2, the driving transistor Md1, the first voltage stabilizing transistor Mst1 and the fourth voltage stabilizing transistor Mst4 are turned off. The gate voltage Q[N] of the driving transistor Md1 is coupled to the low gate level Vgl (that is, the low level in this embodiment), and is maintained at the initial level V0.

The high level described in the above embodiments may be equal to a high gate level Vgh, and the low level may be equal to a low gate level Vgl, and the high gate level Vgh is higher than the low gate level Vgl. Those skilled in the art can easily understand that the high gate level Vgh, the low gate level Vgl, the initial level V0, the first level V1, the second level V2, and the third level V3, the fourth step level V4, the first operation level V1' and the second operation level V2' can be designed according to actual circuit requirements.

In one embodiment, the first scan control signal U2D is higher than the high gate level Vgh. In one embodiment, the first scan control signal U2D is 15 volts, 20 volts or 25 volts, and the second scan control signal D2U is -12 volts. In an embodiment, in each stage of the single-stage gate drive circuits 10_1~10_K, the capacitance of the first capacitor C1 is greater than or equal to that of a gate-source capacitor and a gate-drain capacitor of the first scan control transistor Msc1 The sum of the capacitance values, the capacitance value of the second capacitor C2 is greater than or equal to the sum of the capacitance values of a gate-source capacitance and a gate-drain capacitance of the second scan control transistor Msc2, wherein the gate-source capacitance is the gate and The parasitic capacitance between the source and the gate-drain capacitance is the parasitic capacitance between the gate and the drain.

According to the embodiment of the present invention, the gate driving circuit 1 can adjust the voltage waveform of the scanning signals G[1]~G[K] by raising the gate voltage of the driving transistor Md1 to a higher voltage level, The scan signals G[1]~G[K] with short rise and fall times can be output, so that the gate transistors on the gate line can be turned on or off correctly within the scan time, thereby allowing the display device The pixels in can be correctly written or not written to achieve the effect of improving the picture quality of the display device.

In summary, although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application.

1‧‧‧Gate drive circuit 10_1~10_K‧‧‧Single-stage gate drive circuit 102‧‧‧‧Bidirectional scanning control unit 104‧‧‧Scanning signal output unit 106‧‧‧Regulator unit 108a‧‧‧First voltage Lifting unit 108b ‧‧‧ Second voltage lifting unit U2D‧‧‧ First scan control signal D2U‧‧‧ Second scan control signal G[1]~G[K]‧‧‧Scan signal CK‧‧‧First time Pulse signal XCK‧‧‧ Second clock signal Vr1‧‧‧ First reference voltage Vr2‧‧‧ Second reference voltage Vr3‧‧‧ Third reference voltage Vr4‧‧‧‧ Fourth reference voltage A[N]‧‧‧ First operating voltage B[N]‧‧‧ Second operating voltage M1‧‧‧ First transistor M2‧‧‧ Second transistor M3‧‧‧ Third transistor M4‧‧‧ Fourth transistor Msc1‧‧ ‧First scan control transistor Msc2‧‧‧Second scan control transistor Md1‧‧‧Drive transistor Mst1‧‧‧First stabilized transistor Mst2‧‧‧Second stabilized transistor Mst3‧‧‧ Voltage stabilizing transistor Mst4 ‧‧‧ Fourth voltage stabilizing transistor C1 ‧‧‧ First capacitor C2 ‧‧‧ Second capacitor Cd ‧‧‧ Drive capacitor Cst ‧‧‧ Stabilizing capacitor

FIG. 1 shows a block diagram of a gate driving circuit according to an embodiment of the present invention; FIG. 2 shows a block diagram of one of the single-stage gate driving circuits in the gate driving circuit according to an embodiment of the present invention ; And FIG. 3 shows an operation timing diagram of one of the single-stage gate drive circuits in the gate drive circuit according to an embodiment of the present invention.

1‧‧‧ Gate drive circuit

10_1~10_K‧‧‧single-stage gate drive circuit

102‧‧‧Two-way scanning control unit

104‧‧‧scanning signal output unit

106‧‧‧ Voltage stabilizing unit

108a‧‧‧First voltage lifting unit

108b‧‧‧Second voltage lifting unit

U2D‧‧‧ First scan control signal

D2U‧‧‧Second scan control signal

G[1]~G[K]‧‧‧scan signal

Vr1‧‧‧First reference voltage

Vr2‧‧‧Second reference voltage

Vr3‧‧‧third reference voltage

Vr4‧‧‧ Fourth reference voltage

Claims (10)

A gate drive circuit for a display device, comprising: a plurality of single-level gate drive circuits, each level of the single-level gate drive circuit includes: a bidirectional scanning control unit for receiving a first scanning control signal and a A second scanning control signal; a scanning signal output unit, coupled to the bidirectional scanning control unit, the scanning signal output unit for outputting a scanning signal; a voltage stabilizing unit, coupled to the bidirectional scanning control unit and the scanning signal The output unit, the voltage stabilizing unit stabilizes the scanning signal according to a first clock signal and a second clock signal; a first voltage boosting unit, coupled to the bidirectional scanning control unit, the first voltage boosting unit according to a A first reference voltage of the first-stage single-stage gate drive circuit and a second reference voltage of the previous-stage single-stage gate drive circuit adjust the scan signal; and a second voltage boosting unit, coupled to the bidirectional scan The control unit, the second voltage raising unit adjusts the scan signal according to a third reference voltage of a second-stage single-stage gate drive circuit and a fourth reference voltage of a second-stage single-stage gate drive circuit. The gate drive circuit as described in item 1 of the patent application scope, wherein the first voltage boosting unit includes: a first transistor that is turned on or off according to the first reference voltage; a second transistor that is coupled to the A first transistor, the second transistor is turned on or off according to the first clock signal; and a first capacitor, one end of the first capacitor is coupled to the first transistor, the second transistor and the bidirectional The scan control unit is used to output a first operating voltage to the bidirectional scan control unit, and the other end of the first capacitor receives the second reference voltage, wherein the second voltage boosting unit includes: a third transistor, based on the The third reference voltage is turned on or off; a fourth transistor, coupled to the third transistor, the fourth transistor is turned on or off according to the first clock signal; and a second capacitor, one end of the second capacitor The third transistor, the fourth transistor, and the bidirectional scan control unit are coupled to output a second operating voltage to the bidirectional scan control unit. The other end of the second capacitor receives the fourth reference voltage. The gate driving circuit as described in item 2 of the patent application scope, wherein the scanning signal output unit of the single-stage gate driving circuit at each stage includes: a driving transistor, and a gate of the driving transistor is coupled to the bidirectional A scanning control unit; a driving capacitor, one end of the driving capacitor is coupled to the gate of the driving transistor and the bidirectional scanning control unit, and the other end of the driving capacitor is coupled to the driving transistor and used to output the scanning signal, The first reference voltage is the scan signal output by the previous two-stage single-stage gate drive circuit, the second reference voltage is the scan signal output from the previous one-stage single-stage gate drive circuit, and the third reference voltage is The scan signal output by the second-stage single-stage gate drive circuit, the fourth reference voltage is the scan signal output by the second-stage single-stage gate drive circuit. The gate drive circuit as described in item 3 of the patent application scope, wherein the voltage waveform of the gate of each drive transistor includes a first stage, a second stage, and a third stage. In the first stage, The voltage waveform of the gate of each driving transistor is raised from an initial level to a first-stage level. In the second stage, the voltage waveform of the gate of each driving transistor is changed from the first step The step level is raised to a second step level, and in the third stage, the voltage waveform of the gate of each driving transistor is raised from the second step level to a third step level. The gate drive circuit as described in item 3 of the patent application scope, wherein in the first stage, the first reference voltage is at a high level, the second reference voltage is at a low level, the third reference voltage and the first The four reference voltages are at a low level, and the first clock signal is at a low level; in the second stage, the first reference voltage is changed from a high level to a low level, and the second reference voltage is at a high level, The third reference voltage and the fourth reference voltage are at a low level, the first clock signal is at a low level; in the third stage, the first reference voltage is at a low level, and the second reference voltage is from high The level is changed to a low level, the third reference voltage is a low level, the fourth reference voltage is changed from a low level to a high level, and the first clock signal is a high level. The gate drive circuit as described in item 2 of the patent application scope, wherein the width-to-length ratio of the first transistors and the third transistors is greater than or equal to 143, and those of the second transistors and the fourth transistors The width-to-length ratio is greater than or equal to 25, or the width-to-length ratio of the first transistors M1 and the third transistors M3 is greater than or equal to 143, the widths of the second transistors M2 and the fourth transistors M4 The length ratio is greater than or equal to 25. The gate drive circuit as described in item 2 of the patent application, wherein each of the bidirectional scanning control units includes: a first scanning control transistor, coupled to the scanning signal output unit, the voltage boosting unit and the voltage stabilizing unit, The first scanning control transistor is turned on or off according to the first scanning control signal and the first operating voltage; and a second scanning control transistor is coupled to the scanning signal output unit, the voltage boosting unit and the voltage stabilizing unit , The first scan control transistor and the first scan control transistor are turned on or off according to the first scan control signal and the second operating voltage. The gate drive circuit as described in item 7 of the patent application range, wherein in each of the single-stage gate drive circuits, the capacitance of the first capacitor is greater than or equal to a gate-source capacitance of the first scan control transistor With the sum of the capacitance values of a gate-drain capacitor, the capacitance value of the second capacitor is greater than or equal to the sum of the capacitance values of a gate-source capacitance and a gate-drain capacitance of the second scan control transistor. The gate drive circuit as described in item 1 of the patent application, wherein each of the voltage stabilizing units includes: a first voltage stabilizing transistor, coupled to the scan signal output unit, and turned on or off according to the second clock signal A second voltage-stabilized transistor, coupled to the scan signal output unit and the first voltage-stabilized transistor; a third voltage-stabilized transistor, coupled to the first voltage-stabilized transistor and the second voltage-stabilized transistor And the bidirectional scanning control unit; a fourth voltage stabilizing transistor, coupled to the first voltage stabilizing transistor, the second voltage stabilizing transistor, the third voltage stabilizing transistor and the bidirectional scanning control unit; and a stable A capacitor, one end of the voltage stabilizing capacitor is coupled to the first voltage stabilizing transistor, the second voltage stabilizing transistor, the third voltage stabilizing transistor and the fourth voltage stabilizing transistor, and the other end of the voltage stabilizing capacitor The first clock signal is coupled. The gate drive circuit as described in item 1 of the patent application range, wherein the level of the first scan control signal or the second scan control signal is greater than or equal to the high level of the first clock signal.

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