TW202004713A - Gate driver circuit - Google Patents

Abstract

The present invention discloses a gate driver circuit including multiple stages of single stage shift register circuits. Each stage of the shift register circuits includes a dual-scan control unit, a scan signal output unit, a voltage stabilizer unit and a voltage lifting unit. The dual-scan control unit is configured to receive a first scan control signal and a second scan control signal. The scan signal output unit is coupled to the dual-scan control unit, and is configured to output a scan signal. The voltage stabilizer unit is coupled to the dual-scan control unit and the scan signal output unit, and stabilizes the scan signal according to a first clock signal and a second clock signal. The voltage lifting unit is coupled to the dual-scan control unit and the scan signal output unit, and adjusts the scan signal according to a first reference voltage of a previous two stage of shift register circuit and a second reference voltage of a previous one stage of shift register circuit.

Description

Gate driver circuit

The invention relates to a gate driver circuit, in particular to a gate driver circuit for a display device.

In the prior art, the display panel usually includes multiple gate lines and multiple data lines. The gate lines and the data lines are arranged in a staggered manner. One or more pixels are provided at the position where each gate line and data line intersect. By controlling the switch of the transistor coupled to the gate line with the scan signal, it is selected whether to write the signal on the data line into the pixel, and the display purpose is achieved.

As people's requirements for the resolution of display devices become higher and higher, the number of gate lines and data lines in the display device is bound to increase, and the scanning time between the gate lines and the gate lines is shortened. The shortening of the scanning time will make the rising time and falling time of the scanning signal output by the gate driver circuit to the gate line become more important. If the rise time/fall time is too long, it will make the transistor coupled to the gate line too late to turn on/off, so that the pixels cannot be written to the correct data, which will affect the picture quality of the display device.

Therefore, how to shorten the rise time and fall time of the scan signal output by the gate driver circuit has become one of the goals of the industry.

The purpose of the present invention is to propose a gate drive circuit that can shorten the rise time and fall time of the output scan signal.

The embodiment of the invention discloses a gate driver circuit including a multi-stage single-stage shift register circuit. The shift register circuits at all levels include a bidirectional scanning control unit, a scanning signal output unit, a voltage stabilizing unit, and a voltage boosting unit. The bidirectional scanning control unit is used to receive a first scanning control signal and a second scanning control signal. The scan signal output unit is coupled to the bidirectional scan control unit, and is used to output a scan signal. The voltage stabilizing unit is coupled to the bidirectional scanning control unit and the scanning signal output unit. The voltage stabilizing unit stabilizes the scanning signal according to a first clock signal and a second clock signal. The voltage boosting unit is coupled to the bidirectional scan control unit and the scan signal output unit. The voltage boosting unit is based on a first reference voltage of a previous two-stage shift register circuit and a second reference of a previous one-stage shift register circuit The reference voltage adjusts the scan signal.

According to an embodiment of the present invention, the gate driver circuit can output a scan signal having a short rise time and fall time, so that the transistor on the gate line can be turned on or off correctly within the scan time, thereby enabling the display device Pixels can be correctly written or not written to achieve the effect of improving the picture quality of the display device.

In order to have a better understanding of the above and other aspects of the present invention, the following examples are specifically described in conjunction with the accompanying drawings as follows:

Please refer to FIG. 1, which illustrates a block diagram of a gate driver circuit according to an embodiment of the invention. The gate driver circuit 1 includes a plurality of single-stage shift register circuits 10_1~10_K, where K is the number of shift register circuits and K is a positive integer. The gate driver circuit 1 can be disposed in a display device (not shown). The display device may include multiple gate lines (not shown) and multiple data lines (not shown), and the gate lines and the data lines are alternately arranged. The gate driver circuit 1 can be coupled to these gate lines. Further, the shift register circuits 10_1~10_K of the gate driver circuit 1 are respectively coupled to one of the gate lines to provide scanning signals G[1]~G[K] to the transistors of the gate line ( Not shown).

Each stage of the shift register circuits 10_1~10_K includes a bidirectional scanning control unit 102, a scanning signal output unit 104, a voltage stabilizing unit 106, and a voltage boosting unit 108. It should be understood that, because the shift register circuits 10_1 to 10_K at all levels have similar circuit structures, the shift register circuit 10_N will only be described as a representative example below.

The bidirectional scanning control unit 102 is used to receive a first scanning control signal U2D and a second scanning control signal D2U. For example, when the first scan control signal U2D is at a high level and the second scan control signal D2U is at a low level, the display device performs a scan in a first direction; otherwise, when the first scan control signal U2D is at a low level, When the second scanning control signal D2U is at a high level, the display device performs scanning in a second direction. Generally speaking, the first direction is opposite to the second direction, for example, the first direction is from top to bottom, and the second direction is from bottom to top.

The scan signal output unit 104 is coupled to the bidirectional scan control unit 102 for outputting the scan signal G[N]. The scan signal G[N] can be output to the transistor coupled to the gate line, so that the transistor can be controlled to be turned on or off by the scan signal G[N].

The voltage stabilizing unit 106 is coupled to the bidirectional scanning control unit 102 and the scanning signal output unit 104, and stabilizes the scanning signal G[N] according to a first clock signal and a second clock signal. The first clock signal is different from the second clock signal. In this embodiment, the first clock signal and the second clock signal are substantially opposite. For example, when the first clock signal is at a high level, the second clock signal is at a low level; conversely, when the first clock signal is at a low level, the second clock signal is at a high level. However, considering the needs of the actual circuit, the first clock signal and the second clock signal are not limited to the above limitations.

The voltage boosting unit 108 is coupled to the bidirectional scan control unit 102 and the scan signal output unit 104, and is based on a first reference voltage Vr1 of a previous two-stage shift register circuit 10_N-2 and a previous stage shift register A second reference voltage Vr2 of the circuit 10_N-1 adjusts the scan signal G[N].

The detailed structure of the shift register circuits 10_1~10_K will be further described below.

Please refer to FIG. 2, which illustrates a block diagram of one stage of the shift register circuit in the gate driver circuit according to an embodiment of the invention. Since the shift register circuits 10_1 to 10_K of each stage have similar circuit structures, this embodiment is described by taking the shift register circuit 10_N as a representative example.

The bidirectional scan control unit 102 includes a first scan control transistor Msc1 and a second scan transistor Msc2.

The first scan control transistor Msc1 is coupled to the scan signal output unit 104, the voltage boosting unit 108, and the voltage stabilizing unit 106. The first scan control transistor can be used to receive the first scan control signal U2D, and turn on or off according to the first scan control signal U2D and the scan signal G[N+2] output by the first two-stage shift register circuit 10_N-2 .

The second scan control transistor Msc2 is coupled to the scan signal output unit 104, the voltage boosting unit 108, the voltage stabilizing unit 106, and the first scan control transistor Msc1. The second scan control transistor Mst2 can be used to receive the second scan control signal D2U, and turn on or turn on the scan signal G[N+2] output from the second scan control signal D2U and the one-to-two shift register circuit 10_N+2 shut down.

The scan signal output unit 104 includes a driving transistor Md1 and a driving capacitor Cd. A gate of the driving transistor Md1 is coupled to the voltage boosting unit 108. The other end of the driving transistor Md1 except the gate receives the first clock signal CK. The other end of the driving transistor Md1 except the gate is used to output the scan signal G[N]. One end of the driving capacitor Cd is coupled to the gate of the driving transistor Md1 and the voltage boosting unit 108. The other end of the driving capacitor Cd is coupled to the driving transistor Md1 and used to output the scan signal G[N].

The voltage stabilizing unit 106 includes a first voltage stabilizing transistor Mst1, a second voltage stabilizing transistor Mst2, a third voltage stabilizing transistor Mst3, a fourth voltage stabilizing transistor Mst4, and a voltage stabilizing capacitor Cst.

The first voltage stabilizing transistor Mst1 is coupled to the scanning signal output unit 104, and is turned on or off according to the second clock signal XCK. The second voltage stabilizing transistor Mst2 is coupled to the scan signal output unit 104 and the first voltage stabilizing transistor Mst1. The third voltage stabilizing transistor Mst3 is coupled to the first voltage stabilizing transistor Mst1, the second voltage stabilizing transistor Mst2, and the bidirectional scanning control unit 102. The fourth stabilized transistor Mst4 is coupled to the first stabilized transistor Mst1, the second stabilized transistor Mst2, the third stabilized transistor Mst3, and the bidirectional scanning control unit 102. One end of the voltage stabilizing capacitor Cst is coupled to the first voltage stabilizing transistor Mst1, the second voltage stabilizing transistor Mst2, the third voltage stabilizing transistor Mst3 and the fourth voltage stabilizing transistor Mst4. The other end of the voltage stabilizing capacitor Cst is coupled to the first clock signal CK.

The voltage boosting unit 108 includes a first transistor M1, a second transistor M2, and a first capacitor C1.

The first transistor M1 is turned on or off according to the first reference voltage Vr1 and the second reference voltage Vr2. In this embodiment, the first reference voltage Vr1 is the scan signal G[N-2] output by the first-stage shift register circuit 10_N-2, and the second reference voltage Vr2 is the previous-stage shift register circuit 10_N -1 Scanning signal G[N-1] output.

The second transistor M2 is coupled to the first transistor M1. The second transistor M2 is based on the scan signal G[N+2] output by the second-stage shift register circuit 10_N+2 and the scan signal G[N+ output by the last-stage shift register circuit 10_N+1 1] Turn on or off.

The first capacitor C1 is coupled to the first transistor M1, the second transistor M2, the bidirectional scanning control unit 102 and the scan signal output unit 104.

In one embodiment, during the scanning in the first direction, the level of the gate voltage Q[N] is raised by turning on or off the first transistor M1, and the scanning signal G[N] is adjusted; On the contrary, during the scanning in the second direction, the level of the gate voltage Q[N] is increased mainly by turning on or off the second transistor M2, and then the scanning signal G[N] is adjusted.

Please refer to FIG. 3, which illustrates an operation timing diagram of one stage of the shift register circuit in the gate driver circuit according to an embodiment of the present invention. This embodiment is, for example, a period during which the shift register circuit 10_N shown in FIG. 2 performs scanning in the first direction (that is, the first scan signal U2D is at a high level and the second scan signal D2U is at a low level) Operation timing diagram.

In a first stage S1, the scanning signal G[N-2] of the first-stage shift register circuit 10_N-2 is at a high level, and the scanning signal G[N of the previous-stage shift register circuit 10_N-1 -1] is a low level, the first clock signal CK is a low level, and the second clock signal XCK is a high level. CK1 and XCK1 are another group of clock signals, which are 90 degrees out of phase with the first clock signal CK and the second clock signal XCK, respectively. In this embodiment, they can be used to control the previous stage of the shift register circuit 10_N Operation timings of the shift register circuit 10_N-1 and the shift register circuit 10_N+1 of the subsequent stage. In one embodiment, one set of clock signals CK, XCK is used to control the shift register circuits 10_1, 10_3 of the odd-numbered stages, and the other set of clock signals CK1, XCK1 is used to control the shift of the even-numbered stages The register circuits 10_2, 10_4, etc. In another embodiment, one set of clock signals CK, XCK is used to control even-level shift register circuits 10_2, 10_4, etc., and the other set of clock signals CK1, XCK1 is used to control odd-level shifts Bit register circuits 10_1, 10_3, etc. The first scan control transistor Msc1, the first transistor M1, the driving transistor Md1, the first voltage stabilizing transistor Mst1 and the fourth voltage stabilizing transistor Mst4 are turned on. The second scanning transistor Msc2, the second transistor M2, the second voltage stabilizing transistor Mst2 and the third voltage stabilizing transistor Mst3 are turned off. The gate voltage Q[N] of the driving transistor Md1 is raised from an initial level V0 to a first-level level V1 by charging the first capacitor C1 and the driving capacitor Cd with the first scan signal U2D.

In a second stage S2, the scan signal G[N-1] of the previous stage shift register circuit 10_N-1 is at a high level, the first clock signal CK is at a low level, and the second clock signal XCK is set by The high level is reduced to the low level. The first transistor M1, the driving transistor Md1, the first voltage stabilizing transistor Mst1 and the fourth voltage stabilizing transistor Mst4 are turned on. The first scan control transistor Msc1, the second scan transistor Msc2, the second transistor M2, the second voltage stabilizing transistor Mst2, and the third voltage stabilizing transistor Mst3 are turned off. The gate voltage Q[N] of the driving transistor Md1 is charged to the first capacitor C1 by the scanning signal G[N-1] of the previous stage shift register circuit 10_N-1, and the first level V1 Raise to a second step level V2. The scan signal G[N-2] of the first-stage shift register circuit 10_N-2 will be reduced from the high level to the low level during the second stage S2.

In a third stage S3, the scanning signal G[N-2] of the first-stage shift register circuit 10_N-2 is low level, and the scanning signal G[N of the previous-stage shift register circuit 10_N-1 -1] From the high level to the low level, the first clock signal CK is the high level, and the second clock signal XCK is the low level. The driving transistor Md1 and the fourth voltage stabilizing transistor Mst4 are turned on. The first scanning control transistor Msc1, the second scanning transistor Msc2, the first transistor M1, the second transistor M2, the first voltage stabilizing transistor Mst1, the second voltage stabilizing transistor Mst2, and the third voltage stabilizing transistor Mst3 shut down. The gate voltage Q[N] of the driving transistor Md1 is raised from the second step level V2 to a third step level V3 by charging the driving capacitor Cd with the first clock signal CK. The scan signal G[N] of the shift register circuit 10_N is output in the third stage. After the first stage S1 and the second stage S2, the gate voltage (waveform) of the driving transistor Md1 will be raised to a higher voltage (third stage level V3) in the third stage S3 to adjust Scanning the waveform of the signal G[N] makes the rise time and fall time of the waveform of the scanning signal G[N] shorter.

In a fourth stage S4, the scan signal G[N-2] of the first-stage shift register circuit 10_N-2 is low level, and the scan signal G[N of the previous-stage shift register circuit 10_N-1 -1] is a low level, the first clock signal CK is a low level, and the second clock signal XCK is a low level. The driving transistor Md1 and the fourth voltage stabilizing transistor Mst4 are turned on. The first scanning control transistor Msc1, the second scanning transistor Msc2, the first transistor M1, the second transistor M2, the first voltage stabilizing transistor Mst1, the second voltage stabilizing transistor Mst2, and the third voltage stabilizing transistor Mst3 shut down. The gate voltage Q[N] of the driving transistor Md1 will be pulled down from the third step level V3 to a fourth step level V4 due to the first clock signal CK falling to a low level.

In a fifth stage S5, the scanning signal G[N+2] of the second-stage shift register circuit 10_N+2 is at a high level, and the scanning signal G[N of the previous-stage shift register circuit 10_N-1 -1] is a low level, the first clock signal CK is a low level, and the second clock signal XCK is reduced from a high level to a low level. The second scanning transistor Msc2, the second transistor M2, and the first voltage stabilizing transistor Mst1 are turned on. The first scan control transistor Msc1, the first transistor M1, the driving transistor Md1, the second voltage stabilizing transistor Mst2, the third voltage stabilizing transistor Mst3, and the fourth voltage stabilizing transistor Mst4 are turned off. The driving capacitor Cd is discharged through the first voltage stabilizing transistor Mst1, and the first capacitor C1 is discharged through the second scanning transistor Msc2, so that the gate voltage Q[N] of the driving transistor Md1 is pulled down by the fourth step level V4 To the initial level V0.

In a sixth stage S6, the scanning signal G[N-2] of the first-stage shift register circuit 10_N-2 is at a low level, and the scanning signal G[N of the previous-stage shift register circuit 10_N-1 -1] is low level. The second voltage stabilizing transistor Mst and the third voltage stabilizing transistor Mst3 are turned on. The first scanning control transistor Msc1, the second scanning transistor Msc2, the first transistor M1, the second transistor M2, the driving transistor Md1, the first voltage stabilizing transistor Mst1 and the fourth voltage stabilizing transistor Mst4 are turned off. The gate voltage Q[N] of the driving transistor is coupled to the low gate level Vgl (that is, the low level in this embodiment), and is maintained at the initial level V0.

Please refer to FIG. 4, which is a block diagram of one stage of the shift register circuit in the gate driver circuit according to another embodiment of the present invention. The embodiment shown in FIG. 4 is similar to the embodiment shown in FIG. 2 except for the voltage boosting unit 108. The first reference voltage Vr1 is the voltage Q[N-2] of the gate of the driving transistor Md1 of the first-stage shift register circuit 10_N-2, and the second reference voltage Vr2 is the previous-stage shift register circuit 10_N -1 scan signal G[N-1]. The operation timing of the embodiment shown in FIG. 4 is as shown in FIG. 5. This embodiment is, for example, an operation timing chart during a scan in the first direction (that is, the first scan signal U2D is at a high level and the second scan signal D2U is at a low level).

In a first stage S1', the gate voltage Q[N-2] of the transistor Md1 of the first-stage shift register circuit 10_N-2 is a third-stage level V3', and the previous-stage shift temporarily The scan signal G[N-1] of the memory circuit 10_N-1 is at a low level, the first clock signal CK is at a low level, and the second clock signal XCK is at a high level. CK1 and XCK1 are another set of clock signals, which have a specific phase difference (for example, 90 degrees) from the first clock signal CK and the second clock signal XCK, respectively, and can be used to control the shift register circuit in this embodiment The operation timing of the previous stage shift register circuit 10_N-1 of 10_N and the next stage shift register circuit 10_N+1. The first scan control transistor Msc1, the first transistor M1, the driving transistor Md1, the first voltage stabilizing transistor Mst1 and the fourth voltage stabilizing transistor Mst4 are turned on. The second scanning transistor Msc2, the second transistor M2, the second voltage stabilizing transistor Mst2 and the third voltage stabilizing transistor Mst3 are turned off. The shift register circuit 10_N drives the gate voltage Q[N] of the transistor Md1 to be raised from an initial level V0′ to a first level by charging the first capacitor C1 and the driving capacitor Cd with the first scan signal U2D Step level V1'.

In a second stage S2', the gate voltage Q[N-2] of the transistor Md1 of the first two-stage shift register circuit 10_N-2 is reduced from a fourth step level V4' to a fifth Step level V5', the scan signal G[N-1] of the previous stage shift register circuit 10_N-1 is high level, the first clock signal CK is low level, and the second clock signal XCK is The high level is reduced to the low level. The first transistor M1, the driving transistor Md1, the first voltage stabilizing transistor Mst1 and the fourth voltage stabilizing transistor Mst4 are turned on. The first scan control transistor Msc1, the second scan transistor Msc2, the second transistor M2, the second voltage stabilizing transistor Mst2, and the third voltage stabilizing transistor Mst3 are turned off. The gate voltage Q[N] of the driving transistor Md1 of the shift register circuit 10_N is charged to the first capacitor C1 by the scan signal G[N-1] of the previous stage shift register circuit 10_N-1 It rises from the first step level V1' to a second step level V2'.

In a third stage S3', the gate voltage Q[N-2] of the transistor Md1 of the first-stage shift register circuit 10_N-2 is the initial level V0', and the previous-stage shift register circuit 10_N The scanning signal G[N-1] of -1 is reduced from a high level to a low level, the first clock signal CK is a high level, and the second clock signal XCK is a low level. The driving transistor Md1 and the fourth voltage stabilizing transistor Mst4 are turned on. The first scanning control transistor Msc1, the second scanning transistor Msc2, the first transistor M1, the second transistor M2, the first voltage stabilizing transistor Mst1, the second voltage stabilizing transistor Mst2, and the third voltage stabilizing transistor Mst3 shut down. The gate voltage Q[N] of the driving transistor Md1 is charged from the second step level V2' to the third step level V3' by charging the driving capacitor Cd with the first clock signal CK, and then from the third step level V3' The three-step level V3' is raised to the fourth-step level V4'. The scan signal G[N] of the shift register circuit 10_N is output in the third stage. After the first stage S1' and the second stage S2', the gate voltage (waveform) of the driving transistor Md1 of the shift register circuit 10_N is raised to a higher voltage in the third stage S3' ( The fourth step level V4') is to adjust the waveform of the scanning signal G[N], so that the rising time and the falling time of the scanning signal G[N] waveform are shortened.

In a fourth stage S4', the gate voltage Q[N-2] of the transistor Md1 of the first-stage shift register circuit 10_N-2 is the initial level V0', and the previous-stage shift register circuit 10_N The scan signal G[N-1] of -1 is at a low level, the first clock signal CK is at a low level, and the second clock signal XCK is at a low level. The driving transistor Md1 and the fourth voltage stabilizing transistor Mst4 are turned on. The first scanning control transistor Msc1, the second scanning transistor Msc2, the first transistor M1, the second transistor M2, the first voltage stabilizing transistor Mst1, the second voltage stabilizing transistor Mst2, and the third voltage stabilizing transistor Mst3 shut down. The gate voltage Q[N] of the driving transistor Md1 of the shift register circuit 10_N is pulled down from the fourth step level V4' to the fifth step due to the first clock signal CK falling to a low level Level V5'.

In a fifth stage S5', the gate voltage Q[N-2] of the transistor Md1 of the first-stage shift register circuit 10_N-2 is the initial level V0', and the previous-stage shift register circuit 10_N The scan signal G[N-1] of -1 is low level, the scan signal G[N+2] of the second-stage shift register circuit 10_N+2 is high level, and the first clock signal CK is low Level, the second clock signal XCK is high level. The second scanning transistor Msc2, the second transistor M2, and the first voltage stabilizing transistor Mst1 are turned on. The first scan control transistor Msc1, the first transistor M1, the driving transistor Md1, the second voltage stabilizing transistor Mst2, the third voltage stabilizing transistor Mst3, and the fourth voltage stabilizing transistor Mst4 are turned off. The driving capacitor Cd is discharged through the first voltage stabilizing transistor Mst1, and the first capacitor C1 is discharged through the second scanning transistor Msc2, so that the gate voltage Q[N] of the driving transistor Md1 changes from the fifth step level V5' Pull down to the initial level V0'.

In a sixth stage S6', the gate voltage Q[N-2] of the transistor Md1 of the first-stage shift register circuit 10_N-2 is the initial level V0', and the previous-stage shift register circuit 10_N The scanning signal G[N-1] of -1 is low level. The second voltage stabilizing transistor Mst and the third voltage stabilizing transistor Mst3 are turned on. The first scanning control transistor Msc1, the second scanning transistor Msc2, the first transistor M1, the second transistor M2, the driving transistor Md1, the first voltage stabilizing transistor Mst1 and the fourth voltage stabilizing transistor Mst4 are turned off. The gate voltage Q[N] of the driving transistor is coupled to the low gate level Vgl (that is, the low level in this embodiment), and is maintained at the initial level V0′.

The high level described in the above embodiments may be equal to a high gate level Vgh, and the low level may be equal to a low gate level Vgl, and the high gate level Vgh is higher than the low gate level Vgl. Those skilled in the art can easily understand that the high gate level Vgh, the low gate level Vgl, the initial level V0, V0', the first step level V1, V1', the second step level V2, V2', third-step levels V3, V3', fourth-step levels V4, V4', and fifth-step levels V5, V5' can be designed according to actual circuit requirements.

According to the embodiment of the present invention, the gate driver circuit 1 can adjust the voltage waveform of the scanning signals G[1]~G[K] by raising the gate voltage of the driving transistor Md1 to a higher voltage level, It can output scan signals G[1]~G[K] with shorter rise time and fall time, so that the transistor on the gate line can be turned on or off correctly within the scan time, so that the display device The pixels can be correctly written or not written to achieve the effect of improving the picture quality of the display device.

In summary, although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application.

1‧‧‧Gate driver circuit 10_1~10_K‧‧‧shift register circuit 102‧‧‧bidirectional scanning control unit 104‧‧‧scanning signal output unit 106‧‧‧regulation unit 108‧‧‧voltage rise unit U2D‧‧‧First scan control signal D2U‧‧‧Second scan control signal G[1]~G[K]‧‧‧Scan signal Vr1‧‧‧First reference voltage Vr2‧‧‧Second reference voltage CK‧ ‧‧ First clock signal XCK‧‧‧ Second clock signal M1‧‧‧ First transistor M2‧‧‧Second transistor Msc1‧‧‧First scan control transistor Msc2‧‧‧Second scan control Transistor Md1‧‧‧Drive transistor Mst1‧‧‧First stabilized transistor Mst2‧‧‧Second stabilized transistor Mst3‧‧‧Fourth stabilized transistor Mst4‧‧‧‧Stabilized transistor ‧‧‧ First capacitor Cd‧‧‧Drive capacitor Cst‧‧‧Voltage stabilizing capacitor

FIG. 1 is a block diagram of a gate driver circuit according to an embodiment of the present invention; FIG. 2 is a block diagram of a one-stage shift register circuit in a gate driver circuit according to an embodiment of the present invention FIG. 3 shows an operation timing diagram of one-stage shift register circuit in the gate driver circuit according to an embodiment of the present invention; FIG. 4 shows a gate driver circuit according to another embodiment of the present invention; FIG. 5 is a block diagram of one stage of the shift register circuit; and FIG. 5 shows an operation timing diagram of one stage of the shift register circuit in the gate driver circuit according to another embodiment of the present invention.

1‧‧‧ Gate driver circuit

10_1~10_K‧‧‧Shift register circuit

102‧‧‧Two-way scanning control unit

104‧‧‧scanning signal output unit

106‧‧‧ Voltage stabilizing unit

108‧‧‧Voltage lifting unit

U2D‧‧‧ First scan control signal

D2U‧‧‧Second scan control signal

G[1]~G[K]‧‧‧scan signal

Vr1‧‧‧First reference voltage

Vr2‧‧‧Second reference voltage

Claims (10)

A gate driver circuit includes: a complex-level single-stage shift register circuit, and each level of the shift register circuit includes: a bidirectional scan control unit for receiving a first scan control signal and a second scan Control signal; a scan signal output unit, coupled to the bidirectional scan control unit, the scan signal output unit is used to output a scan signal; a voltage regulator unit, coupled to the bidirectional scan control unit and the scan signal output unit, The voltage stabilizing unit stabilizes the scanning signal according to a first clock signal and a second clock signal; and a voltage boosting unit coupled to the bidirectional scanning control unit and the scanning signal output unit, the voltage boosting unit according to a A first reference voltage of the first-stage shift register circuit and a second reference voltage of the previous-stage shift register circuit adjust the scan signal. The gate driver circuit as described in item 1 of the patent application, wherein each of the voltage raising units includes: a first transistor, which is turned on or off according to the first reference voltage and the second reference voltage; a second transistor , Coupled to the first transistor, the second transistor is turned on or off according to the scan signal output by a rear two-stage shift register circuit; and a first capacitor, coupled to the first transistor, The second transistor, the bidirectional scanning control unit and the scanning signal output unit. The gate driver circuit as described in item 2 of the patent application scope, wherein the scanning signal output unit of the shift register circuit at each stage includes: a driving transistor, and a gate of the driving transistor is coupled to the A voltage raising unit; and a driving capacitor, one end of the driving capacitor is coupled to the gate of the driving transistor and the voltage raising unit, and the other end of the driving capacitor is coupled to the driving transistor and used to output the scan A signal, wherein the first reference voltage is the scan signal output by the previous-stage shift register circuit, and the second reference voltage is the scan signal output by the previous-stage shift register circuit. The gate driver circuit as described in item 3 of the patent application scope, wherein the voltage waveform of the gate of each driving transistor includes a first stage, a second stage, and a third stage. In the first stage, The voltage waveform of the gate of each driving transistor is raised from an initial level to a first-stage level. In the second stage, the voltage waveform of the gate of each driving transistor is changed from the first step The step level is raised to a second step level, and in the third stage, the voltage waveform of the gate of each driving transistor is raised from the second step level to a third step level. The gate driver circuit as described in item 3 of the patent application scope, wherein in the first stage, the first reference voltage is at a high level and the second reference voltage is at a low level; in the second stage, the first A reference voltage is changed from a high level to a low level, and the second reference voltage is a high level; in the third stage, the first reference voltage is a low level, and the second reference voltage is changed from a high level to Low level, and the first clock signal is high level. The gate driver circuit as described in item 2 of the patent application scope, wherein the scanning signal output unit of the shift register circuit at each stage includes: a driving transistor, and a gate of the driving transistor is coupled to the A voltage raising unit; a driving capacitor, one end of the driving capacitor is coupled to the gate of the driving transistor and the voltage raising unit, and the other end of the driving capacitor is coupled to the driving transistor and used to output the scanning signal Where the first reference voltage is the voltage of the gate of the driving transistor of the first-stage shift register circuit, and the second reference voltage is the scan signal of the previous-stage shift register circuit. The gate driver circuit as described in item 6 of the patent application scope, wherein the voltage waveform of the gate of each driving transistor includes a first stage, a second stage and a third stage. In the first stage, The voltage waveform of the gate of each driving transistor is raised from an initial level to a first-stage level. In the second stage, the voltage waveform of the gate of each driving transistor is changed from the first step The step level is raised to a second step level. In the third stage, the voltage waveform of the gate of each driving transistor is raised from the second step level to a third step level, and then The third step level is raised to a fourth step level. The gate driver circuit as described in item 7 of the patent application scope, wherein in the first stage, the first reference voltage is the third step level, and the second reference voltage is the low level; In the second stage, the first reference voltage is changed from the fourth step level to a fifth step level, the second reference voltage is a high level; in the third stage, the first reference voltage is the initial level Level, the second reference voltage changes from a high level to a low level, and the first clock signal is a high level. The gate driver circuit as described in item 1 of the patent application scope, wherein each of the voltage stabilizing units includes: a first voltage stabilizing transistor, coupled to the scan signal output unit, and turned on according to the second clock signal or Off; a second voltage stabilizing transistor, coupled to the scan signal output unit and the first voltage stabilizing transistor; a third voltage stabilizing transistor, coupled to the first voltage stabilizing transistor and the second stabilizing transistor A piezoelectric crystal and the bidirectional scanning control unit; a fourth voltage stabilizing transistor, coupled to the first voltage stabilizing transistor, the second voltage stabilizing transistor, the third voltage stabilizing transistor and the bidirectional scanning control unit ; And a voltage stabilizing capacitor, one end of the voltage stabilizing capacitor is coupled to the first voltage stabilizing transistor, the second voltage stabilizing transistor, the third voltage stabilizing transistor, and the fourth voltage stabilizing transistor, the stable The other end of the piezoelectric capacitor is coupled to the first clock signal. The gate driver circuit as described in item 1 of the patent application scope, wherein each of the bidirectional scan control units includes: a first scan control transistor coupled to the scan signal output unit, the voltage boosting unit and the voltage stabilizing unit , The first scan control transistor is turned on or off according to the first scan control signal and the scan signal output by the first two-stage shift register circuit; and a second scan control transistor, coupled to the scan signal The output unit, the voltage boosting unit, the voltage stabilizing unit, and the first scan control transistor, the second scan control transistor according to the second scan control signal and a scan output by the second-stage shift register circuit The signal is on or off.

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