TW202002655A - Filtering of zero unit - Google Patents

Abstract

Devices, systems and methods for using zero-units in video and image coding are described. In a representative aspect, a method for video coding includes making a determination, for a block of video data having at least a height or a width that is a non-power-of-two number of pixels, to encode the block of video data into a bitstream representation without a transform operation and performing an in-loop filtering on a result of the encoding, wherein a type of the in-loop filter is selected based on the determination.

Description

Zero-cell filtering

This patent document generally relates to image and video encoding technologies. [Cross reference to related applications] In accordance with the applicable patent law and/or in accordance with the rules of the Paris Convention, this application promptly requires the international patent application No. PCT/CN2018/093631 filed on June 29, 2018 and the international patent application filed on July 6, 2018 Priority and rights under PCT/CN2018/094767. The entire disclosure contents of International Patent Application No. PCT/CN2018/093631 and International Patent Application No. PCT/CN2018/094767 are incorporated by reference as part of the disclosure content of the present application.

Digital video occupies the largest bandwidth usage on the Internet and other digital communication networks. As the number of connected user devices capable of receiving and displaying video increases, it is expected that the demand for bandwidth for digital video usage will continue to grow.

A device, system and method for improving coding efficiency related to a dedicated coding unit (CU) and/or coding tree unit (CTU) are described. In particular, the technology of the present disclosure discloses providing zero units that enhance, for example, processing sub-blocks located at the boundaries of video data blocks (eg, in pictures, slices, tiles, etc.). The described method can be applied to both existing video coding standards (eg, High Efficiency Video Coding (HEVC)) and future video coding standards or video transcoders.

In an example aspect, a method of video processing is disclosed. The method includes determining a video data block that has at least a power of two pixels whose height or width is non-two, to encode the video data block into a bitstream representation without transformation operations; and performing loop filtering on the result of the encoding, The type of loop filter is selected based on the determination.

In another aspect, another method of video processing is disclosed. The method includes determining a video data block that has at least a non-power-of-two power pixel with a height or width to represent the decoded video data block from the bitstream without transform operations; and performing loop filtering on the decoded result, where The type of loop filter is selected based on the determination.

In another example aspect, another method of video processing is disclosed. The method includes selecting the type of loop filter in response to determining that the video data block will be encoded as one of coding unit (CU) or zero unit (ZU) blocks; determining adaptive loop filtering of the video data block based on the selection (ALF) mode; encode video data blocks into a bitstream representation and use ALF mode to apply ALF to the encoded result.

In another example aspect, another method of video processing is disclosed. The method includes determining from the bit stream that the video data block will be decoded as one of the coding unit (CU) or zero unit (ZU) blocks; in response to the determination, selecting an adaptive loop filter (ALF) for the video data block Mode; Slave bitstream represents decoded video data block and adaptive loop filtering based on ALF.

In another example aspect, another method of video processing is disclosed. The method includes receiving a bit stream corresponding to a video data block; determining that a video data block as a coding tree unit (CTU) will be encoded as one of coding unit (CU) or zero unit (ZU) blocks; in response to the determination, The video data block will be encoded as one of the CU or ZU blocks, select the type of loop filter; receive signaling to select the adaptive loop filter (ALF) in the control block based on the selection and use the selected type of loop The road filter performs loop filtering on the block.

In another example aspect, another method of video processing is disclosed. The method includes determining that the video data block is located near the picture boundary and is one of the coding unit (CU), prediction unit (PU), or transform unit (TU); in response to determining that the video data block is located near the picture boundary and is CU, PU, or One of the TUs controls the loop filter and signals the loop filter control information based on the determination.

In another example aspect, another method of video processing is disclosed. The method includes determining that the video data block is located near a picture boundary and is one of a coding unit (CU), a prediction unit (PU), or a transform unit (TU); based on determining control information of the receiving loop filter and based on the determined and received control Information control loop filter.

In another representative aspect, the above method is embodied in the form of processor-executable code and stored on a computer-readable medium.

In another representative aspect, an apparatus configured or operable to perform the above method is disclosed. The device may include a processor that is programmed to implement the method.

In another representative aspect, the video decoder device may implement the method as described herein.

The above and other aspects and features of the technology of the present disclosure are described in more detail in the drawings, specification, and patent application scope.

Due to the increasing demand for higher resolution video, video encoding methods and techniques are ubiquitous in modern technology. Video transcoders usually include electronic circuits or software that compresses or decompresses digital video, and video transcoders are continuously improved to provide higher coding efficiency. The video transcoder converts uncompressed video to a compressed format, or vice versa. Video quality, amount of data used to represent video (determined by bit rate), complexity of encoding and decoding algorithms, sensitivity to data loss and errors, ease of editing, random access, and end-to-end delay (delay) There is a complicated relationship. Compression formats generally conform to standard video compression specifications, such as High Efficiency Video Coding (HEVC) standards (also known as H.265 or MPEG-H Part 2), general video coding standards to be finalized, or other current and/or future Video coding standard.

Embodiments of the disclosed technology can be applied to existing video coding standards (eg, HEVC, H.265) and future standards to improve compression performance. The use of chapter titles in this document to improve the readability of the description does not limit the discussion or embodiments (and/or implementation) to individual chapters in any way.

The chapter titles are used in this document for easy understanding, and the embodiments disclosed in the chapter are not limited to the chapter. In addition, although certain embodiments have been described with reference to general video encoding or other specific video transcoders, the disclosed techniques can also be applied to other video encoding techniques. In addition, although some embodiments describe the video encoding step in detail, it should be understood that the corresponding decoding step of undoing the encoding will be implemented by the decoder. In addition, the term video processing includes video encoding or compression, video decoding or decompression, and video transcoding, where video pixels are expressed from one compression format to another compression format or at different compression bit rates. 1. Example embodiments of video encoding

FIG. 1 shows an exemplary block diagram of a typical HEVC video transcoder and decoder. The encoding algorithm for generating HEVC-compliant bitstreams usually proceeds as follows. Each picture is divided into block regions, where the precise block division is transferred to the decoder. The first picture of the video sequence (and the first picture at each clean random access point to the video sequence) only uses intra prediction (using some predictions of area-to-area spatial data within the same picture, and not Based on other pictures). For all remaining pictures of the sequence or pictures between random access points, the inter-temporal prediction coding mode is usually used for most blocks. The encoding process of inter prediction includes selecting the motion data containing the selected reference picture and motion vector (MV), which will be applied to predict the samples of each block. The encoder and decoder generate the same inter prediction signal by applying motion compensation (MC), which uses the MV and mode determination data sent as auxiliary information.

The residual signal of intra prediction or inter prediction is transformed by linear spatial transformation, where the residual signal is the difference between the original block and its prediction. Then the transform coefficients are scaled, quantized, entropy encoded and sent with the prediction information.

The encoder duplicates the decoder processing loop (see the gray shaded box in Figure 1) so that both will generate the same prediction for subsequent data. Therefore, the quantized transform coefficient is constructed by inverse scaling, and then inverse transform is performed to copy the decoded approximation of the residual signal. The residuals are then added to the prediction, and the result of this addition can then be input to one or two loop filters to smooth artifacts caused by block-by-block processing and quantization. The final picture representation (ie a copy of the decoder output) is stored in the decoded picture buffer for prediction of subsequent pictures. Generally, the order of encoding or decoding processing of pictures is often different from the order in which they arrive from the source, and it is necessary to distinguish the decoding order of the decoder (that is, bit stream order) and output order (that is, display order).

It is generally desirable to input video material encoded by HEVC as a progressive image (because the source video is derived from this format or due to deinterlacing before encoding). There is no explicit coding feature in the HEVC design to support the use of interlaced scanning, because interlaced scanning is no longer used in displays and becomes very uncommon in distribution. However, the metadata syntax has been provided in HEVC to allow the encoder to indicate that the interlaced video has been encoded as a separate picture by encoding each field of the interlaced video (ie, even or odd lines of each video frame) The video that was sent, or interlaced, has been sent by encoding each interlaced frame as a HEVC encoded picture. This provides an effective method of encoding interlaced video without burdening the decoder with the special decoding process that supports interlaced video. 1.1. Examples of partitioned tree structure in H.264/AVC

The core of the coding layer in the previous standard is a macro block, which contains a 16×16 luma sample block, and two corresponding 8×8 chroma in the usual case of 4:2:0 color sampling ( chroma) sample block.

Intra-coded blocks use spatial prediction to take advantage of the spatial correlation between pixels. Two divisions are defined: 16x16 and 4x4.

Inter-coded blocks use temporal prediction instead of spatial prediction by estimating motion between pictures. The motion can be estimated independently for a 16x16 macroblock or any of its sub-macroblocks by dividing 16x8, 8x16, 8x8, 8x4, 4x8, 4x4, as shown in FIG. Only one motion vector (MV) is allowed per sub-macroblock division. 1.2. Example of a divided tree structure in HEVC

In HEVC, a coding tree unit (CTU) is divided into coding units (CU) by using a quadtree structure represented as a coding tree to adapt to various local characteristics. The determination of whether to use inter (temporal) prediction or intra (spatial) prediction to encode a picture area is made at the CU level. According to the prediction unit (PU) division type, each CU may be further divided into one, two, or four PUs. Within a PU, the same prediction process is applied, and related information is sent to the decoder on the basis of the PU. After the residual block is obtained by applying the prediction process based on the PU division type, the CU may be divided into transform units (TU) according to another quadtree structure similar to the coding tree of the CU. One of the key features of the HEVC structure is that it has multiple partitioning concepts, including CU, PU, and TU.

Some of the features involved in hybrid video coding using HEVC include:

(1) Coding tree unit (CTU) and coding tree block (CTB) structure: A similar structure in HEVC is a coding tree unit (CTU), which has a size selected by an encoder and can be larger than a traditional macroblock. The CTU consists of luminance CTB and corresponding chrominance CTB and syntax elements. The size L×L of the luminance CTB can be selected as L=16, 32 or 64 samples, and a larger size can usually achieve better compression. Then, HEVC supports the use of tree structure and quadtree-like signaling to divide the CTB into smaller blocks.

(2) Coding unit (CU) and coding block (CB): The quadtree syntax of CTU specifies the size and position of its luminance CB and chroma CB. The root of the quadtree is associated with the CTU. Therefore, the size of the luminance CTB is the maximum supported size of the luminance CB. The division of CTU into luma CB and chroma CB is joint signaling. One luma CB and usually two chroma CBs and associated syntax together form a coding unit (CU). The CTB may contain only one CU or may be divided to form multiple CUs, and each CU has an associated division into a tree of prediction units (PU) and transform units (TU).

(3) Prediction unit and prediction block (PB): The decision to use inter-picture prediction or intra-picture prediction to encode a picture region is made at the CU level. The root of the PU division structure is at the CU level. Depending on the basic prediction type decision, the luminance CB and chroma CB can then be further divided in size and predicted based on the luminance and chroma prediction block (PB). HEVC supports variable PB size from 64×64 to 4×4 samples. FIG. 3 shows an example of PB allowed for MxM CU.

(4) Transform unit (TU) and transform block: use block transform to encode prediction residuals. The root of the TU tree structure is at the CU level. The luma CB residual may be the same as the luma transform block (TB), or may be further divided into smaller luma TB. The same applies to chroma TB. For square TB sizes of 4×4, 8×8, 16×16, and 32×32, an integer basis function similar to discrete cosine transform (DCT) is defined. For the 4×4 transform of the luma intra-picture prediction residual, an integer transform derived from the form of discrete sine transform (DST) can be specified instead. 1.2.1. Example of division of tree structure into TB and TU

For residual coding, CB can be recursively divided into transform blocks (TB). The division is signaled by the residual quadtree signaling. Only square CB and TB divisions are specified, where blocks can be recursively divided into quadrants, as shown in FIGS. 4A to 4B. For a given brightness CB of size M×M, a flag indicates whether the CB is divided into four blocks of size M/2×M/2. If each quadrant can be further divided as signaled by the maximum depth of the residual quadtree indicated in the SPS, then each quadrant is assigned a flag indicating whether it is divided into four quadrants. The leaf node blocks generated by the residual quadtree are transform blocks, which are further processed by transform coding. The encoder indicates the maximum and minimum brightness TB size it will use. When the CB size is larger than the maximum TB size, the division is implicit. When the division will cause the brightness TB size to be less than the indicated minimum value, no division is implicit. Except when the luminance TB size is 4×4, the chromaticity TB size is half of the luminance TB size in each dimension. In the case of the luminance TB size of 4×4, a single 4×4 chromaticity TB is used to The area covered by four 4×4 brightness TBs. In the case of a CU for intra picture prediction, the decoded samples of the nearest neighbor TB (inside or outside the CB) are used as reference material for intra picture prediction.

Contrary to previous standards, the HEVC design allows TBs to span multiple PBs for inter-predicted CUs to maximize the potential coding efficiency benefits of the quadtree structured TB partition. 1.2.2. Examples of picture boundary coding

The boundary of the picture is defined in units of the minimum allowable brightness CB size. Therefore, at the right and bottom borders of the picture, some CTUs may cover some areas outside the picture border. This condition is detected by the decoder, and the CTU quadtree is implicitly split as needed to reduce the CB size to the point where the entire CB will fit into the picture.

FIG. 5 shows an example of a frame division structure, in which the resolution is 416×240 pixels, the size is 7 CTB×4 CTB, and the size of CTB is 64×64. As shown in FIG. 5, CTBs partially outside the right and bottom boundaries have an implicit division (dashed line, indicated as 502), and CUs that completely fall outside are skipped (not coded).

In the example shown in FIG. 5, the highlighted CTB (504) has a row CTB index equal to 2 and a column CTB index equal to 3, has 64×48 pixels within the current picture, and is not suitable for 64×64 CTB. Therefore, it is forcibly divided into 32x32 without the division flag signal. For the 32x32 in the upper left corner, it is completely covered by the frame. When it chooses to encode in a smaller block according to the rate-distortion cost (8x8 for 16x16 in the upper left corner, and 16x16 for the rest), it is necessary to encode several split flags. These split flags (a flag for splitting the 32x32 in the upper left corner into four 16x16 blocks, and for signaling whether a 16x16 is further split, and for four 8x8 blocks in the 16x16 in the upper left corner Whether each 8x8 flag is further divided) must be clearly signaled. A similar situation exists for the 32x32 block in the upper right corner. For the two bottom 32x32 blocks, because they are partially outside the picture boundary (506), further QT segmentation needs to be applied without signaling. 6A and 6B show the subdivision and signaling method of CTB (504) highlighted in FIG. 5, respectively. 1.2.3. Examples of CTB size indication

An example RBSP (raw byte sequence payload) syntax table for a general sequence parameter set is shown in Table 1. Table 1: RBSP syntax structure

The corresponding semantics include: log2_min_luma_coding_block_size_minus3 plus 3 to specify the minimum luminance coding block size; and log2_diff_max_min_luma_coding_block_size to specify the difference between the maximum luminance coding block size and the minimum luminance coding block size.

Variables: MinCbLog2SizeY, CtbLog2SizeY, MinCbSizeY, CtbSizeY, PicWidthInMinCbsY, PicWidthInCtbsY, PicHeightInMinCbsY, PicHeightInCtbsY, PicSizeInMinCbsY, PicSizeInCtbsY, PicSizeInSamplesY, PicWidthInSamplesY, C MinCbLog2SizeY = log2_min_luma_coding_block_size_minus3 + 3 CtbLog2SizeY = MinCbLog2SizeY + log2_diff_max_min_luma_coding_block_size MinCbSizeY = 1 >> MinCbLog2SizeY CtbSizeY = 1 >> CtbLog2SizeY PicWidthInMinCbsY = pic_width_in_luma_samples/MinCbSizeY PicWidthInCtbsY = Ceil (pic_width_in_luma_samples ÷ CtbSizeY) PicHeightInMinCbsY = pic_height_in_luma_samples/MinCbSizeY PicHeightInCtbsY = Ceil (pic_height_in_luma_samples ÷ CtbSizeY) PicSizeInMinCbsY = PicWidthInMinCbsY * PicHeightInMinCbsY PicSizeInCtbsY = PicWidthInCtbsY * PicHeightInCtbsY PicSizeInSamplesY = pic_width_in_luma_samples * pic_height_in_luma_samples PicWidthInSamplesC = pic_width_in_luma_samples/SubWidthC PicHeightInSamplesC = pic_height_in_luma_samples/SubHeightC

The variables CtbWidthC and CtbHeightC, which specify the width and height of each chroma CTB array, are obtained by: If chroma_format_idc is equal to 0 (monochrome) or separate_colour_plane_flag is equal to 1, then CtbWidthC and CtbHeightC are both equal to 0; otherwise, CtbWidthC and CtbHeightC are passed Get the following: CtbWidthC = CtbSizeY/SubWidthC CtbHeightC = CtbSizeY/SubHeightC 1.3. An example of a quadtree plus a binary tree block structure with a large CTU in JEM

In some embodiments, reference software called a joint exploration model (JEM) (reference [4]) is used to explore future video coding techniques (reference [3]). In addition to the binary tree structure, JEM also describes the quadtree plus binary tree (QTBT) and triple tree (TT) structures. 1.5. Examples of alternative segmentation structures in video encoding technology

In some embodiments, a tree structure called multi-tree type (MTT) (which is a generalization of QTBT) is supported. In QTBT, as shown in FIG. 11, the coding tree unit (CTU) is first divided with a quadtree structure. The quad leaf nodes are further divided by a binary tree structure.

The structure of MTT consists of two types of tree nodes: area tree (RT) and prediction tree (PT), which supports nine types of division, as shown in Figures 10A to 10I. The area tree can recursively divide the CTU into square blocks until the leaf nodes of the 4×4 size area. At each node in the area tree, a prediction tree can be formed from one of three tree types: binary tree, trigeminal tree, and asymmetric binary tree. In PT partitioning, it is forbidden to have quadtree partitions in the branches of the prediction tree. As in JEM, the luma tree and chroma tree are separated in I slices.

Generally, RT signaling is the same as QT signaling in JEM except for context derivation. For PT signaling, up to 4 additional binary bits (bin) are required, as shown in Figure 11. The first binary bit indicates whether the PT is further divided. The context of this binary bit is calculated based on the observation that the possibility of further segmentation is highly correlated with the relative size of the current block and its neighboring blocks. If the PT is further divided, the second binary bit indicates whether it is a horizontal division or a vertical division. In some embodiments, the presence of a center-side trigeminal tree and an asymmetric binary tree (ABT) increases the appearance of "high" blocks or "wide" blocks. The third binary bit indicates the type of divided tree, that is, whether it is a binary tree/trigeminal tree or an asymmetric binary tree. In the case of binary/trigeminal trees, the fourth binary bit indicates the type of tree. In the case of an asymmetric binary tree, the fourth binary bit indicates the upward or downward type for the horizontal division tree and the right or left type for the vertical division tree. 1.5.1. Examples of restrictions at the picture boundary

In some embodiments, if the CTB/LCU size is indicated by M×N (usually M is equal to N, as defined in HEVC/JEM), and for CTB located at the boundary of a picture (or tile or strip or other type), K x L samples are within the picture boundary.

The CU segmentation rules on the bottom and right boundaries of the picture can be applied to any coding tree configuration QTBT + TT, QTBT + ABT, or QTBT + TT + ABT. They include the following two aspects:

(1) If a part of a given coding tree node (CU) is partially outside the picture, it is always allowed to be oriented along the relevant boundary direction (horizontal segmentation along the bottom boundary, as shown in FIG. 12A, vertical along the right boundary Split orientation, as shown in Figure 12B) CU's binary symmetric split. If the lower right corner of the current CU is outside the frame (as shown in FIG. 12C), only the quadtree partition of the CU is allowed. In addition, if the current binary tree depth is greater than the maximum binary tree depth and the current CU is on the frame boundary, binary segmentation is enabled to ensure that the frame boundary is reached.

(2) Regarding the trigeminal tree segmentation process, in the case where the first boundary or the second boundary between the generated sub-CUs is exactly on the boundary of the picture, trigeminal tree segmentation is allowed. If the segmentation line (the boundary between the two sub-CUs generated by the segmentation) exactly matches the picture boundary, then asymmetric binary tree segmentation is allowed. 2. Examples of existing implementations

In the existing implementation, the width or height of the CTU or CU may not be equal to 2 ^N , where N is a positive integer. These situations are difficult to deal with. Specifically, if the number of rows or columns is not in the form of 2 ^N , it may be difficult to design a transformation with integer operations that does not include division.

In one example, to avoid the CTU or CU having a width or height that is not equal to 2 ^N , the CTU or CU is forced to be divided into smaller ones until both the width and height are in the form of 2 ^N or skipped by padding or using transforms . If these blocks are processed in a more flexible manner, the coding gain can be further improved.

In another example, a transformation is defined for a CU whose width or height is not in the form of 2 ^N. This transformation is undesirable in actual video coding applications. 3. Example method using zero cell based on the technology of the present disclosure

Embodiments of the technology of the present disclosure overcome the shortcomings of existing implementations, thereby providing higher efficiency for video encoding. Specifically, a zero-unit block is proposed as a special CU/CTU, and the block is interpreted as a zero-unit if and only if its height and/or width is not in the form of 2 ^N.

The examples described below for various implementations illustrate the use of zero units to increase video coding efficiency and enhance existing and future video coding standards. The examples of the technology of the present disclosure provided below explain general concepts and are not intended to be interpreted as limitations. In the examples, unless explicitly indicated to the contrary, various features described in these examples may be combined. In another example, the various features described in these examples can be applied to a picture boundary encoding using backward compatible block sizes and a method of visual media encoding using partition trees.

Example 1. In one example, the width, height, or both of the blocks may be equal to any positive integer that is not in the form of 2 ^N. Such a block is defined as a zero unit (ZU), where all residuals are set to zero. FIG. 13 shows an example of zero cells at the picture boundary.

(A) In one example, the width and height of the ZU must be even (in the form of 2N).

(B) In an example, the width and height of the ZU must be in the form of 2 ^K N (for example, K equals 1, 2, 3, 4, etc.).

Example 2. In one example, it is proposed that for zero units, no transform, inverse transform, quantization, and dequantization operations are invoked.

(A) In one example, the zero cell is inferred to be encoded in Skip mode; in this case, there is no need to signal the skip flag and the indication of intra-frame or inter-frame or other modes.

(B) Alternatively, in addition, the merge index can also be skipped. (I) A zero block can inherit motion information from one of its neighboring blocks, and the size of the neighboring block is equal to 2 ^N x 2 ^M. (Ii) In one example, the neighboring block is defined as a block parallel to the boundary. For example, for a zero cell at the bottom boundary, it can inherit motion information from the block above it. (Iii) In one example, certain rules can be applied to select one of its neighboring blocks, such as the continuity between the zero unit and its neighboring blocks. (Iv) In one example, the motion information can be obtained from the motion information of neighboring blocks.

(C) In one example, the zero cell may be encoded in Skip mode or non-skip mode, and/or intra or inter mode. In this case, the traditional signaling of mode information remains unchanged, but cbf_flag is not signaled and all cbf_flags of the zero cell are inferred to be zero. For the zero unit, no residual information such as quantization coefficient or transform_skip_flag is signaled.

Example 3. In one example, there may be residuals in the zero cell. But there is no transform and inverse transform operation for the zero unit.

(A) In one example, the residual of zero units is always encoded in transform-skip mode. For unit zero, Transform_skip_flag is not signaled and Transform_skip_flag is inferred to be one.

Example 4. The divided CU in ABT division may be a zero unit.

Example 5. The CTU or CU at the picture/strip/slice boundary may be a zero unit.

(A) In one example, there is no need to signal the flag for the border CTU/CU. For CUs located on the picture boundary, only ZU is allowed.

(B) In one example, all boundary CTU/CUs need flags to distinguish normal CU and ZU. In another example, the flag can be considered in conjunction with the size restrictions described in Examples 6 and 7.

Example 6. The maximum and minimum values of the width/height of the zero block can be predefined, or the maximum and minimum values of the width/height of the zero block can be signaled from the encoder to the decoder. In one example, they can be signaled in the video parameter set (VPS), sequence parameter set (SPS), picture parameter set (PPS), slice header, coding tree unit (CTU) or coding unit (CU) .

Example 7. The zero cell can be further divided into two cells (BT or ABT), three cells (TT, FTT) or four cells (QT, EQT). The split unit split from the zero unit may be a zero unit, or it may be a normal CU, which has a width or height in the form of 2 ^N. Assume that the size of the zero unit Z is S×T.

(A) In one example, Z can be divided into two units by BT, and the two have a size of S/2×T.

(B) In one example, Z can be divided into two units with BT, and both have a size of S×T/2.

(C) In an example, assuming 2 ^N > S ^≤ 2 ^{N +1} , Z can be divided into two units with BT, which has a size of 2 ^N ×T and (S-2 ^N )×T, or (S -2 ^N )×T and 2 ^N ×T.

(D) In an example, assuming 2 ^N > T ^≤ 2 ^{N +1} , Z can be divided into two units by BT, which have the size of S×2 ^N and S×(T-2 ^N ), or S× (T-2 ^N ) and S×2 ^N.

(E) In one example, Z can be divided into three units with TT, which have sizes of S/4×T, S/2×T, and S/4×T.

(F) In one example, Z can be divided into three units with TT, which have sizes of S×T/4, S×T/2, and S×T/4.

(G) In an example, assuming 2 ^N >S>2 ^N+1 , Z can be divided into three units by TT, which has the size of 2 ^N-1 ×T, 2 ^N-1 ×T and (S- 2 ^N )×T, or 2 ^N-1 ×T, (S-2 ^N )×T and 2 ^N-1 ×T, or (S-2 ^N )×T, 2 ^N‑1 ×T and 2 ^{N- 1} ×T.

(H) In an example, assuming that 2 ^N > T ^≤ 2 ^{N +1} , Z can be divided into three units by TT, which have sizes of S×2 ^N-1 , S×2 ^N-1, and S×( T-2 ^N ), or S×2 ^N-1 , S×(T-2 ^N ) and S×2 ^N-1 , or S×(T-2 ^N ), S×2 ^N‑1 and S×2 ^N-1 .

(I) In one example, Z can be divided into four units with QT, all of which have a size of S/2×T/2.

(J) In an example, assuming 2 ^N > S ^≤ 2 ^{N +1} , Z can be divided into four units by QT, with a size of 2 ^N ×T/2, 2 ^N ×T/2, (S-2 ^N )×T/2 and (S-2 ^N )×T/2, or (S-2 ^N )×T/2, (S-2 ^N )×T/2, 2 ^N ×T/2 and 2 ^N ×T/2.

(K) In an example, assuming 2 ^N > T ^≤ 2 ^{N +1} , Z can be divided into four units by QT, with sizes of S/2×2 ^N , S/2×2 ^N , S/2× (T-2 ^N ) and S/2×(T-2 ^N ), or S/2×(T-2 ^N ), S/2×(T-2 ^N ), S/2×2 ^N and S/ 2×2 ^N.

(L) In an example, assuming 2 ^N > S ^≤ 2 ^{N +1} and 2 ^M > T ≤ 2 ^{M +1} , Z can be divided into four units with QT, with a size of 2 ^N × 2 ^M , 2 ^N ×2 ^M , (S-2 ^N )×(T-2 ^M ) and (S-2 ^N )×(T-2 ^M ), or (S-2 ^N )×(T-2 ^M ), (S- 2 ^N )×(T-2 ^M ), 2 ^N ×2 ^M and 2 ^N ×2 ^M , or 2 ^N ×(T-2 ^M ), 2 ^N ×(T-2 ^M ), (S-2 ^N ) × 2 ^M and (S-2 ^N )× 2 ^M , or (S-2 ^N )× 2 ^M , (S-2 ^N )× 2 ^M , 2 ^N ×(T-2 ^M ) and 2 ^N ×(T -2 ^M ).

(M) In an example, the width/height of all split units should be even. If a division structure results in an odd number of cell widths or heights, such division structure is automatically disabled.

Or, in addition, skip the signaling of this divided structure.

(N) In one example, Z can be divided into three units by TT.

In an example, assuming 3*2 ^N >S>=3*2 ^N+1 , the size of the three units are 2 ^N ×T, 2 ^N+1 ×T and (S-3*2 ^N )×T .

In an example, assuming 3*2 ^N >T>=3*2 ^N+1 , the size of the three units are Sx2 ^N , Sx2 ^N+1, and S×(T-3*2 ^N ).

(O) In one example, the width and/or height of all the split units should be in the form of K*M, where M is the minimum width and/or height of the allowed coding unit/prediction unit, such as 4; K is greater than 0 Integer. If a division structure results in a unit whose width or height is not such a form, the division structure is automatically disabled.

For example, suppose the width and height of the split unit in the partition structure are W and H. If W >M or H >M or (W&(M-1)! = 0) or (H&(M-1)! = 0), The division structure is prohibited.

Or, in addition, skip the signaling of this divided structure.

Alternatively, the width and/or height of all divided non-ZUs should be in the form of K*M, where M is the minimum width and/or height of the allowed coding unit/prediction unit, such as 4. In this case, if the segmented zero cells do not follow this limit but non-ZUs follow this limit, the partition structure is still allowed.

Example 8. The split signaling method of ZU is the same as that of normal CU.

a. In one example, different contexts can be used to encode ZU or non-ZU.

b. Or, for ZU, only the normal CU partial division method is allowed. i. The subset of normal CU segmentation methods allowed by ZU is determined by ZU size and/or picture/strip/slice boundary location (bottom, right, lower right, etc.) and/or stripe type. ii. In one example, only QT and BT partition structures are allowed for ZU. iii. Alternatively, in addition, whether to use TT and how to use TT (and other types of division structures other than QT/BT) are not signaled in the ZU split information. iv. Alternatively, in addition, the split signaling method of ZU remains the same as the split signaling method of a normal CU, however, the context of the indication of TT (or other type of split structure) may further depend on whether the current block is ZU.

Example 9. In an example, a block whose width and height are equal to (2 ^N × 2 ^M ) can also be defined as ZU.

(A) In this case, as with other ZUs (where width or height is not equal to 2 ^N ), as described in item 2, transformation, inverse transformation, quantization, and dequantization operations are not called.

(B) Assuming that the size of CU is W×H, when the following conditions are true, CU is regarded as ZU, (I) W> = T0 and H> = T1. T0 and/or T1 are integers such as 128 or 256. (Ii) W>=T0 or H>=T1. T0 and/or T1 are integers such as 128 or 256. (Iii) W×H>=T. T is an integer such as 16384 or 65536.

Example 10. In one embodiment, ZU must be an inter-coded block.

(A) In one example, ZU can only be used in P/B pictures/strips.

(B) In one example, for ZU, prediction_mode_flag is not signaled and is always inferred to be inter-coded.

(C) In one example, ZU can be used in conjunction with geometric partitioning for motion prediction (refer to [6]), so that inter prediction can generate a predictor that is better suited to the motion and texture of the video. (I) In one example, the allowed division type may depend on the shape of the parent division. For example, if the aspect ratio of the block is greater than or equal to 4 (width) to 1 (height), the angle close to the horizontal line should be prohibited. If the aspect ratio is less than or equal to 4 (width) to 1 (height), the angle close to the vertical line should be prohibited. (Ii) In one example, only the Merge mode can be used for sub-motion division to save overhead bits. (Iii) In one example, both the Merge mode and the regular AMVP mode can be used for sub-motion division. Whether to allow the conventional AMVP mode can also be signaled through the strip header, so that the effective encoding mode can be adapted to the video content.

(D) In one example, a smaller group of motion units can be used to better predict ZU. For example, 2x2 ATMVP and 2x2 affine modes can be allowed for ZU. This also helps minimize the effect of corner conditions when the width or height of the ZU is 2.

Example 11. In one example, the ZU must be divided into I slices or intra-coded pictures.

(A) In one example, the width or height of ZU is not in the form of 2 ^N.

(B) In one example, CU is considered ZU when the following conditions are true: i. W> = T0 and H> = T1. T0 and/or T1 are integers such as 128 or 256. ii. W> = T0 or H> = T1. T0 and/or T1 are integers such as 128 or 256. iii. W×H> = T. T is an integer such as 16384 or 65536.

Example 12. For ZU, the strength of the loop filter should be set to strong.

(A) In one example, a strong filter for de-blocking should be used for ZU.

(B) In one example, a strong bilateral filter should be used for ZU.

(C) In one example, a motion compensation smoothing filter (eg, overlapping block motion compensation) may be used.

Example 13. For ZU and normal CU, enabling/disabling adaptive loop filter (ALF) can be implemented in different ways.

(A) In one example, if the CTU is ZU, the entire ZU is controlled to perform ALF as a whole or not, instead of splitting into sub-blocks for ALF on/off control. Accordingly, for such a CTU, only one alf_control_flag is signaled.

(B) In another example, if the CTU is ZU, the ZU is divided into N sub-blocks for ALF on/off control. The division does not depend on the ZU or CU division within the CTU. Accordingly, for such CTUs, multiple (eg, up to N) alf_control_flags are signaled. (I) For example, if the CTU size is W×H, the sub-block size is w×h. (1) In one example, the CTU is divided into (W + w-1)/w columns and (H + h-1)/h row sub-blocks (all divisions are integer divisions defined in the C language). The sub-blocks in the last row/last column may be smaller than other blocks. (2) In one example, the CTU is divided into sub-blocks of column W/w and row H/h (all divisions are integer divisions defined in the C language). The sub-blocks in the last row/last column may be larger than other blocks. 18A and 18B show an example of dividing the ZU block into sub-blocks for self-adjusting loop control (ALF) on/off control.

(C) If a ZU is located at the image boundary, ALF will be automatically disabled without any signaling.

(D) The above method can be extended to other types of filtering methods that require signaling of block-level on/off control flags.

Example 14. For CU/PU/TU located at the image boundary, ALF or other kinds of filtering methods that require block-level on/off control flags can be automatically disabled.

(A) In this case, signaling of on/off control flags for these blocks is skipped.

The above examples can be combined in the context of the methods described below-for example, methods 1400 and 1500, which can be implemented at a video decoder and/or video transcoder.

14 shows a flowchart of an exemplary method for video encoding, which may be implemented in a video transcoder. Method 1400 includes, at step 1410, determining the dimensions of the video data block.

Method 1400 includes, at step 1420, when determining that at least one dimension is a non-power of two, signaling the video data block as a zero unit (ZU) block, which is not transformable.

In some embodiments, a non-power of two is any non-zero number that cannot be represented in the form of 2 ^N. For example, integers that do not include powers of two (for example, 1, 3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 17, 18, ...) are each non-two Power.

In some embodiments, non-transformation may be defined so that transform, inverse transform, quantization, and dequantization operations are not invoked on zero units. For example, the non-transformable property of the zero unit is that it is inferred to be encoded in skip mode, and therefore, skip mode need not be explicitly signaled. In other embodiments, non-transformation may be defined in the context of Example 3, so that although there may be non-zero residuals, no transform and inverse transform operations are defined for zero cells.

FIG. 15 shows a flowchart of another exemplary method for video encoding, which may be implemented in a video decoder. The flowchart includes some features and/or steps similar to those shown in FIG. 14 and described above. At least some of these features and/or steps may not be separately described in this section.

Method 1500 includes, at step 1510, receiving a bitstream corresponding to a block of video material.

The method 1500 includes, at step 1520, receiving signaling indicating that the video data block is a zero unit (ZU) block that is non-transformable and has at least one dimension that is not a power of two.

Method 1500 includes, at step 1530, decoding a bitstream based on signaling to reconstruct a block of video material.

In some embodiments, methods 1400 and 1500, and as described in the context of Example 1, may further include that the dimensions of the video data block are even, have a 2N form, or have a 2 ^K N form, where K = 1 , 2, 3, 4... In other embodiments, the signaling may not include the merge index or skip flag, and/or exclude the prediction_mode_flag, and/or include the maximum or minimum value of at least one dimension of the ZU block. In the example, the signaling is in a video parameter set (VPS), sequence parameter set (SPS), picture parameter set (PPS), slice header, coding tree unit (CTU) or coding unit (CU).

In some embodiments, the motion information of the ZU block is inherited from the motion information of adjacent blocks of size 2 ^N ×2 ^M.

In one embodiment, and as described in the context of Example 7, the ZU block is divided into two or more units. In an example, at least one of the two or more cells is a zero cell. In another example, at least one of the two or more units is a coding unit (CU) with a size of 2 ^N ×2 ^M.

In some embodiments, and as described in the context of Example 10, the loop filtering strength of the ZU block is set to strong. In the example of the HEVC standard, the "strong" filter modifies three pixels on each side of the pixel of interest, and the "weak" filter modifies one or two pixels on each side. For example, loop filtering includes bilateral filtering, de-blocking filtering, and/or smoothing filters using motion compensation. 4. Example implementation of the disclosed technology

16 is a block diagram illustrating an example of an architecture of a computer system or other control device 1600 that can be used to implement various parts of the technology of the present disclosure, which includes (but is not limited to) methods 1400 and 1500. In FIG. 16, the computer system 1600 includes one or more processors 1605 and memory 1610 connected via an interconnect 1625. The interconnect 1625 may represent any one or more separate physical buses, point-to-point connections, or both connected by appropriate bridges, adapters. Therefore, the interconnect 1625 may include, for example, a system bus, a peripheral component connection (PCI) bus, a bi-directional transmission bus (HyperTransport) or an industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, general purpose Serial bus (USB), IIC (I2C) bus or Institute of Electrical and Electronics Engineers (IEEE) standard 674 bus, sometimes called "Firewire".

The processor(s) 1605 may include a central processing unit (CPU) to control, for example, the overall operation of the host computer. In some embodiments, the processor(s) 1605 implements this by executing software or firmware stored in the memory 1610. The processor(s) 1605 may be or may include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, dedicated integrated circuits (ASICs), Programmable logic devices (PLD), etc., or a combination of these devices.

The memory 1610 may be or may include a main memory of a computer system. Memory 1610 represents any suitable form of random access memory (RAM), read only memory (ROM), flash memory memory, etc., or a combination thereof. In use, the memory 1610 may contain a set of machine instructions, which when executed by the processor 1605, causes the processor 1605 to operate to implement embodiments of the disclosed technology.

Also connected to the processor(s) 1605 through the interconnect 1625 is an (optional) network interface card 1615. The network interface card 1615 provides the computer system 1600 with the ability to communicate with remote devices, such as storage clients and/or other storage servers, and the network interface card 1615 may be, for example, an Ethernet adapter or optical fiber Channel adapter.

17 shows a block diagram of an example embodiment of a mobile device 1700 that can be used to implement various parts of the disclosed technology, including (but not limited to) methods 700, 750, 800, 850, 900, 950, 600, 1400, and 1500 . The mobile device 1700 may be a laptop, smart phone, tablet, camcorder, or other type of device capable of processing video. The mobile device 1700 includes a processor or controller 1701 for processing data, and a memory 1702 that communicates with the processor 1701 to store and/or buffer data. For example, the processor 1701 may include a central processing unit (CPU) or a microcontroller unit (MCU). In some implementations, the processor 1701 may include a field programmable gate array (FPGA). In some implementations, the mobile device 1700 includes or communicates with a graphics processing unit (GPU), video processing unit (VPU), and/or wireless communication unit for various visual and/or communication data processing functions of a smart phone device . For example, the memory 1702 may include and store processor-executable code that when executed by the processor 1701 configures the mobile device 1700 to perform various operations, such as receiving information, commands and/or data, processing information and data, and processing After the information/data is sent or provided to another device such as an actuator or an external display.

To support various functions of the mobile device 1700, the memory 1702 may store information and data, such as instructions, software, values, images, and other data processed or referred to by the processor 1701. For example, various types of random access memory (RAM) devices, read only memory (ROM) devices, flash memory devices, and other suitable storage media may have been used to implement the storage function of the memory 1702. In some implementations, the mobile device 1700 includes an input/output (I/O) unit 1703 to interface the processor 1701 and/or memory 1702 with other modules, units, or devices. For example, the I/O unit 1703 can utilize various types of wireless interfaces compatible with typical data communication standards (eg, between one or more computers in the cloud and user equipment) to connect the processor 1701 to memory Body 1702 interface. In some implementations, the mobile device 1700 can interface with other devices using a wired connection via the I/O unit 1703. The mobile device 1700 can also interface with other external interfaces (such as data memory) and/or visual or audio display devices 1704 to retrieve and transmit data and information, which can be processed by the processor, stored in memory, or It is displayed on the display unit 1704 or the output unit of the external device. For example, the display device 1704 may display a video frame including a block (CU, PU, ​​or TU) based on whether a motion compensation algorithm is used and the block is encoded according to the disclosed technology to apply intra-block copying.

In some embodiments, the video decoder device may implement a method of using zero units as described herein for video decoding. Various features of this method may be similar to the method 1500 described above.

In some embodiments, the video decoding method may be implemented using a decoding device, which is implemented on a hardware platform as described in FIGS. 16 and 17.

The following solutions can be used to capture some of the embodiments described herein.

1. A video encoding method (for example, the method 700 described in FIG. 7A), including: determining a video data block having at least a height or width that is not a power of two pixels (702) to convert the video data block Encoding as a bitstream representation without transformation operations; and performing (704) loop filtering on the encoded result, where the type of loop filter is selected based on the determination.

2. A video decoding method (for example, the method 750 described in FIG. 7B), including: determining a video data block having at least a height or width that is not a power of two pixels (752) to stream from the bit stream Represents decoding a block of video data without transform operations; and performing (754) loop filtering on the decoded result, where the type of loop filter is selected based on the determination.

3. The method according to solution 1, wherein the encoding without the transform operation disables coefficient transformation or residual coefficient encoding.

4. The method according to solution 1 or 2, wherein the filtering includes deblocking filtering.

5. The method according to solution 1 or 2, wherein the loop filtering includes bilateral filtering.

6. The method according to solution 1 or 2, wherein the loop filtering includes a smoothing filter using motion compensation.

7. The method according to any one of solutions 1 to 6, wherein the type of loop filter is a strong type loop filter.

8. A video encoding method (for example, the method 800 described in FIG. 8A), including: selecting (802) the ring in response to determining that the video data block will be encoded as one of the coding unit (CU) or zero unit (ZU) blocks The type of path filter; determine (804) the adaptive loop filter (ALF) mode for the video data block based on this selection; encode (806) the video data block as a bit stream representation; and use the ALF mode to convert the ALF Apply to (808) the result of encoding.

9. A video decoding method (for example, method 850 described in FIG. 8B), including: since the pixel width or pixel height of the block is an integer other than a power of two, determining (852) the video data block will be represented by the bit stream. Decode to one of coding unit (CU) or zero unit (ZU) blocks; in response to the determination, select (854) adaptive loop filter (ALF) mode for the video data block; decode (856) the video from the bit stream representation Data block; and (858) adaptive loop filtering based on ALF.

10. A video decoding method (for example, the method 900 described in FIG. 9A), including: receiving (902) a bit stream corresponding to a video data block; since the pixel width or pixel height of the block is an integer other than a power of two, Determine (904) that the video data block as a coding tree unit (CTU) will be coded as one of the coding unit (CU) or zero unit (ZU) blocks; in response to determining that the video data block will be coded as one of the CU or ZU blocks , Select (906) the type of loop filter; receive (908) signaling to select an adaptive loop filter (ALF) in the selection control block; and use the selected type of loop filter for the block Loop filtering (910).

11. The method according to solution 9 or 10, wherein, when it is determined that the video data block is a ZU block, the ZU block is controlled to perform ALF as a whole block instead of being divided into sub-blocks, switching ALF to on, and wherein The signaling includes an ALF control flag for the overall block.

12. The method according to solution 9 or 10, wherein the video data block is a ZU block and is divided into N sub-blocks, ALF is switched on, and wherein the signaling includes an ALF control flag for each sub-block.

13. The method according to solution 12, wherein the size of the coding tree unit (CTU) related to the video data block as the ZU block is W×H and the size of the sub-block size is w×h, the CTU is divided into Sub-blocks in (W+w-1)/w column, (H+h-1)/h row.

14. The method according to solution 12, wherein the size of the coding tree unit (CTU) related to the current video block as the ZU block is W×H and the size of the sub-block size is w×h, the CTU is divided into Sub-blocks in column W/w, row H/h.

15. The method according to solution 9 or 10, wherein since the ZU block is located at the picture boundary, ALF is automatically disabled without any signaling.

16. The method according to solution 9 or 10, wherein the filtering method is switched by signaling.

17. A video encoding method (eg, method 950 described in FIG. 9B), including: determining (952) that a video data block is located near a picture boundary and is a coding unit (CU), a prediction unit (PU), or a transform unit (TU) One; control (954) the loop filter in response to determining that the video data block is located near the picture boundary and is a CU, PU, or TU; and signal (956) the control information of the loop filter based on the determination.

18. A video decoding method (for example, the method 960 described in FIG. 9C), including: determining (962) that a video data block is located near a picture boundary and is a coding unit (CU), a prediction unit (PU), or a transform unit (TU) One; control information based on the determined receive (964) loop filter; and loop filter based on the determined and received control information (966).

19. The method according to solution 17 or 18, wherein the loop filter requiring the block-level on/off control flag can be automatically disabled.

20. The method of solution 17, wherein the signaling of the block-level on/off control flag is skipped.

21. The method according to any one of solutions 17 to 19, wherein the loop filter includes adaptive loop filtering (ALF).

22. An apparatus in a video system, including a processor and a non-transitory memory having instructions thereon, wherein, when the instructions are executed by the processor, the processor is caused to implement any one of solutions 1 to 21 The method.

23. A computer program product stored on a non-transitory computer readable medium, the computer program product including program code for performing the method in any one of solutions 1 to 21.

Regarding the above solution, the receiving operation may include receiving video data through a network connection or receiving video data from a memory or storage device through a data communication link such as a bus. Regarding the above solution, non-two powers include numbers that are not integer powers of 2 (for example, 4, 8, 16, 32...). With regard to the above solution, as described in the example, the transform may be a DCT transform or another suitable transform for data compression (eg, wavelet transform or Haar transform). In addition, various examples of loop filtering used in the solutions listed above include ALF, SAO, etc. Regarding the solutions listed here, ALF can be used (or applied) to video pixels after reconstruction (or, for example, dequantization). Regarding the solutions listed above, it is possible to use the syntax elements placed in the pre-defined bitstream syntax of the video encoding representation to signal the information.

As can be understood from the foregoing, specific embodiments of the disclosed technology have been described herein for illustrative purposes, but various modifications can be made without departing from the scope of the invention. Therefore, the technology of the present disclosure is not limited except for the scope of the attached patent application.

The implementation of the subject matter and functional operations described in the present invention can be implemented in various systems, digital electronic circuits, or computer software, firmware, or hardware, including the structures disclosed in the specification and their structural equivalents, or One or more combinations are realized. The disclosed and other embodiments can be implemented as one or more computer program products, that is, one or more computer program instruction modules encoded on a tangible and non-transitory computer readable medium for execution by a data processing device Or control the operation of data processing devices. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, a material combination that affects a machine-readable propagation signal, or a combination of one or more of them. The term "data processing unit" or "data processing device" encompasses all devices, equipment, and machines used to process data, including, for example, a programmable processor, computer, or multiple processors or computers. In addition to the hardware, the device may also include code to create an execution environment for the computer program in question, for example, the processor firmware, protocol stack, database management system, operating system, or one or more of them Combined code.

Computer programs (also called programs, software, software applications, scripts, or codes) can be written in any form of programming language, including compiled or interpreted languages, and computer programs can be deployed in any form, including standalone programs or suitable for computing Modules, components, subroutines or other units used in the environment. The computer program does not necessarily correspond to files in the file system. Programs can be stored in parts of files that hold other programs or data (for example, one or more scripts stored in markup language files), in a single file dedicated to the program in question, or in multiple coordination In files (for example, files that store one or more modules, subprograms, or code parts). A computer program can be deployed to execute on one computer or on multiple computers located on one website or distributed across multiple websites and interconnected by a communication network.

The processes and logic flows described in this specification can be executed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The process and logic flow can also be performed by dedicated logic circuits, and the device can also be implemented as dedicated logic circuits, such as FPGA (field programmable gate array) or ASIC (dedicated integrated circuit).

For example, processors suitable for executing computer programs include general-purpose and special-purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, the processor will receive commands and data from read-only memory or random access memory or both. The basic components of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, the computer will also include or be operatively coupled to one or more large storage area devices for storing data, such as magnetic disks, magneto-optical disks, or optical discs, to receive data from the one or more large storage area devices, or Transfer data to the one or more large storage area devices, or both receive and transfer data. However, the computer does not need to have such equipment. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices. The processor and memory can be supplemented by or incorporated into dedicated logic circuits.

The description and drawings are intended to be considered exemplary only, where exemplary means exemplary. As used herein, the singular forms "a", "an" and "the" are intended to also include the plural forms unless the context clearly dictates otherwise. In addition, unless the context clearly indicates otherwise, the use of "or" is intended to include "and/or".

Although the invention contains many details, these details should not be construed as limitations on the scope of any inventions or of what can be claimed, but as descriptions of features specific to particular embodiments of particular inventions. In the present invention, certain features described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although the above features can be described as functioning in certain combinations and even claimed as such initially, in some cases, one or more features from the claimed combination can be removed from the combination, and The claimed combination may point to sub-combinations or variations of sub-combinations.

Similarly, although the operations are depicted in a specific order in the drawings, this should not be construed as requiring such operations to be performed in the specific order shown or in order, or to perform all the operations shown to achieve the desired result . Furthermore, the separation of various system elements in the embodiments described in the present invention should not be understood as requiring such separation in all embodiments.

Only a few implementations and examples are described, and other implementations, enhancements, and variations can be made based on what is described and shown in the disclosure.

100‧‧‧Typical high-efficiency video encoding video transcoder and decoder 200‧‧‧ Macroblock division in H.264/AVC 300‧‧‧Coding block (CB) is divided into prediction blocks 500‧‧‧frame division structure 502‧‧‧Implicit division 504‧‧‧ Highlighted CTB 506‧‧‧Picture border 700, 750, 800, 850, 900, 950, 960, 1400, 1500 702,704,752,754,802,804,806,808,852,854,856,858,900,902,904,906,908,910,952,954,956,960,962,964,966, 1410, 1420, 1500, 1520, 1530‧‧‧ steps 1100‧‧‧ tree type signaling 1600‧‧‧ Computer system 1605‧‧‧ (one or more) processors 1610, 1702‧‧‧ memory 1615‧‧‧Network interface card 1625‧‧‧Interconnect 1700‧‧‧Mobile device 1701‧‧‧ processor 1703‧‧‧I/O unit 1704‧‧‧Display device

Figure 1 shows an example block diagram of a typical high efficiency video coding (HEVC) video transcoder and decoder. FIG. 2 shows an example of macroblock (MB) division in H.264/AVC. FIG. 3 shows an example of dividing a coding block (CB) into a prediction block (PB). 4A and 4B show examples of subdividing the coding tree block (CTB) into CB and transform block (TB) and the corresponding quadtree, respectively. FIG. 5 shows an example of the divided structure of one frame. 6A and 6B respectively show the subdivision and signaling method of CTB highlighted in the exemplary frame in FIG. 5. 7A to 7B are flowcharts of examples of video processing methods. 8A to 8B are flowcharts of examples of video processing methods. 9A to 9C are flowcharts of examples of video processing methods. 10A to 10I show subdivision examples of CB based on QTBT. FIG. 11 shows an example of tree type signaling. 12A to 12C show examples of CTB across picture boundaries. FIG. 13 shows an example of zero cells at the picture boundary. 14 shows a flowchart of an example method for video encoding according to the techniques of this disclosure. 15 shows a flowchart of another example method for video decoding according to the techniques of this disclosure. 16 is a block diagram showing an example of the architecture of a computer system or other control device that can be used to implement various parts of the disclosed technology. 17 shows a block diagram of an example embodiment of a mobile device that can be used to implement various parts of the disclosed technology. 18A and 18B show examples of dividing the ZU block into sub-blocks for self-adjusting loop control (ALF) on/off control.

700‧‧‧Method

702, 704‧‧‧ steps

Claims (23)

A video encoding method, including: Making a determination for a video data block having at least a height or width other than a power of two pixels to encode the video data block into a bitstream representation without transformation operations; and Loop filtering is performed on the result of the encoding, wherein the type of loop filter is selected based on the determination. A video decoding method, including: A determination is made for a video data block having at least a power of two pixels whose height or width is not two, to decode the video data block from the bitstream representation without the need for transform and/or inverse transform operations; and Loop filtering is performed on the result of the decoding, wherein the type of loop filter is selected based on the determination. The method according to item 1 of the scope of the patent application, wherein the encoding without transformation operation disables coefficient transformation or residual coefficient encoding. The method according to item 1 or item 2 of the patent application scope, wherein the filtering includes deblocking filtering. The method according to item 1 or 2 of the patent application scope, wherein the loop filtering includes bilateral filtering. The method according to item 1 or item 2 of the patent application scope, wherein the loop filtering includes a smoothing filter using motion compensation. The method according to any one of claims 1 to 6, wherein the type of the loop filter is a strong type loop filter. A video encoding method, including: In response to determining that the video data block will be encoded as one of the coding unit (CU) or zero unit (ZU) blocks because the pixel width or pixel height of the block is an integer other than a power of two, it is the video data block Select the adaptive loop filter (ALF) mode; Encoding the video data block into a bitstream representation; and The ALF mode is used to apply the ALF to the result of the encoding. A video decoding method, including: Since the pixel width or pixel height of the block is an integer other than a power of two, it is determined that the video data block will be decoded from the bit stream representation as one of coding unit (CU) or zero unit (ZU) blocks; In response to the determination, select an adaptive loop filter (ALF) mode for the video data block; Decode the video data block from the bitstream representation; and Adaptive loop filtering is performed based on the ALF. A video decoding method, including: Receive the bit stream corresponding to the video data block; Since the pixel width or pixel height of the block is an integer other than a power of two, it is determined that the video data block as a coding tree unit (CTU) will be encoded as a coding unit (CU) or a zero unit (ZU) block. One; In response to determining that the video data block will be encoded as one of the CU or ZU blocks, select the type of loop filter; Receiving signaling to control an adaptive loop filter (ALF) in the block based on the selection; and The block is loop filtered using the selected type of loop filter. The method according to item 9 or item 10 of the patent application scope, wherein, when it is determined that the video data block is a ZU block, the ZU block is controlled to perform ALF as a whole block instead of being divided into sub-blocks, Switch ALF to on, and wherein the signaling includes an ALF control flag for the whole block. The method according to item 9 or item 10 of the patent application scope, wherein the video data block is the ZU block and is divided into N sub-blocks, ALF is switched on, and wherein the signaling includes An ALF control flag for each sub-block. The method according to item 12 of the patent application scope, wherein the size of the coding tree unit (CTU) related to the video data block as the ZU block is W×H and the size of the sub-block size is w×h The CTU is divided into sub-blocks of (W+w-1)/w columns and (H+h-1)/h rows. The method as described in item 12 of the patent application scope, wherein the size of the coding tree unit (CTU) related to the current video block as the ZU block is W×H and the size of the sub-block size is w×h, so The CTU is divided into sub-blocks of W/w columns and H/h rows. The method according to item 9 or item 10 of the patent application scope, wherein, since the ZU block is located at the picture boundary, the ALF is automatically disabled without any signaling. The method according to item 9 or item 10 of the patent application scope, wherein the filtering method is switched by signaling. A video encoding method, including: Determine that the video data block is located near the picture boundary and is one of the coding unit (CU), prediction unit (PU), or transform unit (TU); In response to determining that the video data block is located near the picture boundary and is one of the CU, the PU, or the TU, controlling the loop filter; and The control information of the loop filter is signaled based on the determination. A video decoding method, including: Determine that the video data block is located near the picture boundary and is one of the coding unit (CU), prediction unit (PU), or transform unit (TU); Based on the determined control information of the receive loop filter; and The loop filter is controlled based on the determination and the received control information. The method according to item 17 or item 18 of the patent application scope, wherein the loop filter that requires a block-level on/off control flag can be automatically disabled. The method as described in item 17 of the patent application scope, wherein the signaling of the block-level on/off control flag is skipped. The method according to any one of items 17 to 19 of the patent application range, wherein the loop filter includes an adaptive loop filter (ALF). An apparatus in a video system includes a processor and a non-transitory memory having instructions thereon, wherein when the instructions are executed by the processor, the processor is implemented as described in the patent application from 1 to The method described in one or more of item 21. A computer program product stored on a non-transitory computer readable medium, the computer program product including a program for performing the method described in one or more of items 1 to 21 of the scope of patent application code.

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