TW202002481A - Controller for extending a protection period of a power converter and operational method thereof - Google Patents

Abstract

A controller for extending a protection period of a power converter includes a delay circuit. The delay circuit is coupled to a supply voltage pin of the controller. When the power converter enters a protection mode, the delay circuit is enabled, receives a supply voltage through the supply voltage pin, and extends a protection period corresponding to the protection mode according to the supply voltage.

Description

Controller for extending protection period of power converter and operation method thereof

The invention relates to a controller applied to a power converter and an operation method thereof, in particular to a controller used to extend the protection period of the power converter and an operation method thereof.

In the prior art, when the power converter is used in a TV and enters a protection mode (where the protection mode corresponds to an output short-circuited protection (OSCP) or an over current protection (OCP) ), because the TV cannot be turned off arbitrarily, the gate signal generation circuit applied to the controller of the power converter will generate a burst mode gate control signal to the power converter once. The power switch on the side, that is, during the enable period of the gate control signal (corresponding to the recovery period of the protection mode), the operation of the power switch still generates heat. If the heat generated by the power switch during the recovery period cannot be effectively dissipated during the gate control signal deactivation period (the protection period corresponding to the protection mode), the heat generated by the power switch during the recovery period may be Hazardous to components in the TV. Therefore, how to effectively dissipate the heat generated by the power switch during the recovery period becomes an important issue.

An embodiment of the present invention provides a controller for extending the protection period of a power converter. The controller includes a delay circuit. The delay circuit is coupled to a power supply voltage pin of the controller, wherein when the power converter enters a protection mode, the delay circuit is enabled to receive a power supply voltage through the power supply voltage pin and according to the power supply voltage Extend the protection period corresponding to the protection mode.

Another embodiment of the present invention provides an operation method of a controller for extending the protection period of a power converter, wherein the controller includes a delay circuit and the delay circuit includes a first current source, a delay, and a first Two current sources. The operation method includes the power converter entering a protection mode; the first current source generates a first discharge current according to a protection signal and a supply voltage corresponding to the protection mode, and the first discharge current, the power converter's The capacitor on the primary side and a charging current on the input of the primary side of the power converter determine the supply voltage; the delayer generates a delay response based on the protection signal and the detected voltage on the primary side of the power converter An enable signal, wherein the delayed enable signal corresponds to a predetermined delay time; and the second current source generates a second discharge current according to the delayed enable signal, and the second discharge current and the first discharge current, the capacitor, And the charging current determines the supply voltage.

Another embodiment of the present invention provides an operation method of a controller for extending the protection period of a power converter, wherein the controller includes a delay circuit and the delay circuit includes a current source and a counter. The operation method includes the power converter entering a protection mode; the current source is enabled according to a protection signal corresponding to the protection mode; when a supply voltage is less than a lower limit, the current source generates a first discharge current, and the The first discharge current, the capacitance of the primary side of the power converter, and a charging current related to the input of the primary side of the power converter determine the supply voltage; when the supply voltage is greater than an upper limit, the current source generates A second discharge current, and the second discharge current, the capacitor, and the charging current determine the power supply voltage; and when the number of times the counter counts that the power supply voltage is less than the lower limit value is equal to a predetermined number of times, the counter causes the The current source generates the second discharge current; wherein the first discharge current is less than the charging current, and the second discharge current is greater than the charging current.

The invention provides a controller for extending the protection period of a power converter and an operation method thereof. The controller and the operating method are to use a delay circuit to extend the protection period corresponding to the protection mode according to a supply voltage after the power converter enters the protection mode. Therefore, because the present invention can extend the protection period, compared with the prior art, the present invention can effectively dissipate the heat generated by the power switch of the power converter during the recovery period corresponding to the protection mode. In addition, because the controller directly controls the power supply voltage through a power supply voltage pin, the controller does not require additional pins.

Please refer to FIG. 1, which is a schematic diagram of a controller 200 for extending the protection period of the power converter 100 disclosed in the first embodiment of the present invention, wherein the power converter 100 is a flyback power conversion Flyback power converter, and in order to simplify FIG. 1, FIG. 1 only shows the components of the power converter 100 and the controller 200 related to the present invention. As shown in FIG. 1, the controller 200 includes a delay circuit 202, and the delay circuit 202 includes a first current source 2022, a delay 2024, and a second current source 2026, wherein the first current source 2022 is coupled to a The power supply voltage pin 204, the second current source 2026 is coupled to the delayer 2024 and the power supply voltage pin 204, and the controller 200 receives a power supply voltage VCC through the power supply voltage pin 204. As shown in FIG. 1, the protection circuit in the controller 200 (not shown in the controller 200 in FIG. 1) can determine whether to enable the power converter according to the output current IOUT of the secondary side SEC of the power converter 100 100 enters a protection mode, where the protection mode corresponds to an output short-circuit protection or an overcurrent protection. In addition, the method for the protection circuit to determine whether to enter the protection mode according to the output current IOUT is well-known to those skilled in the art in the field of the present invention, which will not be repeated here.

Please refer to FIG. 2. FIG. 2 is a timing diagram illustrating the power supply voltage VCC of the controller 200 and a gate control signal GCS generated by the controller 200 after the power converter 100 enters the protection mode. As shown in FIG. 2, at a time T1, the supply voltage VCC is greater than an under voltage lock out (under voltage lock out) turn-on voltage UVLOON, so the gate signal generation circuit in the controller 200 (not shown in FIG. 1) In the controller 200), a gate control signal GCS will be generated between a time T2 and a time T3 to the power switch 102 of the primary PRI of the power converter 100, wherein the gate control signal GCS is pulse width modulation (pulse) width modulation, PWM) signal, the gate control signal GCS is transmitted to the power switch 102 through a pin 206 of the controller 200, and the time interval between the time T2 and the time T3 is the recovery period of the power converter 100 corresponding to the protection mode TR. As shown in FIG. 2, at time T3, the gate signal generation circuit may stop generating gate control according to the detection voltage VCS (as shown in FIG. 1) of the primary PRI of the power converter 100 and a reference voltage VREF The signal GCS is sent to the power switch 102, and the protection circuit generates a protection signal OCP to the first current source 2022 and the delay 2024, wherein the detection voltage VCS is caused by the primary current IPRI flowing through the primary PRI of the power converter 100 and A resistor 103 determines, and the controller 200 receives the detection voltage VCS through a pin 208. Therefore, because the protection circuit generates the protection signal OCP to the first current source 2022, the first current source 2022 is enabled and begins to generate a first discharge current IDIS1 to a capacitor 104 according to the supply voltage VCC (as shown in FIG. 1) Discharge, wherein the first discharge current IDIS1 will change with the change of the supply voltage VCC, and the first discharge current IDIS1 flows to a ground terminal GND through the pin 210 of the controller 200. As shown in Figures 1 and 2, during the recovery period TR, because only a charging current IC charges the capacitor 104, the power supply voltage VCC is determined by the charging current IC and the capacitor 104 at this time, resulting in the power supply voltage VCC maintaining a first stability status. After the time T3, the first discharge current IDIS1 starts to discharge the capacitor 104, so the supply voltage VCC is determined by the first discharge current IDIS1, the charging current IC and the capacitor 104. In an embodiment of the present invention, the first discharge current IDIS1 is greater than the charging current IC at time T3, so the supply voltage VCC will gradually decrease until a time T4 (because the first discharge current IDIS1 will change with the change of the supply voltage VCC, so at time T4, the first discharge current IDIS1 It is equal to the charging current IC, which causes the power supply voltage VCC to maintain a second stable state after a time T4 until a time T5).

As shown in FIG. 2, at time T5, the delayer 2024 can generate a delay enable signal DES to the second current source 2026 according to the protection signal OCP and the detection voltage VCS, so the second current source 2026 is enabled and begins to generate A second discharge current IDIS2 discharges the capacitor 104, wherein the delay enable signal DES corresponds to a predetermined delay time, the time interval between the time T3 and the time T5 is the protection period TP corresponding to the protection mode of the power converter 100, and the second The discharge current IDIS2 flows to the ground GND through the pin 210 of the controller 200. As shown in FIG. 2, after time T5, the second discharge current IDIS2 starts to discharge the capacitor 104 (where the first discharge current IDIS1 continues to discharge the capacitor 104, so the supply voltage VCC is determined by the first discharge current IDIS1, the second The discharge current IDIS2, the charge current IC, and the capacitor 104 determine that the supply voltage VCC decreases from the second stable state after time T5 until it is less than a low-voltage lock-off voltage UVLOOFF (time T6 shown in FIG. 2). As shown in FIG. 2, at time T6, because the power supply voltage VCC is lower than the low-voltage lock-off voltage UVLOOFF, the controller 200 disables the delay circuit 2024, causing the power supply voltage VCC to gradually increase until it is greater than the low-voltage lock-on voltage UVLOON (as in Time T7 shown in FIG. 2). As shown in FIG. 2, after time T7, the controller 200 will repeat the above operation principle from time T1 to time T7 until the power converter 100 leaves the protection mode. In addition, the present invention In another embodiment, the second discharge current IDIS2 can be adjusted according to the output voltage of the secondary side SEC of the power converter 100 (where the output voltage is not shown in FIG. 1), for example, when the output voltage is high, the second The discharge current IDIS2 is low, and when the output voltage is low, the second discharge current IDIS2 is high.

Please refer to FIGS. 3 and 4. FIG. 3 is a schematic diagram illustrating the coupling relationship between the first current source 2022, the delay 2024, and the second current source 2026, and FIG. 4 is a schematic diagram illustrating the operation timing of the delay 2024. As shown in FIG. 3, the delayer 2024 includes a comparator 20242, an OR gate 20244, an inverter gate 20246, a pulse generator 20248, and flip-flops D0-DN+1, DF. As shown in Figures 2 and 4, between a time T41 (corresponding to the time T2 in Figure 2) and a time T42 (corresponding to the time T3 in Figure 2), because the gate signal generation circuit generates the gate control signal GCS To the power switch 102, the detection voltage VCS gradually increases from zero until the time T3 is equal to the reference voltage VREF. Therefore, between time T41 and time T42, the comparison signal VCOMP generated by the comparator 20242 is high. In addition, between time T41 and time T42, the protection circuit has not yet generated the protection signal OCP, so the protection signal OCP is at a low potential. In addition, as shown in FIG. 4, after the time T42, the comparison signal VCOMP, the protection signal OCP and the pulse wave signal PUL generated by the pulse wave generator 20248 can make the reset pin R of the flip-flop D0-DN+1 Is low, so the delayer 2024 can use the flip-flop D0-DN+1 to delay a clock signal CLK and generate a delay enable signal DES to the second current source 2026 at a time T43 (corresponding to time T5 in FIG. 2), As a result, the second current source 2026 is enabled and begins to generate a second discharge current IDIS2 to discharge the capacitor 104. As shown in FIG. 4, the series connection of the flip-flops D0-DN+1 is used to determine the predetermined delay time, That is to say, the delay 2024 can use the flip-flops D0-DN+1 to change the length of the predetermined delay time. In addition, the pulse wave generator 20248 generates the pulse wave signal PUL according to the rising edge of the protection signal OCP. In addition, as shown in FIG. 4, after time T42, the reset signal EN of the flip-flop DF is at a low potential to maintain the protection signal OCP at a high potential.

In an embodiment of the present invention, when the power converter 100 is used in a TV and enters the protection mode, since the TV cannot be turned off arbitrarily, the controller 200 will operate according to the timing of FIG. 2. Although as shown in FIG. 2, the gate signal generating circuit still generates the gate control signal GCS to the power switch 102 during the recovery period, but because the delay 2024 can use the flip-flop D0-DN+1 to extend the predetermined delay Time (that is, to extend the protection period TP, where during the protection period TP, the gate signal generation circuit stops generating the gate control signal GCS to the power switch 102), so the controller 200 can enable the power switch 102 of the power converter 100 to recover During this period, the heat generated by the TR is effectively dissipated to protect the components in the TV. In addition, because the controller 200 uses the delay circuit 202 to directly control the power supply voltage VCC through the power supply voltage pin 204, the controller 200 is also a 6-pin integrated circuit, that is to say, the present invention enables the controller 200 without additional Pins.

Please refer to FIG. 5 and FIG. 6, FIG. 5 is a schematic diagram of a controller 500 for extending the protection period of the power converter 100 disclosed in the second embodiment of the present invention, and FIG. 6 is a diagram illustrating the power converter After 100 enters the protection mode, the timing diagram of the power supply voltage VCC of the controller 500 and the gate control signal GCS generated by the controller 500, in order to simplify FIG. 5, so FIG. 5 only shows the power converter 100 and the controller 500 Elements related to the present invention. As shown in FIG. 5, the difference between the controller 500 and the controller 200 is that the controller 500 includes a delay circuit 502, and the delay circuit 502 includes a current source 5022 and a counter 5024, wherein the current source 5022 is coupled to the power supply voltage At pin 204, the counter 5024 is coupled to the current source 5022 and the controller 500 receives the supply voltage VCC through the supply voltage pin 204. In addition, as shown in FIG. 6, the difference between the power supply voltage VCC of the controller 500 and the power supply voltage VCC of the controller 200 lies in the operation principle corresponding to the protection time TP, which is described in detail below.

As shown in FIG. 6, after the power converter 100 enters the protection mode, at time T3, the gate signal generating circuit in the controller 500 (not shown in the controller 500 in FIG. 5) can be converted according to the power supply The detection voltage VCS (as shown in FIG. 5) and the reference voltage VREF of the primary PRI of the device 100 stop generating the gate control signal GCS to the power switch 102, and the protection circuit in the controller 500 (not shown in FIG. 5) In the controller 500 of the figure), a protection signal OCP is generated to the current source 5022. Therefore, because the protection circuit generates the protection signal OCP to the current source 5022, the current source 5022 is enabled and begins to generate a second discharge current IDIS2 to discharge the capacitor 104 (as shown in FIG. 5). After time T3, because the second discharge current IDIS2 starts to discharge the capacitor 104, the supply voltage VCC is determined by the second discharge current IDIS2, the charging current IC, and the capacitor 104, but in an embodiment of the present invention, the second discharge The current IDIS2 is greater than the charging current IC, so the supply voltage VCC will gradually decrease until the supply voltage VCC is less than the lower limit LLI (time T4 shown in FIG. 6). As shown in FIG. 6, at time T4, because the power supply voltage VCC is less than the lower limit value LLI, the current source 5022 generates a first discharge current IDIS1. At this time, the supply voltage VCC is determined by the first discharge current IDIS1, the charge current IC and the capacitor 104, but in an embodiment of the present invention, the first discharge current IDIS1 is less than the charge current IC, so the supply voltage VCC will gradually increase Until the supply voltage VCC is greater than an upper limit ULI (time T5 shown in FIG. 6). In this way, the delay circuit 502 can repeat the above operation principle from time T4 to time T5 until the counter 5024 counts the number of times that the power supply voltage VCC is less than the lower limit LLI (in another embodiment of the present invention, the counter 5024 counts the power supply voltage VCC greater than the upper limit The number of limits ULI) is equal to a predetermined number of times (corresponding to the time T6 shown in FIG. 6). At time T6, because the number of times is equal to the predetermined number of times, the current source 5022 will only generate the second discharge current IDIS2, causing the supply voltage VCC to start to decrease after time T6 until it is less than the low voltage lock-off voltage UVLOOFF (as shown in FIG. 6) Time T7). Therefore, although the gate signal generating circuit TR will still generate the gate control signal GCS to the power switch 102 during the recovery period as shown in FIG. 6, because the delay circuit 502 can utilize the operating principle shown in FIG. 6 above By extending the predetermined delay time (that is, extending the protection period TP), the controller 500 can effectively dissipate the heat generated by the power switch 102 of the power converter 100 during the recovery period to protect the components in the television. In addition, the remaining operating principles of the controller 500 are the same as those of the controller 200, and will not be repeated here.

Please refer to FIGS. 1, 2, and 7, FIG. 7 is a flowchart of a controller operating method for extending the protection period of a power converter disclosed in the third embodiment of the present invention. The operation method of FIG. 7 is explained by using the power converter 100 and the synchronous rectifier 200 of FIG. 1, the detailed steps are as follows:

Step 700: Start;

Step 702: The power converter 100 enters the protection mode;

Step 704: The first current source 2022 generates a first discharge current IDIS1 according to the corresponding protection signal OCP and the power supply voltage VCC;

Step 706: The delayer 2024 generates a delay enable signal DES according to the protection signal OCP and the detection voltage VCS;

Step 708: The second current source 2026 generates a second discharge current IDIS2 according to the delayed enable signal DES;

Step 710: When the power supply voltage VCC is lower than the low voltage lock-off voltage UVLOOFF, the controller 200 disables the delay circuit 202;

Step 712: When the delay circuit 202 is disabled and the power supply voltage VCC is greater than the low voltage lock-on voltage UVLOON, the controller 200 generates the gate control signal GCS to the power switch 102 of the primary side PRI of the power converter 100 again, and skips back to step 704 .

In step 702, as shown in FIG. 1, the protection circuit in the controller 200 (not shown in the controller 200 in FIG. 1) can be determined according to the output current IOUT of the secondary side SEC of the power converter 100 Whether to put the power converter 100 into this protection mode. After the power converter 100 enters the protection mode, at time T1, the power supply voltage VCC is greater than the low voltage lock-on voltage UVLOON, so the gate signal generation circuit in the controller 200 will generate gate control between time T2 and time T3 The signal GCS is sent to the power switch 102, wherein the time interval between the time T2 and the time T3 is the recovery period TR of the power converter 100 corresponding to the protection mode. As shown in FIGS. 1 and 2, in the recovery period TR, since only the charging current IC charges the capacitor 104, the power supply voltage VCC maintains the first stable state. In step 704, as shown in FIG. 2, at time T3, the gate signal generating circuit may stop according to the detection voltage VCS (as shown in FIG. 1) of the primary PRI of the power converter 100 and the reference voltage VREF A gate control signal GCS is generated to the power switch 102, and the protection circuit generates a protection signal OCP to the first current source 2022 and the delay 2024. Therefore, the first current source 2022 is enabled and starts to generate the first discharge current IDIS1 to discharge the capacitor 104 according to the supply voltage VCC, where the first discharge current IDIS1 changes with the change of the supply voltage VCC. After time T3, the first discharge current IDIS1 starts to discharge the capacitor 104, so the supply voltage VCC is determined by the first discharge current IDIS1, the charging current IC and the capacitor 104, where the first discharge current IDIS1 is greater than the charging current at time T3 IC, so the supply voltage VCC will gradually decrease until time T4 (because the first discharge current IDIS1 will change with the change of the supply voltage VCC, so at time T4, the first discharge current IDIS1 is equal to the charging current IC, resulting in the supply voltage VCC The second stable state is maintained after time T4 until time T5). In step 706, as shown in FIG. 2, at time T5, the delayer 2024 can generate the delay enable signal DES to the second current source 2026 according to the protection signal OCP and the detection voltage VCS, so the second current source 2026 causes The second discharge current IDIS2 can be generated and discharged to the capacitor 104, wherein the delay enable signal DES corresponds to a predetermined delay time, and the time interval between the time T3 and the time T5 is the protection period TP of the power converter 100 corresponding to the protection mode . In step 708, as shown in FIG. 2, after time T5, the second discharge current IDIS2 begins to discharge the capacitor 104 (where the first discharge current IDIS1 continues to discharge the capacitor 104, so the power supply voltage VCC is discharged by the first The current IDIS1, the second discharge current IDIS2, the charging current IC, and the capacitor 104 determine that the supply voltage VCC starts to decrease from the second stable state after time T5 until it is less than the low voltage lock-off voltage UVLOOFF (the time shown in FIG. 2) T6). In step 710, as shown in FIG. 2, at time T6, because the power supply voltage VCC is lower than the low voltage lock-off voltage UVLOOFF, the controller 200 disables the delay circuit 2024, causing the power supply voltage VCC to gradually increase until it is greater than Low voltage lock-on voltage UVLOON (time T7 shown in Figure 2). In step 712, as shown in Figure 2, at time T7, the power supply voltage VCC is greater than the low voltage lock-on voltage UVLOON, so the controller 200 The internal gate signal generating circuit (not shown in the controller 200 in FIG. 1) again generates the gate control signal GCS to the power switch 102 of the primary side PRI of the power converter 100.

Please refer to FIGS. 1, 5, 6, and 8, which is a flowchart of a controller operating method for extending the protection period of the power converter disclosed in the fourth embodiment of the present invention. The operation method of FIG. 8 is explained by using the power converter 100 and the synchronous rectifier 500 of FIG. 5, the detailed steps are as follows:

Step 800: Start;

Step 802: The power converter 100 enters the protection mode;

Step 804: The current source 5022 is enabled according to the protection signal OCP corresponding to the protection mode;

Step 806: whether the power supply voltage VCC is less than the lower limit LLI; if yes, proceed to step 808; if not, proceed to step 806 again;

Step 808: The current source 5022 generates the first discharge current IDIS1, and the counter 5024 counts the number of times the power supply voltage VCC is less than the lower limit LLI;

Step 810: whether the power supply voltage VCC is greater than the upper limit ULI; if yes, proceed to step 812; if not, proceed to step 810 again;

Step 812: The current source 5022 generates a second discharge current IDIS2;

Step 814: The counter 5024 counts whether the number of times the power supply voltage VCC is less than the lower limit value LLI is equal to the predetermined number of times; if yes, proceed to step 816; if not, proceed to step 806;

Step 816: When the power supply voltage VCC is lower than the low voltage lock-off voltage UVLOOFF, the controller 500 disables the delay circuit 502;

Step 818: When the delay circuit 502 is disabled and the supply voltage VCC is greater than the low-voltage lock-on voltage UVLOON, the controller 500 generates the gate control signal GCS again to the power switch 102 of the primary-side PRI of the power converter 100, and skips back to step 804 .

The difference between the fourth embodiment of FIG. 8 and the third embodiment of FIG. 7 is that in step 806, at time T3, the current source 5022 is enabled and begins to generate the second discharge current IDIS2 to the capacitor 104 (as shown in FIG. 5) Display) discharge, so the supply voltage VCC will gradually decrease until the supply voltage VCC is less than the lower limit LLI (time T4 shown in Figure 6); in step 808, as shown in Figure 6, at time T4, because The current source 5022 generates the first discharge current IDIS1, so the supply voltage VCC will gradually increase until the supply voltage VCC is greater than the upper limit ULI (time T5 shown in FIG. 6); in step 812, because the current source 5022 generates the Two discharge currents IDIS2, so the supply voltage VCC will gradually decrease until the supply voltage VCC is less than the lower limit LLI; in step 814, the delay circuit 502 may repeat the operation principle from the above time T4 to time T5 until the counter 5024 counts the supply voltage VCC The number of times less than the lower limit LLI (in another embodiment of the present invention, the counter 5024 counts the number of times the supply voltage VCC is greater than the upper limit ULI) is equal to the predetermined number of times (corresponding to time T6 shown in FIG. 6); T6, because the number of times is equal to the predetermined number of times, the current source 5022 will only generate the second discharge current IDIS2, causing the supply voltage VCC to start to decrease after time T6 until it is less than the low voltage lock-off voltage UVLOOFF (the time shown in Figure 6) T7). In addition, the remaining operating principles of the fourth embodiment of FIG. 8 are the same as those of the third embodiment of FIG. 7, and are not repeated here.

In summary, the controller and the operating method provided by the present invention are to use the delay circuit to extend the protection period corresponding to the protection mode according to the power supply voltage after the power converter enters the protection mode. In addition, the content of the above-mentioned embodiments of the present invention takes the protection signals applied to the overcurrent protection and the output short-circuit protection as examples. In fact, the protection signal of the present invention can also be applied to various protection mechanisms or protection modes, such as over voltage protection (over voltage protection, OVP), over load protection (over load protection, OLP), and over temperature protection (over temperature protection (OTP), brown out protection, etc. Therefore, because the present invention can extend the protection period, compared with the prior art, the present invention can effectively dissipate the heat generated by the power switch of the power converter during the recovery period corresponding to the protection mode. In addition, because the controller directly controls the power supply voltage through the power supply voltage pin, the controller does not require additional pins. The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100‧‧‧Power converter 102‧‧‧Power switch 103‧‧‧Resistance 104‧‧‧Capacitance 200, 500‧‧‧ controller 202‧‧‧ Delay circuit 204‧‧‧ Supply voltage pin 206、208、210‧‧‧pin 2022‧‧‧First current source 2024‧‧‧Delay 2026‧‧‧second current source 20242‧‧‧Comparator 20244‧‧‧or gate 20246‧‧‧Reverse gate 20248‧‧‧Pulse generator 502‧‧‧ Delay circuit 5022‧‧‧Current source 5024‧‧‧Counter CLK‧‧‧clock signal D0-DN+1, DF‧‧‧Flip DES‧‧‧delay enable signal EN‧‧‧Reset signal GND‧‧‧Ground GCS‧‧‧Gate control signal IC‧‧‧Charging current IPRI‧‧‧primary side current IOUT‧‧‧Output current IDIS1‧‧‧First discharge current IDIS2‧‧‧Second discharge current LLI‧‧‧Lower limit OCP‧‧‧Protection signal PRI‧‧‧primary side PUL‧‧‧Pulse signal R‧‧‧ reset pin SEC‧‧‧Secondary side T1-T7, T41, T42, T43‧‧‧ time TR‧‧‧During recovery TP‧‧‧Protection period UVLOON‧‧‧Low voltage lock-on voltage UVLOOFF‧‧‧Low voltage lock off voltage ULI‧‧‧Upper limit VCS‧‧‧detect voltage VCC‧‧‧Supply voltage VREF‧‧‧Reference voltage VCOMP‧‧‧Comparison signal 700-712, 800-818‧‧‧ steps

FIG. 1 is a schematic diagram of a controller for extending the protection period of a power converter disclosed in the first embodiment of the present invention. Figure 2 is a schematic diagram illustrating the timing of the power supply voltage of the controller and the gate control signal generated by the controller after the power converter enters the protection mode. FIG. 3 is a schematic diagram illustrating the coupling relationship between the first current source, the delay, and the second current source. FIG. 4 is a schematic diagram illustrating the operation timing of the delay. FIG. 5 is a schematic diagram of a controller for extending the protection period of a power converter disclosed in the second embodiment of the present invention. Fig. 6 is a timing diagram illustrating the power supply voltage of the controller and the gate control signal generated by the controller after the power converter enters the protection mode. FIG. 7 is a flowchart of a controller operation method for extending the protection period of a power converter disclosed in the third embodiment of the present invention. FIG. 8 is a flowchart of a controller operation method for extending the protection period of a power converter disclosed in the fourth embodiment of the present invention.

100‧‧‧Power converter

102‧‧‧Power switch

103‧‧‧Resistance

104‧‧‧Capacitance

200‧‧‧Controller

202‧‧‧ Delay circuit

204‧‧‧ Supply voltage pin

206、208、210‧‧‧pin

2022‧‧‧First current source

2024‧‧‧Delay

2026‧‧‧second current source

DES‧‧‧delay enable signal

GND‧‧‧Ground

GCS‧‧‧Gate control signal

IC‧‧‧Charging current

IPRI‧‧‧primary side current

IOUT‧‧‧Output current

IDIS1‧‧‧First discharge current

IDIS2‧‧‧Second discharge current

OCP‧‧‧Protection signal

PRI‧‧‧primary side

SEC‧‧‧Secondary side

VCS‧‧‧detect voltage

VCC‧‧‧Supply voltage

VREF‧‧‧Reference voltage

Claims (17)

A controller for extending the protection period of a power converter, including: A delay circuit, coupled to a power supply voltage pin of the controller, wherein when the power converter enters a protection mode, the delay circuit is enabled, receives a power supply voltage through the power supply voltage pin, and according to the power supply The voltage extension corresponds to the protection period of the protection mode. The controller according to claim 1, wherein the delay circuit includes: A first current source, coupled to the supply voltage pin, for generating a first discharge current according to a protection signal corresponding to the protection mode and the supply voltage when the power converter enters the protection mode; A delayer for generating a delay enable signal based on the protection signal and the detected voltage on the primary side of the power converter, wherein the delay enable signal corresponds to a predetermined delay time; and A second current source, coupled to the delay and the supply voltage pin, for generating a second discharge current according to the delay enable signal; Where the power supply voltage is determined by the first discharge current, the capacitance of the primary side of the power converter, and a charging current related to the input of the primary side of the power converter, or by the first discharge current, the second The discharge current, the capacitance, and the charge current are determined. The controller according to claim 2, wherein the controller disables the delay circuit when the power supply voltage is lower than an under voltage lock out turn-off voltage. The controller according to claim 3, wherein when the delay circuit is disabled and the supply voltage is greater than a low voltage lock-on voltage, the controller generates a gate control signal to the power of the primary side of the power converter again switch. The controller according to claim 1, wherein the delay circuit includes: A current source for enabling according to a protection signal corresponding to the protection mode, when the supply voltage is less than the lower limit, a first discharge current is generated, and when the supply voltage is greater than an upper limit, a first 2. Discharge current; and A counter for counting the number of times the power supply voltage is less than the lower limit; Where the supply voltage is determined by the first discharge current, the primary side capacitor of the power converter, a charging current related to the input side of the primary side of the power converter, or by the second discharge current, the capacitor, and The charging current determines When the number of times is equal to a predetermined number of times, the counter causes the current source to generate the second discharge current, the first discharge current is less than the charging current, and the second discharge current is greater than the charging current. The controller according to claim 5, wherein when the power supply voltage is lower than a low-voltage lock-off voltage, the controller disables the delay circuit. The controller according to claim 6, wherein when the delay circuit is disabled and the supply voltage is greater than a low-voltage lock-on voltage, the controller generates a gate control signal to the power of the primary side of the power converter again switch. The controller according to claim 2 or 5, wherein the second discharge current is adjusted according to the output voltage of the secondary side of the power converter. The controller according to claim 1, wherein the protection mode corresponds to an output short-circuited protection (OSCP) or an over current protection (OCP). The controller according to claim 1, wherein the protection mode corresponds to an over voltage protection (over voltage protection, OVP), an over load protection (over load protection, OLP), and an over temperature protection (over temperature protection, OTP), or a brown out protection. The controller according to claim 1, wherein the power converter is a flyback power converter. An operation method of a controller for extending the protection period of a power converter, wherein the controller includes a delay circuit and the delay circuit includes a first current source, a delay and a second current source, the operation method includes : The power converter enters a protection mode; The first current source generates a first discharge current according to a protection signal corresponding to the protection mode and a supply voltage, and the first discharge current, the capacitance of the primary side of the power converter, and the primary current related to the power converter A charging current at the input of the side determines the supply voltage; The delayer generates a delay enable signal based on the protection signal and the detected voltage on the primary side of the power converter, wherein the delay enable signal corresponds to a predetermined delay time; and The second current source generates a second discharge current according to the delayed enable signal, and the second discharge current and the first discharge current, the capacitor, and the charging current determine the supply voltage. The operation method as described in claim 12, additionally includes: When the supply voltage is lower than a low voltage lock-off voltage, the controller disables the delay circuit; and When the delay circuit is disabled and the power supply voltage is greater than a low-voltage lock-up voltage, the controller generates a gate control signal to the power switch on the primary side of the power converter again. The operation method according to claim 12, wherein the second discharge current is adjusted according to the output voltage of the secondary side of the power converter. An operation method of a controller for extending the protection period of a power converter, wherein the controller includes a delay circuit and the delay circuit includes a current source and a counter, the operation method includes: The power converter enters a protection mode; The current source is enabled according to a protection signal corresponding to the protection mode; When a power supply voltage is less than the lower limit, the current source generates a first discharge current, and the first discharge current, the capacitance of the primary side of the power converter, and the input of the primary side of the power converter The charging current determines the supply voltage; When the supply voltage is greater than an upper limit, the current source generates a second discharge current, and the second discharge current, the capacitor, and the charging current determine the supply voltage; and When the counter counts that the number of times that the power supply voltage is less than the lower limit value is equal to a predetermined number of times, the counter causes the current source to generate the second discharge current; The first discharge current is smaller than the charging current, and the second discharge current is larger than the charging current. The operation method described in claim 15 additionally includes: When the supply voltage is lower than a low voltage lock-off voltage, the controller disables the delay circuit; and When the delay circuit is disabled and the power supply voltage is greater than a low-voltage lock-up voltage, the controller generates a gate control signal to the power switch on the primary side of the power converter again. The operation method according to claim 15, wherein the second discharge current is adjusted according to the output voltage of the secondary side of the power converter.

Images