TW202002216A - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TW202002216A
TW202002216A TW107146957A TW107146957A TW202002216A TW 202002216 A TW202002216 A TW 202002216A TW 107146957 A TW107146957 A TW 107146957A TW 107146957 A TW107146957 A TW 107146957A TW 202002216 A TW202002216 A TW 202002216A
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conductive
redistribution circuit
circuit structure
sealing body
die
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TW107146957A
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English (en)
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TWI695475B (zh
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張簡上煜
徐宏欣
林南君
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力成科技股份有限公司
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Abstract

一種封裝結構包括第一重佈線路結構、晶粒、多個導電片、多個導電球以及第一密封體。第一重佈線路結構具有第一表面以及相對於第一表面的第二表面。晶粒具有多個連接墊，且與第一重佈線路結構的第一表面電性連接。多個導電片與第一重佈線路結構的第一表面電性連接。多個導電球配置於對應的多個導電片上，且經由多個導電片與第一重佈線路結構的第一表面電耦合。第一密封體密封晶粒、多個導電片與多個導電球。第一密封體暴露出每一導電球的至少一部分。另提供一種半導體封裝的製造方法。

Description

封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種具有導電片（conductive sheet）的封裝結構及其製造方法。
市場上非常需要比上一代同類產品更輕，更纖薄，更短，更小的電子產品。因此，為了有助於減少現有裝置的體積和重量的半導體封裝新技術，而進行了廣泛的研究。3D堆疊技術（例如：封裝層疊）已經被開發以滿足更高封裝密度的需求。
本發明提供一種封裝結構及其製造方法，其能夠以較低的製造成本和較高的製程彈性垂直整合各種元件。
本發明的封裝結構包括第一重佈線路結構、晶粒、多個導電片、多個導電球以及第一密封體。第一重佈線路結構具有第一表面以及相對於第一表面的第二表面。晶粒具有多個連接墊。連接墊與第一重佈線路結構的第一表面電性連接。導電片與第一重佈線路結構的第一表面電性連接。導電球配置於對應的導電片上。導電球藉由導電片與第一重佈線路結構的第一表面電耦合。第一密封體包封晶粒、導電片與導電球。第一密封體暴露出每一導電球的至少一部分。
在本發明的一實施例中，導電球包括焊球。
在本發明的一實施例中，導電片位於圍繞晶粒的週圍區。
在本發明的一實施例中，封裝結構更包括第二重佈線路結構以及配置於第二重佈線路結構上的至少一晶片、至少一子封裝、至少一被動元件或上述之組合。第二重佈線路結構，位於相對於第一重佈線路結構的第一密封體上，且第二重佈線路結構與多個導電球電性連接。至少一晶片、至少一子封裝、至少一被動元件或上述之組合與第二重佈線路結構電性連接。至少一晶片藉由覆晶接合或打線接合與第二重佈線路結構電性連接。
在本發明的一實施例中，封裝結構更包括第二重佈線路結構、配置於第二重佈線路結構上的至少一晶片、至少一子封裝、至少一被動元件或上述之組合以及第二密封體。第二重佈線路結構，位於相對於第一重佈線路結構的第一密封體上，且第二重佈線路結構與多個導電球電性連接。至少一晶片、至少一子封裝、至少一被動元件或上述之組合與第二重佈線路結構電性連接。第二密封體包封至少一晶片、至少一子封裝、至少一被動元件或上述之組合。
在本發明的一實施例中，封裝結構更包括多個導電端子。導電端子位於第一重佈線路結構的第二表面，其中導電端子與第一重佈線路結構電性連接。
本發明的封裝結構的製造方法至少包括以下步驟。提供具有黏著層的載板。形成多個導電片於黏著層上。形成多個導電球於導電片上。放置多個晶粒於黏著層上。每一晶粒具有多個連接墊，且連接墊嵌入黏著層中。形成第一密封體以包封晶粒、導電片與導電球。第一密封體暴露出每一導電球的至少一部分。從晶粒、導電片以及第一密封體上分離黏著層。形成第一重佈線路結構於晶粒、導電片與第一密封體上。第一重佈線路結構與晶粒及導電片電性連接。
在本發明的一實施例中，封裝結構的製造方法更包括以下步驟。形成第二重佈線路結構於相對於第一重佈線路結構的第一密封體上，其中第二重佈線路結構與多個導電球電性連接。配置至少一晶片、至少一子封裝、至少一被動元件或上述之組合於第二重佈線路結構上，其中至少一晶片、至少一子封裝、至少一被動元件或上述之組合與第二重佈線路結構電性連接。藉由第二密封體包封至少一晶片、至少一子封裝、至少一被動元件或上述之組合。
在本發明的一實施例中，封裝結構的製造方法更包括以下步驟。形成多個導電端子於第一重佈線路結構上。
基於上述，本發明的封裝結構採用扇出型設計，適合雙面垂直整合。舉例而言，嵌於第一密封體中的導電球與導電片提供封裝結構中垂直方向的電性連接。由於可以用更簡單及便宜的製程來形成導電球與導電片，進而封裝結構的製程複雜度與製造成本都可以顯著的下降。此外，導電球與導電片的匹配也可以省略傳統上為了形成垂直導電結構所使用的化學濕製程。且由於與耐化學性較無關，故可以更彈性的選擇用來接合黏著晶粒的材料。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1I是依據本發明一些實施例的封裝結構的製造方法的剖面示意圖。請參照圖1A，提供第一載板100，第一載板100上具有第一黏著層110。第一載板100可以是玻璃基板或玻璃支撐板。然而，本發明不限於此。其他合適的基板材料也可以作為第一載板100，只要所述材料能夠承載在其之上所形成的封裝結構且能夠承受後續的製程即可。第一黏著層110可以形成於第一載板100上，以提升第一載板100以及隨後形成於其上的結構之間的黏著。第一黏著層110可以包括光熱轉換（light to heat conversion；LTHC）黏著層、環氧樹脂（epoxy resin）、無機材料、有機聚合物材料或其他適宜的黏著材料。然而，本發明不限於此。在一些替代實施例中，可以使用其他適宜的黏著層。
如圖1A所示，於第一黏著層110上依序形成多個導電片200以及多個導電球210。在一些實施例中，可以於第一黏著層110的相應區域上經由放置預先製造的銅層來形成導電片200。在一些替代實施例中，可以於第一黏著層110上沉積導電材料層（未繪示）來形成導電片200。藉由微影與蝕刻製程圖案化導電材料層，以於第一黏著層110上形成多個導電片200。在一些實施例中，導電片200的材料可以包括銅，但本發明不以此為限。在一些其他的實施例中，導電片200的材料也可以是能夠與其他導電材料相接合的導電材料。於對應的導電片200上配置導電球210。導電球210可以經由以下方法形成。於對應的導電片200上經由取放製程（pick-and-place process）或植球製程（ball placement process）配置每一導電球210。之後，可以於導電球210上執行高溫回焊製程（reflow process），而導電片200於每一導電片200與每一導電球210之間形成金屬間層（intermetallic layer；IML；未繪示），從而導電片200與導電球210物理耦合。在一些實施例中，導電球210包括焊球。然而，本發明不限於此。在一些其他實施例中，導電球210可以由其他導電材料所製成，只要導電球210可以與導電片200形成穩固的接合即可。
請參照圖1B，於第一黏著層110上配置與導電球210一起的多個晶粒300。舉例而言，可以以多個導電片200與多個導電球210圍繞每一晶粒300的方式配置晶粒300。換句話說，於圍繞每一晶粒300的周圍區中配置多個導電片200與多個導電球210。晶粒300例如是特殊應用積體電路（Application-Specific Integrated Circuit；ASIC）。然而，本發明不限於此。晶粒300可以是其他種型的半導體裝置。如圖1B所示，每一晶粒300包括半導體基板302、多個連接墊304以及保護層306。在一些實施例中，半導體基板302可以是具有主動元件（如：電晶體或其他類似者）及選擇性地具有被動元件（如：電阻、電容、電感或其他類似者）形成於其上的矽基板。連接墊304可以是鋁接墊、銅接墊或其他適宜的金屬接墊。於晶粒300的主動面300a上配置連接墊304。在一些實施例中，保護層306可以是由聚合物材料、氧化矽層、氮化矽層、氮氧化矽層或是由其他適宜的介電材料所形成的介電層所製成。保護層306位於晶粒300的主動面300a上，以覆蓋連接墊304。保護層306具有多個開口306a，開口306a暴露出每一連接墊304的至少一部分，以作為進一步的電性連接。如圖1B所示，晶粒300以面朝下（face down）的方式配置。晶粒300的主動面300a可以與第一黏著層110直接接觸。連接墊304可以嵌入於第一黏著層110內。
請參照圖1C，於第一載板100及第一黏著層110上形成密封材料402，且密封材料402完全覆蓋晶粒300、導電片200以及導電球210。密封材料402可以包括由模塑製程所形成的模塑化合物或絕緣材料（如：環氧樹脂、矽基樹脂（silicone）或其他適宜的樹脂）。如圖1C所示，經由包覆模製程（over-molding process）形成密封材料402。密封材料402的厚度T402可以大於晶粒300的厚度T300以及導電片200與導電球210的總厚度T200’，以使密封材料402包封晶粒300、導電球210以及導電片200。
請參照圖1D，減少密封材料402的厚度T402直到暴露出每一導電球210的至少一部分，以形成第一密封體400。可以藉由機械研磨製程（mechanical grinding process）、化學機械研磨製程（chemical-mechanical polishing；CMP）或其他適宜的製程以平坦化密封材料402。在一些實施例中，於平坦化製程時，可以移除每一導電球210的一部分，以形成平坦表面210a。第一密封體400包封晶粒300、導電片200以及導電球210。如圖1D所示，被暴露出的導電球210的表面210a基本上與第一密封體400的第一表面400a共面（coplanar）。被暴露出的導電球210的表面210a可以用於與之後形成的元件電性連接。
請參照圖1E，第一密封體400的第一表面400a以及導電球210的表面210a可以藉由第二黏著層115接合至第二載板105。第二載板105與第二黏著層115可以分別由與第一載板100及第一黏著層110相同的材料製成，故於此不加以贅述。在將第二載板105與第二黏著層115接合於第一密封體400與導電球210之後，移除第一載板100以及第一黏著層110。第一黏著層110與第一載板100可以從晶粒300、導電片200與第一密封體400分離，以暴露出第一密封體400中相對於其第一表面400a的第二表面400b。在接合第二載板105後，暴露出連接墊304、晶粒300以及導電片200。
請參照圖1F，於晶粒300、導電片200以及第一密封體400上形成第一重佈線路結構500。第一重佈線路結構500具有第一表面500a以及相對於第一表面500a的第二表面500b。第一重佈線路結構500的第一表面500a與導電片200、晶粒300以及第一密封體400物理耦合。第一重佈線路結構500的第一表面500a電性連接至晶粒300的連接墊304以及導電片200。在一些實施例中，每一導電片200夾於第一重佈線路結構500與對應的導電球210之間，以將導電球210電耦合至第一重佈線路結構500的第一表面500a。第一重佈線路結構500可以包括至少一介電層502、多個導電圖案504以及多個導通孔506。可以藉由適宜的製造技術，如：旋轉塗佈（spin-on coating）、化學氣相沉積（chemical vapor deposition；CVD）、電漿輔助化學氣相沉積（plasma-enhanced chemical vapor deposition；PECVD）或其他類似者，以形成介電層502。可以藉由濺鍍、蒸鍍、化學鍍（electro-less plating）或電鍍來形成導電圖案504以及導通孔506。介電層502可以由氧化矽、氮化矽、碳化矽、氮氧化矽、聚酰亞胺、苯並環丁烯等的非有機或有機介電材料所製成。導電圖案504與導通孔506嵌入於介電層502中。介電層502與導電圖案504可以交替地堆疊。導通孔506可以穿過介電層502，以使導電圖案504彼此電性連接。導電圖案504與導通孔506可以由銅、鋁、鎳、金、銀、錫、上述之組合、銅/鎳/金的複合結構或是其他適宜的導電材料所組成。
如圖1F所示，第一重佈線路結構500包括三個介電層502。然而，本發明對於介電層502的數量並不加以限制，並且可以基於電路的設計而進行調整。底部的介電層502可以具有多個接觸開口502a，以暴露出晶粒300的連接墊304以及導電片200。於導通孔506位於接觸開口502a中，導通孔506可以與晶粒300的連接墊304以及導電片200直接接觸。中間的介電層502暴露出部分底部的導電圖案504，以使底部的導電圖案504可以經由導通孔506與其他導電圖案504電性連接，而形成晶粒300與導電片200之間的電性連接。頂部的介電層502具有多個接觸開口502b，接觸開口502b暴露出部分頂部的導電圖案504，以用於後續製程的電性連接。在一些實施例中，頂部的導電圖案504可以被稱為凸塊底金屬（under-ball metallurgy；UBM）。
請參照圖1G，在形成第一重佈線路結構500之後，移除第二載板105以及第二黏著層115，以暴露出第一密封體400的第一表面400a以及導電球210的表面210a。對封裝結構陣列進行切割或切單（singulation）製程，以形成如圖1H所示的多個中途的（intermediate）封裝結構。切單製程例如包括以旋轉刀片或雷射光束進行切割。封裝結構陣列可以被切割，以用於打線接合、覆晶（flip chip）的應用或堆疊式（Package-on-Package；PoP）目的。
請參照圖1I，於第一重佈線路結構500的第二表面500b上形成多個導電端子700。導電端子700可以藉由植球製程（ball placement process）以及回焊製程（reflow process）來形成。導電端子700可以是焊球等的導電凸塊。導電端子700可以具有其他可能的形式以及形狀。在一些其他的實施例中，導電端子700可以是導電柱或導電栓塞（conductive posts）。在一些實施例中，於頂部的介電層502所暴露出的頂部的導電圖案504中對應地配置導電端子700。導電端子700經由第一重佈線路結構500電性連接至晶粒300。
在第一重佈線路結構500上形成導電端子700之後，可以於導電球210與第一密封體400上堆疊子封裝SUB1。子封裝SUB1可以是球柵陣列封裝（Ball Grid Array；BGA）、覆晶尺寸封裝（Flip Chip Chip Scale Package；FCCSP）、覆晶球柵陣列封裝（Flip Chip Ball Grid Array；FCBGA）、晶圓級封裝（Wafer Level Chip Scale Package；WLCSP）或被動裝置。子封裝SUB1可以包括晶片600、密封體440、重佈線路520以及多個連接端子750。晶片600與密封體440位於重佈線路520上。密封體440包封晶片600。連接端子750位於重佈線路520上。連接端子750藉由重佈線路520電性連接至晶片600。密封體440、重佈線路520以及連接端子750的材料與形成方法可以分別類似於第一密封體400、第一重佈線路結構500以及導電端子700。如圖1I所示，子封裝SUB1的連接端子750與導電球210直接接觸。雖然於圖1I中，晶片600是以面朝下的方式與重佈線路520電性連接，然而，本發明不限於此。在一些替代實施例中，晶片600可以藉由晶粒黏著膜（die attach film，DAF）以面朝上（face-up）的方式配置於重佈線路520上，且可以藉由導線（未繪示）進行電性連接。
可以於第一密封體400與重佈線路520之間形成底膠800，以將導電球210與導電端子750之間的耦合處保護且隔離。底膠800可以藉由毛細填充膠（capillary underfill filling；CUF）的方式形成，且底膠800可以包括聚合物材料、樹脂或二氧化矽添加物。
封裝結構10包括第一重佈線路結構500、晶粒300、導電片200、導電球210、第一密封體400、導電端子700以及子封裝SUB1。晶粒300與導電片200配置於第一重佈線路結構500的第一表面500a上。導電球210配置於對應的導電片200上。第一密封體400包封晶粒300、導電片200以及導電球210。嵌於第一密封體400中的導電球210與導電片200可以提供封裝結構10中垂直方向的電性連接。如此一來，可以在封裝結構10中實現雙面（dual-side）的堆疊結構。由於可以使用較少成本的製程來形成導電球210與導電片200，進而封裝結構10的製程複雜度與製造成本都可以顯著的下降。此外，導電球210與導電片200可以為預先形成（pre-formed）的構件。因此，可以省略傳統上為了形成垂直導電結構所使用的化學濕製程。且由於與耐化學性較無關，故可以更彈性的選擇用來接合黏著晶粒的材料。
圖2A至圖2G是依據本發明一些替代實施例的封裝結構20的製造方法的剖面示意圖。圖2A所示的結構可以藉由執行類似於圖1A至圖1D中所述的步驟來獲得，故於此不加以贅述。
請參照圖2B，於第一密封體400與導電球210上形成第二重佈線路結構550。可以經由與第一重佈線路結構500相似的製程與材料來形成第二重佈線路結構550。第二重佈線路結構550具有第一表面550a以及相對於第一表面550a的第二表面550b。第二重佈線路結構550的第一表面550a接合於導電球210與第一密封體400。第二重佈線路結構550可以包括至少一介電層552、多個導電圖案554以及多個導通孔556。導電圖案554與導通孔556嵌入於介電層552中。在一些實施例中，介電層552與導電圖案554交替地堆疊。導通孔556穿過介電層552，以使導通孔556與導電圖案554電性連接，或使導電圖案554與其他元件電性連接。
如圖2B所示的第二重佈線路結構550包括兩層介電層552。然而，介電層552的數量可以基於電路的設計而進行調整。底部的介電層552可以具有多個接觸開口552a，以暴露出導電球210。配置於接觸開口552a中的底部導通孔556可以與導電球210直接接觸，以於導電球210與第二重佈線路結構550之間形成電性連接。頂部的介電層552具有多個接觸開口552b，接觸開口552b暴露出導電圖案554，以使導電圖案554可以用於後續製程的電性連接。
請參照圖2C，類似於圖1E中所示的第二載板105與第二黏著層115，第二重佈線路結構550的第二表面550b可以經由第二黏著層115接合於第二載板105上。
圖2D至圖2F所示的步驟可以類似於圖1F至圖1H中所述的步驟，故於此不加以贅述。
請參照圖2G，於第一重佈線路結構500的第二表面500b上形成多個導電端子700。此處所述的導電端子700類似於圖1I中所述的導電端子700，故於此不加以贅述。在第一重佈線路結構500上形成導電端子700之後，可以於第二重佈線路結構550的第二表面550b上配置晶片602。晶片602可以藉由覆晶接合電性連接至第二重佈線路結構550。在一些實施例中，頂部的導電圖案504可以被稱為凸塊底金屬。
於晶片602與第二重佈線路結構550之間可以形成底膠802。底膠802可以類似於圖1I中的底膠800，故於此不加以贅述。
此外，可以於第二重佈線路結構550的第二表面550b上配置被動元件PD，以構成封裝結構20。被動元件PD可以電性連接至第二重佈線路結構550。被動元件PD可以是電容、電阻、電感、融斷器或天線。雖然圖2G中僅繪示一個晶片602與一個被動元件PD，然而，可以於第二重佈線路結構550上配置多於一個的晶片602以及多於一個的被動元件PD。
封裝結構20包括第一重佈線路結構500、晶粒300、導電片200、導電球210、第一密封體400、導電端子700、第二重佈線路結構550、晶片602以及被動元件PD。晶粒300與導電片200配置於第一重佈線路結構500的第一表面500a上。導電球210對應地配置於導電片200上。第一密封體400包封晶粒300、導電片200以及導電球210。於相對於第一重佈線路結構500的第一密封體400上配置第二重佈線路結構550。導電球210與導電片200提供封裝結構20中垂直方向的電性連接，以在封裝結構20中實現雙面的堆疊結構。於第一密封體400的相對兩側可以分別形成第一重佈線路結構500與第二重佈線路結構550，如此一來，可以於第一重佈線路結構500或第二重佈線路結構550的任一個上形成其它元件。由於可以使用較少成本的製程來形成導電球210與導電片200，進而封裝結構20的製程複雜度與製造成本都可以顯著的下降。此外，導電球210與導電片200可以為預先形成的構件。因此，可以省略傳統上為了形成垂直導電結構所使用的化學濕製程。且由於與耐化學性較無關，故可以更彈性的選擇用來接合黏著晶粒的材料。
圖3是依據本發明一些替代實施例的封裝結構30的剖面示意圖。封裝結構30類似於如圖2G所示的封裝結構20，差別在於：於第二重佈線路結構550上形成第二密封體450，以包封晶片602與被動元件PD。第二密封體450可以類似於第一密封體400，故於此不加以贅述。第二密封體450可以保護晶片602與被動元件PD，以降低水氣或可能的損壞。
圖4是依據本發明一些替代實施例的封裝結構40的剖面示意圖。封裝結構40類似於如圖2G所示的封裝結構20，差別在於：於第二重佈線路結構550上配置代替晶片602的子封裝SUB2。子封裝SUB2可以包括晶片600'、密封體450'、重佈線路520'、多個導電柱610'以及多個連接端子750'晶片600'與密封體450'位於重佈線路520'上，且密封體450'包封晶片600'。晶片600’藉由導電柱610’電性連接至重佈線路520’。導電柱610’可以由銅或其他適宜的導電材料所製成。於相對於晶片600’與密封體450’的重佈線路520’上配置連接端子750’。連接端子750'藉由重佈線路520'電性連接至晶片600'。密封體450'、重佈線路520'以及連接端子750'的材料與形成方法可以分別類似於第一密封體400、第一重佈線路結構500以及導電端子700，故於此不加以贅述。子封裝SUB2的連接端子750’電性連接至第二重佈線路結構550。雖然圖4中僅繪示一個子封裝SUB2與一個被動元件PD，然而，可以於第二重佈線路結構550上配置多於一個的子封裝SUB2以及多於一個的被動元件PD。
導電球210與導電片200可以提供封裝結構40中垂直方向的電性連接，以在封裝結構40中實現雙面的堆疊結構。
圖5是依據本發明一些替代實施例的封裝結構50的剖面示意圖。封裝結構50類似於如圖4所示的封裝結構40，差別在於：於第二重佈線路結構550上形成第二密封體450，以包封子封裝SUB2與被動元件PD。第二密封體450可以類似於第一密封體400，故於此不加以贅述。第二密封體450可以保護子封裝SUB2與被動元件PD，以降低水氣或可能的損壞。
圖6是依據本發明一些替代實施例的封裝結構60的剖面示意圖。封裝結構60類似於如圖3所示的封裝結構30，差別在於：於第二重佈線路結構550上配置代替晶片602與被動元件PD（如圖3所示）的晶片堆疊CS。在一些實施例中，晶片堆疊CS可以包括多個晶片604。可以藉由多條導線610使晶片堆疊CS的晶片604與第二重佈線路結構550的導電圖案554之間形成電性連接。導線610可以是金、銅或任何適宜的導電材料。第二重佈線路結構550的導電圖案554可以是包括第一層554a、第二層554b以及第三層554c的多層結構。第一層554a、第二層554b以及第三層554c可以依序互相堆疊。在一些實施例中，第一層554a可以是銅層，第二層554b可以是鎳層，且第三層554c可以是金層。然而，本發明不限於此。在一些替代實施例中，可以使用不同數量的層數或層間可以使用不同材料來形成導電圖案554。導電圖案554的多層結構被配置於提升導電圖案554與導線610之間的接合強度。
綜上所述，本發明的封裝結構採用扇出型設計，適合雙面垂直整合。舉例而言，嵌於第一密封體中的導電球與導電片提供封裝結構中垂直方向的電性連接。由於可以用更簡單及便宜的製程來形成導電球與導電片，進而封裝結構的製程複雜度與製造成本都可以顯著的下降。此外，導電球與導電片的匹配也可以省略傳統上為了形成垂直導電結構所使用的化學濕製程。且由於與耐化學性較無關，故可以更彈性的選擇用來接合黏著晶粒的材料。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、20、30、40、50、60‧‧‧封裝結構100‧‧‧第一載板105‧‧‧第二載板110‧‧‧第一黏著層115‧‧‧第二黏著層200‧‧‧導電片210‧‧‧導電球300‧‧‧晶粒302‧‧‧半導體基板304‧‧‧連接墊306‧‧‧保護層300a、210a、400a、400b、500a、500b、550a、550b‧‧‧表面306a、502a、502b、552a、552b‧‧‧開口400、440、450、450’‧‧‧密封體402‧‧‧密封材料T402、T300、T200’‧‧‧厚度500‧‧‧第一重佈線路結構502、552‧‧‧介電層504、554‧‧‧導電圖案506、556‧‧‧導通孔520、520’‧‧‧重佈線路550‧‧‧第二重佈線路結構554a‧‧‧第一層554b‧‧‧第二層554c‧‧‧第三層700‧‧‧導電端子600、600’、602、604‧‧‧晶片610‧‧‧導線610’‧‧‧導電柱750、750’‧‧‧連接端子800、802‧‧‧底膠CS‧‧‧晶片堆疊PD‧‧‧被動元件SUB1、SUB2‧‧‧子封裝
圖1A至圖1I是依據本發明一些實施例的封裝結構的製造方法的剖面示意圖。 圖2A至圖2G是依據本發明一些替代實施例的封裝結構的製造方法的剖面示意圖。 圖3是依據本發明一些替代實施例的封裝結構的剖面示意圖。 圖4是依據本發明一些替代實施例的封裝結構的剖面示意圖。 圖5是依據本發明一些替代實施例的封裝結構的剖面示意圖。 圖6是依據本發明一些替代實施例的封裝結構的剖面示意圖。
200‧‧‧導電片
210‧‧‧導電球
300‧‧‧晶粒
210a、400a、500a、500b‧‧‧表面
502a、502b‧‧‧開口
400‧‧‧密封體
500‧‧‧第一重佈線路結構
502‧‧‧介電層
504‧‧‧導電圖案
506‧‧‧導通孔

Claims (10)

  1. 一種封裝結構，包括： 第一重佈線路結構，具有第一表面以及相對於所述第一表面的第二表面； 晶粒，具有多個連接墊，且所述多個連接墊與所述第一重佈線路結構的所述第一表面電性連接； 多個導電片，與所述第一重佈線路結構的所述第一表面電性連接； 多個導電球，配置於對應的所述多個導電片上，其中所述多個導電球藉由所述多個導電片與所述第一重佈線路結構的所述第一表面電耦合；以及 第一密封體，包封所述晶粒、所述多個導電片與所述多個導電球，其中所述第一密封體暴露出每一所述多個導電球的至少一部分。
  2. 如申請專利範圍第1項所述的封裝結構，其中所述晶粒的所述多個連接墊與所述第一重佈線路結構直接接觸。
  3. 如申請專利範圍第1項所述的封裝結構，更包括： 子封裝，堆疊於所述多個導電球與所述第一密封體上，其中所述子封裝與所述多個導電球電性連接且直接接觸。
  4. 如申請專利範圍第1項所述的封裝結構，更包括： 第二重佈線路結構，位於相對於所述第一重佈線路結構的所述第一密封體上，且所述第二重佈線路結構與所述多個導電球電性連接；以及 配置於所述第二重佈線路結構上的至少一晶片、至少一子封裝、至少一被動元件或上述之組合，其中所述至少一晶片、所述至少一子封裝、所述至少一被動元件或上述之組合與所述第二重佈線路結構電性連接。
  5. 如申請專利範圍第1項所述的封裝結構，其中： 所述多個導電片位於所述第一重佈線路結構的所述第一表面上，且所述多個導電片與所述第一重佈線路結構為兩個分開的元件；或 每一所述多個導電片夾於所述第一重佈線路結構與對應的所述多個導電球之間。
  6. 一種封裝結構的製造方法，包括： 提供具有黏著層的載板； 形成多個導電片於所述黏著層上； 形成多個導電球於所述多個導電片上； 放置多個晶粒於所述黏著層上，其中每一所述多個晶粒具有多個連接墊，且所述多個連接墊嵌入所述黏著層中； 形成第一密封體，以包封所述多個晶粒、所述多個導電片與所述多個導電球，其中所述第一密封體暴露出每一所述多個導電球的至少一部分； 從所述多個晶粒、所述多個導電片以及所述第一密封體上分離所述黏著層；以及 形成第一重佈線路結構於所述多個晶粒、所述多個導電片與所述第一密封體上，其中所述第一重佈線路結構與所述多個晶粒及所述多個導電片電性連接。
  7. 如申請專利範圍第6項所述的封裝結構的製造方法，其中形成所述多個導電球於所述多個導電片上的步驟包括： 放置所述多個導電球於對應的所述多個導電片上；以及 進行回焊製程，以耦合於所述多個導電球與所述多個導電片。
  8. 如申請專利範圍第6項所述的封裝結構的製造方法，更包括： 堆疊子封裝於所述多個導電球與所述第一密封體上，其中所述子封裝與所述多個導電球電性連接且直接接觸。
  9. 如申請專利範圍第6項所述的封裝結構的製造方法，更包括： 形成第二重佈線路結構於相對於所述第一重佈線路結構的所述第一密封體上，其中所述第二重佈線路結構與所述多個導電球電性連接；以及 配置至少一晶片、至少一子封裝、至少一被動元件或上述之組合於所述第二重佈線路結構上，其中所述至少一晶片、所述至少一子封裝、所述至少一被動元件或上述之組合與所述第二重佈線路結構電性連接。
  10. 如申請專利範圍第6項所述的封裝結構的製造方法，其中形成所述第一密封體的步驟包括： 形成密封材料並完全覆蓋所述多個晶粒、所述多個導電片與所述多個導電球；以及 減少所述密封材料的厚度以形成所述第一密封體。
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