TW202002188A - Three dimensional integrated circuit (3DIC) structure - Google Patents

Abstract

Provided is a three-dimensional integrated circuit (3DIC) structure including a die stack structure, a metal circuit structure, and a protective structure. The die stack structure includes a first die and a second die face-to-face bonded together. The metal circuit structure is disposed over a back side of the second die. The protective structure is disposed within the back side of the second die and separates one of a plurality of through-substrate vias (TSVs) of the second die from the metal circuit structure.

Description

Three-dimensional integrated circuit structure

The embodiment of the invention relates to a three-dimensional integrated circuit structure.

In recent years, the semiconductor industry has experienced rapid growth due to the continuous improvement in the bulk density of various electronic components (ie, transistors, diodes, resistors, capacitors, etc.). This improvement in accumulation density comes from repeated reductions in minimum feature size to allow more smaller components to be integrated into a certain area.

Compared with previous packages, these smaller electronic components also require smaller packages with smaller areas. Exemplary types of semiconductor packages include quad flat package (QFP), pin grid array (PGA), ball grid array (BGA), flip chip (FC) , Three-dimensional integrated circuit (three dimensional integrated circuit, 3DIC), wafer level package (wafer level package, WLP) and stacked package (package on package, PoP) device. Some three-dimensional integrated circuits are prepared by placing chips on top of wafers on the semiconductor wafer level. As the length of interconnects between stacked wafers is reduced, three-dimensional integrated circuits provide higher integrated density and other advantages, such as faster speed and higher bandwidth. However, there are still many challenges to be solved for the three-dimensional integrated circuit technology.

An embodiment of the present invention provides a three-dimensional integrated circuit structure, including a die stack structure, a metal circuit structure, and a protection structure. The die stack structure includes a first die and a second die bonded together face to face. The metal circuit structure is disposed on the rear side of the second die. The protective structure is disposed in the rear side of the second die and separates one of the plurality of substrate vias and the metal circuit structure that separates the second die.

The following disclosure provides many different embodiments or examples for implementing different features of the provided goals. Specific examples of components and configurations described below are for the purpose of conveying the present disclosure in a simplified manner. Of course, these are only examples and not limiting. For example, in the following description, forming the first feature above or on the second feature may include an embodiment where the first feature and the second feature are formed in direct contact, and may also include the first feature and the second feature An additional feature may be formed between the two features so that the first feature and the second feature may not directly contact the embodiment. In addition, the present disclosure may reuse element symbols and/or letters in various examples. The repeated use of element symbols is for simplicity and clarity, and does not represent the relationship between the various embodiments and/or configurations to be discussed.

In addition, for ease of explanation, this article may use, for example, "beneath", "below", "lower", "above", "upper" "Upper" and other spatial relative terms to illustrate the relationship between one element or feature and another element or features shown in the figure. The spatially relative terms are intended to cover different orientations of elements in use or operation. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative terms used herein are interpreted accordingly.

Other features and processes can also be included. For example, a test structure may be included to illustrate the verification test of a three-dimensional (3D) package or a three-dimensional integrated circuit device. The test structure may include, for example, test pads formed in the redistribution layer or on the substrate, the test pads enable testing of 3D packages or 3DICs, use of probes and/or probe cards, and the like. Verification tests can be performed on the intermediate structure and the final structure. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that include intermediate verification of known good dies to improve yield and reduce costs.

1A to 1E are cross-sectional views of a method of forming a three-dimensional integrated circuit structure according to the first embodiment.

Referring to FIG. 1A, a die stack structure 10 is formed. Specifically, the die stack structure 10 includes a first die 100, a second die 200, and a hybrid bonding structure 250. The first die 100 and the second die 200 are mixed and joined together by a hybrid bonding structure 250. The die stack structure 10 is formed according to, for example, the following steps.

As shown in FIG. 1A, a first die 100 including a first semiconductor substrate 102, a first element layer 103, a first interconnect structure 104 and a first passivation layer 110 is provided.

In some embodiments, the semiconductor substrate 102 may include silicon or other semiconductor materials. Additionally or additionally, the first semiconductor substrate 102 may include other element semiconductor materials, such as germanium. In some embodiments, the first semiconductor substrate 102 is made of compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. In some embodiments, the first semiconductor substrate 102 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the first semiconductor substrate 102 includes an epitaxial layer. For example, the first semiconductor substrate 102 has an epitaxial layer overlying the bulk semiconductor.

In some embodiments, the first element layer 103 is formed on the first semiconductor substrate 102 in a front-end-of-line (FEOL) process. The first element layer 103 includes various elements. In some embodiments, the elements include active elements, passive elements, or a combination thereof. In some embodiments, the element may include an integrated circuit element. The element is, for example, a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse element, or other similar elements. In some embodiments, the first device layer 103 includes a gate structure, a source region and a drain region, and an isolation structure, such as a shallow trench isolation (STI) structure (not shown in the figure). In the first element layer 103, various N-type metal oxide semiconductor (NMOS) and/or P-type metal oxide semiconductor (PMOS) elements (such as transistors or memories) can be formed and interconnected to perform one or more Function. Other elements such as capacitors, resistors, diodes, photodiodes, fuses, etc. can also be formed on the first semiconductor substrate 102. The functions of the components may include memory, processor, sensor, amplifier, power distribution, input/output circuit, and the like.

Referring to FIG. 1A, a first interconnect structure 104 is formed on the first element layer 103. In detail, the first interconnect structure 104 includes a first insulating material 106 and a plurality of first metal features 108. The first metal feature 108 is formed in the first insulating material 106 and is electrically connected to the first element layer 103. A portion of the first metal feature 108 (eg, top metal features 108a and 108b) is exposed to the first insulating material 106. In some embodiments, the first insulating material 106 includes an inner-layer dielectric (ILD) layer on the first element layer 103 and at least one inter-metal dielectric (inter-metal dielectric) on the interlayer dielectric layer metal dielectric (IMD) layer. In some embodiments, the first insulating material 106 includes silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material, or a combination thereof. In some alternative embodiments, the first insulating material 106 may be a single layer or multiple layers. In some embodiments, the first metal feature 108 includes a plug and a metal wire. The plug may include contacts formed in the interlayer dielectric layer and vias formed in the intermetal dielectric layer. The contact window is formed between the first element layer 103 and the bottom metal line and connected to the first element layer 103 and the bottom metal line. The through hole is formed between two metal wires and connected to the two metal wires. The first metal feature 108 may be made of tungsten (W), copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or a combination thereof. In some alternative embodiments, a barrier layer (not shown) may be formed between the first metal feature 108 and the first insulating material 106 to prevent the material of the first metal feature 108 from migrating or diffusing to the first element layer 103. The material of the barrier layer includes, for example, tantalum, tantalum nitride, titanium, titanium nitride, cobalt-tungsten (CoW), or a combination thereof.

Referring to FIG. 1A, the first passivation layer 110 is formed on the first interconnection structure 104. The first passivation layer 110 covers the first insulating material 106 and some portions of the top metal features 108a and 108b. In some embodiments, the first passivation layer 110 includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole, PBO) or a combination thereof and formed by a suitable process such as spin coating, chemical vapor deposition, etc. After the first passivation layer 110 is formed on the first interconnect structure 104, the first die 100 is completed. As shown in FIG. 1A, the first die 100 has a front side 100a and a rear side 100b opposite to each other. Here, the front side 100a of the first die 100 faces upward, and the rear side 100b of the first die 100 faces downward. In some embodiments, the front side 100a of the first die 100 is referred to as the active surface.

Referring to FIG. 1A, a first bonding structure 114 is formed on the front side 100 a of the first die 100. In detail, the first bonding structure 114 includes a first bonding dielectric layer 116 and a plurality of first bonding metal layers 118 and 120. In some embodiments, the first bonding metal layers 118 and 120 are formed in the first bonding dielectric layer 116. The first bonding metal layer 118 includes a via plug 118a and a metal feature 118b disposed above the via plug 118a, and the first bonding metal layer 120 includes a via plug 120a and disposed above the via plug 120a Of the metal feature 120b. As shown in FIG. 1A, the via plug 118a penetrates the first passivation layer 110 and is connected to the first metal feature 108a, and the via plug 120a penetrates the first passivation layer 110 and is connected to the first metal feature 108b.

In some embodiments, the first bonding metal layers 118 and 120 may include copper, copper alloys, nickel, aluminum, tungsten, and combinations thereof. In some embodiments, the first bonding metal layers 118 and 120 may use the same material and be formed at the same time. In some other embodiments, the first bonding metal layers 118 and 120 may use different materials and be formed in sequence. The first bonding metal layers 118 and 120 can be formed by depositing conductive materials in the trenches and via openings (not shown) in the first bonding dielectric layer 116, and then by a planarization process ( For example, a chemical mechanical polishing process) removes the conductive material above the top surface of the first bonding dielectric layer 116. After the planarization process, the top surface of the first bonding dielectric layer 116 and the top surfaces of the first bonding metal layers 118 and 120 are substantially coplanar.

Referring to FIG. 1A, the second die 200 is similar to the second die 100. That is, the second die 200 includes the second semiconductor substrate 202, the second element layer 203, the second interconnection structure 204, the second insulating material 206, and the second passivation layer 210. The configuration, material and forming method of the second die 200 are similar to the configuration, material and forming method of the first die 100. Therefore, the details are omitted here. In some embodiments, the size of the second die 200 is smaller than the size of 100 of the first die. In this article, the term "size" refers to length, width, or area. For example, as shown in FIG. 1A, the length of the second die 200 is shorter than the length of the first die 100.

In some embodiments, one of the first die 100 and the second die 200 may be, for example, an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and RF chip, voltage regulator chip or memory chip. In some alternative embodiments, the first die 100 and the second die 200 may include the same function or different functions. The die stack structure 10 shown in FIG. 1A is a chip-on-wafer (CoW) structure. For example, the second die 200 may be a die, the first die 100 may be a wafer, and the die 200 is disposed on the wafer 100. However, the embodiments of the present invention are not limited to this. In other embodiments, the die stack structure 10 includes a chip-on-chip structure, a die-on-die structure, or a combination thereof.

Referring to FIG. 1A, a second bonding structure 214 is formed on the front side 200 a of the second die 200. In detail, the second bonding structure 214 includes a second bonding dielectric layer 216 and a second bonding metal layer 218. In some embodiments, the second bonding metal layer 218 is formed in the second bonding dielectric layer 216. The second bonding metal layer 218 includes a via plug 218a and a metal feature 218b. As shown in FIG. 1A, the via plug 218 a penetrates the second passivation layer 210 and is connected to the second metal feature 208 of the second interconnection structure 204. The metal feature 218b is electrically connected to the second metal feature 208 through the via plug 218a.

In some embodiments, the second bonding metal layer 218 may include copper, copper alloy, nickel, aluminum, tungsten, and combinations thereof. The second bonding metal layer 218 can be formed by depositing a conductive material in the trenches and via openings (not shown) in the second bonding dielectric layer 216, and then through a planarization process (eg, chemical Mechanical polishing process) removing the conductive material above the top surface of the second bonding dielectric layer 216. After the planarization process, the top surface of the second bonding dielectric layer 216 and the top surface of the second bonding metal layer 218 are substantially coplanar.

Referring to FIG. 1A, the second die 200 is further upside down and mounted on the first die 100. In detail, the first die 100 and the second die 200 are face-to-face bonded together by the first bonding structure 114 and the second bonding structure 214. In some embodiments, before bonding the second die 200 to the first die 100, the first bonding structure 114 and the second bonding structure 214 are aligned so that the second bonding metal layer 218 can be bonded to the first bonding The metal layer 118, and the first bonding dielectric layer 116 may be bonded to the second bonding dielectric layer 216. In some embodiments, the alignment of the first bonding structure 114 and the second bonding structure 214 may be achieved by using an optical sensing method. After the alignment is achieved, the first bonding structure 114 and the second bonding structure 214 are bonded together by hybrid bonding to form a hybrid bonding structure 250.

The first bonding structure 114 and the second bonding structure 214 are mixed and bonded together by applying pressure and heat. It should be noted that the hybrid bonding method is related to at least two types of bonding methods, including a metal-to-metal bonding method and a non-metal-to-metal bonding method (for example, a dielectric-to-dielectric bonding method or a fusion bonding method). As shown in FIG. 1A, the hybrid bonding structure 250 includes a first bonding metal layer 118 and a second bonding metal layer 218 that are bonded together by a metal-to-metal bonding method and a first bonding metal layer that is bonded together by a non-metal-to-metal bonding method. A bonding dielectric layer 116 and a second bonding dielectric layer 216. However, the embodiments of the present invention are not limited to this. In other embodiments, the first bonding structure 114 and the second bonding structure 214 may be bonded together by other bonding methods (for example, fusion bonding).

In addition, as shown in FIG. 1A, the second die 200 further includes a plurality of through-substrate vias (TSV) 205. In some embodiments, a substrate via 205 is formed in the second semiconductor substrate 202 to be electrically connected to the second interconnect structure 204. In some embodiments, one of the substrate through holes 205 includes a conductive via and a liner (not shown) surrounding the sidewalls and bottom surface of the conductive via. The conductive via may include copper, copper alloy, aluminum, aluminum alloy, Ta, TaN, Ti, TiN, CoW, or a combination thereof. The liner layer may include a dielectric material, such as silicon oxide. In some embodiments, the substrate via 205 does not penetrate the second semiconductor substrate 202 at the beginning, and the bottom surface of the substrate via 205 is still covered by the second semiconductor substrate 202. In a subsequent process, a thinning process is performed on the rear surface 202b of the second semiconductor substrate 202 to expose the top surface 205s of the substrate via 205, and the substrate via 205 can be connected to other devices. In some embodiments, the thinning process may include a grinding process or a chemical mechanical polishing (CMP) process.

After the thinning process is performed, the rear surface 202b of the second semiconductor substrate 202 is lower than the top surface 205s of the substrate via 205 to ensure that the substrate via 205 can be connected to the metal circuit structure 400 to be formed (as shown in FIG. 1E). After exposing the top surface 205s of the substrate via 205, a nitride layer 220 (eg, a silicon nitride layer) is formed over the second die 200. The nitride layer 220 conformally covers the surface of the substrate perforation 205 exposed by the second semiconductor substrate 202, the rear surface 202b of the second semiconductor substrate 202, the sidewalls of the second die 200, and those not bonded to the second bonding structure 214 The top surface of the first joint structure 114. An oxide layer 222 (for example, a silicon oxide layer) is conformally formed on the nitride layer 220. A nitride layer 224 (for example, a silicon nitride layer) is conformally formed on the oxide layer 222. A dielectric layer 226 (for example, a gap-fill dielectric layer) is formed on the first die 100 and encapsulates the second die 200. That is, the dielectric layer 226 covers the sidewall of the second die 200 and the bottom surface 202a of the second semiconductor substrate 202. In some embodiments, the dielectric layer 226 may include oxide (such as silicon oxide), nitride (such as silicon nitride), oxynitride (such as silicon oxynitride), molding compound, molding underfill (molding) underfill), resin (such as epoxy resin), their combination, etc.

Then, a planarization process (or a first planarization process) is performed. In some embodiments, the planarization process is a chemical mechanical polishing process. After the planarization process, the excess dielectric layer 226, the excess nitride layer 224, the excess oxide layer 222, and the excess nitride layer 220 are removed to expose the top surface 205s of the substrate via 205 and the remaining oxide The top surface 222t of layer 222 is shown in FIG. 1A. The remaining oxide layer 222 laterally encapsulates a portion of the base via 205. The remaining dielectric layer 226 laterally encapsulates the second die 200 to separate the second die 200 from another die bonded to the first die 100 (not shown). After the planarization process is performed, the die stack structure 10 is completed. In this case, the top surface 222t of the remaining oxide layer 222 may be referred to as the back side 200b of the second die 200. After the planarization process is performed, the back side 200b of the second die 200, the top surface 205s of the base via 205, and the top surface 226t of the remaining dielectric layer 226 are at substantially the same level. In this article, when elements are described as "at substantially the same level", these elements are formed in the same layer at substantially the same height, or embedded in the same layer The same location. In some embodiments, elements at substantially the same level are formed using the same material and using the same process steps. In some embodiments, the tops of the elements at substantially the same level are substantially coplanar. For example, as shown in FIG. 1A, the back side 200b of the second die 200, the top surface 205s of the base via 205, and the top surface 226t of the remaining dielectric layer 226 are substantially coplanar.

It should be noted that after a planarization process (or referred to as a first planarization process) or a thinning process, a groove R1 is formed in the back side 200b of the second die 200. The groove R1 may be various defects, such as cracks, sharp morphology, bulge, and the like. The groove R1 is formed because some undesired particles may fall on the surface to be polished, and then performing a planarization process or a thinning process may damage the back side 200b of the second die 200. As shown in FIG. 1A, the groove R1 extends in the direction D1 from the rear side 200 b of the second die 200 toward the hybrid bonding structure 250. The groove R1 recesses the base through hole 205b of the second die 200 so that the top surface 205s' of the base through hole 205b is lower than the top surface 205s of the base through hole 205a. In addition, the top surface 205s' of the base perforation 205b has an uneven surface or a sharp shape. In contrast, the top surface 205s of the substrate perforation 205a that is not damaged by defects has a smooth surface or a flat surface.

Referring to FIG. 1B, after the planarization process is performed, a conformal layer 305 is formed on the die stack structure 10. The conformal layer 305 conformally covers the back side 200b of the second die 200, the top surface 205s of the base via 205, and the top surface 226t of the remaining dielectric layer 226. In addition, the conformal layer 305 also conformally and completely covers the surface of the groove R1 (or the top surface 205s' of the substrate perforation 205b) to prevent plasma etching arcing during subsequent patterning ). In some embodiments, when the groove R1 is detected, a conformal layer 305 may be formed to cover the surface of the groove R1. In some alternative embodiments, when the groove R1 is too slight to be detected, a conformal layer 305 may still be formed to cover the surface of the groove R1. The conformal layer 305 is formed by, for example, an atomic layer deposition (ALD) process. In some embodiments, the conformal layer 305 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In alternative embodiments, the conformal layer 305 may be a single-layer structure, a double-layer structure, or a multi-layer structure. In other embodiments, the thickness of the conformal layer 305 is 500 Å to 3500 Å. Herein, the so-called conformal layer can be regarded as a layer with a uniform thickness, and the layer has a thickness difference of less than 50 Å (for example, 30 Å~50 Å).

In addition, in some embodiments, before the conformal layer 305 is formed, a nitride layer 304 (eg, a silicon nitride layer) is formed on the second die 200. In some embodiments, the nitride layer 304 is formed by a suitable deposition process (eg, chemical vapor deposition process or atomic layer deposition process), and the thickness of the nitride layer 304 is 300 Å to 1000 Å. In alternative embodiments, the thickness of the conformal layer 305 is greater than the thickness of the nitride layer 304. In other embodiments, the nitride layer 304 and the conformal layer 305 include the same material or different materials.

1C, a chemical vapor deposition process is performed to form a filling layer 306 on the conformal layer 305. In some embodiments, the filling layer 306 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In other embodiments, the thickness of the filling layer 306 is 5KÅ to 30KÅ. Since the conformal layer 305 has better step coverage than the filling layer 306, the conformal layer 305 can completely cover the surface of the groove R1 having a sharp shape. In some embodiments, the conformal layer 305 and the filling layer 306 have the same material or different materials. In some alternative embodiments, the thickness of the filling layer 306 is greater than or equal to the thickness of the conformal layer 305. However, the embodiments of the present invention are not limited to this.

After the filling layer 306 is formed, a mask pattern 307 is formed on the filling layer 306. In some embodiments, the mask pattern 307 includes photoresist and is formed by a suitable process (for example, spin coating and lithography process). After the mask pattern 307 is formed, an etching process is performed by using the mask pattern 307 as an etching mask to remove the filling layer 306, the conformal layer 305, the nitride layer 304, the dielectric layer 226, and the nitride layer 224 , Some portions of the oxide layer 222 and the nitride layer 220, thereby forming the opening 308. As shown in FIG. 1C, the opening 308 exposes the first bonding metal layer 120. After the opening 308 is formed, the mask pattern 307 is removed.

1C and 1D, a conductive material (not shown) is formed to fill in the opening 308, and the conductive material is extended to cover the filling layer 306. A planarization process (or referred to as a second planarization process) is performed to remove portions of the conductive material, the filling layer 306, the conformal layer 305, and the nitride layer 304 and expose the top surface 205s of the substrate through hole 205. After the planarization process, a through dielectric via (TDV) 310 is formed in the dielectric layer 226, and the protective structure 300 is formed in the back side 200b of the second die 200, as shown in FIG. 1D. A dielectric layer through hole 310 is formed in the dielectric layer 226 to be electrically connected to the first bonding metal layer 120 and the metal circuit structure 400 to be formed (as shown in FIG. 1E ).

Referring to FIG. 1D, in some embodiments, the protection structure 300 includes a nitride layer 304, a conformal layer 305, and a filling layer 306 filled in the groove R1. The conformal layer 305 is formed between the nitride layer 304 and the filling layer 306. The protection structure 300 shown in FIG. 1D is a three-layer structure, however, the embodiments of the present invention are not limited thereto. In other embodiments, the protective structure 300 may include a single-layer structure, a double-layer structure, or a multi-layer (ie, more than three-layer) structure. For example, the protective structure 300 may be made of only the conformal layer 305, or only the nitride layer 304 and the conformal layer 305, or only the conformal layer 305 and the filling layer 306. After the planarization process is performed, the top surface 300t of the protection structure 300, the back side 200b of the second die 200, the top surface 205s of the substrate through hole 205, the top surface 226t of the dielectric layer 226 and the top surface of the dielectric layer through hole 310 310t is substantially coplanar. Although only one dielectric layer via 310 is shown in FIG. 1D, more than one dielectric layer via 310 may be formed.

Referring to FIG. 1E, a back-end-of-line (BEOL) process forms a metal circuit structure 400 on the back side 200 b of the second die 200. After the metal circuit structure 400 is formed, the three-dimensional integrated circuit structure 1 is formed. In detail, a dielectric layer 402 is formed on the back side 200b of the second die 200 and the top surface 226t of the dielectric layer 226. The metal feature 404 is formed in the dielectric layer 402 through a patterning process and a suitable deposition process (eg, a plating process). The metal feature 404 is electrically connected to the dielectric layer via 310 and the substrate via 205a not covered by the protective structure 300. In some embodiments, the dielectric layer 402 includes silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material, or a combination thereof. In some alternative embodiments, the dielectric layer 402 may be a single layer or multiple layers. In some embodiments, the metal features 404 include plugs and metal wires. The plug is formed between two metal wires and connected to the two metal wires. The metal feature 404 may be made of tungsten (W), copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or a combination thereof.

After forming the metal feature 404, a passivation layer 406 is formed to cover the dielectric layer 402 and expose a portion of the metal feature 404. In some embodiments, the passivation layer 406 includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), or a combination thereof and by It is formed by a suitable process (such as spin coating, chemical vapor deposition, etc.). A bonding pad 408 is formed over the passivation layer 406, and the bonding pad 408 extends to cover the metal feature 404. The material of the bonding pad 408 is different from the material of the first metal feature 404. In some embodiments, the material of the bonding pad 408 is softer than the material of the first metal feature 404. In some embodiments, the bonding pad 408 includes a metal material, such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof. The bonding pad 408 can be formed by depositing a metal material layer by a suitable process (eg, electrochemical plating process, chemical vapor deposition, atomic layer deposition (ALD), physical vapor deposition, etc.), and then patterning Metallized material layer.

It should be noted that the protection structure 300 filled in the groove R1 is disposed between the base through hole 205b of the second die 200 and the metal feature 404 of the metal circuit structure 400 to separate or electrically isolate the base through hole 205b of the second die 200 Metal feature 404 with metal circuit structure 400. As shown in FIG. 1E, the protection structure 300 completely covers the substrate through holes 205b of the second die 200, therefore, during the patterning process of the metal circuit structure 400, the substrate through holes 205b with a sharp shape will not cause plasma etching arc discharge . That is, the reliability and yield of the three-dimensional integrated circuit structure 1 are improved accordingly. On the other hand, although the substrate via 205b is electrically isolated from the metal circuit structure 400, the signal of the second device layer 203 below the substrate via 205b can still be transmitted to the metal circuit structure 400 through other substrate vias (eg, substrate via 205a) . Although only two substrate perforations 205a and 205b are shown in FIG. 1E, more than two substrate perforations 205a and 205b may be formed. That is, more than one protective structure 300 completely covers more than one base perforation 205b.

2 is a cross-sectional view of a three-dimensional integrated circuit structure according to a second embodiment.

Referring to FIG. 2, the three-dimensional integrated circuit structure 2 of the second embodiment is similar to the three-dimensional integrated circuit structure 1 of the first embodiment shown in FIG. 1E. The difference between them is that the number of the protection structures 300 of the three-dimensional integrated circuit structure 2 is plural. The protection structure 300 includes protection structures 301 and 302. As shown in FIG. 2, the protective structures 301 and 302 are formed on the second semiconductor substrate 202 and both extend in the direction D1 from the rear side 200 b of the second die 200 toward the hybrid bonding structure 250. The protection structure 301 covers the base through holes 205b of the second die 200, while the protection structure 302 does not cover any base through holes 205 (including the base through holes 205a and 205b) of the second die 200. Specifically, the groove R2 obtained by the planarization process or the thinning process may be formed in a region where no substrate through hole 205 is formed. A conformal layer 305 is deposited in both grooves R1 and R2 to form protective structures 301 and 302 at the same time. Although FIG. 1E only shows two protective structures 301 and 302, more than two protective structures 301 and 302 may be formed.

3 is a cross-sectional view of a three-dimensional integrated circuit structure according to a third embodiment.

3, the three-dimensional integrated circuit structure 3 of the third embodiment is similar to the three-dimensional integrated circuit structure 1 of the first embodiment shown in FIG. 1E. The difference between them is that the three-dimensional integrated circuit structure 3 includes a protective structure 303 extending from the rear side 200b of the second die 200 into the hybrid bonding structure 250. After the planarization process or the thinning process, the groove R3 is formed. The groove R3 is deep and has a sharp shape, so the conformal layer 305 can completely cover the uneven and sharp surfaces of the groove R3 and the groove R1 to prevent plasma etching during the patterning process of the metal circuit structure 400 Arc discharge. In some embodiments, the protective structure 303 extends from the back side 200 b of the second die 200 to the interface 15 between the first bonding structure 114 of the first die 100 and the second bonding structure 214 of the second die 200 .

4 is a cross-sectional view of a package according to some embodiments.

Referring to FIG. 4, the three-dimensional integrated circuit structure 4 is mounted on the dielectric layer 11 through the adhesive layer 21. In some embodiments, the three-dimensional integrated circuit structure 4 may be one of the three-dimensional integrated circuit structures 1, 2 and 3 described above. The three-dimensional integrated circuit structure 4 includes a plurality of second dies 201 a and 201 b arranged in parallel on the first die 100. The second die 201a and 201b are joined face-to-face with the first die 100. The number of second crystal grains 201a and 201b is not limited in this disclosure.

In this embodiment, the three-dimensional integrated circuit structure 4 further includes a plurality of connectors 18 and a passivation layer 19. The connector 18 is formed on the bonding pad 408 not covered by the passivation layer 410 and is electrically connected to the bonding pad 408 not covered by the passivation layer 410. For the sake of clarity, other elements under the bonding pad 408 are not shown in FIG. 4, such as the dielectric layer 402 and the metal feature 404 shown in FIG. 1E. The connector 18 includes solder bumps, gold bumps, copper bumps, copper pillars, copper pillars, and the like. The passivation layer 19 is formed on the passivation layer 410 and beside the connector 18 to cover the sidewall of the connector 18.

Referring to FIG. 4, an insulating package 22 is formed beside the three-dimensional integrated circuit structure 4 to encapsulate the three-dimensional integrated circuit structure 4. A plurality of conductive pillars 14 are formed in the insulating envelope 22, and the plurality of conductive pillars 14 surround the three-dimensional integrated circuit structure 4. A redistribution layer (RDL) structure 23 is formed on the three-dimensional integrated circuit structure 4 and the conductive pillar 14, and the redistribution layer structure 23 is electrically connected to the three-dimensional integrated circuit structure 4 and the conductive pillar 14. In some embodiments, the redistribution layer structure 23 includes a plurality of polymer layers PM1, PM2, PM3, and PM4 and a plurality of redistribution layers RDL1, RDL2, RDL3, and RDL4 that are alternately stacked. The number of polymer layers or redistribution layers is not limited by this disclosure.

In other words, the redistribution layer RDL1 penetrates the polymer layer PM1 and is electrically connected to the connector 18 and the conductive pillar 14 of the three-dimensional integrated circuit structure 4. The rewiring layer RDL2 penetrates the polymer layer PM2 and is electrically connected to the rewiring layer RDL1. The rewiring layer RDL3 penetrates the polymer layer PM3 and is electrically connected to the rewiring layer RDL2. The rewiring layer RDL4 penetrates the polymer layer PM4 and is electrically connected to the rewiring layer RDL3. In some embodiments, each of the polymer layers PM1, PM2, PM3, and PM4 includes a photosensitive material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene ( PCB), their combination, etc. In some embodiments, each of the redistribution layers RLD1, RDL2, RDL3, and RDL4 includes a conductive material. The conductive material includes metals (such as copper, nickel, titanium, combinations thereof, etc.), and is formed by an electroplating process. In some embodiments, the redistribution layers RDL1, RDL2, RDL3, and RDL4 respectively include a seed layer (not shown in the figure) and a metal layer formed on the seed layer (not shown in the figure). The seed layer may be a metal seed layer, such as a copper seed layer. In some embodiments, the seed layer includes a first metal layer (eg, a titanium layer) and a second metal layer (eg, a copper layer) over the first metal layer. The metal layer may be copper or other suitable metals. In some embodiments, the redistribution layers RDL1, RDL2, RDL3, and RDL4 include multiple vias and multiple traces connected to each other, respectively. The vias are connected to traces, and the traces are respectively located on the polymer layers PM1, PM2, PM3, and PM4, and extend on the top surfaces of the polymer layers PM1, PM2, PM3, and PM4, respectively.

In some embodiments, the topmost redistribution layer RDL4 includes RDL4a and RDL4b. The redistribution layer RDL4a is also referred to as an under-ball metallurgy (UBM) layer for ball mounting. The redistribution layer RDL4b may be a micro-bump for connecting to an integrated passive device (IPD) 26 formed in a subsequent process.

Then, a plurality of connectors 24 are formed over the rewiring layer RDL4a of the rewiring layer structure 23, and the plurality of connectors 24 are electrically connected to the rewiring layer RDL4a of the rewiring layer structure 23. In some embodiments, the connector 24 is made of a conductive material with low resistivity (such as Sn, Pb, Ag, Cu, Ni, Bi, or their alloys), and by a suitable manufacturing process (such as evaporation, plating Coating, ball drop or screen printing). The integrated passive element 26 is formed on the rewiring layer RDL4b of the rewiring layer structure 23 and is electrically connected to the rewiring layer RDL4b of the rewiring layer structure 23 by solder bumps 28. The integrated passive element 26 may be a capacitor, resistor, inductor, etc., or a combination thereof. The number of integrated passive elements 26 is not limited to the number shown in FIG. 4 but can be adjusted according to the design of the product. The underfill layer 27 is formed between the integrated passive device 26 and the polymer layer PM4, and surrounds and covers the exposed RDL4b, the solder bump 28, and the bottom surface of the integrated passive device 26.

As shown in FIG. 4, the dielectric layer 11 is then patterned so that the bottom surface of the conductive pillar 14 is exposed by the dielectric layer 11. After the conductive terminals 30 are formed on the bottom surfaces of the conductive pillars 14, respectively, the integrated fan-out package P1 with double-sided terminals is completed. Then another package P2 is provided. In some embodiments, the package P2 is, for example, a memory device. The package P2 is stacked on the integrated fan-out package P1 and electrically connected to the integrated fan-out package P1 through the conductive terminals 30 to form a stacked package (PoP) structure.

According to some embodiments, a three-dimensional integrated circuit (3DIC) structure includes a die stack structure, a metal circuit structure, and a first protection structure. The first die has a front side and a back side, and the second die has a front side and a back side. The front side of the first die is bonded to the front side of the second die. The second die includes a plurality of base vias (TSV). The metal circuit structure is provided on the rear side of the second die. The protection structure is disposed in the rear side of the second die and separates one of the plurality of substrate vias from the metal circuit structure.

In some embodiments, the top surface of the first protection structure is substantially coplanar with the back side of the second die.

In some embodiments, the first protective structure includes a conformal layer or a composite structure. The composite structure includes a conformal layer and a filler layer disposed above the conformal layer.

In some embodiments, the conformal layer and the filling layer are formed of different materials.

In some embodiments, the die stack structure further includes a hybrid bonding structure disposed between the first die and the second die.

In some embodiments, the three-dimensional integrated circuit structure further includes a second protection structure disposed in the back side of the second die, wherein the first protection structure directly contacts the plurality of substrate perforations One of the two, and the second protection structure is spaced apart from the plurality of substrate perforations.

In some embodiments, the first protective structure extends from the rear side of the second die into the hybrid junction structure.

In some embodiments, the other of the plurality of substrate vias is electrically connected to the metal circuit structure, and the top surface of the one of the plurality of substrate vias of the second die is low The top surface of the other one of the plurality of substrate perforations of the second die.

In some embodiments, the three-dimensional integrated circuit structure further includes: a dielectric layer and a dielectric layer via (TDV). The dielectric layer laterally encapsulates the second die. The dielectric layer is perforated in the dielectric layer and electrically connected to the first die and the metal circuit structure.

In some embodiments, the top surface of the dielectric layer, the top surface of the perforated dielectric layer, the top surface of the first protection structure, and the back side of the second die are substantially Coplanar.

In some embodiments, the die stack structure includes a wafer-on-wafer (CoW) structure, a wafer-on-wafer structure, a die-on-die structure, or a combination thereof.

According to some embodiments, a method of manufacturing a three-dimensional integrated circuit structure includes the following steps. A grain stack structure including a first grain and a second grain bonded together face to face is formed. A first planarization process is performed to expose a plurality of substrate vias (TSVs) of the second die on the back side of the second die. The second die has a groove extending into one of the plurality of substrate perforations of the second die. The protective structure is filled into the first groove in the form of a conformal layer. A metal circuit structure is formed on the rear side of the second die to be electrically connected to the die stack structure through another one of the plurality of substrate vias.

In some embodiments, the filling the protection structure into the first groove includes performing an atomic layer deposition (ALD) process to form the common on the rear side of the second grain A conformal layer, wherein the conformal layer completely covers the surface of the first groove; performing a chemical vapor deposition (CVD) process to form a filling layer above the conformal layer; and performing a second planarization process, To expose the other one of the plurality of substrate perforations of the second die.

In some embodiments, the forming the die stack structure includes: providing the first die and the second die; and forming between the first die and the second die A hybrid bonding structure to bond the first die and the second die.

In some embodiments, after performing the first planarization process, the back side of the second die includes a second groove, the first groove and the second groove The rear side of the second die extends toward the hybrid bonding structure, and the second groove is spaced apart from the plurality of substrate perforations of the second die.

In some embodiments, after performing the first planarization process, the first groove extends from the rear side of the second die into the hybrid junction structure.

In some embodiments, after the first planarization process is performed, the top surface of the one of the plurality of substrate vias of the second die is lower than that of the second die The top surface of the other one of the plurality of substrate perforations.

In some embodiments, after the second planarization process is performed, the top surface of the protection structure and the back side of the second die are substantially coplanar.

According to some embodiments, a package includes a three-dimensional integrated circuit structure, an insulating encapsulation body, a redistribution layer (RDL) structure, and multiple connectors. The three-dimensional integrated circuit structure includes a die stack structure, a metal circuit structure, and a protection structure between the die stack structure and the metal circuit structure. The metal circuit structure is electrically connected to the die stack structure through one of a plurality of substrate vias (TSVs) of the die stack structure. The protection structure separates and electrically isolates the other of the substrate vias of the die stack structure from the metal circuit structure. The insulating encapsulation encapsulates the three-dimensional integrated circuit structure laterally. The redistribution layer structure is provided on the three-dimensional integrated circuit structure and the insulating package. The plurality of connectors are provided on the three-dimensional integrated circuit structure and electrically connected to the three-dimensional integrated circuit structure through the redistribution layer structure.

In some embodiments, the die stack structure includes a first die and a plurality of second die arranged in parallel above the first die.

The above summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to perform the same purposes and/or achieve the implementations as described in the embodiments described herein. Examples have the same advantages. Those skilled in the art should also realize that these equivalent constructions do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and alterations to them without departing from the spirit and scope of the present invention.

1, 2, 3, 4‧‧‧‧Three-dimensional integrated circuit structure 10‧‧‧ die stacking structure 11,226,402‧‧‧‧dielectric layer 14‧‧‧conducting column 15‧‧‧interface 18‧‧‧ connection Parts 19, 410, 406‧‧‧ Passivation layer 21‧‧‧ Adhesive layer 22‧‧‧‧Insulation encapsulant 23‧‧‧Rewiring layer structure 24‧‧‧Connector 26‧‧‧ Integrated passive element 27‧‧ ‧Bottom filling adhesive layer 28‧‧‧Solder bump 30‧‧‧Conductive terminal 100‧‧‧First die 100a‧‧‧Front side 100b‧Back side 102‧‧‧First semiconductor substrate 103‧‧‧ One element layer 104‧‧‧ First interconnect structure 106‧‧‧ First insulating material 108‧‧‧ First metal feature 108a, 108b‧‧‧ Top metal feature 110‧‧‧ First passivation layer 114‧‧‧ A bonding structure 116‧‧‧ first bonding dielectric layer 118, 120‧‧‧ first bonding metal layer 118a, 120a, 218a‧‧‧ through hole plug 118b, 120b, 218b, 404‧‧‧ metal feature 200, 201a, 201a ‧‧‧ second die 200a ‧‧‧ front side of second die 200b ‧‧‧ rear side of second die 202 ‧‧‧ second semiconductor substrate 202b ‧‧‧ rear surface 203 Second element layer 204‧‧‧Second interconnect structure 205, 205a, 205b ‧‧‧ base perforation 205s, 205s', 222t, 226t, 300t, 310t ‧‧‧ top surface 208‧‧‧ second metal feature 210‧‧ ‧Second passivation layer 214‧‧‧Second junction structure 216‧‧‧Second junction dielectric layer 218‧‧‧‧Second junction metal layer 220, 224, 304‧‧‧‧Nitride layer 222‧‧‧ Oxide layer 250‧‧‧ Hybrid junction structure 300, 301, 302, 303‧‧‧ Protective structure 305‧‧‧ Conformal layer 306‧‧‧ Fill layer 307‧‧‧ Cover pattern 308‧‧‧ Opening 310‧‧‧ Dielectric Layer perforation 400 ‧‧‧Metal circuit structure 408‧‧‧ Bonding pad D1‧‧‧ Direction P1‧‧‧Integrated fan-out package P2‧‧‧Package PM1, PM2, PM3, PM4 , R2‧‧‧Rough RDL1, RDL2, RDL3, RDL4, RDL4a, RDL4b‧‧‧‧ Redistribution layer

Reading the following detailed description in conjunction with the accompanying drawings will best understand the various aspects of the present invention. It should be noted that according to standard practices in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features can be arbitrarily increased or decreased. 1A to 1E are cross-sectional views of a method of forming a three-dimensional integrated circuit (3DIC) structure according to the first embodiment. 2 is a cross-sectional view of a three-dimensional integrated circuit structure according to a second embodiment. 3 is a cross-sectional view of a three-dimensional integrated circuit structure according to a third embodiment. 4 is a cross-sectional view of a package according to some embodiments.

1‧‧‧Three-dimensional integrated circuit structure

10‧‧‧ Die stack structure

100‧‧‧First grain

114‧‧‧The first joint structure

200‧‧‧Second grain

200b‧‧‧ Rear side of the second die

205, 205a, 205b

214‧‧‧Second joint structure

226, 402‧‧‧ dielectric layer

226t‧‧‧Top surface

250‧‧‧ Hybrid joint structure

300‧‧‧Protection structure

310‧‧‧Perforation of dielectric layer

400‧‧‧Metal circuit structure

404‧‧‧Metal features

406‧‧‧ Passivation layer

408‧‧‧joint pad

R1‧‧‧groove

Claims (1)

A three-dimensional integrated circuit structure includes: a die stacking structure including a first die and a second die, the first die has a front side and a back side, and the second die has a front side and a back side, so The front side of the first die is bonded to the front side of the second die, the second die includes a plurality of base perforations; a metal circuit structure is disposed behind the second die On the side; and a first protective structure disposed in the rear side of the second die and separating one of the plurality of substrate vias of the second die from the metal circuit structure.

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