CN112151529A

CN112151529A - Semiconductor package

Info

Publication number: CN112151529A
Application number: CN202010113698.3A
Authority: CN
Inventors: 陈明发; 吴念芳; 叶松峯; 刘醇鸿; 史朝文
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-06-27
Filing date: 2020-02-24
Publication date: 2020-12-29

Abstract

Embodiments of the invention disclose semiconductor packages and methods of forming the same. One of the semiconductor packages includes a first die, a second die, a via, and a dielectric encapsulant. The second die is bonded to the first die. The through-hole is disposed beside the second die and electrically connected to the first die. The bore includes a stepped sidewall. The dielectric encapsulation body encapsulates the second die and the through hole.

Description

Semiconductor package

Technical Field

Embodiments of the present invention relate to a semiconductor package.

Background

In recent years, the semiconductor industry has experienced rapid growth due to the continued increase in integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density is due to the continuous reduction in minimum feature size (minimum feature size), which enables more components to be integrated in a given area.

These smaller electronic components also require smaller packages that occupy less area than previous packages. Examples of the package type of the semiconductor include a Quad Flat Package (QFP), a Pin Grid Array (PGA), a Ball Grid Array (BGA), a Flip Chip (FC), a three-dimensional integrated circuit (3 DIC), a Wafer Level Package (WLP), and a package on package (PoP) device. Some 3 DICs are fabricated by placing a chip on top of a chip on the semiconductor wafer level. The 3DIC provides increased integration density and other advantages, such as faster speed and higher bandwidth, due to the reduced length of the interconnects between the stacked chips. However, there are still many challenges associated with 3 DIC.

Disclosure of Invention

A semiconductor package of an embodiment of the invention includes a first die, a second die, a via, and a dielectric encapsulant. The second die is bonded to the first die. The perforation is disposed alongside the second die and electrically connected to the first die. The bore includes a stepped sidewall. The dielectric encapsulant encapsulates the second die and the through-hole.

A semiconductor package of an embodiment of the invention includes a first die, a plurality of second dies, a via, a first dielectric layer, and a second dielectric layer. The second die is bonded to the first die. The perforations are disposed between the second dies and electrically connected to the first dies. The via includes a first portion and a second portion between the first portion and the first die. The first dielectric layer encapsulates the first portion. The second dielectric layer is different from the first dielectric layer and encapsulates the second die, the second portion of the via, and the first dielectric layer.

A method of forming a semiconductor package of an embodiment of the present invention includes the following steps. A first die and a plurality of second dies bonded to the first die are provided. A first dielectric layer is formed over the first die to cover the plurality of second dies. A first opening is formed in the first dielectric layer between the second die. A perforation is formed. The perforation is partially disposed in the first opening and partially protrudes from the first opening. A first portion of the perforations protruding from the first opening has a first width, and a second portion of the perforations located in the first opening has a second width different from the first width. A second dielectric layer is formed on the sidewalls of the second die between the through-hole and the first dielectric layer.

Drawings

Fig. 1 is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 2 is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 3A is a top view of a semiconductor package according to some embodiments.

Fig. 3B is a sectional view taken along line I-I' of fig. 3A.

Fig. 4 is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 5 is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 6 is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 7 is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 8 is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 9 is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 10A is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 10B is a simplified view of a first via and a second via in the semiconductor package of fig. 10A.

Fig. 11A is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 11B is a simplified view of an inductor in the semiconductor package of fig. 11A.

Fig. 12 is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 13 is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 14A-14E are cross-sectional views of various intermediate structures during an exemplary method of forming a semiconductor package according to some embodiments.

Fig. 15A-15F are cross-sectional views of various intermediate structures during an exemplary method of forming a semiconductor package according to some embodiments.

Fig. 16 is a cross-sectional view of a semiconductor package according to some embodiments.

Fig. 17 is a cross-sectional view of a semiconductor package according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to convey the disclosure in a simplified manner. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a second feature over or on a first feature may include embodiments in which the second feature is formed in direct contact with the first feature, and may also include embodiments in which additional features may be formed between the second feature and the first feature, such that the second feature may not be in direct contact with the first feature. Additionally, the same reference numbers and/or letters may be used in various examples of the disclosure to refer to the same or similar components. Such reuse of reference numbers is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below … (beneath)", "below … (below)", "lower (lower)", "above … (on)", "above … (over)", "above … (overlapping)", "above … (above)", "upper (upper)" may be used herein to facilitate the description of one element or feature in relation to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have additional orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

Referring to fig. 1, a first die 100 is provided. The first die 100 may be, for example, an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency (radio frequency) chip, a voltage regulator chip, or a memory chip. In some embodiments, the first die 100 may include active components or passive components. In some embodiments, the first die 100 includes a first semiconductor substrate 102, a first interconnect structure 104, and a first connection structure 110.

The first semiconductor substrate 102 includes an elemental semiconductor (e.g., silicon, germanium) and/or a compound semiconductor (e.g., silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide). In some embodiments, the first semiconductor substrate 102 comprises a silicon-containing material. The first semiconductor substrate 102 is, for example, a silicon-on-insulator (SOI) substrate or a silicon substrate. In various embodiments, the first semiconductor substrate 102 may take the form of a planar substrate, a substrate with multiple fins, a nanowire, or other forms known to those of ordinary skill in the art. The first semiconductor substrate 102 may be a P-type substrate or an N-type substrate and may have doped regions therein, depending on design requirements. The doped regions may be configured for either N-type devices or P-type devices. In some embodiments, the first semiconductor substrate 102 may have through substrate vias therein according to process requirements.

The first semiconductor substrate 102 comprises an isolation structure defining at least one active area and at least one first device 103 is disposed on/in the active area. The first device 103 includes one or more functional devices. In some embodiments, the functional device includes active components, passive components, or a combination thereof. In some embodiments, the functional device may comprise an integrated circuit device. Such as transistors, capacitors, resistors, diodes, photodiodes, fuse devices, and/or other similar devices. In some embodiments, the first device 103 includes a gate dielectric layer, a gate electrode, source/drain regions, spacers, and the like. In some embodiments, the first die 100 is also referred to as a "first device die".

The first interconnect structure 104 is disposed over a first side (e.g., front side) of the first semiconductor substrate 102. Specifically, a first interconnect structure 104 is disposed over the first device 103 and electrically connected to the first device 103. In some embodiments, the first interconnect structure 104 includes at least one first insulating layer 106 and a plurality of first metal features 108. The first metal features 108 are disposed in the first insulating layer 106 and electrically connected to each other. A portion of the first metal feature 108 (e.g., a first top metal feature) is exposed by the first insulating layer 106. In some embodiments, the first insulating layer 106 includes an inter-layer dielectric (ILD) layer on the first semiconductor substrate 102 and at least one inter-metal dielectric (IMD) layer on the ILD layer. In some embodiments, the first insulating layer 106 includes silicon oxide, silicon oxynitride, silicon nitride, benzocyclobutene (BCB) polymer, Polyimide (PI), Polybenzoxazole (PBO), or a combination thereof, and is formed by a suitable process such as spin-on coating (spin-on coating), Chemical Vapor Deposition (CVD), or the like. The first insulating layer 106 may be a single-layer structure or a multi-layer structure. In some embodiments, the first metal feature 108 includes a metal via and a metal line. The via hole may include a contact formed in the interlayer dielectric layer and a via hole (via) formed in the inter-metal dielectric layer. The contacts are formed between and in contact with the bottom metal lines and the underlying first device 103. The via is formed between and in contact with two metal lines. The first metal feature 108 may include tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, or a combination thereof. In some embodiments, a barrier layer may be disposed between each first metal feature 108 and the first insulating layer 106 to prevent material of the first metal feature 108 from migrating to the underlying first device 103. The barrier layer comprises, for example, Ta, TaN, Ti, TiN, CoW, or combinations thereof. In some embodiments, the first interconnect structure 104 is formed by a dual damascene process. In an alternative embodiment, the first interconnect structure 104 is formed by multiple single damascene processes. In still other alternative embodiments, the first interconnect structure 104 is formed by an electroplating process.

The first connection structure 110 is disposed over a first side (e.g., front side) of the first semiconductor substrate 102. Specifically, the first connecting structure 110 is disposed on the first interconnect structure 104. In some embodiments, the first connection structure 110 includes at least one first dielectric layer 112 and a plurality of first connection metal features. In some embodiments, the first dielectric layer 112 comprises silicon oxide, silicon nitride, a polymer, or a combination thereof. The first connecting metal features are disposed in the first dielectric layer 112 and electrically connected to each other. In some embodiments, the first connecting metal feature includes a first via 114V electrically connected to the first interconnect structure 104 and a first pad 114P electrically connected to the first via 114V. The first connecting metal feature may include tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, or a combination thereof. In some embodiments, a barrier layer may be disposed between the first link metal feature and the first dielectric layer 112. The barrier layer comprises, for example, Ta, TaN, Ti, TiN, CoW, or combinations thereof. In some embodiments, the first connection structure 110 is formed by a dual damascene process. In an alternative embodiment, the first connection structure 110 is formed by a plurality of single damascene processes. In still other alternative embodiments, the first connection structure 110 is formed by an electroplating process.

A second die 200 is then placed over the first die 100. The second die 200 may be, for example, an Application Specific Integrated Circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, or a memory chip. The second die 200 may be the same type of die or a different type of die as the first die 100. In some embodiments, the second die 200 may include active components or passive components. In some embodiments, the second die 200 is smaller than the first die 100.

The second die 200 may have a structure similar to that of the first die 100. In some embodiments, the second die 200 includes a second semiconductor substrate 202, a second interconnect structure 204, and a second connection structure 210. Accordingly, the differences between the second die 200 and the first die 100 are detailed below, and the similarities between the two are not repeated herein.

The second semiconductor substrate 202 may be similar in material and configuration to the first semiconductor substrate 102. In some embodiments, the second semiconductor substrate 202 includes an isolation structure defining at least one active area and at least one second device 203 is disposed on/in the active area. The second device 203 comprises one or more functional devices. In some embodiments, the functional device includes active components, passive components, or a combination thereof. In some embodiments, the functional device may comprise an integrated circuit device. Such as transistors, capacitors, resistors, diodes, photodiodes, fuse devices, and/or other similar devices. In some embodiments, the second device 203 comprises a gate dielectric layer, a gate electrode, source/drain regions, spacers, and the like. In some embodiments, the second die 200 is also referred to as a "second device die".

The second interconnect structure 204 may have a structure similar to that of the first interconnect structure 104. In some embodiments, the second interconnect structure 204 is disposed over a first side (e.g., front side) of the second semiconductor substrate 202. Specifically, the second interconnect structure 204 is disposed over the second device 203 and electrically connected to the second device 203. In some embodiments, the second interconnect structure 204 includes at least one second insulating layer 206 and a plurality of second metal features 208. In some embodiments, the second metal features 208 include metal vias and metal lines. Second metal features 208 are disposed in the second insulating layer 206 and electrically connected to each other. A portion of the second metal feature 208 (e.g., the second top metal feature) is exposed by the second insulating layer 206.

The second connection structure 210 is similar to the first connection structure 110. Similarly, the second connection structure 210 is disposed over a first side (e.g., front side) of the second semiconductor substrate 202. Specifically, the second connecting structure 210 is disposed on the second interconnect structure 204. In some embodiments, the second connection structure 210 includes at least one second dielectric layer 212 and a plurality of second connection metal features. The second connecting metal features are disposed in the second dielectric layer 212 and electrically connected to each other. In some embodiments, the second connecting metal feature includes a second via 214V electrically connected to the second interconnect structure 204 and a second pad 214P electrically connected to the second via 214V.

One difference between the second die 200 and the first die 100 is the die size. The size (size) of the second die 200 is different from (e.g., smaller than) the size of the first die 100. As used herein, the term "size" refers to length, width, and/or area. For example, as shown in fig. 1, the size of the second die 200 is smaller than the size of the first die 100.

The second die 200 is bonded to the first die 100. In some embodiments, the second die 200 is bonded back-to-back with the first die 100 by a dielectric-to-dielectric bond. Specifically, the second die 200 is bonded to the first die 100 through the second semiconductor substrate 202 and the first dielectric layer 112 of the first connection structure 110. In some embodiments, a dielectric layer (not shown) is formed on a second side (e.g., backside) of the second semiconductor substrate 202, and the second die 200 is bonded to the first die 100 through the dielectric layer and the first dielectric layer 112.

A dielectric encapsulant 300 is formed over the first die 100 and around or beside the second die 200. Specifically, the dielectric encapsulant 300 surrounds the sidewalls 200s of the second die 200, exposes the top surface 200a of the second die 200, and overlies the top surface 100a of the first die 100. In some embodiments, the top surface 200a of the second die 200 is substantially coplanar with the top surface 300a of the dielectric encapsulant 300. In some embodiments, the dielectric encapsulation 300 comprises silicon oxide, silicon oxynitride, silicon nitride, etc., and is formed by spin-on coating, lamination, deposition, etc., followed by a polishing process or planarization process. In some alternative embodiments, the dielectric encapsulation 300 includes a polymer material, such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), combinations thereof, and the like. In some alternative embodiments, the dielectric encapsulant 300 includes a molding compound, a molding underfill, a resin (e.g., an epoxy), etc., and is formed by a molding process followed by a grinding process until the top surface 200a of the second die 200 is exposed.

A plurality of through holes 310 are formed in the dielectric encapsulation 300 next to the second die 200. The through-holes 310 are electrically connected to the first die 100 through the first pads 114P. The perforation 310 is formed to surround the second die 200. In other words, the perforation 310 may be disposed at the sidewall 200s of the second die 200. In some embodiments, perforations 310 include multiple portions having different widths. For example, the perforation 310 includes a first portion 312 having a first width W1 and a second portion 314 having a second width W2 different from the first width W1. In some embodiments, the first portion 312 may also be referred to as a Through Dielectric Metal (TDM), and the second portion 314 may also be referred to as a Through Dielectric Via (TDV). The first portion 312 is physically and electrically connected to the second portion 314, and the second portion 314 is disposed between the first portion 312 and the first die 100. Since the first portion 312 and the second portion 314 have different widths, the sidewall 310s of the through-hole 310 is stepped as shown in fig. 1. The sidewalls 310s of the perforations 310 have a saw tooth geometry. In some embodiments, the second width W2 is less than the first width W1. The first width W1 and the second width W2 are respectively in the range of 1 μm to 100 μm. First portion 312 has a first thickness T1, and second portion 314 has a second thickness T2. The first thickness T1 may be the same as or different from the second thickness T2. The total thickness of the through-holes 310 (i.e., the total thickness of the first thickness T1 and the second thickness T2) is in a range of, for example, 10 μm to 100 μm.

In some embodiments, the perforations 310 comprise a conductive layer. The vias 310 may be formed by a dual damascene process, multiple single damascene processes, or other suitable methods. The conductive layer comprises aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. In some embodiments, the perforation 310 may further include a seed layer (not shown) between the conductive layer and the dielectric encapsulant 300. For example, the seed layer is continuously disposed on the stepped sidewalls 310s and the bottom of the connecting sidewalls 310 s. The seed layer may comprise a titanium/copper composite layer and be formed by a sputtering process. In some alternative embodiments, a barrier layer (not shown) may be disposed between the seed layer and the dielectric encapsulant 300. The barrier layer comprises, for example, Ta, TaN, Ti, TiN, CoW, or combinations thereof.

In some embodiments, at least one through-hole 320 is formed beside the perforation 310. Vias 320 extend from the top surface of the dielectric encapsulant 300 into the dielectric encapsulant 300. The vias 320 are formed without penetrating the dielectric encapsulation 300, and thus the vias 320 are not electrically connected to the first die 100. The through-hole 320 may be formed simultaneously with the first portion 312 of the through-hole 310. Accordingly, the material and profile of the via 320 may be similar or substantially the same as the first portion 312 of the via 310. For example, the length and width of the via 320 are substantially the same as the length and width of the first portion 312 of the via 310. However, the present invention is not limited thereto. In some alternative embodiments, the length and width of the via 320 may be different from the length and width of the first portion 312 of the through-hole 310.

A redistribution layer structure 400 is formed over the second die 200, the via 310, and the dielectric encapsulation 300. The redistribution layer structure 400 includes at least one dielectric layer 402 and at least one conductive layer 404 stacked alternately. In some embodiments, a portion of the redistribution layer structure 400 is electrically connected to the second interconnect structure 204 of the second die 200, and another portion of the redistribution layer structure 400 is electrically connected to the via 310. Additionally, in some embodiments, a portion of the redistribution layer structure 400 is electrically connected to the via 320. In some embodiments, dielectric layer 402 comprises silicon oxide, silicon oxynitride, silicon nitride, polymer-based dielectric materials (e.g., Polybenzoxazole (PBO), Polyimide (PI), benzocyclobutene (BCB), combinations thereof, and the like). In some embodiments, conductive layer 404 includes copper, nickel, titanium, combinations thereof, and the like. In some embodiments, a barrier layer may be disposed between the conductive layer 404 and the dielectric layer 402. The barrier layer comprises, for example, Ta, TaN, Ti, TiN, CoW, or combinations thereof. In some embodiments, the redistribution layer structure 400 is formed by a dual damascene process. In an alternative embodiment, the redistribution layer structure 400 is formed by a plurality of single damascene processes. In still other alternative embodiments, the redistribution layer structure 400 is formed by an electroplating process.

Thereafter, pads 406 are formed on the redistribution layer structure 400. In some embodiments, the pads 406 are Under Bump Metallization (UBM) pads for mounting conductive connectors, such as conductive pillars, micro-bumps, and the like. The pads 406 comprise a metal or metal alloy. The pad 406 comprises aluminum, copper, nickel, or alloys thereof.

After that, the terminal connection 408 is provided on the rewiring layer structure 400 and the terminal connection 408 is electrically connected to the rewiring layer structure 400. The terminal connection 408 may include a solder material including a tin alloy, a lead alloy, a silver alloy, a copper alloy, a nickel alloy, a bismuth alloy, or combinations thereof. In some embodiments, the terminal connections 408 may be arranged in an array. For example, the terminal connections 408 include conductive pillars, micro-bumps, controlled collapse chip connection (C4) bumps, Ball Grid Array (BGA), electroless nickel-palladium immersion gold (ENEPIG) technology formed bumps, combinations thereof (e.g., having metal pillars 408a with solder caps 408b attached thereon as shown in fig. 1), and the like. After the terminal connections 408 are formed, the semiconductor package 10 is thus completed. In some embodiments, the semiconductor package 10 may be Integrated as a System-on-Integrated-Chip (SoIC) package, a Chip-on-Wafer-on-Substrate (cogos) or an Integrated fan out (inpo) Wafer level package.

In some embodiments, the upper portion (i.e., first portion 312) of perforation 310 has a greater width than the lower portion (i.e., second portion 314). However, the present invention is not limited thereto. In some alternative embodiments, as shown in fig. 2, second width W2 of second portion 314 is greater than first width W1 of first portion 312. The through-holes 310 may be formed by the following steps. First, after bonding the second die 200 to the first die 100, a dielectric layer 302 is formed over the first die 100 to encapsulate the lower portion of the sidewalls 200s of the second die 200. Then, a plurality of openings are formed in the dielectric layer 302, and the second portion 314 is formed in the openings. After that, a dielectric layer 304 is formed over the dielectric layer 302 to encapsulate the upper portion of the sidewalls 200s of the second die 200. For example, the material of the dielectric layer 304 is different from the material of the dielectric layer 302. However, in some alternative embodiments, the material of the dielectric layer 304 is the same as the material of the dielectric layer 302. Then, a plurality of openings are formed in the dielectric layer 304, and the first portions 312 and the vias 320 are formed in the openings. The material of the first portion 312 and the via 320 may be different from or the same as the material of the second portion 314. In some embodiments, the dielectric encapsulant 300 includes a dielectric layer 302 and a dielectric layer 304, and the dielectric encapsulant 300 encapsulates the second die 200 and the via 310. In some embodiments, the first portion 312 of the perforation 310 is disposed in the dielectric layer 304 and has a first width W1, the second portion 314 of the perforation 310 is disposed in the dielectric layer 302 and has a second width W2, and the sidewall 310s of the perforation 310 is stepped.

In the above embodiment, one second die 200 is shown. However, the present invention is not limited thereto. In some alternative embodiments, as shown in fig. 3A and 3B (fig. 3B is a cross-sectional view along line I-I' of fig. 3A), a plurality of second dies 200 are disposed over the first die 100. The second die 200 is bonded to the first die 100 and arranged side-by-side over the first die 100. The perforation 310 is formed to surround the second die 200.

In some alternative embodiments, as shown in fig. 4 and 5, a plurality of second dies 200 are stacked on the first die 100. The second die 200 is encapsulated by a dielectric encapsulant 300, and a plurality of through-holes 310 are formed in the dielectric encapsulant 300 beside the second die 200. A redistribution layer structure 400, 400' is formed over the second die 200 and the adjacent dielectric encapsulation 300. The redistribution layer structure 400, 400' includes at least one dielectric layer 402 and at least one conductive layer 404 stacked alternately. A redistribution layer structure 400' is disposed between the two stacked second dies 200 and the two stacked dielectric encapsulants 300. In some embodiments, the topmost conductive layer 404a of the redistribution layer structure 400' may include vias 404V electrically connected to the underlying conductive layer 404 and pads 404P electrically connected to the vias 404V. The through hole 404V is disposed between the through hole 310 and the pad 404P and contacts the through hole 310 and the pad 404P. The redistribution layer structure 400, 400' is electrically connected to the first die 100 through the via 310 therebetween. In some embodiments, as shown in fig. 4, each perforation 310 has a similar profile. For example, first width W1 of first portion 312 of perforation 310 is greater than second width W2 of second portion 314. However, the present invention is not limited thereto. In some alternative embodiments, as shown in FIG. 5, first width W1 of first portion 312 of some perforations 310 is greater than second width W2 of second portion 314, and first width W1 'of first portion 312 of some perforations 310 is less than second width W2' of second portion 314.

In the embodiments of fig. 4 and 5, each dielectric encapsulant 300 encapsulates one second die 200. However, the present invention is not limited thereto. In some alternative embodiments, as shown in fig. 6 and 7, the dielectric encapsulant 300 encapsulates the one or more second die 200. Additionally, in the above embodiments, the second dies 200 of different layers are shown aligned with each other. For example, as shown in fig. 4-6, the sidewalls 200s of the upper second die 200 are aligned with the sidewalls 200s of the lower second die 200. However, the present invention is not limited thereto. In some alternative embodiments, as shown in fig. 8 and 9, the sidewalls 200s of the upper second die 200 are not aligned with the sidewalls 200s of the lower second die 200, in other words, a shift SF is formed between the sidewalls 200s of the upper second die 200 and the sidewalls 200s of the lower second die 200. In addition, as shown in fig. 9, the second dies 200 of different layers may have different sizes (e.g., widths). Further, second dies 200 of the same layer may have different sizes (e.g., widths).

In some embodiments, vias 320 and/or perforations 310 are formed to provide additional routing layers for capacitors, inductors, transmission lines, and the like. For example, as shown in fig. 10A, a plurality of first vias 320A and a plurality of second vias 320B are formed beside the via 310 in the dielectric encapsulation 300. The first and second through

holes

320A and 320B are alternately disposed and have top surfaces substantially coplanar with the top surfaces of the through holes 310. In some embodiments, the first via 320A is electrically isolated from the redistribution layer structure 400 and the first die 100. Thus, a capacitor C1 is formed between the bottommost conductive layer 404b and the first via 320A, and a capacitor C2 is formed between the first via 320A and the metal feature 108 a. The capacitance value of the capacitor C1 depends on the distance d1 between the bottommost conductive layer 404b and the first via 320A. Similarly, the capacitance value of the capacitor C2 depends on the distance d2 between the first via 320A and the metal feature 108 a. For example, the capacitance value of the capacitor C1 increases as the distance d1 becomes smaller, and the capacitance value of the capacitor C2 increases as the distance d2 becomes smaller. Additionally, in some embodiments, as shown in fig. 10B, the first vias 320A of fig. 10A may be physically connected to each other to form a comb structure, and similarly, the second vias 320B of fig. 10A may be physically connected to each other to form a comb structure. Since the first via 320A and the second via 320B are electrically isolated by the dielectric encapsulation 300 therebetween, a capacitor C3 is formed between each adjacent two of the first via 320A and the second via 320B. The capacitance value of the capacitor C3 can be adjusted by controlling the distance d3 between the first via 320A and the second via 320B, the area of the first via 320A facing the second via 320B, and the area of the second via 320B facing the first via 320A. For example, the capacitance value of the capacitor C3 increases as the distance d3 between the first via 320A and the second via 320B becomes smaller, and the capacitance value of the capacitor C3 increases as the area becomes larger.

In some embodiments, as shown in fig. 11A and 11B, first portion 312 of via 310A, second portion 314 of via 310A, and metal feature 114a form part of inductor IND. The vias 310A are electrically connected to the metal features 114a of the first die 100. In some embodiments, the first portion 312 of the via 310A, the second portion 314 of the via 310A, and the metal feature 114a belong to different layers, and the second portion 314 is disposed between the first portion 312 and the metal feature 114 a. Thus, a portion of inductor IND in the lower layer (i.e., metal feature 114a) is connected to a portion of inductor IND in the upper layer (i.e., first portion 312) by second portion 314, second portion 314 being located between the upper and lower layers. In addition, the Q value of inductor IND may be adjusted by controlling the thickness T1 of first portion 312 of via 310A. For example, the Q value of inductor IND increases as thickness T1 of first portion 312 becomes greater.

In the above embodiment, the second die 200 is bonded back to back with the first die 100. However, the present invention is not limited thereto. In some alternative embodiments, as shown in fig. 12 and 13, the second die 200 is bonded face-to-face with the first die 100 by the first connection structure 110 and the second connection structure 210. In the embodiments of fig. 12 and 13, the first connection structure 110 can also be referred to as a first bonding structure, the first dielectric layer 112 can also be referred to as a first bonding dielectric layer, the first via 114V can also be referred to as a first bonding via, and the first pad 114P can also be referred to as a first bonding pad. Similarly, the second connection structure 210 can also be referred to as a second bonding structure, the second dielectric layer 212 can also be referred to as a second bonding dielectric layer, the second via hole 214V can also be referred to as a second bonding via, and the second pad 214P can also be referred to as a second bonding pad. In some embodiments, prior to bonding the second die 200 to the first die 100, the second connection structures 210 are aligned with the first connection structures 110 such that the second pads 214P are bonded to the first pads 114P and the second dielectric layer 212 is bonded to the first dielectric layer 112. In some embodiments, the alignment of the first connection structure 110 with the second connection structure 210 may be achieved by using an optical sensing method. After alignment is achieved, the first connection structure 110 and the second connection structure 210 are bonded together by a hybrid bond that includes a metal-to-metal bond and a dielectric-to-dielectric bond.

The structures of fig. 12 and 13 are similar to the structures of fig. 1 and 2, respectively, and differ primarily in that the second die 200 of fig. 12 and 13 also includes through-substrate TSVs that penetrate the second semiconductor substrate 202. In some embodiments, when the second semiconductor substrate 202 is a silicon-containing substrate, the through-substrate TSV is referred to as a "through-silicon via". The through-substrate TSV is electrically connected to the second interconnect structure 204 and the redistribution layer structure 400. In some embodiments, the through-substrate TSV includes a via. The via includes copper, a copper alloy, aluminum, an aluminum alloy, or a combination thereof. In some embodiments, each through-substrate TSV also includes a diffusion barrier layer between the vias and the second semiconductor substrate 202. The diffusion barrier layer comprises Ta, TaN, Ti, TiN, CoW, or combinations thereof.

Fig. 14A-14E are cross-sectional views of various intermediate structures during an exemplary method of forming a semiconductor package according to some embodiments. The semiconductor package formed by the method of fig. 14A-14E is similar to that of fig. 1, so the same reference numerals are used to refer to the same and similar parts and a detailed description thereof will be omitted herein. The differences are exemplified in detail below.

Referring to fig. 14A, a first die 100 is provided and a plurality of second dies 200 are bonded to the first die 100. A dielectric layer 502 is then formed over the first die 100 to cover the second die 200. In some embodiments, dielectric layer 502 is conformally formed on the exposed surface of second die 200 and the exposed surface of first die 100 between second die 200. For example, the dielectric layer 502 covers the top surface 200a and sidewalls 200s of the second dies 200 and the top surface 100a of the first die 100 between the respective second dies 200. In some embodiments, the top surface S1 of the dielectric layer 502 between the second dies 200 is lower than the top surface 200a of the second dies 200. In some embodiments, the material of the dielectric layer 502 comprises silicon oxide, silicon oxynitride, silicon nitride, etc., and is formed by spin-on coating, lamination, deposition, etc.

Referring to fig. 14B, a plurality of openings 504 are formed in the dielectric layer 502 between the second dies 200. The openings 504 are formed corresponding to the first pads 114P of the first die 100, and the openings 504 expose portions of the first pads 114P, respectively. Then, a seed layer 510 is formed over the dielectric layer 502 having the opening 504. In some embodiments, the seed layer 510 is conformally formed on the top surface S1 of the dielectric layer 502, the sidewalls of the opening 504, and the bottom of the opening 504. The seed layer 510 includes a titanium/copper composite layer and is formed by, for example, a sputtering process. After that, a mask M is formed over the seed layer 510. The mask M has a plurality of openings OP, OP'. The opening OP is disposed directly above the opening 504 and the opening OP' is disposed beside the opening OP. The width W1 of the opening OP is greater than the width W2 of the opening 504. Thus, the opening OP completely exposes the opening 504, and the opening OP exposes a portion of the seed layer 510 on the opening 504. The opening OP ' has a width W1 ', and the width W1 ' may be the same as or different from the width W1 of the opening OP. The opening OP' exposes a portion of the seed layer 510 above the dielectric layer 502.

Referring to fig. 14B and 14C, a plurality of conductive layers 512 filling the openings OP and 504 are formed, and a conductive layer 512 'filling the opening OP' is formed. For example, a plating process is performed to form

conductive layers

512, 512 'on portions of the seed layer 510 exposed by the openings OP, OP'. The material of the

conductive layers

512, 512' includes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. In some embodiments, conductive layer 512 is partially disposed in opening 504 and partially protrudes from opening 504. Then, the mask M is removed by a stripping process, and the exposed seed layer 510 is removed by an etching process. In some embodiments, after removing mask M, a gap SP is formed between a portion of dielectric layer 502 located on sidewalls 200s of second die 200 and a portion of

conductive layers

512, 512' protruding from dielectric layer 502.

Referring to fig. 14D, a dielectric layer 514 filling the gap SP is formed. A plurality of vias 530 are then formed in dielectric layer 514 and dielectric layer 502, and vias 540 are formed in dielectric layer 514. For example, a layer of dielectric layer 514 is formed over first die 100 to cover dielectric layer 502 and

conductive layers

512, 512'. The material layer of dielectric layer 514 is then planarized until the second die 200 is exposed. In some embodiments, the

conductive layers

512, 512' and the dielectric layer 502 are also subjected to a planarization process. For example, the material layers of dielectric layer 514,

conductive layers

512, 512', and dielectric layer 502 are planarized until second die 200 is exposed. Dielectric layer 514, vias 530 and vias 540 are then formed. In some embodiments, top surface 200a of second die 200, top surface S1 of dielectric layer 502, top surface S2 of through hole 530, top surface S3 of via 540, and top surface S4 of dielectric layer 514 are substantially coplanar. In some embodiments, the planarization process includes a mechanical grinding process and/or a Chemical Mechanical Polishing (CMP) process. However, the present disclosure is not limited thereto. In some alternative embodiments, an etching process or a fly-cutting process may be suitable for performing the planarization process.

In some embodiments, dielectric layer 502 encapsulates dielectric layer 514, and dielectric layer 502 and dielectric layer 514 form a dielectric encapsulation 520. A dielectric encapsulant 520 encapsulates the second die 200. In some embodiments, dielectric layer 514 is a different material than dielectric layer 502. However, in some alternative embodiments, the material of dielectric layer 514 is the same as dielectric layer 502. In some embodiments, dielectric layer 514 comprises polyimide, benzocyclobutene (BCB), Polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. The dielectric layer 514 may be formed, for example, by a suitable fabrication technique such as spin-on coating, Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In some embodiments, the material of the dielectric layer 514 includes a molding compound, a molding underfill, a resin (e.g., an epoxy), combinations thereof, and the like. Dielectric layer 514 may be formed by a molding process.

In some embodiments, the through hole 530 is encapsulated by the dielectric encapsulation body 520, and the through hole 530 penetrates through the dielectric encapsulation body 520 to electrically connect the first pad 114P of the first die 100. In some embodiments, the perforation 530 includes a first portion 532 and a second portion 534. The second portion 534 is disposed between the first die 100 and the first portion 532 and is electrically connected to the first die 100 and the first portion 532. First portion 532 is encapsulated by dielectric layer 514 and second portion 534 is encapsulated by dielectric layer 502. In some embodiments, top surface S4 of dielectric layer 514 is substantially coplanar with top surface S2 of through-hole 530, and bottom surface S5 of dielectric layer 514 (i.e., bottom surface S5 opposite top surface S4) is substantially flush with the interface IF between first portion 532 and second portion 534. In some embodiments, first portion 532 includes seed layer 510a (i.e., a portion of seed layer 510) and conductive layer 512a (i.e., a portion of conductive layer 512). The seed layer 510a is disposed under an edge portion of the bottom surface of the conductive layer 512 a. The second portion 534 includes the seed layer 510b (i.e., a portion of the seed layer 510) and the conductive layer 512b (i.e., a portion of the conductive layer 512). The seed layer 510b surrounds the sidewalls and bottom surface of the conductive layer 512 b. In some embodiments, seed layer 510a is integrally formed with seed layer 510b, and conductive layer 512a is integrally formed with conductive layer 512 b. Seed layer 510a is disposed next to interface IF between conductive layer 512a and conductive layer 512 b. Seed layer 510b is disposed between conductive layer 512b and dielectric encapsulant 520 and between conductive layer 512b and first die 100.

In some embodiments, a first portion 532 of the perforation 530 is disposed in the dielectric layer 502 and a second portion 534 of the perforation 530 protrudes from the dielectric layer 502. In some embodiments, first portion 532 has a first width W1, and second portion 534 has a second width W2 that is different than first width W1. In some embodiments, the first width W1 is greater than the second width W2. However, the present invention is not limited thereto. In some alternative embodiments, the first width W1 is less than the second width W2.

In some embodiments, vias 540 pass through dielectric layer 514. In some embodiments, the via 540 includes a seed layer 510 and a conductive layer 512'. The conductive layer 512 'is disposed on the seed layer 510, and sidewalls of the conductive layer 512' are substantially flush with sidewalls of the seed layer 510. In some embodiments, seed layer 510 of via 540 is formed simultaneously with

seed layers

510a, 510b of via 530, and conductive layer 512' of via 540 is formed simultaneously with

conductive layers

512a, 512b of via 530. In other words, the through-hole 540 is formed through the same process as the through-hole 530. In some embodiments, the via 540 has a width W1'. Width W1' may be the same as or different from first width W1 of first portion 532.

Referring to fig. 14E, a redistribution layer structure 400 is formed over the second die 200, the through-hole 530, the via 540, and the dielectric encapsulation 520. The redistribution layer structure 400 includes at least one dielectric layer 402 and at least one conductive layer 404 stacked alternately. In some embodiments, a portion of the redistribution layer structure 400 is electrically connected to the second interconnect structure 204 of the second die 200, and another portion of the redistribution layer structure 400 is electrically connected to the via 530. Additionally, in some embodiments, a portion of the redistribution layer structure 400 is electrically connected to the via 540. The rewiring layer structure 400 may be similar to the rewiring layer structure 400 described with respect to fig. 1, and thus a detailed description thereof is omitted herein. Then, a plurality of pads 406 are formed on the redistribution layer structure 400, and a plurality of terminal connectors 408 are formed to electrically connect the pads 406. Pad 406 and terminal connector 408 may be similar to pad 406 and terminal connector 408 described with respect to fig. 1, and therefore a detailed description thereof is omitted herein. After the terminal connections 408 are formed, the semiconductor package 10 is thus completed.

Fig. 15A-15F are cross-sectional views of various intermediate structures during an exemplary method of forming a semiconductor package according to some embodiments. The method of fig. 15A-15F is similar to the method of fig. 14A-14E, so the same reference numbers are used to refer to the same and similar parts, and a detailed description thereof will be omitted herein. The differences are exemplified in detail below.

Referring to fig. 15A, a first die 100 is provided and a plurality of second dies 200 are bonded to the first die 100. A dielectric layer 602 is then formed over the first die 100 to cover the second die 200. In some embodiments, the top surface S1 of the dielectric layer 602 between the second dies 200 is lower than the top surface 200a of the second dies 200. After that, a plurality of openings 604 are formed in the dielectric layer 602. The openings 604 are formed corresponding to the first pads 114P of the first die 100, and the openings 604 respectively expose portions of the first pads 114P. The dielectric layer 602 and the opening 604 may be similar to the dielectric layer 502 and the opening 504 described with respect to fig. 14A and 14B, and thus a detailed description thereof is omitted herein.

Referring to fig. 15B, a seed layer 606 is formed on the sidewalls and bottom surface of the opening 604, respectively, and a conductive layer 608 is formed to fill the opening 604, respectively. In some embodiments, the top surface of the seed layer 606 and the top surface of the conductive layer 608 are substantially coplanar with the top surface S1 of the dielectric layer 602 between the second die 200. In some embodiments, the seed layer 606 comprises a titanium/copper composite layer, and the seed layer 606 is formed by a sputtering process. In some embodiments, the conductive layer 608 can include aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, and the conductive layer 608 is formed by a sputtering process.

Referring to fig. 15C, a seed layer 610 is formed over the dielectric layer 602, the conductive layer 608, and the seed layer 606. In some embodiments, seed layer 610 is conformally formed over dielectric layer 602, conductive layer 608, and seed layer 606. Seed layer 610 comprises a titanium/copper composite layer and is formed by, for example, a sputtering process. After that, a mask M is formed over the seed layer 610. The mask M has a plurality of openings OP, OP'. An opening OP is disposed directly above the conductive layer 608, and an opening OP' is disposed beside the opening OP. In some embodiments, the width W1 of opening OP is less than the total width W2 of conductive layer 608 and seed layer 606. Thus, the opening OP exposes a portion of the seed layer 610 that is over the conductive layer 608. The opening OP ' has a width W1 ', and the width W1 ' may be the same as or different from the width W1 of the opening OP. The opening OP' exposes a portion of the seed layer 610 over the dielectric layer 602.

Referring to fig. 15C and 15D, a plurality of conductive layers 612 are formed on the seed layer 610 in the openings OP, and conductive layers 612 'filling the openings OP' are formed. For example, a plating process is performed to form conductive layers 612, 612 'on the seed layer 610 exposed by the openings OP, OP'. The material of the conductive layers 612, 612' includes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. Then, the mask M is removed by a stripping process, and the exposed seed layer 510 is removed by an etching process. In some embodiments, after removing the mask M, a gap SP is formed between a portion of the dielectric layer 602 located on the sidewalls 200s of the second die 200 and the conductive layers 612, 612'.

Referring to fig. 15E, a dielectric layer 614 is formed to fill the gap SP. A plurality of vias 630 are then formed in dielectric layer 614 and dielectric layer 602, and vias 640 are formed in dielectric layer 514. For example, a layer of dielectric 614 material is formed over the first die 100 to cover the dielectric layer 602 and the conductive layers 612, 612'. The material layer of the dielectric layer 614 is then planarized until the second die 200 is exposed. In some embodiments, the conductive layers 612, 612' and the dielectric layer 602 are also subjected to a planarization process. For example, the material layer of the dielectric layer 614, the conductive layer 612, and the dielectric layer 602 are planarized until the second die 200 is exposed. Then, dielectric layer 614, vias 630 and vias 640 are formed. In some embodiments, the top surface 200a of the second die 200, the top surface S1 of the dielectric layer 602, the top surface S2 of the through hole 630, the top surface S3 of the via 640, and the top surface S4 of the dielectric layer 614 are substantially coplanar. In some embodiments, the planarization process includes a mechanical grinding process and/or a Chemical Mechanical Polishing (CMP) process. However, the present disclosure is not limited thereto. In some alternative embodiments, an etching process or a fly-cutting process may be suitable for performing the planarization process.

In some embodiments, the dielectric layer 602 encapsulates the dielectric layer 614, and the dielectric layer 602 and the dielectric layer 614 form a dielectric encapsulation 620. The dielectric encapsulant 620 encapsulates the second die 200. In some embodiments, the material of the dielectric layer 614 is different from the dielectric layer 602. However, in some alternative embodiments, the material of the dielectric layer 614 is the same as the dielectric layer 602. In some embodiments, dielectric layer 614 comprises polyimide, benzocyclobutene (BCB), Polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. The dielectric layer 614 may be formed, for example, by a suitable fabrication technique such as spin-on coating, Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like. In some embodiments, the material of the dielectric layer 614 comprises a molding compound, a molding underfill, a resin (e.g., an epoxy), combinations thereof, and the like. The dielectric layer 614 may be formed by a molding process.

In some embodiments, the through hole 630 is encapsulated by the dielectric encapsulation body 620, and the through hole 630 penetrates through the dielectric encapsulation body 620 to electrically connect the first pad 114P of the first die 100. In some embodiments, the perforation 630 includes a first portion 632 and a second portion 634. The second portion 634 is disposed between the first die 100 and the first portion 632 and is electrically connected to the first die 100 and the first portion 632. The first portion 632 is encapsulated by the dielectric layer 614 and the second portion 634 is encapsulated by the dielectric layer 602. In some embodiments, the top surface S4 of the dielectric layer 614 is substantially coplanar with the top surface S2 of the through-hole 630, and the bottom surface S5 of the dielectric layer 614 (i.e., the bottom surface S5 opposite the top surface S4) is substantially flush with the interface IF between the first portion 632 and the second portion 634. In some embodiments, the first portion 632 includes a seed layer 610 and a conductive layer 612. Seed layer 610 is disposed entirely below the bottom surface of conductive layer 612. The second portion 632 includes the seed layer 606 and the conductive layer 608. The seed layer 606 surrounds the sidewalls and bottom surface of the conductive layer 608. In some embodiments, seed layer 610 and seed layer 606 are formed separately, and conductive layer 612 and conductive layer 608 are formed separately. In some embodiments, the seed layer 610 is physically separated from the seed layer 606. Seed layer 610 is disposed at an interface IF between conductive layer 612 and conductive layer 608. Seed layer 606 is disposed between conductive layer 608 and dielectric encapsulant 620 and between conductive layer 608 and first die 100.

In some embodiments, a first portion 632 of the perforations 630 is disposed in the dielectric layer 602 and a second portion 634 of the perforations 630 protrudes from the dielectric layer 602. In some embodiments, first portion 632 has a first width W1, and second portion 634 has a second width W2 that is different than first width W1. In some embodiments, the first width W1 is less than the second width W2.

In some embodiments, the vias 640 pass through the dielectric layer 614. In some embodiments, via 640 includes seed layer 610 and conductive layer 612'. A conductive layer 612 'is disposed on the seed layer 610, and the sidewalls of the conductive layer 612' are substantially flush with the sidewalls of the seed layer 610. In some embodiments, seed layer 610 of via 640 is formed simultaneously with seed layer 610 of via 630, and conductive layer 612' of via 640 is formed simultaneously with conductive layer 612 of via 630. In other words, the through-hole 640 is formed through the same process as the first portion 632 of the through-hole 630. In some embodiments, the via 640 has a width W1'. The width W1' may be the same as or different from the first width W1 of the first portion 632.

Referring to fig. 15F, a redistribution layer structure 400 is formed over the second die 200, the through-hole 630, the via 640, and the dielectric encapsulation 620. The redistribution layer structure 400 includes at least one dielectric layer 402 and at least one conductive layer 404 stacked alternately. In some embodiments, a portion of the redistribution layer structure 400 is electrically connected to the second interconnect structure 204 of the second die 200, and another portion of the redistribution layer structure 400 is electrically connected to the via 630. Additionally, in some embodiments, a portion of the redistribution layer structure 400 is electrically connected to the via 640. The rewiring layer structure 400 may be similar to the rewiring layer structure 400 described with respect to fig. 1, and thus a detailed description thereof is omitted herein. Then, a plurality of pads 406 are formed on the redistribution layer structure 400, and a plurality of terminal connectors 408 are formed to electrically connect the pads 406. Pad 406 and terminal connector 408 may be similar to pad 406 and terminal connector 408 described with respect to fig. 1, and therefore a detailed description thereof is omitted herein. After the terminal connections 408 are formed, the semiconductor package 10 is thus completed.

In the embodiments of fig. 14E and 15F, each

dielectric layer

514, 614 encapsulates one through-

hole

530, 630 or via 540, 640. However, the present invention is not limited thereto. In some alternative embodiments, as shown in fig. 16 and 17,

dielectric layers

514, 614 encapsulate at least two of

vias

530, 630 and vias 540, 640. In some embodiments, the second die 200 may be similar to the second die 200 described with respect to fig. 12 and 13, and thus a detailed description thereof is omitted herein.

In summary, in the semiconductor package, the through hole includes a plurality of portions having different widths, and thus the through hole has a stepped sidewall. The perforated sections may be integrally formed or separately formed. In addition, different portions of the perforations may be encapsulated by the same material or separately encapsulated by different materials. In other words, the dielectric encapsulant used to fill the gaps between the dies and to encapsulate the dies and the through-holes may comprise the same material (i.e., a homogenous material) or a different material (i.e., a heterogeneous material). Furthermore, at least one via may be formed simultaneously with the perforation in the dielectric encapsulation, and the via may provide an additional wiring layer according to design.

According to some embodiments of the present disclosure, a semiconductor package includes a first die, a second die, a via, and a dielectric encapsulant. The second die is bonded to the first die. The perforation is disposed alongside the second die and electrically connected to the first die. The bore includes a stepped sidewall. The dielectric encapsulant encapsulates the second die and the through-hole.

In some embodiments, the perforation includes a first portion having a first width and a second portion having a second width different from the first width, and the second portion is disposed between the first portion and the first die.

In some embodiments, the first portion includes a first seed layer and a first conductive layer, the second portion includes a second seed layer and a second conductive layer, the first seed layer is disposed alongside an interface between the first conductive layer and the second conductive layer, and the second seed layer is disposed between the second conductive layer and the dielectric encapsulant and between the second conductive layer and the first die.

In some embodiments, the first seed layer is physically separated from the second seed layer.

In some embodiments, the first seed layer is integrally formed with the second seed layer.

In some embodiments, the semiconductor package further comprises a plurality of first vias and a plurality of second vias in the dielectric encapsulation beside the through-holes, wherein the first vias and the second vias are alternately disposed and have top surfaces that are substantially coplanar with top surfaces of the through-holes, and the first vias are electrically isolated from the second vias.

In some embodiments, the first vias are electrically connected to each other and the second vias are electrically connected to each other.

According to an alternative embodiment of the present disclosure, a semiconductor package includes a first die, a plurality of second dies, a via, a first dielectric layer, and a second dielectric layer. The second die is bonded to the first die. The perforations are disposed between the second dies and electrically connected to the first dies. The via includes a first portion and a second portion between the first portion and the first die. The first dielectric layer encapsulates the first portion. The second dielectric layer is different from the first dielectric layer and encapsulates the second die, the second portion of the via, and the first dielectric layer.

In some embodiments, the second dielectric layer is disposed between the second die and the first dielectric layer and between the second die and the first portion.

In some embodiments, a bottom surface of the first dielectric layer is substantially flush with an interface between the first portion and the second portion.

In some embodiments, a top surface of the second die, a top surface of the first dielectric layer, a top surface of the via, and a top surface of the second dielectric layer are substantially coplanar.

In some embodiments, the width of the first portion is different from the width of the second portion.

In some embodiments, the first portion includes a first conductive layer and a first seed layer located below a bottom of the first conductive layer, and the second portion includes a second conductive layer and a second seed layer surrounding sidewalls and a bottom of the second conductive layer.

According to still further alternative embodiments of the present disclosure, a method of forming a semiconductor package includes the following steps. A first die and a plurality of second dies bonded to the first die are provided. A first dielectric layer is formed over the first die to cover the plurality of second dies. A first opening is formed in the first dielectric layer between the second die. A perforation is formed. The perforation is partially disposed in the first opening and partially protrudes from the first opening. A first portion of the perforations protruding from the first opening has a first width, and a second portion of the perforations located in the first opening has a second width different from the first width. A second dielectric layer is formed on the sidewalls of the second die between the through-hole and the first dielectric layer.

In some embodiments, the first dielectric layer is formed conformally with the top surface and sidewalls of the second die and the top surface of the first die between the second die.

In some embodiments, the first dielectric layer is formed between and in contact with the second dielectric layer and the second die.

In some embodiments, forming the perforations comprises: forming a seed layer over the first dielectric layer having the first opening; forming a mask over the seed layer, the mask having a second opening that is larger than the first opening and exposes a portion of the seed layer in the first opening; forming a conductive layer in the first opening and the second opening; removing the mask, wherein a gap is formed between the first dielectric layer and the conductive layer; and removing the seed layer not covered by the conductive layer.

In some embodiments, the method further comprises: forming the second dielectric layer in the gap to cover the first dielectric layer and the conductive layer and fill the gap; and planarizing a top surface of the first dielectric layer, a top surface of the second dielectric layer, a top surface of the conductive layer, and a top surface of the second die.

In some embodiments, forming the perforations comprises: filling a first conductive layer and a first seed layer surrounding the first conductive layer into the first opening; forming a second seed layer over the first dielectric layer, the first conductive layer, and the first seed layer; forming a mask over the second seed layer, the mask having a second opening smaller than the first opening; forming a second conductive layer in the second opening; removing the mask, wherein a gap is formed between the first dielectric layer and the second conductive layer; and removing the second seed layer not covered by the second conductive layer.

In some embodiments, the method further comprises: forming the second dielectric layer to cover the first dielectric layer and the second conductive layer and fill the gap; and planarizing a top surface of the first dielectric layer, a top surface of the second conductive layer, and a top surface of the second die.

The present disclosure may also include other features and processes. For example, test structures may be included to facilitate verification testing of 3D packages or 3DIC devices. The test structure may, for example, include test pads formed in a redistribution layer or on a substrate to enable testing of a 3D package or 3DIC, use of probes and/or probe cards (probe card), and the like. Verification testing may be performed on the intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods that include intermediate verification of known good dies (known good die) to improve yield and reduce cost.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising:

a first die;

a second die bonded to the first die;

a through-hole disposed alongside the second die and electrically connected to the first die, wherein the through-hole comprises a stepped sidewall; and

a dielectric encapsulant encapsulating the second die and the through-hole.