TW201947759A - Transparent display panel and manufacturing method thereof - Google Patents

Abstract

Provided is a transparent display panel including the following devices. An active layer is located on a substrate. A gate insulating layer is located on the active layer. A gate is located on the gate insulating layer. A first insulating layer is located on the gate and the gate insulating layer. A second insulating layer in located on the first insulating layer. An auxiliary structure is located on the second insulating layer and defines a transparent region. A source and a drain are located on the second insulating layer and electrically connected to the active layer respectively. A third insulating layer is located on the source and the drain. A fourth insulating layer is located on the third insulating layer and is in contact with the first insulating layer in the transparent region. An electro-luminescent device is located on the fourth insulating layer.

Description

Transparent display panel and manufacturing method thereof

The invention relates to a display panel and a manufacturing method thereof, and in particular to a transparent display panel and a manufacturing method thereof.

Organic electroluminescent device (organic electroluminescent device) is a semiconductor device that can convert electrical energy into light energy and has high conversion efficiency. Its common uses are light emitting devices such as indicator lights and display panels. Since organic electroluminescent elements have characteristics such as no viewing angle problem, simple process, low cost, high response speed, wide operating temperature range and full color, etc., they meet the requirements of display characteristics in the multimedia era and are expected to become the mainstream of flat panel displays.

At present, there are research and development cases in which organic electroluminescent elements are applied to transparent electronic products, so that viewers can view images through a transparent background. Such transparent electronic products are, for example, automotive glass, smart windows, transparent displays, and the like.

An embodiment of the present invention provides a transparent display panel and a manufacturing method thereof, which can increase the transmittance of the transparent display panel and reduce the yellowing phenomenon.

An embodiment of the present invention provides a method for manufacturing a transparent display panel, the steps of which are as follows. An active layer is formed on the substrate. A gate insulation layer is formed on the active layer. A gate electrode is formed on the gate insulating layer. A first interlayer insulating layer is formed on the gate electrode and the gate insulating layer. A second interlayer insulating layer is formed on the first interlayer insulating layer. An auxiliary structure is formed on the second interlayer insulating layer. A source electrode and a drain electrode are formed on the second interlayer insulating layer and are electrically connected to the active layer, respectively. A third interlayer insulating layer is formed on the source electrode and the drain electrode, and extends to cover the auxiliary structure. With the auxiliary structure as an etch stop layer, a part of the third interlayer insulating layer and a part of the second interlayer insulating layer are removed to expose the first interlayer insulating layer in the predetermined transparent area. A fourth interlayer insulating layer is formed on the third interlayer insulating layer. A lower electrode is formed on the fourth interlayer insulating layer and is electrically connected to the drain electrode. A pixel definition layer is formed on the fourth interlayer insulating layer, wherein the pixel definition layer has an opening located in a developing region. An electroluminescent layer is formed in the opening. An upper electrode is formed on the electroluminescent layer.

An embodiment of the present invention provides a transparent display panel including a substrate, an active layer, a gate insulation layer, a gate electrode, a first interlayer insulation layer, a second interlayer insulation layer, an auxiliary structure, a source electrode, a drain electrode, and a third interlayer. An insulating layer, a fourth interlayer insulating layer, and an electroluminescent element. The active layer is on the substrate. The gate insulation layer is located on the active layer. The gate is located on the gate insulation. The first interlayer insulating layer is located on the gate electrode and the gate insulating layer. The second interlayer insulating layer is located on the first interlayer insulating layer. The auxiliary structure is located on the gate insulation layer and defines a transparent area, wherein the thickness of the auxiliary structure is 400 nm to 700 nm. The source and the drain are located on the second interlayer insulating layer and are electrically connected to the active layer, respectively. The third interlayer insulating layer is located on the source and the drain. The fourth interlayer insulating layer is located on the third interlayer insulating layer. The electroluminescent element is located on the fourth interlayer insulating layer.

An embodiment of the present invention provides a method for manufacturing a transparent display panel, the steps of which are as follows. An active layer is formed on the substrate. A first gate insulating layer is formed on the active layer. A second gate insulating layer is formed on the first gate insulating layer. A gate electrode and an auxiliary structure are formed on the second gate insulation layer. A first interlayer insulating layer is formed on the gate electrode, the second gate insulating layer and the auxiliary structure. A second interlayer insulating layer is formed on the first interlayer insulating layer. A source electrode and a drain electrode are formed on the second interlayer insulating layer and are electrically connected to the active layer, respectively. A third interlayer insulating layer is formed on the source electrode, the drain electrode, and the second interlayer insulating layer. Using the auxiliary structure as an etch stop layer, removing a portion of the third interlayer insulating layer, a portion of the second interlayer insulating layer, a portion of the first interlayer insulating layer, and a portion of the second gate insulating layer to expose the first gate insulation Layered on a predetermined transparent area. A fourth interlayer insulating layer is formed on the third interlayer insulating layer, wherein at least a part of the fourth interlayer insulating layer is located in a predetermined transparent region. A lower electrode is formed on the fourth interlayer insulating layer and is electrically connected to the drain electrode. A pixel definition layer is formed on the fourth interlayer insulating layer, wherein at least a part of the pixel definition layer is located in a predetermined transparent area, and the pixel definition layer has an opening in the development area. An electroluminescent layer is formed in the opening. An upper electrode is formed on the electroluminescent layer.

Based on the above, an embodiment of the present invention uses the auxiliary structure as an etch stop layer to precisely control the thickness of the insulating layer in the transparent region. Therefore, the configuration of the stacked layers in the transparent region can increase the transmittance of the transparent display panel and reduce the yellowing phenomenon. In addition, the auxiliary structure can be formed at the same time as the gate or source / drain, without adding additional process steps.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

The invention is explained more fully with reference to the drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1A to 1F are schematic diagrams of a manufacturing process of a transparent display panel according to a first embodiment of the present invention. FIG. 2 is a schematic diagram of a pixel circuit unit of a transparent display panel according to a first embodiment of the present invention.

A first embodiment of the present invention provides a method for manufacturing a transparent display panel 1, the steps of which are as follows. Referring to FIG. 1A, a substrate 100 is provided. In an embodiment, the material of the substrate 100 may be an inorganic transparent material (such as glass, quartz, other suitable materials, and combinations thereof), an organic transparent material (such as polyolefin, polyfluorene, polyalcohol, polyester, Rubber, thermoplastic polymer, thermosetting polymer, polyaromatic hydrocarbon, polymethylpropionate, polycarbonate, other suitable materials, derivatives thereof and combinations thereof) or a combination thereof.

Next, an active layer 102 is formed on the substrate 100. In one embodiment, the material of the active layer 102 includes a semiconductor material. The semiconductor material includes, but is not limited to, a silicon-based semiconductor material (such as polycrystalline silicon), an oxide-based semiconductor material (such as indium oxide, tin oxide, zinc oxide, indium gallium zinc oxide, etc.), or a combination thereof.

After that, a gate insulating layer 104 is formed on the active layer 102. The gate insulation layer 104 covers the surfaces of the active layer 102 and the substrate 100. In one embodiment, the material of the gate insulating layer 104 includes an oxide of silicon (such as silicon oxide), a nitride of silicon (such as silicon nitride), or a combination thereof. Although FIG. 1A illustrates only a single layer of the gate insulating layer 104, the present invention is not limited thereto. In other embodiments, the gate insulation layer 104 may have a two-layer structure or a multi-layer structure.

Then, a gate electrode 106 is formed on the gate insulating layer 104. As shown in FIG. 1A, the gate insulation layer 104 is disposed between the active layer 102 and the gate electrode 106. In one embodiment, the gate electrode 106 may include a metal material, such as molybdenum, aluminum, chromium, gold, titanium, nickel, copper, and alloys thereof.

Next, a first interlayer insulating layer 108 is formed on the gate electrode 106 and the gate insulating layer 104, and a second interlayer insulating layer 110 is formed on the first interlayer insulating layer 108. In an embodiment, the material of the first interlayer insulating layer 108 includes an inorganic dielectric material, which includes an oxide of silicon (such as silicon oxide), a nitride of silicon (such as silicon nitride), or a combination thereof. In an embodiment, the material of the second interlayer insulating layer 110 includes an inorganic dielectric material, which includes an oxide of silicon (such as silicon oxide), a nitride of silicon (such as silicon nitride), or a combination thereof. In an alternative embodiment, the material of the first interlayer insulating layer 108 is the same as the material of the second interlayer insulating layer 110. In other embodiments, the material of the first interlayer insulating layer 108 is different from the material of the second interlayer insulating layer 110. For example, the first interlayer insulating layer 108 may be silicon oxide; the second interlayer insulating layer 110 may be silicon nitride.

Referring to FIG. 1A, after the first interlayer insulating layer 108 and the second interlayer insulating layer 110 are formed, openings 10 and 12 are formed. The openings 10 and 12 penetrate the second interlayer insulating layer 110, the first interlayer insulating layer 108, and the gate insulating layer 104, respectively, so as to expose a part of the top surface of the active layer 102.

Referring to FIG. 1B, a conductive layer 112 is formed on the second interlayer insulating layer 110. The conductive layer 112 fills the openings 10 and 12 and extends to cover the top surface of the second interlayer insulating layer 110. In one embodiment, the conductive layer 112 includes a metal, a metal oxide, or a combination thereof. The metal may be, for example, molybdenum, aluminum, chromium, gold, titanium, nickel, copper, and alloys thereof. The metal oxide may be, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or a combination thereof.

Referring to FIGS. 1B and 1C, the conductive layer 112 is patterned to form a source 114, a drain 116, and an auxiliary structure 118 on the second interlayer insulating layer 110. That is, the auxiliary structure 118, the source 114, and the drain 116 are formed by patterning the same film layer (ie, the conductive layer 112). Therefore, no additional process steps are required to form the auxiliary structure 118. For example, the source electrode 114 is formed in the opening 10 and is electrically connected to the active layer 102. The drain electrode 116 is formed in the opening 12 and is also electrically connected to the active layer 102. The thin film transistor TR includes a source 114, a drain 116, an active layer 102, and a gate 106. The auxiliary structure 118 is disposed beside the thin film transistor TR and is used to define a predetermined transparent region R2 '.

In addition, the auxiliary structure 118 may not be formed at the same time as the source 114 and the drain 116. For example, after forming the source 114 and the drain 116, an auxiliary layer (not shown) may be formed on the second interlayer insulating layer 110. Then, the auxiliary layer is patterned, thereby forming an auxiliary structure 118. In this embodiment, the material of the auxiliary structure 118 may be different from that of the source 114 and the drain 116. In one embodiment, the material of the auxiliary structure 118 includes a metal, a metal oxide, an organic compound, or a combination thereof, and has a thickness of 400 nm to 700 nm.

In addition, as shown in FIG. 1C, in the perspective of the cross-sectional view, the shape of the auxiliary structure 118 is two blocks separated from each other. From the perspective of the top view, as shown in FIG. 2, the auxiliary structure 118 may be an auxiliary structure 118 a having a single frame, an auxiliary structure 118 b having a single round frame, and an auxiliary structure 118 c having a single cross shape. The auxiliary structure 118d having a plurality of strips, the auxiliary structure 118e having a plurality of round frames, or the auxiliary structure 118f having a plurality of frames. In some embodiments, each pixel unit P may include auxiliary structures 118 of different shapes. In an alternative embodiment, each pixel unit P may include the auxiliary structure 118 of the same shape.

Please continue to refer to FIGS. 1C and 1D. After the auxiliary structure 118 is formed, a third interlayer insulating layer 120 is formed on the second interlayer insulating layer 110. The third interlayer insulating layer 120 covers the source 114 and the drain 116, and extends to cover the auxiliary structure 118. In an embodiment, the material of the third interlayer insulating layer 120 includes an inorganic dielectric material, which includes an oxide of silicon (such as silicon oxide), a nitride of silicon (such as silicon nitride), or a combination thereof. Next, as shown in FIG. 1D, an opening 14 is formed in the third interlayer insulating layer 120. The opening 14 exposes the top surface of the drain electrode 116.

Referring to FIG. 1D and FIG. 1E, after the opening 14 is formed, a photoresist pattern 122 is formed on the third interlayer insulating layer 120. The photoresist pattern 122 has an opening 16 to correspond to a predetermined transparent region R2 '. In one embodiment, the area of the opening 16 is larger than the area of the predetermined transparent region R2 'and partially overlaps the auxiliary structure 118. Next, as shown in FIG. 1E, an etching process is performed using the photoresist pattern 122 as an etching mask and the auxiliary structure 118 as an etching stop layer to remove a part of the third interlayer insulating layer 120 and the second interlayer insulating layer 110. A portion and a portion of the first interlayer insulating layer 108 are exposed to expose the first interlayer insulating layer 108b in the predetermined transparent region R2 '. In this case, since the third interlayer insulating layer 120 and the second interlayer insulating layer 110 in the predetermined transparent region R2 'have been removed, the following paragraph may refer to the predetermined transparent region R2' as the transparent region R2. In some embodiments, the etching process may be an anisotropic etching process, such as a reactive ion etching (RIE) process. In an alternative embodiment, the etching selection ratio of the auxiliary structure 118 and the third interlayer insulating layer 120 by the etching process is 3% to 8%; the etching selection of the auxiliary structure 118 and the second interlayer insulating layer 110 by the etching process is selected. The ratio is 2% to 5%.

As shown in FIG. 1E, after the etching process, the thickness T1 of the first interlayer insulating layer 108a outside the transparent region R2 is 200 nm to 400 nm; and the first interlayer insulating layer remaining in the transparent region R2 The thickness T2 of 108b is 20 nm to 100 nm. That is, the thickness T1 of the first interlayer insulating layer 108a outside the transparent region R2 is larger than the thickness T2 of the first interlayer insulating layer 108b remaining in the transparent region R2.

It is worth noting that in this embodiment, the auxiliary structure 118 can be used as an etch stop layer to precisely control the thickness T2 of the first interlayer insulating layer 108b in the transparent region R2. For example, when the film characteristics of the first interlayer insulating layer 108, the second interlayer insulating layer 110, and the third interlayer insulating layer 120 are similar, it is difficult to determine the etching endpoint during the etching process. The auxiliary structure 118 of this embodiment can be used as an etching end point of the etching process to completely remove the second interlayer insulating layer 110 and the third interlayer insulating layer 120 in the transparent region R2 and accurately control the remaining first layers. The thickness T2 of the interlayer insulating layer 108b. In one embodiment, when the thickness T2 of the first interlayer insulating layer 108b is controlled to 20 nm to 100 nm, it can increase the transmittance of the transparent region R2 and reduce the yellowing phenomenon.

Referring to FIGS. 1E and 1F, after the photoresist pattern 122 is removed, a fourth interlayer insulating layer 124 is formed on the third interlayer insulating layer 120. The fourth interlayer insulating layer 124 extends to cover the first interlayer insulating layer 108b in the transparent region R2. As shown in FIG. 1F, the fourth interlayer insulating layer 124 directly contacts the first interlayer insulating layer 108b in the transparent region R2. In one embodiment, the fourth interlayer insulating layer 124 includes an organic dielectric material, an inorganic dielectric material, or a combination thereof. The organic dielectric material may be, for example, a photoresist material, an acrylic resin, an epoxy resin, a polyimide resin, or a combination thereof. The inorganic dielectric material includes an oxide of silicon (such as silicon oxide), a nitride of silicon (such as silicon nitride), or a combination thereof.

Then, an opening 18 is formed in the fourth interlayer insulating layer 124. The opening 18 may correspond to the opening 14 and overlap the opening 14, but the invention is not limited thereto. Next, a lower electrode 128 is formed in the openings 14 and 18. The lower electrode 128 fills the openings 14 and 18 and extends to cover a part of the top surface of the fourth interlayer insulating layer 124. As shown in FIG. 1F, the lower electrode 128 is in contact with the drain electrode 116 and is electrically connected.

As shown in FIG. 1F, after the lower electrode 128 is formed, a pixel definition layer 126 is formed on the fourth interlayer insulating layer 124. The pixel definition layer 126 covers the lower electrode 128 and extends to cover the third interlayer insulating layer 120 in the transparent region R2. In one embodiment, the pixel definition layer 126 includes an organic dielectric material, an inorganic dielectric material, or a combination thereof. The organic dielectric material may be, for example, a photoresist material, an acrylic resin, an epoxy resin, a polyimide resin, or a combination thereof. The inorganic dielectric material includes an oxide of silicon (such as silicon oxide), a nitride of silicon (such as silicon nitride), or a combination thereof.

Next, an opening 20 is formed in the pixel definition layer 126, and an electroluminescent layer 130 is formed in the opening 20. In one embodiment, the electroluminescent layer 130 may include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. However, the present invention is not limited to this. In other embodiments, the configuration of the electroluminescent layer 130 can be adjusted or changed according to the design. Then, an upper electrode 132 is formed on the electroluminescent layer 130. The upper electrode 132 covers the electroluminescent layer 130 and extends to cover the top surface of the pixel definition layer 126. In other embodiments, when the upper electrode 132 is a transparent electrode, it may also extend to cover the pixel definition layer 126 in the transparent region R2. In this embodiment, the electroluminescent element EL includes a lower electrode 128, an electroluminescent layer 130, and an upper electrode 132, but the invention is not limited thereto.

After the upper electrode 132 is formed, the transparent display panel 1 of the first embodiment of the present invention is completed. The transparent display panel 1 includes a display area R1 and a transparent area R2. The transparency of the transparent region R2 is higher than the transparency of the developing region R1. The electroluminescent element EL is located in the display area R1 and is used to display an image. The stacked layers formed by the gate insulating layer 104, the first interlayer insulating layer 108b, the fourth interlayer insulating layer 124, and the pixel definition layer 126 are located in the transparent region R2. The stacked layers can increase the transmittance of the transparent display panel 1 and reduce the yellowing phenomenon. Therefore, the transparent display panel 1 can be regarded as a transparent state, so that the viewer can more clearly view the image displayed in the development area R1.

As shown in FIGS. 1F and 2, the transparent display panel 1 includes a plurality of pixel units P arranged in an array. Although the pixel units P shown in FIG. 2 are arranged in a 2 × 3 array, the present invention can adjust the number and configuration of the pixel units P according to design requirements. As shown in FIG. 2, the pixel unit P includes a display area R1 and a transparent area R2. In this embodiment, the area of the transparent region R2 is larger than the area of the display region R1 so that external light can pass through the transparent region R2, so that the viewer can see the object under the substrate 100. Therefore, the viewer can view the image displayed in the display area R1 through the transparent background. The development area R1 includes a pixel circuit unit PC. The pixel circuit unit PC includes a first thin film transistor TR1, a second thin film transistor TR2, and a capacitor C. The first thin film transistor TR1 is electrically connected to the scan line S and the data line D. The second thin film transistor TR2 is electrically connected to the first thin film transistor TR1 and the power line Vdd. The capacitor C is electrically connected to the first thin film transistor TR1 and the second thin film transistor TR2. In an embodiment, the first thin film transistor TR1 may be a switching transistor; the second thin film transistor TR2 may be a driving transistor. The first thin film transistor TR1 and the second thin film transistor TR2 are electrically connected to the lower electrode 128 (as shown in FIG. 1F), and the second thin film transistor TR2 is a thin film transistor TR. In some embodiments, the first thin film transistor TR1 and the second thin film transistor TR2 may be P-type transistors. However, the present invention is not limited thereto. In other embodiments, at least one of the first thin film transistor TR1 and the second thin film transistor TR2 may be an N-type transistor. Although the pixel circuit unit PC shown in FIG. 2 includes two thin film transistors TR1 and TR2 and a single capacitor C, the present invention can adjust the number and configuration of the thin film transistors and capacitors according to design requirements.

3 is a schematic cross-sectional view of a transparent display panel according to a second embodiment of the present invention.

Referring to FIG. 3, the transparent display panel 2 of the second embodiment is basically similar to the transparent display panel 1 of the first embodiment. The difference between the above two is that the pixel definition layer 126 of the transparent display panel 2 of the second embodiment directly contacts the first interlayer insulating layer 108b in the transparent region R2. For example, after the opening 14 is formed in the third interlayer insulating layer 120, a fourth interlayer insulating layer 124 is formed on the third interlayer insulating layer 120. Then, a photoresist pattern (not shown) is formed on the fourth interlayer insulating layer 124. Then, the photoresist pattern is used as an etching mask, and the auxiliary structure 118 is used as an etching stop layer. An etching process is performed to remove a part of the fourth interlayer insulating layer 124, a part of the third interlayer insulating layer 120, and a second interlayer. A part of the insulating layer 110 and a part of the first interlayer insulating layer 108 are exposed to expose the first interlayer insulating layer 108b in the transparent region R2. Therefore, a stacked layer of the gate insulating layer 104, the first interlayer insulating layer 108b, and the pixel definition layer 126 is formed in the transparent region R2 of the finally formed transparent display panel 2. The stacked layers can increase the transmittance of the transparent display panel 2 and reduce the yellowing phenomenon.

4 is a schematic cross-sectional view of a transparent display panel according to a third embodiment of the present invention.

Referring to FIG. 4, the transparent display panel 3 of the third embodiment is basically similar to the transparent display panel 1 of the first embodiment. The difference between the above two is that the auxiliary structure 218 of the transparent display panel 3 of the third embodiment is formed on the gate insulating layer 104. For example, the gate insulating layer 104 includes a first gate insulating layer 101 and a second gate insulating layer 103. The second gate insulating layer 103 is formed on the first gate insulating layer 101, and the first gate insulating layer 101 is disposed between the substrate 100 and the second gate insulating layer 103. In one embodiment, the first gate insulating layer 101 includes an inorganic dielectric material, which includes an oxide of silicon (such as silicon oxide), a nitride of silicon (such as silicon nitride), or a combination thereof. The second gate insulating layer 103 includes an inorganic dielectric material, which includes an oxide of silicon (such as silicon oxide), a nitride of silicon (such as silicon nitride), or a combination thereof. In an alternative embodiment, the first gate insulating layer 101 and the second gate insulating layer 103 include different materials. For example, the first gate insulating layer 101 may be silicon oxide, and the second gate insulating layer 103 may be silicon nitride.

In addition, in this embodiment, the auxiliary structure 218 and the gate electrode 106 are formed by patterning the same film layer. That is, the auxiliary structure 218 and the gate electrode 106 are formed at the same time and have the same material. However, the present invention is not limited thereto. In other embodiments, the auxiliary structure 218 and the gate electrode 106 may be sequentially formed.

As shown in FIG. 4, after the auxiliary structure 218 is formed, a first interlayer insulating layer 108, a second interlayer insulating layer 110, and a third interlayer insulating layer 120 are sequentially formed on the auxiliary structure 218. Then, using the auxiliary structure 218 as an etching stop layer, an etching process is performed to remove a part of the third interlayer insulating layer 120, a part of the second interlayer insulating layer 110, a part of the first interlayer insulating layer 108, and a second gate insulation A part of the layer 103 and a part of the first gate insulating layer 101 expose the first gate insulating layer 101b in the transparent region R2. As shown in FIG. 4, after the etching process, the thickness T3 of the first gate insulating layer 101a outside the transparent region R2 remains 200 nm to 450 nm; and the first gate insulating layer 101b remaining in the transparent region R2 The thickness T4 is 20 nm to 150 nm. After the etching process, a fourth interlayer insulating layer 124 and a pixel definition layer 126 are sequentially formed on the first gate insulating layer 101b. Therefore, a stacked layer of the first gate insulating layer 101b, the fourth interlayer insulating layer 124, and the pixel definition layer 126 is formed in the transparent region R2 of the finally formed transparent display panel 3. The stacked layers can increase the transmittance of the transparent display panel 3 and reduce the yellowing phenomenon.

5 is a schematic cross-sectional view of a transparent display panel according to a fourth embodiment of the present invention.

Referring to FIG. 5, the transparent display panel 4 of the fourth embodiment is basically similar to the transparent display panel 3 of the third embodiment. The difference between the above two is that the pixel definition layer 126 of the transparent display panel 4 of the fourth embodiment directly contacts the first gate insulating layer 101b in the transparent region R2. For example, after the opening 14 is formed in the third interlayer insulating layer 120, a fourth interlayer insulating layer 124 is formed on the third interlayer insulating layer 120. Then, a photoresist pattern (not shown) is formed on the fourth interlayer insulating layer 124. Then, the photoresist pattern is used as an etching mask, and the auxiliary structure 218 is used as an etching stop layer. An etching process is performed to remove a part of the fourth interlayer insulating layer 124, a part of the third interlayer insulating layer 120, and a second interlayer. A part of the insulating layer 110, a part of the first interlayer insulating layer 108, a part of the second gate insulating layer 103, and a part of the first gate insulating layer 101 are exposed to expose the first gate insulating layer 101b in the transparent region R2. After the etching process, a pixel definition layer 126 is formed on the first gate insulating layer 101b. Therefore, a stacked layer of the first gate insulating layer 101b and the pixel definition layer 126 is formed in the transparent region R2 of the finally formed transparent display panel 4. The stacked layers can increase the transmittance of the transparent display panel 4 and reduce the yellowing phenomenon.

In summary, at least one embodiment of the present invention uses the auxiliary structure as an etch stop layer to precisely control the thickness of the insulating layer in the transparent region. Therefore, the configuration of the stacked layers in the transparent region can increase the transmittance of the transparent display panel and reduce the yellowing phenomenon. In addition, the auxiliary structure can be formed at the same time as the gate or source / drain, without adding additional process steps.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

1, 2, 3, 4‧‧‧ transparent display panel

10, 12, 14, 16, 18, 20‧‧‧ opening

100‧‧‧ substrate

101‧‧‧First gate insulation

101a‧‧‧The first gate insulation layer outside the transparent area

101b‧‧‧The first gate insulation layer in the transparent area

102‧‧‧Active Level

103‧‧‧Second gate insulation layer

104‧‧‧Gate insulation

106‧‧‧Gate

108‧‧‧First interlayer insulation

108a‧‧‧The first interlayer insulation layer outside the transparent area

108b‧‧‧The first interlayer insulation in the transparent area

110‧‧‧Second interlayer insulation layer

112‧‧‧ conductive layer

114‧‧‧Source

116‧‧‧ Drain

118, 118a, 118b, 118c, 118d, 118e, 118f, 218‧‧‧ auxiliary structures

120‧‧‧ Third interlayer insulation

122‧‧‧Photoresist pattern

124‧‧‧ Fourth interlayer insulation

126‧‧‧pixel definition layer

128‧‧‧ lower electrode

130‧‧‧electroluminescent layer

132‧‧‧up electrode

C‧‧‧Capacitor

D‧‧‧ Data Line

EL‧‧‧ EL

S‧‧‧scan line

P‧‧‧Pixel Unit

PC‧‧‧Pixel Circuit Unit

R1‧‧‧Development area

R2‧‧‧ transparent area

R2’‧‧‧ scheduled transparent area

T1, T2, T3, T4‧‧‧thickness

TR‧‧‧Thin Film Transistor

TR1‧‧‧The first thin film transistor

TR2‧‧‧Second Thin Film Transistor

Vdd‧‧‧ Power Cord

1A to 1F are schematic diagrams of a manufacturing process of a transparent display panel according to a first embodiment of the present invention. FIG. 2 is a schematic diagram of a pixel circuit unit of a transparent display panel according to a first embodiment of the present invention. 3 is a schematic cross-sectional view of a transparent display panel according to a second embodiment of the present invention. 4 is a schematic cross-sectional view of a transparent display panel according to a third embodiment of the present invention. 5 is a schematic cross-sectional view of a transparent display panel according to a fourth embodiment of the present invention.

Claims (20)

A manufacturing method of a transparent display panel includes: forming an active layer on a substrate; forming a gate insulating layer on the active layer; forming a gate electrode on the gate insulating layer; forming a first interlayer insulating layer on The gate electrode and the gate insulating layer; forming a second interlayer insulating layer on the first interlayer insulating layer; forming an auxiliary structure on the second interlayer insulating layer; forming a source electrode and a drain electrode on the A second interlayer insulating layer is electrically connected to the active layer, respectively; a third interlayer insulating layer is formed on the source and the drain, and extends to cover the auxiliary structure; using the auxiliary structure as an etch stop layer, remove A part of the third interlayer insulating layer and a part of the second interlayer insulating layer to expose the first interlayer insulating layer in a predetermined transparent area; forming a fourth interlayer insulating layer on the third interlayer insulating layer, At least a part of the fourth interlayer insulating layer is located in the predetermined transparent area; a lower electrode is formed on the fourth interlayer insulating layer and is electrically connected to the drain electrode; and a pixel definition layer is formed between the fourth interlayer. On the edge layer, wherein at least a part of the pixel definition layer is located in the predetermined transparent area, the pixel definition layer has an opening in a developing area; forming an electroluminescent layer in the opening; and forming an upper electrode On the electroluminescent layer. The method for manufacturing a transparent display panel according to item 1 of the scope of patent application, wherein the step of forming the auxiliary structure on the second interlayer insulating layer includes: forming an auxiliary layer on the second interlayer insulating layer; and patterning The auxiliary layer exposes the second interlayer insulating layer, thereby forming the auxiliary structure to define the predetermined transparent area. The method for manufacturing a transparent display panel according to item 1 of the scope of patent application, wherein the auxiliary structure is a single box, a single round frame, a single cross, multiple bars, multiple round frames, multiple squares Box or combination. The method for manufacturing a transparent display panel according to item 1 of the scope of patent application, wherein the auxiliary structure is used as an etching stop layer, and the step of removing the portion of the third interlayer insulating layer and the portion of the second interlayer insulating layer The method includes: forming a photoresist pattern on the third interlayer insulating layer; and using the photoresist pattern as a mask, removing the part of the third interlayer insulating layer, the part of the second interlayer insulating layer, and the first A part of the interlayer insulating layer such that the thickness of the first interlayer insulating layer outside the predetermined transparent region is T1, and the thickness of the remaining first interlayer insulating layer located in the predetermined transparent region is T2,200 Nanometer ≦ T1 ≦ 400 nanometer and 20 nanometer ≦ T2 ≦ 100 nanometer. The method for manufacturing a transparent display panel according to item 4 of the scope of patent application, wherein the auxiliary structure is used as an etching stop layer, and the step of removing the portion of the third interlayer insulating layer and the portion of the second interlayer insulating layer After that, the fourth interlayer insulating layer directly contacts the remaining first interlayer insulating layer. The method for manufacturing a transparent display panel according to item 4 of the scope of patent application, wherein the auxiliary structure is used as an etching stop layer, and the step of removing the portion of the third interlayer insulating layer and the portion of the second interlayer insulating layer The method includes: removing a portion of the fourth interlayer insulating layer to expose the first interlayer insulating layer in the predetermined transparent area, and the pixel definition layer directly contacts the remaining first interlayer insulating layer. The method for manufacturing a transparent display panel according to item 1 of the scope of patent application, wherein the material of the first interlayer insulating layer is silicon oxide or silicon nitride, and the material of the second interlayer insulating layer is silicon Nitride or silicon oxide. The method for manufacturing a transparent display panel according to item 1 of the scope of patent application, wherein the material of the auxiliary structure includes metal, metal oxide, organic compound, or a combination thereof, and the thickness of the auxiliary structure is 400 nm to 700 nm . The manufacturing method of the transparent display panel according to item 1 of the scope of patent application, wherein the etching selection ratio of the auxiliary structure to the third interlayer insulating layer is 3% to 8%; The etching selection ratio is 2% to 5%. The method for manufacturing a transparent display panel according to item 1 of the scope of patent application, wherein the auxiliary structure, the source electrode and the drain electrode are formed by patterning the same film layer. A transparent display panel includes: an active layer on a substrate; a gate insulation layer on the active layer; a gate electrode on the gate insulation layer; a first interlayer insulation layer on the gate electrode and the gate insulation A second interlayer insulating layer is located on the first interlayer insulating layer; an auxiliary structure is located on the gate insulating layer and defines a transparent area, wherein the auxiliary structure has a thickness of 400 nm to 700 nm; A source and a drain are located on the second interlayer insulating layer and are electrically connected to the active layer, respectively; a third interlayer insulating layer is positioned on the source and the drain electrode; a fourth interlayer insulating layer is positioned between the third layer On the insulating layer; and an electroluminescent element is on the fourth interlayer insulating layer. The transparent display panel according to item 11 of the scope of patent application, further comprising a pixel definition layer on the fourth interlayer insulating layer, wherein the auxiliary structure is further located on the second interlayer insulating layer and located outside the transparent area. The thickness of the first interlayer insulating layer is T1, and the thickness of the first interlayer insulating layer in the transparent region is T2, 200 nm ≦ T1 ≦ 400 nm and 20 nm ≦ T2 ≦ 100 nm, The fourth interlayer insulating layer or the pixel defining layer is in contact with the first interlayer insulating layer in the transparent region. The transparent display panel according to item 11 of the scope of patent application, further comprising a pixel definition layer on the fourth interlayer insulating layer, wherein the auxiliary structure is located between the gate insulating layer and the first interlayer insulating layer, The gate insulating layer includes a first gate insulating layer on the active layer and a second gate insulating layer on the first gate insulating layer. The thickness of the first gate insulating layer outside the transparent region is T3. The thickness of the first gate insulation layer in the transparent region is T4, 200 nm ≦ T3 ≦ 450 nm and 20 nm ≦ T4 ≦ 150 nm. The fourth interlayer insulation layer or the pixel definition layer is The transparent region is in contact with the first gate insulating layer. The transparent display panel according to item 11 of the scope of patent application, wherein the material of the auxiliary structure includes metal, metal oxide, organic compound, or a combination thereof, and the auxiliary structure is a single box, a single round frame, a single The material of the first interlayer insulating layer is a cross, a plurality of bars, a plurality of round frames, a plurality of boxes, or a combination thereof, and the material of the second interlayer insulating layer is silicon oxide or silicon nitride. Silicon nitride or silicon oxide. A manufacturing method of a transparent display panel includes: forming an active layer on a substrate; forming a first gate insulating layer on the active layer; forming a second gate insulating layer on the first gate insulating layer; forming a A gate electrode and an auxiliary structure on the second gate insulating layer; forming a first interlayer insulating layer on the gate electrode, the second gate insulating layer and the auxiliary structure; forming a second interlayer insulating layer on the first gate insulating layer; Forming an interlayer insulating layer; forming a source electrode and a drain electrode on the second interlayer insulating layer and being electrically connected to the active layer respectively; forming a third interlayer insulating layer on the source electrode, the drain electrode and the On the second interlayer insulating layer; using the auxiliary structure as an etch stop layer, removing a part of the third interlayer insulating layer, a part of the second interlayer insulating layer, a part of the first interlayer insulating layer, and the second gate A part of the insulating layer to expose the first gate insulating layer in a predetermined transparent area; forming a fourth interlayer insulating layer on the third interlayer insulating layer, wherein at least a part of the fourth interlayer insulating layer is located in the predetermined through Bright area; forming a lower electrode on the fourth interlayer insulating layer and electrically connecting to the drain electrode; forming a pixel defining layer on the fourth interlayer insulating layer, wherein at least a part of the pixel defining layer is located in the A predetermined transparent area, the pixel defining layer having an opening in a developing area; forming an electroluminescent layer in the opening; and forming an upper electrode on the electroluminescent layer. The method for manufacturing a transparent display panel according to item 15 of the scope of patent application, wherein the auxiliary structure is used as an etch stop layer, the part of the third interlayer insulating layer, the part of the second interlayer insulating layer, the The step of the part of the first interlayer insulating layer and the part of the second gate insulating layer includes: forming a photoresist pattern on the third interlayer insulating layer; and using the photoresist pattern as a mask, removing the The portion of the third interlayer insulating layer, the portion of the second interlayer insulating layer, the portion of the first interlayer insulating layer, the portion of the second gate insulating layer, and a portion of the first gate insulating layer such that The thickness of the first gate insulation layer outside the predetermined transparent area is T3, and the thickness of the remaining first gate insulation layer located in the predetermined transparent area is T4, 200 nm ≦ T3 ≦ 450 nm and 20 nm ≦ T4 ≦ 150 nm. The method for manufacturing a transparent display panel according to item 16 of the scope of patent application, wherein the auxiliary structure is used as an etch stop layer, the part of the third interlayer insulating layer, the part of the second interlayer insulating layer, the After the steps of the part of the first interlayer insulating layer and the part of the second gate insulating layer, the fourth interlayer insulating layer directly contacts the remaining first gate insulating layer. The method for manufacturing a transparent display panel according to item 16 of the scope of patent application, wherein the auxiliary structure is used as an etch stop layer, the part of the third interlayer insulating layer, the part of the second interlayer insulating layer, the The step of the portion of the first interlayer insulating layer and the portion of the second gate insulating layer includes: removing a portion of the fourth interlayer insulating layer to expose the first gate insulating layer in the predetermined transparent region, and The pixel definition layer directly contacts the remaining first gate insulating layer. The method for manufacturing a transparent display panel according to item 15 of the scope of patent application, wherein an etching selection ratio of the auxiliary structure to the third interlayer insulating layer is 3% to 8%; The etching selection ratio is 2% to 5%. The method for manufacturing a transparent display panel according to item 15 of the scope of the patent application, wherein the auxiliary structure and the gate electrode are formed by patterning the same film layer.