TW201944549A - Electronic package and method for fabricating the same - Google Patents

Abstract

An electronic package and a fabrication method of the same are proposed, in which a first shield layer and a first electronic element are provided on a first side of a carrier structure, and a second electronic and a packaging layer encapsulating said second electronic element are provided on a second side of said carrier structure, and then a second shield layer is disposed on said packaging layer to prevent interference between electromagnetic radiation from said first and second electronic elements by the design of said first and second shield layers so as to enhance the reliability of said electronic package.

Description

   Electronic package and manufacturing method thereof   

The invention relates to a semiconductor manufacturing process, in particular to an electronic package and a manufacturing method thereof.

With the vigorous development of the electronics industry, electronic products are gradually moving towards multifunctional and high performance. Among them, the technologies used in the chip packaging field include chip scale packaging (CSP), and direct chip packaging (Direct Chip Attached (DCA) or Multi-Chip Module (MCM)) and other flip-chip packaging modules, or three-dimensional stacking of the chips into a three-dimensional integrated circuit (3D IC) chip Stacking technology, etc.

FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package 1 of a 3D IC chip stack. The semiconductor package 1 includes a Through Silicon Interposer (TSI) 10. The Silicon Intermediate Board 10 has an opposite crystal side 10a and a substrate. The connection side 10b and a plurality of through-silicon vias (TSV) 100 connecting the crystal-side 10a and the transfer side 10b, and a redistribution layer (redistribution layer) is formed on the transfer side 10b. (Abbreviated as RDL) 101 in order to electrically bond the electrode pads 190 of the semiconductor wafer 19 with a small pitch to the crystal placement side 10a by a plurality of solder bumps 102, and then cover the solder bumps 102 with a primer 192, Furthermore, a packaging colloid 18 is formed on the silicon interposer 10 to cover the semiconductor wafer 19, and on the circuit redistribution layer 101, a plurality of conductive elements 103 such as bumps are electrically coupled to the packaging substrate 17 with a larger pitch. The pads 170 are covered with a primer 172 to the conductive elements 103.

Furthermore, when the semiconductor package 1 is manufactured, the semiconductor wafer 19 is first placed on the silicon interposer 10, and then the silicon interposer 10 is connected to the package substrate 17 with the conductive elements 103. The encapsulating gel 18 is then formed.

In addition, in the subsequent assembly process of applying the semiconductor package 1, the semiconductor package 1 is bonded to a circuit board (not shown) through the lower side of the package substrate 17 to use the conductive silicon through-holes 100 as the The medium for signal transmission between the semiconductor wafer 19 and the circuit board.

However, in the conventional method of manufacturing the semiconductor package 1, when the semiconductor wafer 19 is a high-contact (I / O) functional chip with a thin line width and a line pitch, the silicon interposer 10 is used as the semiconductor wafer 19 and the For the medium of signal transmission between the packaging substrates 17, the silicon interposer 10 needs to have a certain aspect ratio control (that is, the conductive silicon perforation 100 has an aspect ratio of 100um / 10um) in order to produce a suitable silicon interposer 10 Therefore, a large amount of process time and the cost of chemical agents are often consumed, thereby increasing the difficulty and cost of the process.

Furthermore, because the semiconductor wafer 19 needs to be transferred to the circuit board through the silicon interposer 10 and the packaging substrate 17, and the packaging substrate 17 has a core layer containing a glass fiber material, the thickness of the packaging substrate 17 is quite thick. Therefore, it is not conducive to the thinness and shortness of terminal electronic products.

In addition, when the semiconductor wafer 19 is a high-contact (I / O) functional chip with a thin line width and a fine pitch, the area of the layout of the silicon interposer 10 needs to be increased to connect multiple functional chips to the silicon interposer. On the same side of the board 10, the area of the layout of the corresponding packaging substrate 17 is also increased, which is not conducive to reducing the thickness and thickness of the terminal electronic product.

Furthermore, even if the packaging substrate 17 with a core layer containing glass fiber material is avoided, and a high-contact (I / O) function chip is connected to the circuit layer, in order to achieve the purpose of reducing the overall thickness, some After frequent operation, electromagnetic radiation is generated, and for wafers arranged on both sides of the circuit layer, only a few thin circuit layers are separated. This electromagnetic radiation will seriously affect the operation of other chips.

Therefore, how to overcome the problems of the above-mentioned conventional technologies has become an issue that is urgently sought to be solved at present.

In view of the above-mentioned shortcomings of various conventional technologies, the present invention provides an electronic package including: a load-bearing structure having a first side and a second side opposite to each other and including a circuit layer; and a first shielding layer provided on the The first electronic component is provided on the first side of the bearing structure and is electrically connected to the circuit layer; the second electronic component is provided on the second side of the bearing structure and is electrically connected The circuit layer is electrically connected; the packaging layer is provided on the second side of the carrier structure to cover the second electronic component; and the second shielding layer is provided on the packaging layer.

The invention also provides a method for manufacturing an electronic package, comprising: providing a supporting structure having opposite first and second sides and including a circuit layer; and providing a first on a first side of the supporting structure The shielding layer and the first electronic component, and the first electronic component is electrically connected to the circuit layer; a second electronic component is disposed on the second side of the bearing structure, and the second electronic component is electrically connected to the circuit layer Forming a packaging layer on the second side of the carrier structure to cover the second electronic component; and forming a second shielding layer on the packaging layer.

In the aforementioned electronic package and its manufacturing method, the first shielding layer is not in contact with the first electronic component.

In the aforementioned electronic package and its manufacturing method, the first shielding layer is not electrically connected to the circuit layer.

In the aforementioned electronic package and its manufacturing method, the first shielding layer is formed by depositing a plurality of conductive particles.

In the aforementioned electronic package and its manufacturing method, the second shielding layer is not electrically connected to the circuit layer.

In the aforementioned electronic package and its manufacturing method, the second shielding layer is electrically connected to the circuit layer.

In the aforementioned electronic package and its manufacturing method, the second shielding layer is formed by depositing a plurality of conductive particles.

In the aforementioned electronic package and its manufacturing method, the packaging layer has a recessed portion exposing the second side, and the second shielding layer is reset in the recessed portion, so that the second shielding layer is set on top of the packaging layer. Face and side.

In the foregoing electronic package and its manufacturing method, the method further includes covering the first electronic component with a covering layer on a first side of the supporting structure.

In the foregoing electronic package and its manufacturing method, the method further includes forming a conductive element on the first shielding layer.

In the foregoing electronic package and manufacturing method thereof, the method further includes forming a conductive element on the circuit layer to electrically connect the circuit layer.

As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly replace the conventional silicon interposer with the carrier structure as the medium for signal transmission between the external device and the first or second electronic component, so compared with According to the conventional technology, the present invention does not need to make TSV, thus greatly reducing the difficulty and cost of the process.

Furthermore, the present invention directly attaches a high I / O function chip (such as the first and second electronic components) to the carrier structure, so there is no need to use a package substrate including a core layer and a TSV Silicon interposer, so compared with the conventional technology, the thickness of the electronic package of the present invention can be greatly reduced.

In addition, when the first and second electronic components are high-contact functional chips with thin line width and space, the first and second electronic components are respectively connected to the first side and the second of the carrier structure. The side design, so as not to increase the area of the layout of the load-bearing structure, therefore, compared with the conventional technology, the present invention can help reduce the weight, thickness, and shortness of terminal electronic products.

In addition, through the design of the first and second shielding layers, the electromagnetic radiation of the first and second electronic components will not affect each other, so the problem of poor operation of the chip can be avoided, and the reliability of the electronic package can be improved. degree.

1‧‧‧ semiconductor package

10‧‧‧ Silicon Interposer

10a‧‧‧Set crystal side

10b‧‧‧ transfer side

100‧‧‧Conductive Silicon Perforation

101‧‧‧ route redistribution layer

102‧‧‧solder bump

103,27,27’‧‧‧ conductive element

17‧‧‧ package substrate

170‧‧‧pad

172,192‧‧‧primer

18‧‧‧ encapsulated colloid

19‧‧‧Semiconductor wafer

190,210‧‧‧electrode pads

2,2’‧‧‧electronic package

2a‧‧‧Package Unit

20,20’‧‧‧ coating

200‧‧‧perforation

21‧‧‧The first electronic component

21a‧‧‧active surface

21b‧‧‧ non-active surface

22,22’‧‧‧first shielding layer

22a, 26a‧‧‧ conductive particles

220‧‧‧open area

23‧‧‧bearing structure

23a‧‧‧first side

23b‧‧‧Second side

230‧‧‧ Dielectric layer

231‧‧‧line layer

232‧‧‧Conductive blind hole

24‧‧‧Second electronic component

240‧‧‧Conductive bump

25‧‧‧Encapsulation Layer

25a‧‧‧Top

25c‧‧‧side

250‧‧‧ Recess

26,260‧‧‧Second shielding layer

S‧‧‧ cutting path

Figure 1 is a schematic sectional view of a conventional semiconductor package; Figures 2A to 2G are schematic sectional views of a method for manufacturing an electronic package of the present invention; Figure 2A 'is a schematic diagram of a partial process of Figure 2A; and 2C 'Figure is a schematic diagram of another embodiment of Figure 2C; Figure 2E' is a schematic diagram of a partial process of Figure 2E; and Figure 2G 'is a schematic diagram of another embodiment of Figure 2G.

The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The limited conditions are not technically significant. Any modification of the structure, change of the proportional relationship, or adjustment of the size should still fall within the scope of this invention without affecting the effects and goals that can be achieved by the present invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of description, and are not intended to limit the scope of the present invention. Changes or adjustments in their relative relationships shall be considered to be the scope of the present invention without substantial changes in the technical content.

2A to 2G are schematic cross-sectional views of a method for manufacturing the electronic package 2 according to the present invention.

As shown in FIG. 2A, a cladding layer 20 embedded with a plurality of first electronic components 21 is provided, and a first shielding layer 22 is formed on the cladding layer 20 and the first electronic component 21.

In this embodiment, the material forming the coating layer 20 is polyimide (PI), dry film, epoxy, or packaging material.

Furthermore, the first electronic component 21 is an active component, a passive component, or a combination thereof, wherein the active component is, for example, a semiconductor wafer, and the passive component is, for example, an antenna, a resistor, a capacitor, and an inductor. For example, the first electronic component 21 is a semiconductor wafer, which has opposite active surfaces 21a and non-active surfaces 21b, and the active surface 21a is exposed from the coating layer 20 and has a plurality of electrode pads 210.

In addition, the plurality of conductive particles 22a are flatly formed on the coating by a deposition method such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD) or sputtering. On the active surface 21a of the layer 20 and the first electronic component 21 (as shown in FIG. 2A ′), the conductive particles 22a are used as the first shielding layer 22.

As shown in FIG. 2B, a plurality of opening areas 220 are formed on the first shielding layer 22 so that part of the opening areas 220 exposes the active surfaces 21a of the first electronic components 21, so that the first shielding layer 22 does not contact the first An active surface 21 a of an electronic component 21.

In this embodiment, the opening regions 220 are formed on the first shielding layer 22 by etching a metal material.

As shown in FIG. 2C, a bearing structure 23 having a first side 23 a and a second side 23 b opposite to each other is formed on the active surface 21 a of the first shielding layer 22 and the first electronic component 21.

In this embodiment, the supporting structure 23 is bonded to the cladding layer 20 with its first side 23a to contact and bond the first shielding layer 22 and the first electronic component 21, so that the first shielding layer 22 is sandwiched. Between the first side 23 a of the supporting structure 23 and the cladding layer 20.

Furthermore, the supporting structure 23 can be formed by a redistribution layer (RDL) process. Specifically, the carrier structure 23 has at least one dielectric layer 230 and at least one circuit layer 231 formed in the dielectric layer 230, and the circuit layer 231 is electrically connected to the first electronic component through a conductive blind hole 232. 21 electrode pad 210, and the first shielding layer 22 is not electrically connected to the circuit layer 231. Alternatively, the opening area 220 of the first shielding layer 22 may also expose each of the electrode pads 210, so that the first shielding layer 22 'contacts a part of the active surface 21a without contacting the electrode pads 210, as shown in FIG. 2C' As shown, the circuit layer 231 is electrically connected to the electrode pad 210 through the conductive blind hole 232.

As shown in FIG. 2D, following the process of FIG. 2C, a plurality of second electronic components 24 are disposed on the second side 23b of the carrier structure 23, and an encapsulation layer 25 is formed on the second side 23b of the carrier structure 23. In order to make the packaging layer 25 cover the second electronic components 24. Next, a plurality of recessed portions 250 are formed on the encapsulation layer 25 to expose a part of the surface of the second side 23 b of the supporting structure 23.

In this embodiment, the second electronic component 24 is an active component, a passive component, or a combination thereof, wherein the active component is, for example, a semiconductor wafer, and the passive component is, for example, an antenna, a resistor, a capacitor, and an inductor.

In addition, the second electronic component 24 is electrically connected to the circuit layer 231 in a flip-chip manner through a plurality of conductive bumps 240; or, the second electronic component 24 may also be electrically connected to the circuit layer in a wired manner (not shown).线 层 231。 Line layer 231. It should be understood that there are various types of ways for the second electronic component 24 to be electrically connected to the circuit layer 231, and are not limited to the above.

In addition, the material forming the packaging layer 25 is polyimide (PI), dry film, epoxy, or packaging material, and the materials of the packaging layer 25 and the coating layer 20 may be Same or different.

In addition, the recessed portion 250 is formed on the packaging layer 25 by a laser cutting method to separate a plurality of packaging units 2 a.

As shown in FIG. 2E, second shielding layers 26 and 260 are formed on the top surface 25 a and the side surface 25 c of the packaging layer 25 and in the recess 250.

In this embodiment, a plurality of conductive particles 26a are formed on the encapsulation layer 25 and the recess 250 by using a deposition method such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or sputtering. As shown in FIG. 2E ′), the conductive particles 26 a are used as the second shielding layers 26, 260, and the second shielding layers 26, 260 are not electrically connected to the circuit layer 231. In another embodiment, since the second shielding layer 26, 260 cannot extend to the side of the carrying structure 23, it should be understood that the second shielding layer 260 in the recess 250 can be electrically connected to the circuit layer 231 as required. A part of the circuit surface exposed on the second side 23b (not shown).

As shown in FIG. 2F, a plurality of conductive elements 27, 27 'are formed on the cladding layer 20, so that some of the conductive elements 27 contact and are electrically connected to the first shielding layer 22.

In this embodiment, the conductive elements 27, 27 'are solder balls, metal bumps or metal pins.

Furthermore, the conductive element 27, 27 'is manufactured by forming a plurality of through-holes 200 on the cladding layer 20 exposing the first shielding layer 22 and the circuit layer 231, and then forming the conductive elements 27 in the through-holes 200. , Part of the conductive element 27 is extended into the cladding layer 20 to be electrically connected (or grounded) to the first shielding layer 22, and another part of the conductive element 27 ′ is passed through (not in contact with) the first shielding layer 22 (Another open region 220) is electrically connected to the circuit layer 231.

As shown in FIG. 2G, a singulation process is performed along the cutting path S shown in FIG. 2F to obtain a plurality of electronic packages 2 of the present invention.

In this embodiment, the cutting path S can correspond to the recess 250, and the electronic package 2 can be bonded to an external device (not shown) like a circuit board through the conductive elements 27, 27 '.

Furthermore, before the conductive elements 27, 27 'are formed, a leveling process may be performed on the cladding layer 20', as shown in FIG. 2G ', and the first electronic component 21 is rendered non-functional as shown in the grinding method. The surface 21b exposes (eg flushes) the surface of the cladding layer 20 ', and then performs a singulation process to obtain a plurality of electronic packages 2' of the present invention.

The manufacturing method of the present invention is to replace the conventional silicon interposer with the carrier structure 23 and use the conductive elements 27, 27 'as signals between the external device (circuit board) and the first electronic component 21 or the second electronic component 24. Compared with the conventional technology, the manufacturing method of the present invention does not need to make TSV, thus greatly reducing the difficulty and cost of the process.

Furthermore, the manufacturing method of the present invention is to directly place a high I / O function wafer (such as the first electronic component 21 and the second electronic component 24) on the carrier structure 23, so there is no need to use a core layer-containing chip. The packaging substrate and a silicon interposer with TSV, compared with the conventional technology, the manufacturing method of the present invention can reduce the thickness of the electronic package 2,2 '.

In addition, when the first electronic component 21 and the second electronic component 24 are high-contact (I / O) functional chips with thin line width and line pitch, the first electronic component 21 and the second electronic component 24 are respectively separated. The design of the first side 23a and the second side 23b connected to the supporting structure 23 does not need to increase the area of the layout of the supporting structure 23, which is conducive to reducing the thickness, thickness and shortening of the terminal electronic products.

In addition, the second shielding layer 26, 260 covers the encapsulation layer 25, so that the electromagnetic radiation of the second electronic component 24 (such as a chip, an antenna, etc.) is not affected by the outside world, so that the problem of poor operation of the chip can be avoided, and Can improve the reliability of the electronic package 2,2 '. On the other hand, by designing that the first shielding layer 22, 22 'surrounds the area other than the first electronic component 21, and that the first shielding layer 22, 22' does not contact the design of the first electronic component 21, The electromagnetic radiation of the first and second electronic components 21, 24 (such as wafers, antennas, etc.) will not affect each other, so the problem of poor operation of the wafers can be avoided, and the reliability of the electronic packages 2, 2 'can be improved .

The present invention further provides an electronic package 2, 2 ', comprising: a carrier structure 23, a first shielding layer 22, 22', at least a first electronic component 21, at least a second electronic component 24, and a packaging layer. 25 and a second shielding layer 26,260.

The supporting structure 23 has a first side 23 a and a second side 23 b opposite to each other, and the supporting structure 23 includes at least one circuit layer 231.

The first shielding layers 22, 22 ′ are flatly attached to the first side 23 a of the supporting structure 23.

The first electronic component 21 is disposed on the first side 23 a of the supporting structure 23 and is electrically connected to the circuit layer 231.

The second electronic component 24 is disposed on the second side 23 b of the supporting structure 23 and is electrically connected to the circuit layer 231.

The packaging layer 25 is disposed on the second side 23 b of the supporting structure 23 to cover the second electronic component 24.

The second shielding layers 26 and 260 are disposed on the packaging layer 25.

In one embodiment, the first shielding layer 22 is not in contact with the first electronic component 21.

In one embodiment, the first shielding layers 22, 22 'are not electrically connected to the circuit layer 231.

In one embodiment, the first shielding layers 22, 22 'are conductive layers.

In one embodiment, the second shielding layer 26, 260 is not electrically connected to the circuit layer 231.

In one embodiment, the second shielding layer 260 is electrically connected to the circuit layer 231.

In one embodiment, the second shielding layer 26 is a conductive layer.

In one embodiment, the second shielding layer 26 is disposed on the top surface 25 a and the side surface 25 c of the packaging layer 25.

In an embodiment, the electronic package 2, 2 ′ includes a cladding layer 20, 20 ′, which is coupled to the first side 23 a of the carrier structure 23 to cover the first electronic component 21, The non-active surface 21b of the first electronic component 21 can be exposed (or flush) with the outer surface of the coating layer 20 'according to requirements.

In an embodiment, the electronic package 2, 2 ′ includes a plurality of conductive elements 27 formed on the first shielding layer 22, 22 ′, penetrating through the cladding layers 20, 20 ′ and protruding. Surfaces of the cladding layers 20, 20 '.

In an embodiment, the electronic package 2, 2 ′ includes a plurality of conductive elements 27 ′, which are formed on the circuit layer 231 to electrically connect the circuit layer 231 and pass through the cladding layer 20, 20 'and the first shielding layer 22, 22' and protrude from the surface of the cladding layer 20, 20 '.

In summary, the electronic package and its manufacturing method of the present invention replace the conventional silicon interposer with the carrier structure as the medium for signal transmission between the external device and the first or second electronic component. The invention does not need to make a TSV, thereby greatly reducing the difficulty and cost of the process.

Furthermore, a high I / O function chip (such as the first and second electronic components) is connected to the carrier structure, so it is not necessary to use a package substrate containing a core layer and a silicon interposer with TSV. Therefore, the thickness of the electronic package can be reduced.

In addition, by designing the first and second electronic components respectively connected to the first side and the second side of the supporting structure, there is no need to increase the area of the layout of the supporting structure, which is beneficial to the thinness and thinness of the terminal electronic products. Shortened.

In addition, the design that the second shielding layer covers the encapsulation layer and that the first shielding layer surrounds the area outside the first electronic component makes the electromagnetic radiation of the first and second electronic components not affect each other. Therefore, the problem of poor operation of the chip can be avoided, and the reliability of the electronic package can be improved.

The above embodiments are used to exemplify the principle of the present invention and its effects, but not to limit the present invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

Claims (20)

    An electronic package includes: a bearing structure having first and second sides opposite to each other, and the bearing structure includes a circuit layer; a first shielding layer is provided on the first side of the bearing structure; An electronic component is provided on the first side of the carrier structure and is electrically connected to the circuit layer; a second electronic component is provided on the second side of the carrier structure and is electrically connected to the circuit layer; a packaging layer, The second shielding layer is disposed on the second side of the supporting structure to cover the second electronic component. The second shielding layer is disposed on the packaging layer.         The electronic package as described in claim 1, wherein the first shielding layer is not in contact with the first electronic component.         The electronic package according to item 1 of the scope of patent application, wherein the first shielding layer is not electrically connected to the circuit layer.         The electronic package according to item 1 of the scope of patent application, wherein the second shielding layer is not electrically connected to the circuit layer.         The electronic package according to item 1 of the scope of patent application, wherein the second shielding layer is electrically connected to the circuit layer.         The electronic package according to item 1 of the scope of patent application, wherein the second shielding layer is disposed on a top surface and a side surface of the packaging layer.         The electronic package according to item 1 of the patent application scope, further comprising a coating layer bonded to the first side of the carrier structure to cover the first electronic component.         The electronic package according to item 1 of the patent application scope, further comprising a conductive element formed on the first shielding layer.         The electronic package according to item 1 of the scope of patent application, further comprising a conductive element formed on the circuit layer to electrically connect the circuit layer.         An electronic package manufacturing method includes: providing a supporting structure having opposite first and second sides and including a circuit layer; and providing a first shielding layer and a first on a first side of the supporting structure An electronic component, and the first electronic component is electrically connected to the circuit layer; a second electronic component is disposed on the second side of the carrier structure, and the second electronic component is electrically connected to the circuit layer; and a packaging layer is formed on The second side of the supporting structure is used for covering the second electronic component; and a second shielding layer is formed on the encapsulation layer.         According to the manufacturing method of the electronic package described in item 10 of the patent application scope, wherein the first shielding layer is not in contact with the first electronic component.         According to the manufacturing method of the electronic package described in item 10 of the patent application scope, wherein the first shielding layer is not electrically connected to the circuit layer.         According to the method for manufacturing an electronic package described in item 10 of the scope of patent application, wherein the first shielding layer is formed by depositing a plurality of conductive particles.         According to the manufacturing method of the electronic package described in item 10 of the patent application scope, wherein the second shielding layer is not electrically connected to the circuit layer.         According to the manufacturing method of the electronic package described in item 10 of the patent application scope, wherein the second shielding layer is electrically connected to the circuit layer.         According to the manufacturing method of the electronic package described in item 10 of the scope of the patent application, wherein the second shielding layer is formed by depositing a plurality of conductive particles.         According to the manufacturing method of the electronic package described in item 10 of the scope of the patent application, wherein the packaging layer has a recessed portion exposing the second side, and the second shielding layer is reset in the recessed portion.         According to the manufacturing method of the electronic package described in item 10 of the scope of patent application, the method further includes covering the first electronic component with a covering layer on the first side of the supporting structure.         According to the manufacturing method of the electronic package described in item 10 of the patent application scope, the method further includes forming a conductive element on the first shielding layer.         According to the manufacturing method of the electronic package described in item 10 of the scope of patent application, the method further includes forming a conductive element on the circuit layer to electrically connect the circuit layer.