TW201944190A - Low dropout voltage regulator - Google Patents

Abstract

A low dropout voltage regulator incorporates an N-channel MOS pass transistor, a main error amplifier, a first buffer circuit, an auxiliary error amplifier, a second buffer circuit, and a decision circuit. The auxiliary error amplifier consumes less bias current. In one embodiment, the decision circuit compares the portion of the output voltage with a bias voltage to control the gate of the N-channel MOS pass transistor, wherein the value of the bias voltage is less than the value of the reference voltage.

Description

   Low Dropout Voltage Regulator   

The present invention relates to a low dropout voltage regulator, and more particularly, to a low dropout regulator with a controllable slow-start mechanism.

The low dropout voltage regulator is a DC linear voltage regulator with a small difference between the input and output voltages. The advantages of low-dropout voltage regulators include low power supply voltage, high operating efficiency, and low heat consumption. The components of a typical low-dropout voltage regulator include a power transistor and an error amplifier. Through the negative feedback loop formed by the power transistor and the error amplifier, the low dropout voltage regulator can maintain a stable output voltage value.

However, if the low-dropout voltage regulator is not well controlled during the initial supply of the power supply voltage, it may damage internal components or cause damage to the load. For example, during the slow start, if the error amplifier detects that the output voltage has not reached the expected voltage value, the power transistor will be over-driven to generate an inrush current, or the output voltage is at the end of the slow start A voltage overshoot occurs. Both inrush current and voltage overshoot can cause damage to the internal components of the LDO regulator or to the load. Therefore, it is necessary to provide a low dropout voltage regulator with a controllable slow start mechanism to solve the above problems.

A low dropout voltage regulator according to an embodiment of the present invention includes a main error amplifier, an auxiliary error amplifier, a first buffer circuit, a second buffer circuit, a control circuit, and an N-channel power transistor. The N-channel power transistor has a drain for receiving a power voltage and a source for generating an output voltage. The main error amplifier has a positive input terminal for receiving a feedback voltage proportional to the output voltage, a negative input terminal for receiving a reference voltage, and an amplified output terminal. The first buffer circuit is coupled between the amplified output terminal of the main error amplifier and a gate of the N-channel power transistor. The auxiliary error amplifier has a first positive input terminal for receiving the feedback voltage proportional to the output voltage, a second positive input terminal, a negative input terminal for receiving the reference voltage, and an amplified output terminal. . The second buffer circuit is coupled between the amplified output terminal of the auxiliary error amplifier and the gate of the N-channel power transistor. The control circuit is used to compare the voltage value of the feedback voltage proportional to the output voltage with the voltage value of a bias voltage to control the gate of the N-channel power transistor. The auxiliary error amplifier consumes less current than the main error amplifier. The voltage value of the reference voltage is greater than the voltage value of the bias voltage.

100,100’‧‧‧‧Low Dropout Voltage Regulator

12‧‧‧The first buffer circuit

14‧‧‧Second buffer circuit

144‧‧‧first output stage

146‧‧‧Second output stage

16,16’‧‧‧Control circuit

162‧‧‧Output stage

18‧‧‧Voltage Dividing Circuit

CMP‧‧‧ Comparator

C1, C2‧‧‧Capacitors

CL‧‧‧Capacitor

I1, I3‧‧‧ current source

M2, M6‧‧‧P channel transistor

M3, M4, M7‧‧‧‧N-channel transistors

MN‧‧‧N channel power transistor

OP1‧‧‧Main Error Amplifier

OP2‧‧‧Auxiliary Error Amplifier

R1, R2‧‧‧Resistance

X2‧‧‧Enable element

The first figure shows a block diagram of a low dropout voltage regulator combined with an embodiment of the present invention.

The second figure shows a circuit diagram of a low-dropout voltage regulator combined with another embodiment of the present invention.

The third figure shows a circuit diagram of a control circuit incorporating an embodiment of the present invention.

Certain terms are used in the description and the scope of subsequent patent applications to refer to specific elements. Those of ordinary skill in the art will understand that manufacturers may use different terms to refer to the same components. The scope of this specification and subsequent patent applications does not take the difference in names as a way to distinguish components, but rather uses the difference in functions of components as a criterion for distinguishing components. "Inclusion" mentioned throughout the specification and subsequent claims is an open-ended term and should be interpreted as "including but not limited to." In addition, the term "coupled" includes any direct and indirect means of electrical connection. Therefore, if a first device is described as being coupled to a second device, it means that the first device can be electrically connected directly to the second device or indirectly electrically connected to the second device through other devices or connection means.

The first figure shows a block diagram of a low-dropout voltage regulator 100 according to an embodiment of the present invention. Referring to the first figure, the low dropout voltage regulator 100 includes a main error amplifier OP1, a first buffer circuit 12, an N-channel power transistor MN, and a voltage divider circuit 18.

Referring to the first figure, the N-channel power transistor MN has a drain coupled to a power supply voltage VDD and a source coupled to the voltage divider 18 and an output capacitor CL.

A negative input terminal of the main error amplifier OP1 is used to receive a reference voltage VREF. In one embodiment, the reference voltage VREF is generated by a bandgap circuit (not shown), and its voltage value is about 1.2V. The voltage dividing circuit 18 includes resistors R1 and R2. The resistors R1 and R2 divide an output voltage OUT of the low-dropout voltage regulator 100 to generate a feedback voltage FB that is proportional to the output voltage OUT. The feedback voltage FB is transmitted to a positive input terminal of the main error amplifier OP1. The main error amplifier OP1 is used to compare the voltage value of the reference voltage VREF and the feedback voltage FB to generate an error signal N1. The first buffer circuit 12 is coupled to an output terminal of the main error amplifier OP1, and is used for shifting the voltage value of the error signal N1 to push the N-channel power transistor MN.

During normal operation, that is, after the slow start, the main error amplifier OP1 drives a gate terminal of the N-channel power transistor MN through the first buffer circuit 12 to provide a stable output voltage OUT. In this situation, the main error amplifier OP1, the first buffer circuit 12 and the N-channel power transistor MN form a first negative feedback path. The first negative feedback path causes the voltage value of the feedback voltage FB and the voltage value of the reference voltage VREF to be substantially the same. Therefore, the voltage value of the output voltage OUT is proportional to the voltage value of the reference voltage VREF according to the resistance values of the resistors R1 and R2.

However, during the slow start period, when the power supply voltage VDD starts to be supplied, the first buffer circuit 12 will raise the voltage value of the node N2 from the ground potential to a voltage value, such as the gate-source voltage difference of a transistor. Value VGS. Therefore, the N-channel power transistor MN is turned on to generate an inrush current, thereby causing damage to the element. In order to solve this problem, the low-dropout voltage regulator 100 needs another feedback path to control the conduction state of the N-channel power transistor MN.

Referring to the first figure, in order to add another feedback path, the low dropout voltage regulator 100 further includes an auxiliary error amplifier OP2, a second buffer circuit 14 and a control circuit 16. The auxiliary error amplifier OP2 consumes less current than the main error amplifier OP1 that requires a complicated design because it does not perform additional temperature compensation or process differentiation or high-speed operation. In an embodiment of the present invention, the current consumed by the auxiliary error amplifier OP2 is less than 10 μA.

Referring to the first figure, the control circuit 16 compares the voltage value of the feedback voltage FB with the voltage value of a bias voltage VB to generate a control signal FBX. A first positive input terminal of the auxiliary error amplifier OP2 is used to receive the feedback voltage FB, a second positive input terminal is used to receive the control signal FBX, and a negative input terminal is used to receive the reference voltage VREF. An input terminal of the second buffer circuit 14 is coupled to an output terminal of the auxiliary error amplifier OP2, and is used to shift a voltage value of the error signal N3. An output terminal of the second buffer circuit 14 is coupled to the gate of the N-channel power transistor MN.

The second figure shows a circuit diagram of a low-dropout voltage regulator 100 'combined with another embodiment of the present invention. Referring to the second figure, the first buffer circuit 12 includes a P-channel transistor M2 and a current source I1, wherein the P-channel transistor M2 has a drain terminal coupled to a ground terminal and coupled to the main error amplifier. A gate terminal of the output terminal of OP1 and a source terminal coupled to the current source I1.

The second buffer circuit 14 includes a first output stage 144 and a second output stage 146. The first output stage 144 has an input terminal coupled to the output terminal of the auxiliary error amplifier OP2, and an output terminal coupled to the second output stage 146. The second output stage 146 has an output terminal coupled to the gate terminal of the N-channel power transistor MN.

In one embodiment, the first output stage 144 includes an N-channel transistor M4. The N-channel transistor M4 has a drain coupled to the output terminal of the main error amplifier OP1, a gate for receiving the error signal N3, and a source coupled to the ground.

In one embodiment, the second output stage 146 includes an N-channel transistor M3 and a capacitor C1. The N-channel transistor M3 has a gate for receiving the error signal N3, a drain coupled to the gate of the N-channel power transistor MN, and a source coupled to the ground. The capacitor C1 is coupled between the gate of the N-channel power transistor MN and the gate of the N-channel transistor M3.

Referring to the second figure, the control circuit 16 includes a comparator CMP and an output stage 162. The comparator CMP is used to compare the voltage value of the feedback voltage FB and the voltage value of the bias voltage VB to generate a comparison signal CMPX. An output terminal of the comparator CMP is coupled to an input terminal of the output stage 162.

In one embodiment, the output stage 162 includes an N-channel transistor M7, a uniform energy element X2, a current source I3, and a capacitor C2. The N-channel transistor M7 has a gate for receiving the comparison signal CMPX, a drain coupled to the enabling element X2, and a source coupled to the current source I3. In one embodiment, the enabling element X2 is composed of a P-channel transistor M6, as shown in the third figure. The P-channel transistor M6 has a source for receiving the power voltage VDD, a gate for receiving the uniform energy signal EN, and a drain coupled to the drain of the N-channel transistor M7.

Referring to the second figure, during the slow start period, when the power supply voltage VDD starts to be supplied, the voltage value of the reference voltage VREF in the low dropout voltage regulator 100 'is first reset to 0V (ground voltage value). At this time, the voltage value of the feedback voltage FB is smaller than the voltage value of the bias voltage VB (about 0.3V). Therefore, the comparator CMP outputs a logic 0 signal CMPX, and the N-channel transistor M7 is turned off. When the N-channel transistor M7 is turned off, the enabling element X2 will quickly pull up the control signal FBX to the voltage value of the power supply voltage VDD, so that the voltage value of the control signal FBX is greater than the voltage of the feedback signal FB. value. At this time, the voltage value of the reference voltage VREF is very small, so the auxiliary error amplifier OP2 outputs an error signal N3 of logic 1.

When the auxiliary error amplifier OP2 outputs an error signal N3 of logic 1, the transistor M4 is turned on, so that the voltage value of the node N1 will be pulled down to the ground potential. At the same time, the transistor M3 is turned on, so that the voltage value of the node N2 will be pulled down to the ground potential. Therefore, the N-channel power transistor MN is turned off. Since the N-channel power transistor MN is turned off, the output voltage OUT will remain pulled down to the ground potential when the power supply voltage VDD starts to be supplied.

Then, the reference voltage VREF starts to rise with a fixed slope. When the voltage value of the feedback signal FB is less than the voltage value of the bias voltage VB, the auxiliary error amplifier OP2, the N-channel transistor M3, the capacitor C1, and the N-channel power circuit in the second buffer circuit 14 Crystal MN forms a second negative feedback path. The second negative feedback path causes the voltage value of the feedback voltage FB and the voltage value of the reference voltage VREF to be substantially the same.

When the voltage value of the feedback signal FB rises to a voltage value close to the bias voltage VB, the comparator CMP outputs a signal CMPX of logic 1 to turn on the N-channel transistor M7. When the N-channel transistor M7 is turned on, the current source I3 discharges the capacitor C2, so the voltage value of the control signal FBX starts to decrease with a fixed slope. When the voltage value of the control signal FBX is less than the voltage value of the feedback signal FB, the auxiliary error amplifier OP2 outputs an error signal N3 of logic 0, so that the transistors M3 and M4 are turned off. Therefore, the N-channel power transistor MN is instead driven by the first negative feedback path, and the second negative feedback path is not activated.

In summary, with the alternate start of the first negative feedback path and the second negative feedback path, the low-dropout voltage regulator disclosed by the present invention can avoid surges because it has a controllable slow-start mechanism. Damage caused by current and voltage overshoot.

The technical content and technical features of the present invention have been disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to those disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention, and should be covered by the scope of subsequent patent applications.

Claims (10)

    A low-dropout voltage regulator includes: an N-channel power transistor having a drain for receiving a power supply voltage and a source for generating an output voltage; a main error amplifier having A positive input terminal receiving a feedback voltage proportional to the output voltage is used to receive a negative input terminal of a reference voltage and an amplified output terminal. A first buffer circuit is coupled to the main error amplifier. Between the amplified output end and a gate of the N-channel power transistor; an auxiliary error amplifier having a first positive input end and a second positive input for receiving the feedback voltage proportional to the output voltage A negative input terminal for receiving the reference voltage and an amplified output terminal; and a second buffer circuit coupled to the amplified output terminal of the auxiliary error amplifier and the gate of the N-channel power transistor And a control circuit for comparing the voltage value of the feedback voltage proportional to the output voltage and the voltage value of a bias voltage to control the gate of the N-channel power transistor; wherein the auxiliary The error amplifier consumes less current than the main error amplifier; and wherein the voltage value of the reference voltage is greater than the voltage value of the bias voltage.         The low-dropout voltage regulator according to the first patent application range, wherein the first buffer circuit includes: a P-channel transistor having a source coupled to the gate of the N-channel power transistor, coupled A gate connected to the amplifying output of the main error amplifier and a drain coupled to a ground; and a current source coupled to the source of the P-channel transistor.         The low-dropout voltage regulator according to the first patent application range, wherein the second buffer circuit includes: a first output stage having an input terminal coupled to the amplified output terminal of the auxiliary error amplifier, and coupled An output terminal to the amplification output terminal of the main error amplifier; and a second output stage having an input terminal coupled to the amplification output terminal of the auxiliary error amplifier, and a second output stage coupled to the N-channel power transistor An output terminal of the gate.         The low-dropout voltage regulator according to item 3 of the patent application, wherein the first output stage includes a first N-channel transistor having a gate coupled to the amplified output terminal of the auxiliary error amplifier. A drain connected to the amplified output terminal of the main error amplifier, and a source connected to the ground terminal.         The low-dropout voltage regulator according to item 3 of the patent application, wherein the second output stage includes a second N-channel transistor having a gate coupled to the amplified output terminal of the auxiliary error amplifier. A drain connected to the gate of the N-channel power transistor and a source connected to the ground terminal; and a first capacitor coupled to the gate and the first channel of the N-channel power transistor Between the gates of two N-channel transistors.         The low-dropout voltage regulator according to item 1 of the patent application scope, wherein the control circuit includes a comparator for comparing the voltage value of the feedback voltage proportional to the output voltage with the voltage value of the bias voltage. Generating a comparison signal; and an output stage having an input terminal for receiving the comparison signal and an output terminal coupled to the second positive input terminal of the auxiliary error amplifier.         The low-dropout voltage regulator according to item 6 of the patent application, wherein the output stage of the control circuit includes a third N-channel transistor having a gate for receiving the comparison signal and coupled to the gate. A drain of the second positive input terminal of the auxiliary error amplifier; a capacitor coupled to the drain of the third N-channel power transistor; and a current source coupled to a third of the third N-channel transistor Source.         The low-dropout voltage regulator according to item 1 of the scope of patent application, wherein during the slow start, the reference voltage is reset to 0V, and then starts to rise with a first fixed slope; when the feedback is proportional to the output voltage When the voltage value of the voltage is less than the voltage value of the bias voltage, the auxiliary error amplifier, the second buffer circuit and the N-channel power transistor form a first negative feedback path, which makes the feedback proportional to the output voltage The voltage value of the applied voltage is the same as the voltage value of the reference voltage.         The low dropout voltage regulator according to item 8 of the patent application, wherein when the voltage value of the feedback voltage proportional to the output voltage is greater than the voltage value of the bias voltage, the main error amplifier and the first buffer circuit A second negative feedback path is formed with the N-channel power transistor, which makes the voltage value of the feedback voltage proportional to the output voltage and the voltage value of the reference voltage the same.         The low-dropout voltage regulator according to item 8 of the application, wherein when the voltage value of the feedback voltage proportional to the output voltage rises to the voltage value of the bias voltage, the control circuit transmits a second fixed voltage. A control signal with a slope drop to the second positive input terminal of the auxiliary error amplifier, and when the voltage value of the control signal is less than the voltage value of the feedback voltage proportional to the output voltage, the second negative feedback path Activated and the first negative feedback path is not activated.