TW201943170A - Charger - Google Patents

Abstract

A charger includes a thermal conductive plate for heat dissipation, and a transistor. The transistor includes a drain terminal of a first pulsating voltage level, and a source terminal of a second pulsating voltage level. The second pulsating voltage level is lower than the first pulsating voltage level. The source terminal is connected to the thermal conductive plate. The thermal conductive plate is disposed on a first surface of a mother board. The mother board comprises one or more thermal conductive layers embedded in the mother board between the first surface and a second surface opposite the first surface. The one or more thermal conductive layers are connected to the thermal conductive plate.

Description

charger

This disclosure relates to a power charging device. More specifically, the present disclosure relates to a charger for charging an electronic device.

Chargers such as mobile phone chargers are known. With more and more applications, especially multimedia applications running on mobile phones, the battery power of mobile phones can be consumed very quickly. The same can happen with other consumer electronics devices, such as MP3 players, game consoles, cameras, and mobile phone Bluetooth headsets. These electronic devices may require frequent charging. To meet this power demand, portable power supplies have been developed.

Some embodiments of the present disclosure provide a charger. The charger includes a heat conducting plate for heat dissipation, and a transistor. The transistor includes a drain terminal at a first pulsating voltage level and a source terminal at a second pulsating voltage level. The second pulsating voltage level is lower than the first pulsating voltage level. Wherein, the source terminal is connected to the heat conducting plate, and the heat conducting plate is located on a first surface of a mother board, the mother board includes one or more heat conducting layers, the heat conducting layer is embedded on the first surface and is In the motherboard between the first surface opposite to the second surface, and the one or more thermally conductive layers are connected to the thermally conductive plate.

In one embodiment, the source terminal is attached to a carrier, and the drain terminal is a plurality of first pins wire-bonded and connected to the carrier.

In another embodiment, the carrier includes a plurality of second pins attached to the thermally conductive plate.

In another embodiment, the thermal conductive plate includes a copper clad.

In another embodiment, the one or more thermally conductive layers include one or more copper claddings.

In another embodiment, the charger further includes a controller configured to control the on-time of the transistor.

In another embodiment, the controller includes one of a pulse-width modulation (PWM) controller or a constant on-time (COT) controller.

In another embodiment, the controller and the transistor are co-packaged in a semiconductor device.

In another embodiment, the charger further includes a transformer, wherein the drain terminal of the transistor is coupled to a dotted terminal of a primary winding of the transformer.

Some embodiments of the present disclosure also provide a charger. The charger includes a heat conducting plate for heat dissipation, and a semiconductor device. The semiconductor device includes a carrier including a die pad, a first pin and a second pin, and a transistor attached to the carrier. The transistor includes a drain terminal at a first pulsating voltage level and a source terminal at a second pulsating voltage level. The second pulsating voltage level is lower than the first pulsating voltage level. The drain terminal is the first pins that are wire-bonded and connected to the carrier. The source terminal is attached to the die pad of the carrier. The second pins are exposed from the semiconductor device and attached to the thermally conductive plate.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are only examples and are not intended to limit the disclosure. For example, in the description, the formation of the first feature above or on the second feature may include an embodiment in which the first and second features are in direct contact, and may also include the formation of other features on the first and second The embodiment between the features makes the first and second features not in direct contact. In addition, the disclosure may repeat element symbols and / or text in different examples. This repetition is for the purpose of simplification and clarification, and does not itself determine the relationship between the various embodiments and / or architectures discussed.

According to some embodiments of the present disclosure, FIG. 1 is a circuit diagram of a charger 10. The charger 10 may include a portable charger for instantly charging a mobile phone or other portable electronic device.

Referring to FIG. 1, the charger 10 includes a controller 11, a transistor 12, and a transformer 14. The controller 11 is configured to generate a control signal CTRL, which controls the on-time and off-time of the transistor 12. In one embodiment, the controller 11 includes a pulse-width modulation (PWM) controller or a constant on-time (COT) controller. The controller 11 detects the intensity of the current flowing through the source pin of the transistor 12 at the current sensing pin CS, and measures the duty cycle of the control signal CTRL. By changing the duty cycle of the control signal CTRL provided to the transistor 12, the controller 11 causes the transformer 14 to generate a desired output voltage Vout for the electronic device, that is, the load in FIG. 1. In this embodiment, the controller 11 and the transistor 12 function as an AC-to-DC converter.

The transistor 12 may include a metal-oxide-semiconductor field-effect transistor (MOSFET). The drain terminal of the transistor 12 is connected to the dotted terminal (indicating the polarity) of the primary winding of the transformer 14. A source terminal (to be described in detail below) of the transistor 12 is attached to a heat conducting plate, such as a heat sink for heat dissipation. The gate of the transistor 12 is connected to the controller 11 to receive the control signal CTRL. In operation, the drain ripple voltage can be at least hundreds of volts (V), and the source ripple voltage can be as low as 1 V. The drain voltage is significantly greater than the source voltage and can be at least two orders of magnitude (a hundred times greater). The transistor 12 functions as a switch that operates in a high-voltage environment.

In this embodiment, the charger 10 also includes an input stage 15, a filter 16, a snubber 17, and an output stage 18. In response to an alternating current (ac) voltage Vac, which may be the main supply voltage, the input stage 15 is configured to provide an input voltage Vin. In some Asian countries, Vac can be 110V, and in the United States or Europe can range from 220V to 240V. The input stage 15 includes a bridge rectifier 155 for converting Vac to a direct current (dc) voltage. The voltage Vin is filtered at the filter 16 to remove AC ripple, and is processed at a snubber 17 to suppress voltage transients. In the illustrated embodiment, the filter 16 includes a capacitive element C1 connected between the bridge rectifier 155 and a reference voltage (eg, a ground voltage). Furthermore, the snubber 17 includes a capacitive element C2 and a resistive element R1 connected in parallel, and is then connected in series with a diode D between the terminals of the primary winding of the transformer 14. The anode of the diode D1 is connected to the co-located end of the primary winding of the transformer 14.

The transformer 14 is configured to convert a relatively large input voltage Vin into a relatively small output voltage Vout. The relationship between Vout and Vin can be expressed by the following equation.

Wherein D represents the duty cycle of the control signal CRTL, and N1 and N2 represent the number of coils of the primary winding and the secondary winding of the transformer 14, respectively.

In one embodiment, Vin is close to Vout depends on the application and usually ranges from about 5 to 12V, or in some cases can approach 20V. An output voltage Vout is provided at the output stage 18. In the illustrated embodiment, the output stage 18 includes a resistive element R2 and a capacitive element C3, which are connected in series between the cathode of the diode D2 and the non-colocated end of the secondary winding of the transformer 14. The resistive element R2 functions as an equivalent series resistor (ESR). The anode of the diode D2 is connected to the co-located end of the secondary winding of the transformer 14.

FIG. 2A is a schematic diagram illustrating the transistor 12 of the charger 10 shown in FIG. 1 according to the embodiment of the disclosure.

Referring to FIG. 2A, the transistor 12 is attached at its source terminal to a support substrate or carrier, such as a lead frame LF. The lead frame LF includes a die pad 120, a first pin D and a second pin S. The gate and drain terminals of the transistor 12 are wire-bonded to corresponding pins G and D of the lead frame LF via a bonding wire BW. The source terminal of the transistor is attached to the die pad 120 of the lead frame LF. The transistor 12 is packaged together with the bonding wire BW in a molding compound 25 (shown as a dotted rectangular frame). Those skilled in the art will understand that depending on the voltage level applied to them, the drain and source terminals of the MOS transistor are interchangeable. For example, in operation, the drain voltage is typically higher than the source voltage in an n-type MOS (NMOS) transistor and lower than the source voltage in a p-type MOS (PMOS) transistor.

FIG. 2B is a cross-sectional view illustrating the transistor shown in FIG. 2A along line AA.

Referring to FIG. 2B, the transistor 12 includes a gate terminal G, a drain terminal D, a source terminal S, and an active layer 128 between the drain terminal D and the source terminal S. The active layer 128 may include a semiconductor layer and an interconnect structure to enable a transistor function. The source terminal S and the drain terminal D are located on opposite sides of the active layer 128. The source terminal S of the transistor 12 is attached to a lead frame LF, which is attached to a heat sink on a motherboard, such as a printed circuit board. Therefore, it can be said that the transistor 12 has a bottom source structure, in which the source terminal S is closer to the heat sink than the drain terminal D. The advantages of transistor 12 are discussed below, where source S is coupled to a heat sink.

In the existing charger, compared to the top drain bottom source transistor structure in the charger 10 of the present disclosure, the drain terminal of the transistor is attached to the carrier and then attached to a heat sink on the printed circuit board. As mentioned earlier, in ACDC applications, the drain voltage is higher than several hundred volts. For heat dissipation, a relatively large copper cladding is required as a heat sink to cool the transistor. However, in the bottom drain transistor structure, the pulse voltage of the drain pin is an emitter of electromagnetic influence (EMI). Although a large copper cladding is used for better thermal performance, stronger radiation can occur and worsen EMI issues. Therefore, an efficient EMI filter is needed to reduce EMI radiation, which may inevitably complicate circuit design and increase the cost of the charger.

Unlike existing chargers, the bottom source transistor structure has a relatively low source ripple voltage, which can be as low as 1V as previously described, which is significantly lower than the drain ripple voltage. Compared with the existing method based on the bottom-drain transistor structure, the charger 10 of the present disclosure enjoys a relatively large heat sink, which enhances thermal performance while avoiding EMI problems caused by high pulsating voltage as an emission source.

Available in U.S. Patent No. 7,394,151 ('151 Patent) (titled `` Semiconductor package with Plated Connection' ') or U.S. Patent No. 8,008,716 (' 716 Patent) (titled `` Inverted-Trench Grounded-Source FET Structure with Trenched Source Body Short Electrode "), the bottom source structure is found, and both patents are licensed to the same assignee. In particular, the bottom source structure is disclosed in, for example, FIGS. 7A and 7B and related descriptions in the '151 patent, or in FIGS. 2 and 3 and related descriptions in the' 716 patent. The relevant descriptions of the '151 and' 716 patents are incorporated herein by reference.

Existing transistors with a bottom-drain structure (such as planar MOSFETs and trench MOSFETs) can also be applied in this embodiment without modification. In some embodiments, the transistor is "flipped" with its source terminal facing the lead frame and is attached to the lead frame at the source terminal to form the bottom source structure shown in Figures 2A and 2B.

FIG. 3A is a schematic top view illustrating the semiconductor device 30 according to the embodiment of the disclosure, which includes the controller 11 and the transistor 12 of the charger 10 shown in FIG. 1.

Referring to FIG. 3A, the controller 11 and the transistor 12 of the charger 10 are packaged together in a semiconductor device 30. Specifically, the controller 11 attached to the first carrier LF1 and the transistor 12 attached to the second carrier LF2 are packaged in a molding compound 35. In order to control the transistor 12, the controller 11 transmits a control signal CTRL to the gate of the transistor 12 via the first bonding wire BW1. The drain terminal of the transistor 12 is electrically connected to the first pin (drain pin D) of the second carrier LF2 via the second bonding wire BW2. Considering the relatively large drain voltage, the second carrier LF2 includes several drain pins.

FIG. 3B is a bottom view illustrating the semiconductor device 30 shown in FIG. 3A. Referring to FIG. 3B, some second pins (source pins S) of the second carrier LF2 are exposed from the semiconductor device 30. These exposed source pins S work with the heat sink to help dissipate heat.

FIG. 4 is a schematic diagram illustrating the charger 10 shown in FIG. 1 according to the embodiment of the present disclosure.

Referring to FIG. 4, the second carrier LF2 is attached to the heat sink 42 on the motherboard 40 by, for example, solder paste. In this embodiment, the die pad 120 where the source terminal of the transistor 12 is located is attached to the heat sink 42. The heat generated by the semiconductor device 30 (especially the transistor 12) can be dissipated to the heat sink 42 through the bottom source terminal, and can also be dissipated to the heat sink 42 through the exposed source pin S. Therefore, the exposed source pin S provides an additional heat dissipation path.

FIG. 5 is a cross-sectional view illustrating a charger 50 according to an embodiment of the present disclosure.

5, the charger 50 includes a transistor 12 and a transformer 14, which are located on a first surface 61 of the motherboard 60. In this embodiment, the transistor 12 is packaged as a single semiconductor device. Alternatively, as shown in FIG. 3A, the transistor 12 may be co-packaged with the controller 11 in a semiconductor device. The source terminal of the transistor 12 is attached to a carrier, which is attached to a copper cladding 42 on the first surface 61. The copper cladding 42 serves as a heat sink. The motherboard 60 includes at least one thermally conductive layer for heat dissipation. In this embodiment, the at least one thermally conductive layer includes copper claddings 71 and 72 embedded in the motherboard 60. In other embodiments, the number of copper cladding layers is not limited to two. The additional copper cladding layers 71 and 72 are coupled to the copper cladding 42 via the conductive path 68, so that the transistor 12 passes through the copper cladding 42 and the copper cladding layers 71 and 72 on the first surface 61 toward The second surface 62 dissipates heat.

Those skilled in the art can understand that modifications to the embodiments disclosed herein can be made. For example, the total number of pins can be changed. Those skilled in the art can make other modifications, and all such modifications fall into this disclosure as defined by the scope of the patent application.

10‧‧‧ Charger

11‧‧‧ Controller

12‧‧‧ Transistor

14‧‧‧Transformer

15‧‧‧input stage

16‧‧‧Filter

17‧‧‧ buffer

18‧‧‧ output stage

25‧‧‧moulding compound

30‧‧‧Semiconductor device

35‧‧‧moulding compound

40‧‧‧Motherboard

42‧‧‧ heat sink

50‧‧‧ charge gas

60‧‧‧Motherboard

61‧‧‧first surface

62‧‧‧Second surface

68‧‧‧ conducting pathway

71‧‧‧ copper cladding

72‧‧‧ copper cladding

120‧‧‧ Die Pad

128‧‧‧Active layer

155‧‧‧bridge rectifier

S‧‧‧Source

D‧‧‧ Drain

G‧‧‧Gate

BW‧‧‧bonding wire

BW1‧‧‧First bonding wire

BW2‧‧‧Second Bonding Wire

LF‧‧‧Lead frame

LF1‧‧‧First carrier

LF2‧‧‧Second carrier

GND‧‧‧ Ground

CS‧‧‧ Current Sensing Pin

Source‧‧‧Source

Controller‧‧‧Controller

CTRL‧‧‧Control signal

MOSFET‧‧‧metal oxide semiconductor field effect transistor

Drain‧‧‧ Drain

VCC‧‧‧ Power

Vac‧‧‧AC voltage

Vin‧‧‧ input voltage

C1‧‧‧Capacitor element

C2‧‧‧Capacitor element

C3‧‧‧Capacitor element

D1‧‧‧diode

D2‧‧‧ Diode

R1‧‧‧ resistance element

R2‧‧‧ resistance element

Vout‧‧‧Output voltage

Load‧‧‧Load

Please note that according to industry standards, various features are not drawn to scale. In fact, the dimensions of various features can be enlarged or reduced for clarity. FIG. 1 is a circuit diagram illustrating a charger according to an embodiment of the present disclosure. FIG. 2A is a schematic diagram illustrating a transistor of the charger shown in FIG. 1 according to an embodiment of the disclosure. FIG. 2B is a cross-sectional view illustrating the transistor shown in FIG. 2A along line AA. 3A is a schematic top view illustrating a semiconductor device including a transistor and a controller of the charger shown in FIG. 1 according to an embodiment of the disclosure. FIG. 3B is a bottom view illustrating the semiconductor device shown in FIG. 3A. FIG. 4 is a schematic diagram illustrating the charger shown in FIG. 1 according to the embodiment of the present disclosure. FIG. 5 is a cross-sectional view illustrating a charger according to an embodiment of the disclosure.

Claims (18)

A charger includes: a heat conducting plate for heat dissipation; and a transistor including: a drain terminal at a first pulsating voltage level; and a source terminal at a second pulsating voltage level, the first Two pulsating voltage levels are lower than the first pulsating voltage level; wherein the source terminal is connected to the heat conducting plate; wherein the heat conducting plate is on a first surface of a motherboard; wherein the motherboard includes one or more A thermally conductive layer embedded in the motherboard between the first surface and a second surface opposite to the first surface; and wherein the one or more thermally conductive layers are connected to the thermally conductive plate. The charger according to claim 1, wherein the source terminal is attached to a carrier, and wherein the drain terminal is wire-bonded and connected to the plurality of first pins of the carrier. The charger as claimed in claim 2, wherein the carrier comprises a plurality of second pins attached to the thermally conductive plate. The charger according to claim 1, wherein the heat conducting plate comprises a copper clad. The charger according to claim 1, wherein the one or more thermally conductive layers include one or more copper claddings. The charger according to claim 1, further comprising: a controller configured to control the on-time of the transistor. The charger according to claim 6, wherein the controller comprises one of a pulse-width modulation (PWM) controller or a constant on-time (COT) controller. The charger according to claim 7, wherein the controller and the transistor are co-packaged in a semiconductor device. The charger according to claim 1, further comprising a transformer, wherein the drain terminal of the transistor is coupled to a dotted terminal of a primary winding of the transformer. A charger includes: a thermal conductive plate for heat dissipation; and a semiconductor device including: a carrier including a die pad, a plurality of first pins and a plurality of second pins; and a transistor Attached to the carrier, the transistor includes: a drain terminal of a first pulsating voltage level, the drain terminal being wire-bonded and connected to the plurality of first pins of the carrier; and a first A source terminal of two pulsating voltage levels, the second pulsating voltage level is lower than the first pulsating voltage level, the source terminal is attached to the die pad of the carrier, wherein the plurality of second terminals Pins are connected to the die pad; wherein the plurality of second pins are exposed from the semiconductor device; and wherein the plurality of second pins are attached to the heat conductive plate. The charger as recited in claim 10, wherein the die pad of the carrier is attached to the thermally conductive plate. The charger according to claim 10, wherein the heat conducting plate comprises a copper coating. The charger according to claim 10, wherein the heat conductive plate is located on a motherboard; wherein the motherboard includes: a heat conductive layer embedded in the motherboard; and wherein the heat conductive layer is connected to the heat conductive plate . The charger according to claim 13, wherein the thermally conductive layer comprises a copper coating. The charger according to claim 10, further comprising: a controller configured to control the on-time of the transistor. The charger according to claim 15, wherein the controller comprises one of a pulse-width modulation (PWM) controller or a constant on-time (COT) controller. The charger according to claim 16, wherein the controller and the transistor are co-packaged in the semiconductor device. The charger according to claim 10, further comprising a transformer, wherein the drain terminal of the transistor is coupled to a dotted terminal of a primary winding of the transformer.