TW201941600A - Image processing device - Google Patents

Abstract

Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

Description

Image processing device

The invention relates to an image processing device.

More and more applications require high-resolution video images and high-frame rate images. Therefore, the amount of data access to the memory (ie, bandwidth) for storing these images through various multimedia intellectual property (IP) blocks of the image processing device has greatly increased.

Each image processing device has limited processing capabilities. When the bandwidth increases, the processing power of the image processing device may reach this limit. As a result, users of image processing devices may experience reduced speed when recording or playing video images.

At least one embodiment of the inventive concept provides an image processing apparatus having an improved processing speed.

According to an exemplary embodiment of the inventive concept, there is provided an image processing apparatus configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, and perform entropy encoding on the second image data to encode the second image data. The data is compressed into third image data, a header indicating the compression ratio of the third image data is generated, and the third image data is stored in the memory device together with the header as the compressed first image data.

According to an exemplary embodiment of the inventive concept, there is provided an image processing apparatus configured to compress first image data. The image processing device includes an encoding circuit having a mode selection circuit configured to determine whether to set the first mode to a lossless compression mode or a lossy compression mode based on the received signal; a first logic circuit Configured to compress the first image data into second image data including prediction data and residual data; a second logic circuit configured to quantize the second image using at least one quantization parameter (QP) Image data; and a third logic circuit configured to i) the output of the first logic circuit when the first mode is set to the lossless compression mode and ii) the output of the first logic circuit when the first mode is set to the lossy compression mode One of the outputs of the second logic circuit performs entropy coding.

According to an exemplary embodiment of the inventive concept, there is provided an image processing apparatus configured to decompress a first compressed image data. The image processing device includes a mode selection circuit configured to set the first mode to lossless decompression when compressing the first compressed image data in a lossless manner, and to compress the first compressed image data in a lossy manner. When the first mode is set to lossy decompression; the first logic circuit performs entropy decoding on the first compressed image data; the second logic circuit performs the first logic circuit when the first mode is set to lossy decompression The inverse quantization of the output; and a third logic circuit configured to decompress by adding residual data to the prediction data received in the output of the first logic circuit when the first mode is set to lossless decompression, And when the first mode is set to lossy decompression, decompression is performed by adding residual data to the prediction data received in the output of the second logic circuit.

An image processing apparatus according to an exemplary embodiment of the inventive concept will now be described with reference to FIGS. 1 to 14.

FIG. 1 is a block diagram of an image processing apparatus according to at least one embodiment of the inventive concept.

Referring to FIG. 1, an image processing apparatus according to at least one embodiment of the inventive concept includes a multimedia intellectual property (IP) 100 (eg, an IP core and IP blocks, circuits, etc.), a frame buffer compressor (FBC) ) 200 (for example, a circuit, a digital signal processor, etc.), a memory 300, and a system bus 400.

In an exemplary embodiment, the multimedia IP 100 is a part of an image processing device that directly performs image processing of the image processing device. The multimedia IP 100 may include multiple modules for performing image recording and reproduction (such as video recording, playback, etc.).

The multimedia IP 100 receives first data (eg, video data) from an external device such as a camera and converts the first data into second data. For example, the first data may be moving original image data or original still image data. The second data may be data generated by the multimedia IP 100, and may also include data generated by the multimedia IP 100 that processes the first data. The multimedia IP 100 can repeatedly store the second data in the memory 300 and update the second data through various steps. The second data may contain all the data used in these steps. The second data may be stored in the memory 300 in the form of the third data. Therefore, the second data may be data before being stored in the memory 300 or after being read from the memory 300.

In an exemplary embodiment, the multimedia IP 100 includes an image signal processor (ISP) 110, a shake correction module (G2D) 120, and a multi-format codec (MFC). ) 130, a graphics processing unit (GPU) 140, and a display 150. However, the inventive concept is not limited to this case. That is, the multimedia IP 100 may include at least one of the ISP 110, G2D 120, MFC 130, GPU 140, and display 150 described above. In other words, the multimedia IP 100 can be implemented by a processing module that must access the memory 300 in order to process data representing a moving image or a still image.

The ISP 110 receives the first data and converts the first data into the second data by preprocessing the first data. Here, the first data may be image source data in an RGB format. For example, the ISP 110 may convert the first data in the RGB format into the second data in the YUV format.

The RGB format is a data format that represents color based on the three primary colors of light. That is, the image is represented using three types of colors, that is, red, green, and blue. On the other hand, the YUV format refers to a data format that independently represents a luminance (ie, a luma signal) and a chroma signal. That is, Y indicates a luma signal, and U (Cb) and V (Cr) indicate a chroma signal, respectively. U indicates the difference between the lightness signal and the blue signal component, and V indicates the difference between the lightness signal and the red signal component. Here, the project Y, the project U (Cb), and the project V (Cr) may be limited to a plane. For example, the data on the lightness signal can be referred to as the data of the Y plane, and the data on the chrominance signal can be referred to as the data of the U (Cb) plane or the data of the V (Cr) plane.

Data in the YUV format can be obtained by converting the data in the RGB format using a conversion formula. For example, a conversion formula (such as Y = 0.3R + 0.59G + 0.11B, U = (B-Y) × 0.493, V = (R-Y) × 0.877) can be used to convert the data in the RGB format to the data in the YUV format.

Because the human eye is sensitive to light signals but not sensitive to color signals, it is easier to compress data in YUV format than RGB data. Therefore, the ISP 110 can convert the first data in the RGB format into the second data in the YUV format.

After the ISP 110 converts the first data into the second data, the ISP stores the second data in the memory 300.

G2D 120 can perform shake correction on image data or moving image data. The G2D 120 may read the first data or the second data stored in the memory 300 to perform shake correction. Here, shake correction refers to detecting the shake of the camera in the moving image data and removing the shake.

The G2D 120 may generate new second data or update the second data by correcting jitter in the first data or the second data, and may store the generated or updated second data in the memory 300.

MFC 130 may be a codec for compressing moving image data. Generally speaking, the size of moving image data is extremely large. Therefore, a compression module for reducing the size of moving image data is needed. The moving image data can be compressed based on the association relationship between multiple frames, and this compression can be performed by the MFC 130. The MFC 130 may read and compress the first data or may read and compress the second data stored in the memory 300.

The MFC 130 may generate new second data or update the second data by compressing the first data or the second data, and store the new second data or the updated second data in the memory 300.

The GPU 140 may perform an arithmetic process to calculate and generate two-dimensional or three-dimensional graphics. The GPU 140 may calculate the first data or the second data stored in the memory 300. The GPU 140 can exclusively process graphics data and can process graphics data in parallel.

The GPU 140 may generate new second data or update the second data by compressing the first data or the second data, and store the new second data or the updated second data in the memory 300.

The display 150 can display the second data stored in the memory 300 on the screen. The display 150 may display image data (ie, second data processed by other components of the multimedia IP 100) on the screen, which other components are ISP 110, G2D 120, MFC 130, and GPU 140. However, the inventive concept is not limited to this case.

Each of the ISP 110, the G2D 120, the MFC 130, the GPU 140, and the display 150 of the multimedia IP 100 can be individually operated. That is, each of the ISP 110, G2D 120, MFC 130, GPU 140, and display 150 can individually access the memory 300 to write or read data.

In one embodiment, the FBC 200 converts the second data into the third data by compressing the second data before the components of the multimedia IP 100 individually access the memory 300. The FBC 200 can transmit the third data to the multimedia IP 100, and the multimedia IP 100 can transmit the third data to the memory 300.

Therefore, the third data generated by the FBC 200 can be stored in the memory 300. Conversely, the third data stored in the memory 300 can be loaded by the multimedia IP 100 and transmitted to the FBC 200. The FBC 200 may convert the third data into the second data by decompressing the third data. The FBC 200 can transmit the second data to the multimedia IP 100.

That is, whenever the ISP 110, G2D 120, MFC 130, GPU 140, and display 150 of the multimedia IP 100 access the memory 300 separately, the FBC 200 can compress the second data into the third data and the first data Three data are transferred to the memory 300. For example, after one of the components of the multimedia IP 100 generates the second data and stores the second data in the memory 300, the frame buffer compressor 200 can compress the stored data and store the compressed data to Memory 300. Conversely, whenever the memory 300 makes a data request to the ISP 110, G2D 120, MFC 130, GPU 140, and display 150 of the multimedia IP 100, the FBC 200 can decompress the third data into the second data and the second data Transmission to each of the ISP 110, the G2D 120, the MFC 130, the GPU 140, and the display 150 of the multimedia IP 100.

The memory 300 may store the third data generated by the FBC 200 and provide the stored third data to the FBC 200 so that the FBC 200 may decompress the third data.

In one embodiment, the system bus 400 is connected to each of the multimedia IP 100 and the memory 300. Specifically, the ISP 110, G2D 120, MFC 130, GPU 140, and display 150 of the multimedia IP 100 may be separately connected to the system bus 400. The system bus 400 may serve as a path through which the ISP 110, G2D 120, MFC 130, GPU 140, and display 150 and memory 300 of the multimedia IP 100 exchange data with each other.

In one embodiment, the FBC 200 is not connected to the system bus 400, and when each of the ISP 110, G2D 120, MFC 130, GPU 140, and display 150 of the multimedia IP 100 accesses the memory 300 Convert the second data into the third data or convert the third data into the second data.

FIG. 2 is a detailed block diagram of the FBC 200 illustrated in FIG. 1.

Referring to FIG. 2, the FBC 200 includes an encoder 210 (eg, an encoding circuit) and a decoder 220 (eg, a decoding circuit).

The encoder 210 may receive the second data from the multimedia IP 100 and generate the third data. Here, the second data may be transmitted from each of the ISP 110, the G2D 120, the MFC 130, the GPU 140, and the display 150 of the multimedia IP 100. The third data may be transmitted to the memory 300 via the multimedia IP 100 and the system bus 400.

Conversely, the decoder 220 may decompress the third data stored in the memory 300 into the second data. The second data can be transmitted to the multimedia IP 100. Here, the second data may be transmitted to each of the ISP 110, the G2D 120, the MFC 130, the GPU 140, and the display 150 of the multimedia IP 100.

FIG. 3 is a detailed block diagram of the encoder 210 illustrated in FIG. 2.

3, the encoder 210 includes a first mode selector 219 (for example, a mode selection circuit), a prediction module 211 (for example, a logic circuit or processor), a quantization module 213 (for example, a logic circuit or processor), Entropy encoding module 215 (eg, a logic circuit or processor) and padding module 217 (eg, a logic circuit or processor).

In an embodiment, the first mode selector 219 determines whether the encoder 210 will operate in a lossless mode (eg, lossless compression) or a lossy mode (eg, lossy compression). When the encoder 210 operates in the lossless mode based on the determination result of the first mode selector 219, the second data may be compressed along the lossless path of FIG. When the encoder 210 operates in a lossy mode, the second data may be compressed along a lossy path.

The first mode selector 219 may receive a signal from the multimedia IP 100 for determining whether to perform lossless compression or lossy compression. Here, lossless compression indicates that compression of data is not lost and has a compression ratio that varies depending on the data. Lossy compression, on the other hand, indicates compression in which data is partially lost. Lossy compression has a higher compression ratio than lossless compression, and has a preset fixed compression ratio.

In the case of a lossless mode, the first mode selector 219 enables the second data to flow along the lossless path to the prediction module 211, the entropy encoding module 215, and the padding module 217. In contrast, in the case of a lossy mode, the first mode selector 219 enables the second data to flow along the lossy path to the prediction module 211, the quantization module 213, and the entropy encoding module 215.

The prediction module 211 converts the second data into predicted image data. The predicted image data is a compressed representation of the second data as a combination of the predicted data and the residual data. In one embodiment, the prediction data is image data of one pixel of the image data, and the residual data is generated from the difference between the prediction data of the pixel adjacent to one pixel of the image data and the image data. For example, if the image data of a pixel has a value of 0 to 255, 8 bits may be required to represent the value. When the neighboring pixels have a value similar to that of the one pixel, the residual data of each of the neighboring pixels is much smaller than the predicted data. For example, if adjacent pixels have similar values, only the difference (ie, residual) from the values of adjacent pixels can be represented without loss of data, and the difference needed to represent the difference The number of bits of data may be much smaller than 8 bits. For example, when pixels with values of 253, 254, and 255 are sequentially arranged, if the prediction data is 253, the residual data representation (253 (forecast), 1 (residual), 2 (residual)) may be sufficient, And the residual data indicates that the number of bits required per pixel can be 2 bits much smaller than 8 bits. For example, 24 bits of 253, 254, and 255 data can be attributed to 8 bits of predicted data 253 (11111101), 2 bits of residual data 254-251 = 1 (01), and 2 bits The residual data of 255-253 = 2 (10) and reduced to 12 bits.

Therefore, the prediction module 211 can compress the overall size of the second data by dividing the second data into prediction data and residual data. Various methods can be used to determine prediction data.

The prediction module 211 may perform prediction on a pixel-by-pixel basis or a block-by-block basis. Here, the block may be an area formed by a plurality of adjacent pixels. For example, prediction on a pixel basis may mean generating all residual data from one of the pixels, and prediction on a block basis may mean generating residual data for each block from the pixels of the corresponding block.

The quantization module 213 can further compress the second data compressed by the prediction module 211. The quantization module 213 may use a preset quantization parameter (QP) to remove lower bits of the second data (eg, use QP to quantize the second data). For example, if the prediction data is 253 (11111101), the prediction data can be reduced from 8 bits to 6 bits by removing the lower 2 bits, which generates prediction data 252 (111111 ). Specifically, the representative value can be selected by multiplying the data by QP, in which the number below the decimal point is discarded, thereby causing a loss. If the pixel data has a value of 0 to 2 ⁸ -1 (= 255), the QP can be limited to 1 / (2 ⁿ -1) (where n is an integer of 8 or less). However, the current embodiment is not limited to this case.

Here, since the removed lower bits are not recovered later, the lower bits are lost. Therefore, the quantization module 213 is used only in the lossy mode. Compared with the lossless mode, the lossy mode may have a relatively high compression ratio, and may have a preset fixed compression ratio. Therefore, no information about the compression ratio is needed afterwards.

The entropy encoding module 215 can compress the second data compressed by the quantization module 213 in a lossy mode or the second data compressed by the prediction module 211 in a lossless mode via entropy decoding. In entropy coding, the number of bits can be allocated according to frequency.

In one embodiment, the entropy encoding module 215 uses Huffman decoding to compress the second data. In an alternative embodiment, the entropy encoding module 215 compresses the predicted image data via exponential Golomb coding or Golomb rice coding. In one embodiment, the entropy coding module 215 uses k values to generate a table, and the entropy coding module uses the generated table to compress the predicted image data. The k value may be an entropy coded value used in the entropy coding.

The padding module 217 may perform padding on the second data compressed by the entropy encoding module 215 in a lossless mode. Here, padding can mean adding meaningless data to fit a specific size. This situation will be described in more detail later.

The filling module 217 can be activated not only in a lossless mode but also in a lossy mode. In the lossy mode, the second data can be compressed by the quantization module 213 with a compression ratio greater than desired. In this case, even in the lossy mode, the second data can be transmitted through the padding module 217, converted into third data, and then transmitted to the memory 300. In an exemplary embodiment, the padding module 217 is omitted so that padding is not performed.

The compression manager 218 determines the combination of the QP table and the entropy table for quantization and entropy decoding, and controls the compression of the second data according to the determined combination of the QP table and the entropy table.

In this case, the first mode selector 219 determines that the encoder 210 will operate in a lossy mode. Therefore, the second data is compressed along the lossy path of FIG. 3. That is, based on the assumption that the FBC 200 uses a lossy compression algorithm to compress the second data, the compression manager 218 determines the required combination of the QP table and the entropy table and compresses the second data according to the determined combination of the QP table and the entropy table. .

Specifically, the QP table may include one or more entries, and each of the entries may include a QP for quantifying the second data.

In an embodiment, the entropy table refers to a plurality of code tables identified by the k value to perform an entropy decoding algorithm. An entropy table that may be used in some embodiments may include at least one of an exponential Columbus code and a Columbus code.

The compression manager 218 determines a QP table containing a predetermined number of entries, and the FBC 200 uses the determined QP table to quantify the predicted second data. Further, the compression manager 218 determines that a predetermined number of k- value entropy tables are used, and the FBC 200 uses the determined entropy table to perform entropy decoding on the quantized second data. That is, the FBC 200 generates the third data based on the combination of the QP table and the entropy table determined by the compression manager 218.

Then, the FBC 200 may write the generated third data into the memory 300. In addition, the FBC 200 may read the third data from the memory 300, decompress the read third data, and provide the decompressed third data to the multimedia IP 100.

FIG. 4 is a detailed block diagram of the decoder 220 illustrated in FIG. 2.

3 and 4, the decoder 220 includes a second mode selector 229 (for example, a mode selection circuit), an unfilled module 227 (for example, a logic circuit or processor), and an entropy decoding module 225 (for example, a logic circuit ), An inverse quantization module 223 (for example, a logic circuit or processor), and a predictive compensation module 221 (for example, a logic circuit or processor).

The second mode selector 229 determines whether the third data stored in the memory 300 has been generated by the lossless compression or the lossy compression of the second data. In an exemplary embodiment, the second mode selector 229 determines whether the third data has been generated by compressing the second data in a lossless mode or a lossy mode based on the presence or absence of a header. In an embodiment, the third data is compressed in a lossy mode when the third data includes at least one quantization parameter, and the third data is compressed in a lossless mode when the third data does not include a quantization parameter. In another embodiment, the compressed data stores a flag indicating whether the data is compressed in a lossy or lossless manner.

If the third data has been generated by compressing the second data in the lossless mode, the second mode selector 229 enables the third data to flow along the lossless path to the unfilled module 227, the entropy decoding module 225, and the prediction compensation mode. Group 221. Conversely, if the third data has been generated by compressing the second data in the lossy mode, the second mode selector 229 enables the third data to flow along the lossy path to the entropy decoding module 225 and the inverse quantization module 223 And prediction compensation module 221.

The unfilled module 227 may remove a portion of the data that has been filled by the fill module 217 of the encoder 210. When the filling module 217 is omitted, the unfilled module 227 may be omitted.

The entropy decoding module 225 can decompress the data that has been compressed by the entropy encoding module 215. The entropy decoding module 225 may perform decompression using Huffman decoding, exponential Columbus decoding, or Columbus decoding. Since the third data contains a k value, the entropy decoding module 225 may use the k value to perform decoding.

The inverse quantization module 223 can decompress the data that has been compressed by the quantization module 213. The inverse quantization module 223 may use a predetermined quantization parameter (QP) to recover the second data compressed by the quantization module 213. For example, the inverse quantization module 223 may perform an inverse quantization operation on the output of the entropy decoding module 225. However, the inverse quantization module 223 cannot fully recover the data lost during the compression process. Therefore, the inverse quantization module 223 is only in the lossy mode.

The prediction compensation module 221 may perform prediction compensation to restore data represented by the prediction module 211 as prediction data and residual data. For example, the prediction compensation module 221 can convert the residual data representation (253 (forecast), 1 (residual), 2 (residual)) into (253, 254, 255). For example, the prediction compensation module 221 may recover data by adding residual data to the prediction data.

The prediction compensation module 221 can recover data predicted by the prediction module 211 on a pixel-by-pixel basis or a block-by-block basis. Therefore, the second data may be recovered, or the third data may be decompressed and then transmitted to the multimedia IP 100.

The decompression manager 228 may perform an operation that appropriately reflects the combination of the QP table and the entropy table in the decompression of the third data, as described above with reference to FIG. Second information.

In an exemplary embodiment, the second data of the image processing device is data in a YUV format. Here, the data in the YUV format may have the YUV 420 format or the YUV 422 format.

5 is a conceptual diagram for explaining three operation modes of a YUV 420 data format processed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

1 to 5, the encoder 210 and the decoder 220 of the FBC 200 may have three operation modes. In FIG. 5, the second data in the YUV 420 format has a 16 × 16 brightness signal block Y, an 8 × 8 first chroma signal block Cb or U, and an 8 × 8 second chroma signal block Cr or V. . Here, the size of each block indicates how many columns and rows of pixels are arranged, and the 16 × 16 size indicates the size of a block composed of 16 columns and 16 rows of pixels.

The FBC 200 can include three modes of operation: cascade mode①, partial cascade mode②, and separation mode③. The three modes are about the compression format of the data, and may be operation modes that are respectively determined according to the lossy mode and the lossless mode. In an exemplary embodiment, only two of the three modes of operation are available. In another exemplary embodiment, only one of the three operation modes is available.

The cascade mode ① is an operation mode for compressing and decompressing the luma signal block Y, the first chroma signal block Cb, and the second chroma signal block Cr together. That is, in the cascade mode ①, the compression unit block is a block that combines the luma signal block Y, the first chroma signal block Cb, and the second chroma signal block Cr as described in FIG. 5. Therefore, the compression unit block may have a size of 16 × 24. For example, a single compression operation may be used to compress a data block including a luma signal block Y, a first chroma signal block Cb, and a second chroma signal block Cr.

In the partial cascade mode ②, the first chroma signal block Cb and the second chroma signal block Cr are combined with each other and compressed and decompressed together, and the lightness signal block Y is independently compressed and decompressed. Therefore, the luma signal block Y may have its original size of 16 × 16, and a block combining the first chroma signal block Cb and the second chroma signal block Cr may have a size of 16 × 8. For example, a first compression operation may be used to compress the luma signal block Y, and a second compression operation may be used to compress a data block including the first chroma signal block Cb and the second chroma signal block Cr.

The separation mode ③ is an operation mode for compressing and decompressing the luma signal block Y, the first chroma signal block Cb, and the second chroma signal block Cr, respectively. Here, in order to make the compression unit block and the decompression unit block the same size, the luma signal block Y is maintained at its original size of 16 × 16, and the first chroma signal block Cb and the second chroma signal block Cr is each enlarged to a size of 16 × 16. For example, a first compression operation may be used to compress the luma signal block Y, a second compression operation may be used to compress the first chroma signal block Cb, and a third compression operation may be used to compress the second chroma signal region Block Cr.

Therefore, if the number of luma signal blocks Y is N, the number of the first chroma signal blocks Cb and the number of the second chroma signal blocks Cr can be reduced to N / 4 each.

When the FBC 200 of the image processing apparatus according to an exemplary embodiment of the inventive concept operates in the cascade mode ①, all required data can be read via a single access request to the memory 300. In particular, when multimedia IP 100 requires data in RGB format instead of YUV format, it is advantageous for FBC 200 to operate in cascade mode①. This is because in the cascade mode ① all the luma signal blocks Y, the first chroma signal block Cb, and the second chroma signal block Cr can be obtained at one time, and this is because all the luma signal blocks Y, the first A chroma signal block Cb and a second chroma signal block Cr to obtain RGB data.

When the compression unit block is smaller in cascade mode ①, separation mode ③ may require less hardware resources. Therefore, when multimedia IP 100 requires materials in YUV format (rather than in RGB format), the separation mode ③ may be more advantageous.

Finally, part of the cascade mode ② is a compromise between the cascade mode ① and the separation mode ③. Even when RGB data is required, the partial cascade mode ② requires less hardware resources than the cascade mode ① and makes fewer access requests (two access requests) to the memory 300 than the split mode ③.

The first mode selector 219 determines in which of the three modes (ie, cascade mode ①, partial cascade mode ②, and separation mode ③) the second data will be compressed. The first mode selector 219 may receive a signal from the multimedia IP 100 indicating which one of the cascade mode ①, the partial cascade mode ②, and the separation mode ③ will be executed. For example, the signal can be set to a first voltage level used to indicate a cascade mode, a second voltage level used to indicate a portion of the cascade mode, and a third voltage level used to indicate a separation mode. A voltage level to a third voltage level are different from each other.

The second mode selector 229 may decompress the third data according to which one of the cascade mode ①, the partial cascade mode ②, and the separation mode ③ has been compressed into the third data. For example, if cascading mode is used to compress the second data, the second mode selector 229 can perform a single access to retrieve the lightness signal block Y, the first chrominance signal block Cb, and the second chrominance. Compressed data of signal block Cr. For example, if the second data is compressed using a partial cascade mode, the second mode selector 229 can perform two accesses to retrieve the first compressed data including the luma signal block Y and the first chroma signal. The second compressed data of the block Cb and the second chrominance signal block Cr. For example, if the second data is compressed using the split mode, the second mode selector 229 can perform three accesses to retrieve the first compressed data including the luma signal block Y and the first chroma signal block Cb. The second compressed data and the third compressed data including the second chrominance signal block Cr.

6 is a conceptual diagram for explaining three operation modes of a YUV 422 data format of an image processing apparatus according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 1 to 4 and FIG. 6, the encoder 210 and the decoder 220 of the FBC 200 may also have three operation modes in YUV 422 format. In FIG. 6, the second data in the YUV 422 format has 16 × 16 lightness signal blocks Y and 16 × 8 first chroma signal blocks Cb or U and 16 × 8 second chroma signal blocks Cr or V. .

In the cascade mode ①, the compression unit block is a block that combines the luma signal block Y, the first chroma signal block Cb, and the second chroma signal block Cr. Therefore, the compression unit block may have a size of 16 × 32.

In the partial cascade mode ②, the first chroma signal block Cb and the second chroma signal block Cr are combined with each other and compressed and decompressed together, and the lightness signal block Y is independently compressed and decompressed. Therefore, the luma signal block Y may have its original size of 16 × 16, and a block combining the first chroma signal block Cb and the second chroma signal block Cr may have a size of 16 × 16. Therefore, the size of the luma signal block Y may be equal to the size of a block combining the first chroma signal block Cb and the second chroma signal block Cr.

The separation mode ③ is an operation mode for compressing and decompressing the luma signal block Y, the first chroma signal block Cb, and the second chroma signal block Cr, respectively. Here, in order to make the compression unit block and the decompression unit block the same size, the luma signal block Y is maintained at its original size of 16 × 16, and the first chroma signal block Cb and the second chroma signal block Cr is each enlarged to a size of 16 × 16.

Therefore, if the number of luma signal blocks Y is N, the number of the first chroma signal blocks Cb and the number of the second chroma signal blocks Cr are each reduced to N / 2.

FIG. 7 illustrates a structure of data losslessly compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept. FIG. 8 is a table for explaining a compression method of the losslessly compressed data of FIG. 7.

Referring to FIGS. 1 to 8, the third data (ie, compressed data) includes a payload and a header.

The header indicates the compression ratio, and the payload contains the actual compressed data and the values needed for decompression.

In FIG. 8, a table for explaining lossless compression of a 16 × 16 block is explained by way of example. Since the data format is YUV 420 and the operation mode is separate mode ③, the luma signal block Y, the first chroma signal block Cb, or the second chroma signal block Cr in FIG. 5 may correspond to this table. Pixel depth indicates the bit value of the value represented in a pixel. For example, a pixel depth of 8 bits is required to represent values from 0 to 255. Therefore, in the example of FIG. 8, the value represented in each pixel may be 0 to 255.

In the memory 300, the size of the data that can be accessed at one time in hardware is predetermined. The size of the data access unit of the memory 300 may indicate the size of data that can be accessed in the memory 300. In FIG. 8, the size of the data access unit of the memory 300 is assumed to be 32 bytes for convenience.

One pixel may have 8 bits of data (ie, 1 byte) of data, and a 16 × 16 block may have a total of 256 bytes of data. That is, the size of the second data (ie, uncompressed data) may be 256 bytes.

For lossless compression, the size of the compressed data may be different every time. In order to read the compressed data from the memory 300, the size of the compressed data must be recorded separately. However, if the size of the compressed data is recorded as it is, the compression efficiency can be reduced by the recorded size. Therefore, the compression ratio can be standardized to improve the compression efficiency.

Specifically, in FIG. 8, the range of the compression ratio is defined based on 32 bytes, which is the size of the data access unit of the memory 300. That is, if the size of the compressed data is 0 bytes to 32 bytes, the compression ratio is 100% to 87.5%. In this case, an operation of adjusting the compression ratio to 87.5% (that is, an operation of adjusting the size of the compressed data to 32 bytes) may be performed, and 0 may be recorded in the header. Similarly, if the size of the compressed data is 161 bytes to 192 bytes, the compression ratio is 37.5% to 25%. In this case, an operation of adjusting the compression ratio to 25% (that is, an operation of adjusting the size of the compressed data to 192 bytes) may be performed, and 5 may be recorded in the header.

The padding module 217 of FIG. 3 can perform the operation of adjusting the size of the compressed data to the maximum size of the corresponding range. That is, if the size of the compressed data is 170 bytes, since the 170 bytes are between 161 bytes and 192 bytes, a 22-byte " 0 "padding operation to adjust the size of the compressed data to 192 bytes.

The compressed data whose size has been adjusted to the maximum size of the corresponding range by the padding module 217 can be changed into the payload of the third data. Therefore, the size of the payload (n1 bits) may be an integer multiple of the size of the data access unit of the memory 300.

The header may include a header index of FIG. 8. The size of the header can vary depending on the size of the compressed data, but it can be 3 bits in terms of FIG. 8 because the header only represents 0 to 7.

In an exemplary embodiment, the header and the payload are stored in different regions of the memory 300. That is, a header may be stored adjacent to another header, and a payload may be stored adjacent to another payload.

In one embodiment, the payload includes a binary code and a k- value code. The binary code may represent the compressed second data. The k value code may represent a k value determined by the entropy coding module 215.

Binary codes can contain data values for the entire block. Therefore, the binary code can successively contain the data of each pixel contained in the block.

Since the current mode is the separation mode ③, the k value code is the k value of any one of the luma signal block Y, the first chroma signal block Cb, and the second chroma signal block Cr.

FIG. 9 illustrates the structure of data losslessly compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept. FIG. 10 is a table for explaining a compression method of the losslessly compressed data of FIG. 9.

In FIG. 10, a table for explaining lossless compression of a 16 × 8 block is explained by way of example. Since the data format is YUV 420 and the operation mode is a partial cascade mode ②, a block combining the first chroma signal block Cb and the second chroma signal block Cr of FIG. 5 may correspond to this table. In FIG. 10, the size of the data access unit of the memory 300 is assumed to be 32 bytes for convenience.

A 16 × 8 block may have a total of 128 bytes of data. That is, the size of the second data may be 128 bytes.

The range of the compression ratio is defined based on 32 bytes, which is the size of the data access unit of the memory 300. That is, if the size of the compressed data is 0 to 32 bytes, the compression ratio is 100% to 75%. In this case, an operation of adjusting the compression ratio to 75% (that is, an operation of adjusting the size of the compressed data to 32 bytes) may be performed, and 0 may be recorded in the header. Similarly, if the size of the compressed data is 97 bytes to 128 bytes, the compression ratio is 25% to 0%. In this case, an operation of adjusting the compression ratio to 0% (that is, an operation of adjusting the size of the compressed data to 128 bytes) may be performed, and 3 may be recorded in the header. This operation may be performed by the filling module 217 of FIG. 3.

Referring to FIG. 9, the compressed data whose size has been adjusted to the maximum size of the corresponding range by the padding module 217 can be changed into the payload of the third data. Therefore, the size of the payload (n2 bits) may be an integer multiple of the size of the data access unit of the memory 300.

In one embodiment, the payload includes a binary code and a k- value code. Since the current mode is a partial cascade mode② and the 16 × 8 block is a block that combines the first chroma signal block Cb and the second chroma signal block Cr, the k value code includes the first chroma signal block Cb value of k code block and the second chrominance signal Cr k value code. The arrangement order of the k- value codes of the first chrominance signal block Cb and the k- value codes of the second chrominance signal block Cr can be changed.

The payload of the image processing apparatus of the exemplary embodiment includes only one value of k code, instead of a first chroma signal blocks each having a k value Cb chrominance signal block and the second code value of k code Cr. In this case, the k- value code is the same in the first chroma signal block Cb and the second chroma signal block Cr.

Since FIG. 9 illustrates a data structure in which the blocks of the first chrominance signal block Cb and the second chrominance signal block Cr are combined in the partial cascade mode ②, the binary code may include information about the first chroma signal region Both the data of the block Cb and the data about the second chrominance signal block Cr.

In the binary code, first, information about the first chroma signal block Cb can be placed for all pixels, and then data about the second chroma signal block Cr can be placed for all pixels. That is, the data of the first chroma signal block Cb and the data of the second chroma signal block Cr may be arranged separately. The arrangement order of the data of the first chroma signal block Cb and the data of the second chroma signal block Cr can be changed.

Alternatively, the binary code of the image processing apparatus according to the exemplary embodiment has an interleaved structure, in which the data of the first chroma signal block Cb and the data of the second chroma signal block Cr are sequentially arranged for one pixel, and The data of the first chrominance signal block Cb and the data of the second chrominance signal block Cr are sequentially arranged for another pixel.

It is not necessary to consider this structure in the separation mode ③, because only one plane is included in the separation mode ③. However, since multiple planes are included in the cascade mode ① and part of the cascade mode ②, a staggered structure can be used.

Therefore, in the cascade mode ①, the data of the luma signal block Y for all pixels, the data of the first chroma signal block Cb, and the second chroma signal can be arranged in the binary code. Block Cr data. The arrangement order of the data of the luma signal block Y, the data of the first chroma signal block Cb, and the data of the second chroma signal block Cr can be changed.

Alternatively, in the binary code of the cascade mode ①, the data of the luma signal block Y, the data of the first chroma signal block Cb, and the data of the second chroma signal block Cr may be arranged for one pixel. Then, the data of the luma signal block Y, the data of the first chroma signal block Cb, and the data of the second chroma signal block Cr can be arranged for another pixel.

That is, in the binary code, data can be arranged for each plane or data can be arranged for each pixel (interleaved structure).

FIG. 11 illustrates a structure of data losslessly compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

Referring to FIG. 11, if the current mode is the cascade mode ①, a block combining the luma signal block Y, the first chroma signal block Cb, and the second chroma signal block Cr is compressed. Accordingly, the k value k value of the code may comprise code lightness Y of the signal block, the first block of Cb chrominance signal values of k code block and the second chrominance signal Cr k value code. Here, the arrangement order of the k- value code of the luma signal block Y, the k- value code of the first chroma signal block Cb, and the k- value code of the second chroma signal block Cr may be changed.

The image processing apparatus payload embodiment includes only a code value k, the k value does not have code block luminance signal Y, the first chrominance signal Cb block and the second code value of k chrominance signal region The k value code of the block Cr. In this case, the k- value code is the same in the luma signal block Y, the first chroma signal block Cb, and the second chroma signal block Cr.

Alternatively, if only two of the three planes share the same k- value code, a total of two k- value codes may be included in the payload.

In one embodiment, the size (n3 bits) of the payload including the binary code and the k- value code is an integer multiple of the size of the data access unit of the memory 300.

FIG. 12 illustrates a structure of data that is lossy-compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

Referring to FIG. 12, the third data generated by compressing the second data in a lossy mode includes only a payload without a header.

In one embodiment, the payload includes a binary code, a k- value code, and a QP code. In one embodiment, the QP code includes a QP used by the quantization module 213 in FIG. 3. In one embodiment, the inverse quantization module 223 of the decoder 220 decompresses the data compressed by the quantization module 213 using a QP code.

The third data of FIG. 12 may be a structure of the third data corresponding to the separation mode ③. Therefore, the k- value code and the QP code may exist only for one of the luma signal block Y, the first chroma signal block Cb, and the second chroma signal block Cr.

Since the compression ratio is fixed in the lossy mode, the size of the third data (that is, the size of the payload (m1 bits)) may be fixed.

FIG. 13 illustrates the structure of data that is lossy compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

Referring to FIG. 13, the payload includes a binary code, a k- value code, and a QP code. The third data of FIG. 13 may be a structure of the third data in which the first chroma signal block Cb and the second chroma signal block Cr are combined in the partial cascade mode ②. Therefore, there are two k- value codes and two QP codes. Specifically words, the payload signal block comprising a first chrominance Cb value of k symbols, the second block of Cr chrominance signal values of k symbols, the first block of Cb chrominance signal and a second chrominance signal QP codes QP code for block Cr.

A first chrominance signal Cb value of k code block, the second block of Cr chrominance signal values of the code k, a first chrominance signal Cb, QP code block, the second block of Cr chrominance signal and QP code The order of the binary codes (ie, the compressed data) can vary.

In one embodiment, two k- value codes are shared. Therefore, when the same k- value code is shared, only one k- value code exists.

Similarly, two QP codes can be shared. Therefore, when the same QP code is shared, only one QP code exists. FIG. 14 illustrates the structure of data that is lossy compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

Referring to FIG. 14, the payload includes a binary code, a k- value code, and a QP code. The third data of FIG. 14 may be a structure of the third data in which the luma signal block Y, the first chroma signal block Cb, and the second chroma signal block Cr are combined in the cascade mode ①. Therefore, there are three k- value codes and three QP codes. Specific, payload code comprising k values of Y luminance signal block, the first block of Cb chrominance signal values of k symbols, the second block of Cr chrominance signal values of k code, Y is the brightness signal block QP Code, the QP code of the first chroma signal block Cb, and the QP code of the second chroma signal block Cr.

Y luminance signal block values of k symbols, the first chrominance signal Cb value of k code block, the second block of Cr chrominance signal values of the code k, the brightness signal Y QP code block, a first chrominance signal The order of the QP code of the block Cb, the QP code of the second chrominance signal block Cr, and the binary code may be changed.

In one embodiment, three k- value codes are shared. Therefore, when the same k value is shared, there is only one k value code. When only two of the three planes share k- value codes, there are only two k- value codes.

Similarly, three QP codes can be shared. Therefore, when the same QP code is shared, only one QP code exists. When only two of the three planes share a QP code, there are only two QP codes.

An image processing apparatus according to an exemplary embodiment of the inventive concept will now be described with reference to FIGS. 1 to 6 and 15.

FIG. 15 illustrates a structure of data that is lossy-compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

Referring to FIG. 1 to FIG. 6 and FIG. 15, in the lossy mode, the payload may include only a binary code and a maximum QP code without a k- value code. Here, the QP stored in the maximum QP code may be the maximum value among possible QPs. If the pixel data has a value of 0 to 2 ⁸ -1 (= 255), the QP can be limited to 1 / (2 ⁿ -1) (where n is an integer of 8 or less). However, the current embodiment is not limited to this case.

In one embodiment, the entropy encoding module 215 performs entropy decoding by allocating bits based on frequency of similar data. If QP is the maximum, the frequency of similar data is not high. Therefore, performing entropy coding can increase the data size.

Therefore, the second data of the image processing apparatus according to the embodiment of the inventive concept is directly converted into the third data by the quantization module 213 of the encoder 210 and is not transmitted through the entropy encoding module 215.

Therefore, when the QP of the quantization module 213 has a maximum value, the encoder 210 of the image processing apparatus according to the embodiment does not include the k- value code in the payload, and only includes the binary code and the maximum QP code in the payload. in.

An image processing apparatus according to an exemplary embodiment will now be described with reference to FIG. 16.

FIG. 16 is a block diagram of an image processing apparatus according to an exemplary embodiment of the inventive concept.

Referring to FIG. 16, an FBC 200 of an image processing apparatus according to an exemplary embodiment of the inventive concept is directly connected to a system bus 400.

The FBC 200 is not directly connected to the multimedia IP 100, but is connected to the multimedia IP 100 via the system bus 400. Specifically, each of the ISP 110, G2D 120, MFC 130, GPU 140, and display 150 of the multimedia IP 100 may exchange data with the FBC 200 via the system bus 400 and transmit the data to the memory via the system bus 400 300.

That is, in the compression operation, each of the ISP 110, G2D 120, MFC 130, GPU 140, and display 150 of the multimedia IP 100 may transfer the second data (ie, uncompressed data) via the system bus 400. Transfer to FBC 200. Then, the FBC 200 may compress the second data into the third data and transmit the third data (ie, the compressed data) to the memory 300 via the system bus 400.

Similarly, in the decompression operation, the FBC 200 may receive the third data stored in the memory 300 via the system bus 400 and decompress the third data into the second data. Then, the FBC 200 may transmit the second data to each of the ISP 110, the G2D 120, the MFC 130, the GPU 140, and the display 150 of the multimedia IP 100 via the system bus 400.

In the embodiment of FIG. 16, although the FBC 200 is not directly connected to the ISP 110, G2D 120, MFC 130, GPU 140, and display 150 of the multimedia IP 100, the FBC may be indirectly connected to the multimedia IP via the system bus 400 100 ISP 110, G2D 120, MFC 130, GPU 140, and display 150. Therefore, the hardware configuration can be simplified and the operation speed can be increased.

An image processing apparatus according to an exemplary embodiment of the inventive concept will now be described with reference to FIG. 17.

FIG. 17 is a block diagram of an image processing apparatus according to an exemplary embodiment of the inventive concept.

Referring to FIG. 17, the image processing apparatus according to the embodiment is configured such that the memory 300 and the system bus 400 are connected to each other via the FBC 200.

That is, the memory 300 is not directly connected to the system bus 400, but is only connected to the system bus 400 via the FBC 200. In addition, the ISP 110, G2D 120, MFC 130, GPU 140, and display 150 of the multimedia IP 100 can be directly connected to the system bus 400. Therefore, the ISP 110, G2D 120, MFC 130, GPU 140, and display 150 of the multimedia IP 100 can access the memory 300 only through the FBC 200.

Since the FBC 200 involves all accesses to the memory 300 in the current embodiment, the FBC 200 may be directly connected to the system bus 400 and the memory 300 may be connected to the system bus 400 via the FBC 200. This can reduce errors in data transmission and increase operation speed.

100‧‧‧Multimedia intellectual property rights

110‧‧‧Image Signal Processor

120‧‧‧Shake correction module

130‧‧‧Multi-format codec

140‧‧‧Graphics Processing Unit

150‧‧‧ Display

200‧‧‧Frame buffer compressor

210‧‧‧ Encoder

211‧‧‧ Forecast Module

213‧‧‧Quantitative module

215‧‧‧Entropy coding module

217‧‧‧ Fill module

218‧‧‧Compression Manager

219‧‧‧Mode selector

220‧‧‧ decoder

221‧‧‧ Forecast Compensation Module

223‧‧‧Inverse quantization module

225‧‧‧ Entropy Decoding Module

227‧‧‧Unfilled Module

228‧‧‧Unzip Manager

229‧‧‧Mode selector

300‧‧‧Memory

400‧‧‧System Bus

Cb‧‧‧The first chroma signal block

Cr‧‧‧Second Chroma Signal Block

Y‧‧‧Brightness signal block

①‧‧‧Cascade Mode

②‧‧‧Partial Cascade Mode

③‧‧‧Separation mode

The invention will become apparent by describing its exemplary embodiments in detail with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of an image processing apparatus according to an exemplary embodiment of the inventive concept.

FIG. 2 is a detailed block diagram of the frame buffer compressor (FBC) illustrated in FIG. 1.

FIG. 3 is a detailed block diagram of the encoder illustrated in FIG. 2.

FIG. 4 is a detailed block diagram of the decoder illustrated in FIG. 2.

5 is a conceptual diagram for explaining three operation modes of a YUV 420 format material of an image processing apparatus according to an exemplary embodiment of the inventive concept.

6 is a conceptual diagram for explaining three operation modes of a YUV 422 format material of an image processing apparatus according to an exemplary embodiment of the inventive concept.

FIG. 7 illustrates a structure of data losslessly compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

FIG. 8 is a table for explaining a compression method of the losslessly compressed data of FIG. 7.

FIG. 9 illustrates the structure of data losslessly compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

FIG. 10 is a table for explaining a compression method of the losslessly compressed data of FIG. 9.

FIG. 11 illustrates a structure of data losslessly compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

FIG. 12 illustrates a structure of data that is lossy-compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

FIG. 13 illustrates the structure of data that is lossy compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

FIG. 14 illustrates the structure of data that is lossy compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

FIG. 15 illustrates a structure of data that is lossy-compressed by an image processing apparatus according to an exemplary embodiment of the inventive concept.

FIG. 16 is a block diagram of an image processing apparatus according to an exemplary embodiment of the inventive concept.

FIG. 17 is a block diagram of an image processing apparatus according to an exemplary embodiment of the inventive concept.

Claims (20)

An image processing device configured to compress first image data, the image processing device includes: An encoding circuit configured to compress the first image data into second image data including prediction data and residual data, and performing entropy encoding on the second image data to compress the second image data into The third image data generates a header indicating a compression ratio of the third image data, and stores the third image data together with the header as a compressed first image data in a memory device. The image processing device described in item 1 of the patent application scope further includes: Intellectual Property Rights (IP) core directly connected to the encoding circuit; and A data bus directly connected to the IP core and the memory device, The encoding circuit directly receives the first image data from the IP core, the encoding circuit directly transmits the compressed first image data to the IP core, and the IP core converges through the data And transmitting the compressed first image data for storage in the memory device. The image processing device described in item 1 of the patent application scope further includes: Intellectual Property Rights (IP) core; and The data bus is directly connected to the IP core, the encoding circuit, and the memory device, The encoding circuit receives the first image data indirectly from the IP core via the data bus, and the encoding circuit indirectly transmits the compressed first image data to the data bus through the data bus. Memory device. The image processing device described in item 1 of the patent application scope further includes: Intellectual Property Rights (IP) core; and The data bus is directly connected to the IP core and the encoding circuit, The encoding circuit receives the first image data from the IP core indirectly via the data bus, and the encoding circuit directly transmits the compressed first image data to the memory device. The image processing device according to item 1 of the patent application range, wherein the header includes an index corresponding to a compression ratio range among a plurality of available compression ratio ranges, and the compression ratio of the third image data satisfies The one compression range. The image processing device according to item 1 of the scope of patent application, wherein the encoding circuit adjusts a size of the first compressed data to a size of a data access unit of the memory device. The image processing device according to item 1 of the scope of patent application, wherein the compressed first image data further includes at least one entropy coding value used for the entropy coding. The image processing apparatus according to item 7 of the scope of patent application, wherein the entropy coding includes quantizing the second image data using at least one quantization parameter (QP), and performing entropy coding on a result of the quantization. The image processing device according to item 8 of the scope of patent application, wherein the compressed first image data further includes the at least one QP. The image processing device according to item 1 of the scope of patent application, wherein the encoding circuit includes a mode selection circuit configured to receive information, and the information indicates that the compression mode is i) a cascade mode, ii ) One of a partial cascade mode and iii) a separation mode, During the cascade mode, the encoding circuit compresses the first combination of lightness data, first chrominance data, and second chrominance data into a first combination data and compresses the first combination data. video material, During the partial cascade mode, the encoding circuit compresses the lightness data, combines the first chrominance data and the second chrominance data into a second combination data, and compresses the second Combining data to compress the first image data, and During the separation mode, the encoding circuit compresses the first image data by compressing the luma data, the first chroma data, and the second chroma data, respectively. An image processing device configured to compress first image data, the image processing device includes: Encoding circuit, including: A mode selection circuit configured to determine whether to set the first mode to a lossless compression mode or a lossy compression mode based on the received signal; A first logic circuit configured to compress the first image data into second image data including prediction data and residual data; A second logic circuit configured to quantize the second image data using at least one quantization parameter (QP); A third logic circuit configured to i) output the first logic circuit when the first mode is set to the lossless compression mode and ii) set the first mode to the One of the outputs of the second logic circuit in the lossy compression mode performs entropy coding. The image processing device according to item 11 of the patent application scope further includes: Intellectual Property Rights (IP) core directly connected to the encoding circuit; and A data bus directly connected to the IP core and the memory device, The encoding circuit directly receives the first image data from the IP core, and the encoding circuit directly transmits the compressed first image data generated based on the output of the third logic circuit to the IP core, And the IP core transmits the compressed first image data through the data bus so as to be stored in the memory device. The image processing device according to item 11 of the patent application scope further includes: Intellectual Property Rights (IP) core; and The data bus is directly connected to the IP core, the encoding circuit, and the memory device, Wherein the encoding circuit receives the first image data indirectly from the IP core via the data bus, and the encoding circuit will generate a process based on the output of the third logic circuit via the data bus. The compressed first image data is indirectly transmitted to the memory device. The image processing device according to item 11 of the patent application scope further includes: Intellectual Property Rights (IP) core; and The data bus is directly connected to the IP core and the encoding circuit, The encoding circuit receives the first image data from the IP core indirectly through the data bus, and the encoding circuit directly generates the compressed first image data based on the output of the third logic circuit. To the memory device. The image processing device according to item 11 of the scope of patent application, wherein the encoding circuit determines a compression ratio of the data output by the third logic circuit, generates a header indicating the compression ratio, and converts the third The output of the logic circuit is stored in the memory device together with the header as compressed first image data. The image processing device according to item 15 of the patent application range, wherein the header includes an index corresponding to a compression ratio range among a plurality of available compression ratio ranges, and the compression ratio conforms to the one compression range. The image processing device according to item 11 of the patent application scope, wherein the encoding circuit adjusts a size of the first compressed data to a size of a data access unit of the memory device. The image processing device according to item 15 of the scope of patent application, wherein the compressed first image data further includes at least one entropy encoding value using the entropy encoding. The image processing device according to item 15 of the scope of patent application, wherein when the first mode is set to the lossy compression mode, the compressed first image data further includes the at least one QP. The image processing device according to item 11 of the scope of patent application, wherein the mode selection circuit is configured to determine whether to set the second mode to i) cascade mode, ii) partial cascade mode, and iii) separate mode One of During the cascade mode, the first logic circuit compresses the lightness data, the first chrominance data, and the second chrominance data into a first combination data and compresses the first combination data. First image data, During the partial cascade mode, the first logic circuit compresses the lightness data, combines the first chroma data and the second chroma data into a second combination data, and compresses the light data. A second combination of data to compress the first image data, and During the separation mode, the first logic circuit compresses the first image data by compressing the luma data, the first chroma data, and the second chroma data, respectively.