TW201939610A - Method of manufacturing semiconductor device, method of manufacturing electronic device, semiconductor device and electronic device - Google Patents

Abstract

A method of manufacturing a semiconductor device including a first film-forming step of forming a film of an organic semiconductor layer (30, 60) on a substrate (P) on which an electrode is formed, a second film-forming step of forming a first protective layer (32, 62) on a surface of the organic semiconductor layer, a first pattern-forming step of forming a predetermined pattern in the first protective layer by irradiating the first protective layer with light to expose the first protective layer, and a second film-forming step of forming the predetermined pattern in the organic semiconductor layer by etching the organic semiconductor layer using the first protective layer with the predetermined pattern as a mask.

Description

Manufacturing method of semiconductor element, manufacturing method of electronic device, semiconductor element and electronic device

The present invention relates to a method for manufacturing a semiconductor element, a method for manufacturing an electronic device, a semiconductor element, and an electronic device on an organic semiconductor layer formed on a substrate on which an electrode is formed to form a passivation film as a protective layer.

Among known thin film transistors as a semiconductor element, there are organic thin film transistors and inorganic thin film transistors. Organic thin film transistors can be made at a lower temperature than inorganic thin film transistors using conventional inorganic materials (silicon, etc.). The material is flexible, so it can be used in soft resins such as PET (polyethylene terephthalate). An organic thin film transistor is formed on the substrate. In addition, organic thin-film transistors can be formed using a solution process that is inexpensive and suitable for large-scale production. Therefore, it is expected that organic thin-film transistors can be manufactured using a roll-to-roll manufacturing system and used as a new generation of soft electronic equipment. The core research is carried out. In this roll-to-roll manufacturing system, the substrate supplied by the supply roll that rolls the substrate into a roll is subjected to a specific treatment and is taken up by a recovery roll.

In order to apply organic thin film transistors to devices such as electronic paper or organic EL displays, it is necessary to use a passivation film (protective layer) to eliminate damage to the organic semiconductor layer caused by the organic thin film transistor manufacturing steps (photoetching steps, etc.). membrane. As a method for forming a passivation film, in order to flexibly utilize the advantages of a solution manufacturing process of an organic thin film transistor or to have flexibility and the like, it is ideal to form a film by a solution manufacturing process.

Japanese Patent Publication No. 2013-504186 discloses a two-layer passivation layer (a first passivation layer and a second passivation layer) which can be formed into a film by a solution process. The first passivation layer protects the organic semiconductor layer with a resin that can be dissolved with water or a fluorine-based solvent, and the second passivation layer is laminated on the first passivation layer with a chemical-resistant resin, thereby suppressing the processing caused by subsequent steps Degradation of the organic semiconductor layer. It is desirable to form an organic semiconductor layer into a desired pattern in such an organic thin film transistor.

A first aspect of the present invention includes: a first film forming step of forming an organic semiconductor layer on a substrate on which an electrode is formed; and a second film forming step of forming a first protective layer on a surface of the organic semiconductor layer. A film; a first pattern forming step, which exposes the first protective layer by irradiating the first protective layer with light, and forms a specific pattern on the first protective layer; and a second pattern forming step, which involves The first protective layer on which the specific pattern is formed serves as a mask and the organic semiconductor layer is etched to form the specific pattern on the organic semiconductor layer.

A second aspect of the present invention is a method for manufacturing an electronic device, which includes the method for manufacturing the semiconductor element according to the first aspect.

A third aspect of the present invention is a semiconductor element including an organic semiconductor layer formed on a substrate on which an electrode is formed, a first protective layer formed on a surface of the organic semiconductor layer, and a first protective layer covering the first semiconductor layer. The second protective layer formed as a protective layer, wherein the first protective layer is made of a first resin that is hardened by light.

A fourth aspect of the present invention is a semiconductor element including an organic semiconductor layer formed on a substrate on which an electrode is formed, a first protective layer formed on a surface of the organic semiconductor layer, and a first protective layer covering the first semiconductor layer. The second protective layer formed as a protective layer has a lower solubility in the first solvent than the first protective layer.

A fifth aspect of the present invention is an electronic device including the semiconductor element of the third or fourth aspect.

The above-mentioned objects, features, and advantages should be easily understood from the following description of the embodiments described with reference to the accompanying drawings.

In the following, preferred embodiments of the method for manufacturing a semiconductor element according to the present invention, a method for manufacturing an electronic device including the method for manufacturing the semiconductor element, a semiconductor element, and an electronic device having the semiconductor element are proposed, with reference to the accompanying The attached drawings are explained in detail. In addition, the aspects of the present invention are not limited to the forms of implementation, but also include those implementing various changes or improvements. That is, the constituent elements described below include those that can be easily assumed by those in the industry and are substantially the same, and the constituent elements described below can be appropriately combined. In addition, various omissions, substitutions, or changes of constituent elements can be made without departing from the gist of the present invention.

[First Embodiment]
In the first embodiment, a method for manufacturing a semiconductor element (organic thin film transistor with a passivation film) having a bottom gate and bottom contact type organic thin film transistor (organic TFT) will be described. The semiconductor device of the first embodiment has a structure in which a gate electrode layer, an insulator layer, a source electrode, a drain electrode layer, an organic semiconductor layer, a first protective layer, and a second protective layer are laminated on a substrate in the above-mentioned order. on.

Although not shown in the first embodiment, semiconductor devices are manufactured using a roll-to-roll manufacturing system. The roll-to-roll manufacturing system refers to the supply of a substrate that is rolled into a roll. After the substrate supplied by the roller is subjected to a specific treatment, it is taken up by a recovery roller. Therefore, the substrate on which the semiconductor element is formed must be a sheet-like substrate having softness, that is, flexibility.

The substrate is made of, for example, a resin film or a foil made of a metal or an alloy such as stainless steel. Examples of the material of the resin film include polyethylene resin, polypropylene resin, polyester resin, ethylene copolymer resin, polyvinyl chloride resin, cellulose resin, polyamide resin, polyimide resin, and polycarbonate. At least one of an ester resin, a polystyrene resin, and a vinyl acetate resin. In addition, the thickness or rigidity (Young's modulus) of the substrate need only be within the range that the substrate does not cause creases or irreversible wrinkles due to bending when passing through a conveyance path such as an exposure device. As the base material of the substrate, a film such as PET (polyethylene terephthalate) or PEN (polyethylene naphthalate) having a thickness of about 25 μm to 200 μm is typical of a preferred sheet substrate.

As the substrate, heat may be applied to the substrate, so it is preferable to select a material composed of a material whose thermal expansion coefficient is not significantly large. For example, a thermal expansion coefficient can be suppressed by mixing an inorganic filler with a resin film. Examples of the inorganic filler include titanium oxide, zinc oxide, aluminum oxide, and silicon oxide. In addition, the substrate may be a single-layer body of ultra-thin glass having a thickness of about 100 μm manufactured by a float method or the like, or a laminated body in which the above-mentioned resin film, foil, and the like are bonded to the ultra-thin glass.

In addition, the so-called flexibility of the substrate refers to the property that the substrate can be bent without being cut or broken even if a force of about its own weight is applied to the substrate. In addition, the property of being bent by a force of its own weight is also flexible. In addition, the degree of flexibility varies depending on the material, size, thickness of the substrate, the layer structure formed on the substrate, the environment such as temperature and humidity, and the like. In any case, as long as the substrate can be correctly wound around various conveying direction-changing members such as conveying rollers and drums provided in the conveying path in the roll-to-roll manufacturing system, it is allowed to bend without leaving. Lower creases can be used to convey substrates smoothly without causing breakage (cracks or breaks). The formation of each layer of the semiconductor device will be described below.

(About the formation of the gate electrode layer)
A soft substrate P such as PET is a member that is difficult to be plated. Therefore, as shown in FIG. 1A, an amine layer 10 is first formed on the substrate P. The amine layer 10 is a silane coupling agent layer having a primary or secondary amine group. That is, the surface of the substrate P is coated with an amine solution obtained by adding a solvent to a silane coupling agent (amine molecule) having a primary or secondary amine group. As a coating method, a generally known method such as spin coating, dip coating, spray coating, roll coating, brush coating, flexographic printing, or screen printing can be used. Then, the solvent is volatilized by heat treatment to form a film of the amine layer 10. Since the amine layer 10 is an extremely thin silane coupling agent layer, it is a transparent film without light scattering. Therefore, when the gate electrode layer is produced, it is only necessary to form the entire amine layer 10 into a film, and it is easy to form a film.

As shown in FIG. 1B, a positive-type photoresist layer 12 is formed on the amine layer 10. Furthermore, the photoresist layer 12 is formed by coating a photoresist material on the amine layer 10 and performing pre-baking. Then, the light is irradiated (UV light (ultraviolet light) in this embodiment) through a mask M1 (mask M1 having an opening portion ma1 in a region where the gate electrode G is formed) formed with a specific pattern. The photoresist layer 12 is exposed. Thereafter, by immersing the photoresist layer 12 (substrate P) in a developing solution (for example, TMAH, etc.), as shown in FIG. 1C, the photoresist layer 12 of the portion (the exposed portion) irradiated with UV light is dissolved and Was removed. Thereby, a specific pattern corresponding to the gate electrode G is formed in the photoresist layer 12. That is, a pattern having an opening portion 12a is formed in a region where the gate electrode G is formed.

Then, as shown in FIG. 2A, a catalyst solution containing a catalyst (Pd) 14 for electroless plating is applied to the substrate P. The photoresist layer 12 having a specific pattern is laminated on the amine layer 10, so the catalyst 14 is provided on the amine layer 10 in a region exposed through the opening portion 12a. The primary or secondary amine group contained in the amine layer 10 has the property of reducing Pd ions contained in the catalyst solution to Pd metal and capturing it. Therefore, the activation treatment for reducing Pd ions, which is usually necessary, can be omitted, and the process can be environmentally friendly. Thereafter, as shown in FIG. 2B, the entire substrate P is immersed in an electroless plating solution such as nickel-phosphorus, and metal ions are reduced and precipitated on the surface of the catalyst 14. The deposited metal layer becomes the gate electrode layer 16. Therefore, a gate electrode layer 16 having a gate electrode G is selectively formed on the substrate P. Thereafter, the photoresist layer 12 (substrate P) is immersed in a developing solution by exposing UV light to the entire surface of the remaining photoresist layer 12, and the photoresist layer 12 is removed as shown in FIG. 2C.

Through the above steps, the gate electrode layer 16 is formed on the substrate P. The amine layer 10 is very thin, so that the surface of the substrate P can be hardly formed into a film, and the gate electrode layer 16 having high flatness can be obtained. Therefore, it is possible to fabricate a multilayer metal structure with low leakage. Furthermore, the gate electrode layer 16 can also be formed by patterning by a method of etching a metal film such as aluminum or a printing method.

(About formation of insulator layer)
The insulator layer 18 is made of a photo-curable photosensitive resin having an insulating property, for example, a UV-curable acrylic resin, a UV-curable epoxy resin, a UV-curable olefin-thiol resin, or a UV-curable resin. It is made of polysiloxane resin. Since the photo-curable resin is used, the insulator layer 18 can be patterned by irradiation with UV light.

First, as shown in FIG. 3A, an insulator layer solution is coated on the substrate P on which the gate electrode layer 16 is formed, and the insulator layer 18 is formed into a film. A mask M2 having a specific pattern is formed (for forming an insulator layer) A mask M2 having an opening ma2 in the area of 18) radiates UV light to the insulator layer 18. As a result, as shown in FIG. 3B, the insulator layer 18 in a region irradiated with UV light (the region where the insulator layer 18 is to be formed) is hardened. In FIG. 3B, the hardened portion is indicated by dots, and the unhardened portion is indicated by hatching. As such, the insulator layer 18 can be selectively hardened by using the mask M2. Furthermore, at this time, it is more preferable to perform a heat treatment for promoting a chemical reaction in a region irradiated with UV light. Then, as shown in FIG. 3C, an insulator layer 18 is formed by dissolving and removing a portion that is not irradiated with UV light (a portion indicated by hatching) with a developing solution, and the insulator layer 18 is formed corresponding to the mask M2 Specific patterns. That is, the portion of the insulator layer 18 that remains irradiated with UV light and hardens remains.

Through the above steps, an insulator layer 18 is formed on the gate electrode layer 16. Furthermore, in order to suppress leakage between the gate electrode G and the source and drain electrodes S and D (see FIG. 5A), the insulator layer 18 needs to have a thickness of several hundred nm. The thickness of the insulator layer 18 can be controlled by the resin concentration or the coating conditions. The insulator layer 18 can also be formed by performing a patterning process such as a printing method on a material such as a photocurable resin or a thermosetting resin. Therefore, it can be applied as long as it has insulating properties and can be applied.

(About the formation of source and drain electrode layers)
The source and drain electrode layers can be manufactured by a process substantially the same as the manufacturing steps of the gate electrode layer 16 described above. First, as shown in FIG. 4A, an amine layer 20 is formed on the insulator layer 18. As shown in FIG. 4B, a positive-type photoresist layer 22 is formed on the amine layer 20, and a mask M3 having a specific pattern is formed (there are openings in a region where the source electrode S and the drain electrode D are formed). The mask M3 of ma3) irradiates UV light, thereby exposing the photoresist layer 22. Thereafter, by immersing the photoresist layer 22 (substrate P) in a developing solution, as shown in FIG. 4C, the photoresist layer 22 of the portion (the exposed portion) irradiated with UV light is dissolved and removed. Thereby, a pattern corresponding to the source electrode S and the drain electrode D is formed in the photoresist layer 22. That is, a pattern having an opening portion 22a is formed in a region where the source electrode S and the drain electrode D are formed.

Next, a catalyst solution containing a catalyst (Pd) 24 for electroless plating is applied to the substrate P, and the entire substrate P is immersed in an electroless plating solution such as nickel phosphorus as shown in FIG. 5A. The metal ions are reduced and precipitated on the surface of the catalyst 24. A photoresist layer 22 having a specific pattern formed thereon is laminated on the amine layer 20, and a catalyst 24 is provided on the amine layer 20 in an area exposed in the opening 22a, and a metal is precipitated on the surface of the catalyst 24. The deposited metal layer becomes the source and drain electrode layers 26. Therefore, on the substrate P (on the insulator layer 18), a source and a drain electrode layer (metal layer) 26 having a source electrode S and a drain electrode D are selectively formed. Thereafter, the entire surface of the remaining photoresist layer 22 is exposed to UV light, and the photoresist layer 22 (substrate P) is immersed in a developing solution, as shown in FIG. 5B, to remove the photoresist layer 22.

In addition, since the substrate P is immersed in the plating-replacement gold bath and then immersed in the plating-reduction gold bath, as shown in FIG. 5C, the surfaces of the source and drain electrode layers 26 are covered with gold 28. Thereby, the source electrode S and the drain electrode D are covered with gold 28. When an organic semiconductor layer with a high HOMO energy level, such as thick pentabenzene, is formed on the surface of the source and drain electrode layers 26 (see FIG. 6A), it is desirable to cover the source electrode S and the drain electrode D with gold 28. Furthermore, although it is covered with gold 28, it may be covered with a metal material having a work function suitable for the HOMO / LUMO energy level of an organic semiconductor material.

Through the above steps, a source electrode and a drain electrode layer 26 are formed on the insulator layer 18. According to this method, the source and drain electrode layers 26 having high flatness can be produced without roughening the surface of the insulator layer 18, so that the flatness of the interface between the organic semiconductor layer 30 and the insulating film described below can be maintained. Therefore, the organic film transistor can be produced by a wet process without increasing the carrier movement resistance. Further, since a metal layer having a high flatness is obtained, a multilayer metal structure having two or more layers with less leakage can be produced. The term “insulating film interface” refers to a surface portion of the insulator layer 18 between the source electrode S and the drain electrode D.

(About formation (film formation) of organic semiconductor layer)
An organic semiconductor layer 30 is formed on the substrate P on which the gate electrode layer 16, the insulator layer 18, and the source and drain electrode layers 26 are formed. TIPS thick pentabenzene (6,13-bis (triisopropylsilylethynyl) pentacene) Soluble thick pentabenzene, or P3HT (poly (3-hexylthiophene-2,5-diyl)) Organic semiconductors such as organic semiconductor polymers are soluble in organic solvents such as toluene. Therefore, an organic semiconductor solution obtained by dissolving an organic semiconductor in an organic solvent is applied to the substrate P, and then the solvent is evaporated (evaporated) by heating, whereby the organic semiconductor layer 30 can be easily formed into a film. FIG. 6A shows the organic semiconductor layer 30 formed on the substrate P. FIG. Although the organic semiconductor layer 30 is produced by a wet method, the organic semiconductor layer 30 may be formed into a film by a sublimation method, a transfer method, or the like. Through the above steps, the organic semiconductor layer 30 is formed into a film.

(About the formation of the first protective layer)
The first protective layer 32 as the first passivation film is made of a photosensitive resin. Therefore, the first protective layer 32 can be patterned by irradiation with UV light. First, as shown in FIG. 6B, a photopolymerization initiator (first photopolymerization initiator) containing a first resin, a first resin hardened by UV light is applied, and the first resin is dissolved and the photopolymerization initiator is applied. The first protective layer solution (first solution), which is the first solvent of the solvent, forms the first protective layer 32 on the surface of the organic semiconductor layer 30. As the first resin, for example, a resin that can be dissolved in water or a fluorine-based solvent (a water-soluble resin or a fluorine-based solvent-soluble resin) can be used, and as the first solvent, for example, water or a fluorine-based solvent can be used. When the water-soluble resin is used as the first resin and water is used as the first solvent, the water contact angle of the first protective layer 32 is, for example, 62 degrees. When the first resin or the first solvent has the properties of a photopolymerization initiator, the first protective layer solution may not contain a photopolymerization initiator.

As shown in FIG. 6C, the first protective layer 32 is irradiated with UV light through a mask M4 (a mask M4 having an opening ma4 in a region where the first protective layer 32 is to be formed) formed with a specific pattern. As a result, as shown in FIG. 7A, the first protective layer 32 in a region irradiated with UV light (a region where the first protective layer 32 is to be formed) is hardened. In FIG. 7A, the directions of hatching in the hardened portion and the unhardened portion are shown as different. In this manner, the first protective layer 32 can be selectively hardened by using the mask M4. Furthermore, at this time, it is more preferable to perform a heat treatment for promoting a chemical reaction in a region irradiated with UV light. Then, as shown in FIG. 7B, the first solvent (water, fluorine-based solvent, etc.) is used to dissolve and remove the portion that is not irradiated with UV light, thereby forming a first pattern having a specific pattern corresponding to the mask M4. 1 保护 层 32。 1 protective layer 32. That is, the first protective layer 32 of a portion that is irradiated with UV light and hardened remains. The region where the first protective layer 32 is to be formed includes a region between the source electrode S and the drain electrode D.

As the first protective layer solution, BIOSURFINE (registered trademark) -AWP-MRH manufactured by Toyo Kasei Kogyo Co., Ltd. can be used to dilute it to 3 wt% with water. In addition, for example, a water-soluble resin having a vinyl alcohol-ethylene oxide copolymer and 3- [4-azidophenyl] -N- (3-methylamidino) propyl-2- [N-terminal The first protective layer solution of a photopolymerization initiator of an acetal compound of phosphonomethylphenylcarbonyl] acetamidine.

(Regarding the formation (patterning) of organic semiconductor layers)
The substrate P on which the first protective layer 32 having a specific pattern is formed is immersed in an organic solvent capable of dissolving the organic semiconductor layer 30 (in the case of using TIPS thick pentabenzene as an organic semiconductor, such as toluene), such as As shown in FIG. 7C, the first protective layer 32 is used as a mask, and a portion of the organic semiconductor layer 30 that is not covered by the first protective layer 32, that is, an exposed portion is etched. That is, the exposed organic semiconductor layer 30 is dissolved and removed. Thereby, the organic semiconductor layer 30 is formed between the source electrode S and the drain electrode D, and the target organic semiconductor layer 30 can be obtained. The gate electrode layer 16 (gate electrode G), the insulator layer 18, the source, the drain electrode layer 26 (the source electrode S and the drain electrode D), and the organic semiconductor layer 30 constitute an organic thin film transistor. Furthermore, the organic semiconductor can be reused by refining the organic semiconductor from the organic solvent in which the exposed organic semiconductor layer 30 is dissolved.

(About the formation of the second protective layer)
The second protective layer 34 as the second passivation film is made of a photosensitive resin (photocurable photosensitive resin). Therefore, the second protective layer 34 can be patterned by irradiation of UV light. First, as shown in FIG. 8A, a second protective layer solution (a second solution) in which a photosensitive resin is dissolved in a solvent is coated on the substrate P so as to cover the first protective layer 32, and the second protective layer 34 is formed into a film. . The contact angle of the second protective layer 34 with respect to the first solvent is larger than the contact angle of the first protective layer 32 with respect to the first solvent. For example, when water is used as the first solvent of the first protective layer solution, the water contact angle of the second protective layer 34 becomes larger than the water contact angle of the first protective layer 32 (for example, 62 degrees). Angle (for example, 73 degrees).

The second protective layer solution includes a second resin, a photopolymerization initiator (second photopolymerization initiator) that hardens the second resin by UV light, and a second resin that dissolves the second resin and the photopolymerization initiator. 2 solvent solution. As the second resin, for example, an organic solvent-soluble resin (organic solvent-soluble resin) can be used, and as the second solvent, for example, an organic solvent can be used. As the second protective layer solution, for example, one in which SU-8 3005 manufactured by Nippon Kayaku Co., Ltd. is diluted 2.5 times with cyclohexanone can be used. When the second resin or the second solvent has the properties of a photopolymerization initiator, the second protective layer solution may not contain a photopolymerization initiator.

The second protective layer 34 is formed so as to cover at least the first protective layer 32 and the organic semiconductor layer 30 (side surface of the organic semiconductor layer 30). Then, the second protective layer 34 is irradiated with UV light through a mask M5 (a mask M5 having an opening ma5 in an area where the second protective layer 34 is to be formed) formed with a specific pattern. As a result, as shown in FIG. 8B, the second protective layer 34 in the region irradiated with the UV light (the region where the second protective layer 34 is to be formed) is hardened. In FIG. 8B, the directions of the hatching in the hardened portion and the unhardened portion are shown as different. In this manner, the second protective layer 34 can be selectively hardened by using the mask M5. Furthermore, at this time, it is more preferable to perform a heat treatment for promoting a chemical reaction in a region irradiated with UV light.

Then, as shown in FIG. 8C, the second solvent (organic solvent, etc.) is used to dissolve and remove the portion (second protective layer 34) that is not irradiated with UV light to form a specific material corresponding to the mask M5. Patterned second protective layer 34. That is, the second protective layer 34 remaining on the part hardened by the UV light remains. The region where the second protective layer 34 is to be formed is a region necessary to cover the organic semiconductor layer 30 and the first protective layer 32. Therefore, the second protective layer 34 that is not necessary to cover the organic semiconductor layer 30 and the first protective layer 32 is removed. Thereby, even after the second protective layer 34 is formed with a specific pattern, the organic semiconductor layer 30 (side surface of the organic semiconductor layer 30) and the first protective layer 32 are covered with the second protective layer 34. Since the contact angle of the second protective layer 34 with respect to the first solvent is larger than the contact angle of the first protective layer 32 with respect to the first solvent, the second protective layer 34 is more resistant to the first protective layer than the first protective layer 32. Liquid repellency of solvents. Therefore, compared with the first protective layer 32, the second protective layer 34 has lower solubility in the first solvent and lower liquid absorption. Furthermore, a specific pattern can be formed on the second protective layer 34 in a manner that the second protective layer 34 does not cover the organic semiconductor layer 30.

By going through the above steps, a bottom gate, bottom contact type organic thin film transistor with a passivation film can be manufactured. Here, the reason for dividing the passivation film into two layers of the first protective layer 32 and the second protective layer 34 will be described. In order not to dissolve the organic semiconductor layer 30 and to form the first protective layer 32 with a solution, it is necessary to use a solution that does not dissolve the organic semiconductor (for example, a solution dissolved in water or a fluorine-based solvent) to the organic semiconductor layer 30. A first protective layer 32 is formed thereon. That is, if the second protective layer 34 is directly formed on the organic semiconductor layer 30 with an organic solvent-based solution without passing through the first protective layer 32, the organic semiconductor layer 30 will be dissolved by the organic solvent-based solution. Further, the reason for forming the second protective layer 34 having a low liquid-absorptivity in the first solvent on the first protective layer 32 so as to cover the first protective layer 32 and the organic semiconductor layer 30 is to prevent the organic semiconductor layer. The side of 30 is exposed and functions as a passivation film. Since the first protective layer 32 is made of a first resin (a water-soluble resin or a fluorine-based solvent-soluble resin), it has a property of easily absorbing water or a fluorine-based solvent. Therefore, if the first protective layer 32 contains water or a fluorine-based solvent, the function as a passivation film is not complete, and water or a fluorine-based solvent will affect the channel portion. Therefore, the second protective layer 34 is formed into a film and completely Ground seal water or fluorine-based solvents.

(Example 1)
In Example 1, the light patterning of the high-resolution organic semiconductor layer 30 was studied by the process of the first embodiment. In this Example 1, a PET film (COSMOSHINE A-4100 uncoated) manufactured by Toyobo Co., Ltd. was used as the substrate P, and TIPS thick pentabenzene was used as the organic semiconductor for the organic semiconductor layer 30. As the first protective layer solution for the first protective layer 32, BIOSURFINE (registered trademark) -AWP-MRH manufactured by Toyo Kogyo Co., Ltd. was used. BIOSURFINE (registered trademark) -AWP-MRH is a photopolymerization initiator containing a water-soluble resin (first resin) and a water-soluble resin hardened by UV light. The water contact angle of the water-soluble photosensitive resin (BIOSURFINE (registered trademark) -AWP-MRH) constituting the first protective layer 32 was 62 degrees.

In the film formation of the organic semiconductor layer 30 on the substrate P, a dip coating method is used. The substrate P was immersed in an organic semiconductor solution (a solution in which the organic semiconductor was diluted to 2 wt%) in which a TIPS thick pentaphenyl organic semiconductor was dissolved in a toluene solution (organic solvent), and repeatedly pulled at a pulling speed of 30 mm / s 1 mm and hold for 10 seconds. Thereafter, in order to volatilize the toluene solution used in the organic solvent, a heat treatment was performed at 105 ° C. for 10 minutes, thereby forming the organic semiconductor layer 30 on the substrate P. Then, the first protective layer solution in which BIOSURFINE (registered trademark) -AWP-MRH (first solvent) was diluted to 3 wt% with water was applied by a spin coating method. The conditions for spin coating are set to a rotation speed of 1000 rpm and a rotation time of 60 seconds. Then, a heat treatment was performed at 70 ° C. for 10 minutes to evaporate water as a solvent to form a first protective layer 32. Then, the area where the first protective layer 32 and the organic semiconductor layer 30 are to be formed is selectively irradiated with UV light through the mask M4, and unexposed parts are washed and washed with water, and the first protective layer 32 is formed corresponding to the mask M4. Specific pattern. Then, the first protective layer 32 was dried at 105 ° C for 30 minutes. An optical microscope image of the patterned first protective layer 32 is shown in FIG. 9A. The pattern size is set to 100 μm.

Thereafter, the substrate P on which the first protective layer 32 has been prepared is immersed in toluene (organic solvent), and the organic semiconductor layer 30 of the portion not covered by the first protective layer 32 is etched using the first protective layer 32 as a mask. A pattern is formed on the organic semiconductor layer 30. An optical microscope image of the patterned organic semiconductor layer 30 is shown in FIG. 9B. It was confirmed that the organic semiconductor layer 30 was patterned in the same shape as the first protective layer 32. It can be proved that the degree of side etching is also low, and it can be easily patterned as long as the size is about 100 μm. When patterned in this size (100 μm), it can be sufficiently applied to electronic devices such as displays.

(Example 2)
In Example 2, the formation of an organic transistor was studied. The substrate P, the organic semiconductor solution used in the organic semiconductor layer 30, and the first protective layer solution used in the first protective layer 32 are the same as those used in the first embodiment.

(About the formation of the gate electrode layer)
As the amine material constituting the amine layer 10, KBE-903 (manufactured by Shin-Etsu Chemical Industry Co., Ltd.) and N-PHENYLAMINOPROPYLTRIMETHOXYSILANE (manufactured by Azmax Co., Ltd.) were used as amine-based silane coupling agents. An amine solution containing methyl isobutyl ketone (MIBK) was prepared so that KBE-903 became 0.5 wt% and N-PHENYLAMINOPROPYLTRIMETHOXYSILANE became 0.15 wt%. After the substrate P was washed with an atmospheric O ₂ plasma, an amine solution was applied to the substrate P by a dip coating method. The pulling speed of the dip coating was set to 1 mm / s. In order to volatilize methyl isobutyl ketone (MIBK) as a solvent, a heat treatment was performed at 105 ° C. for 15 minutes to form a film of the amine layer 10.

Next, a photoresist (SUMIRESIST PFI-34A6) manufactured by Sumitomo Chemical Co., Ltd. was applied to the entire surface of the substrate P formed with the amine layer 10 by a dip coating method, and pre-baked at 105 ° C for 5 minutes. Bake, thereby forming the photoresist layer 12. The dipping coating was pulled at a speed of 1 mm / s to form a photoresist layer 12 having a thickness of about 1 μm. Thereafter, by exposing UV light of 43 mW / cm ² intensity through the mask M1 for 3 seconds, heating (post-baking) at 105 ° C for 5 minutes, and immersing in an aqueous solution (developing solution) of 2.38 wt% TMAH ) For 150 seconds, a specific pattern having an opening portion 12 a is formed on the photoresist layer 12. The pattern formed on the photoresist layer 12 is a pattern corresponding to the mask M1.

Then, the substrate P was subjected to ultrasonic water washing at room temperature for 30 seconds, and then the substrate P was immersed in a catalyst colloid solution (Melplate, Activator 7331) for electroless plating manufactured by Meltex Co., Ltd. 60 at room temperature. The catalyst (Pd) 14 is adhered to the amine layer 10 exposed from the opening 12 a of the photoresist layer 12 in seconds. After the surface was cleaned, the substrate P was immersed in an electroless plating solution (Melplate N1-6575) manufactured by Meltex Co., Ltd. at 83 ° C for 25 seconds, and exposed from the opening 12 a of the photoresist layer 12. Nickel-phosphorus is deposited on the catalyst 14 and nickel-phosphorus plating is performed to form the gate electrode layer 16. Then, after the surface was washed with water and dried, the entire surface including the remaining photoresist layer 12 was exposed to UV light having an intensity of 43 mW / cm ² for 1 minute, and further, the photoresist layer 12 was removed by being immersed in ethanol for 1 minute. . A photo of the gate electrode G produced on the substrate P is shown in FIG. 10A, and an optical microscope image of the gate electrode G is shown in FIG. 10B.

(About formation of insulator layer)
The fabricated gate electrode G is washed with an alkali solution and 2-propanol, and then UV-washed to remove organic residues on the surface. Then, the insulator layer solution was applied by a dip coating method. The insulator layer solution was obtained by diluting SU-8 3005 manufactured by Nippon Kayaku Co., Ltd. 2.5 times with cyclohexanone, and the pulling speed of dip coating was set to 1 mm / s. Thereafter, pre-baking was performed at 105 ° C. for 10 minutes to form a film of the insulator layer 18. Further, UV light having an intensity of 43 mW / cm ^{2 was} exposed through a mask M2 for 5 seconds, and heated at 105 ° C. for 60 minutes. Next, the substrate P was immersed in PGMEA (propylene glycol-1-monomethyl ether-2-acetate) to dissolve the unexposed portion of the UV light of the insulating film, thereby forming a specific pattern corresponding to the mask M2. The pattern of the insulator layer 18. Thereafter, an insulator layer 18 having a thickness of 1 μm was formed by post-baking for 30 minutes at 105 ° C. A photograph of the insulator layer 18 patterned and formed on the gate electrode G is shown in FIG. 11A, and an optical microscope image of the insulator layer 18 near the gate electrode G is shown in FIG. 11B.

(About the formation of source and drain electrode layers)
The source and drain electrode layers 26 are formed in such a manner that they have the desired shape by using the same steps as those of the fabrication of the gate electrode layer 16. To put it simply, that is, by forming the photoresist layer 22 into a film after forming the amine layer 20 and exposing UV light through the mask M3, a specific pattern corresponding to the mask M3 is formed on the photoresist layer 22. Thereafter, the substrate P is immersed in a catalyst colloid solution for electroless plating, and a catalyst (Pd) 24 is attached to the amine layer 20 exposed from the opening 22 a of the photoresist layer 22. Thereafter, the substrate P is immersed in an electroless plating solution, and nickel phosphorus is precipitated on the catalyst 14 exposed from the opening 22 a of the photoresist layer 22 to form a source-drain electrode layer 26. The formation of the amine layer 20, the photoresist layer 22, the catalyst colloid solution, and the electroless plating material or other conditions is the same as the formation of the gate electrode G. That is, the difference between the formation of the gate electrode layer 16 and the source and drain electrode layers 26 is only the mask M used, and the other steps are the same. In addition, after the source and drain electrode layers 26 are fabricated, gold 28 is coated on the surfaces of the metals (nickel phosphorus) forming the source electrode S and the drain electrode D, so the substrate P is immersed in a plating-replacement gold bath for 1 minute. Then, immerse for 3 minutes in a bath of reduced gold. Then, it washed with water, dried at 105 degreeC for 30 minutes, and covered the source and drain electrode layer 26 with gold 28. As shown in FIG.

FIG. 12A shows a photo of the source electrode S and the drain electrode D formed on the insulator layer 18, and FIG. 12B shows an optical microscope image near the gate electrode G. The wiring 40 in FIG. 12B is a part of the source electrode S, and the wiring 42 is a part of the drain electrode D. On the area where the gate electrode G is formed, the two wirings 40 and 42 are arranged with a gap therebetween, and the gap (5 μm) forms the channel portion 44. The wirings 40 and 42 have a line width of about 10 μm. The channel length (length in the up-down direction in FIG. 12B) of the channel portion 44 is 500 μm. The channel portion 44 is a region between the source electrode S and the drain electrode D, and a region where the organic semiconductor layer 30 is formed.

(About film formation of organic semiconductor layer)
In the same manner as in Example 1, the substrate P on which the source and drain electrode layers 26 were prepared was immersed in an organic semiconductor liquid, and the organic semiconductor layer 30 was formed by a dip coating method. An optical microscope image of a substrate P on which an organic semiconductor (TIPS thick pentaphenyl) is formed by dip coating is shown in FIG. 13. The materials and film forming conditions for forming the organic semiconductor layer 30 are the same as those in the first embodiment.

(About the formation of the first protective layer)
After forming the organic semiconductor layer 30 in the same manner as in Example 1, the first protective layer 32 was formed into a film by spin coating, and the first protective layer 32 was patterned by light to form a specific pattern. An optical microscope image of the substrate P on which the first protective layer 32 is patterned is shown in FIG. 14. In addition, the materials and film forming conditions used for the film formation of the first protective layer 32 are the same as in Example 1 (wherein, the pattern is larger in size than in Example 1).

(About the patterning of organic semiconductor layers)
As in Example 1, the patterned substrate P of the first protective layer 32 was immersed in toluene (organic solvent), and the first protective layer 32 was used as a mask to etch portions that were not covered by the first protective layer 32. The organic semiconductor layer 30 forms a pattern on the organic semiconductor layer 30. An optical microscope image of the substrate P after the organic semiconductor layer 30 is patterned is shown in FIG. 15.

(About the formation of the second protective layer)
After the organic semiconductor layer 30 is patterned, a second protective layer solution is applied by a dip coating method, and pre-baking is performed at 105 ° C. for 10 minutes to form a second protective layer 34. As the second protective layer solution, a product obtained by diluting SU-8 3005 of Nippon Kayaku Co., Ltd. by 2.5 times with cyclohexanone was used, and the pulling speed of the dip coating was set to 1 mm / s. SU-8 3005 is a photopolymerization initiator containing an organic solvent-soluble resin (second resin) that can be dissolved by an organic solvent and a hardening of the organic solvent-soluble resin by UV light. Cyclohexanone is an organic solvent ( 2nd solvent). The organic solvent-soluble photosensitive resin (SU-8 3005) constituting the second protective layer 34 had a water contact angle of 73 degrees.

Then, it was exposed to UV light with an intensity of 43 mW / cm ² for 5 seconds through a mask M5, and then heated at 105 ° C for 60 minutes. With this mask M5, UV light is exposed in a region that completely covers the first protective layer 32 and the organic semiconductor layer 30, so that a portion of the exposed second protective layer 34 is hardened. Next, the substrate P is immersed in PGMEA (propylene glycol-1-monomethyl ether-2-acetate), and the portion of the second protective layer 34 that is not irradiated with UV light is dissolved to form a specific one corresponding to the mask M5. Patterned second protective layer 34. Then, post-baking was performed at 105 ° C for 30 minutes. An optical microscope image of the substrate P on which the second protective layer 34 is patterned is shown in FIG. 16.

FIG 17 represents a system, the characteristics of the graph showing the results of an organic thin film transistor gate passivation film attached by the above step of manufacture of the electrode voltage V _G and drain current I _D of the evaluation. It was confirmed that the produced organic thin film transistor with a passivation film operated as an n-type transistor. A passivation film carrier film attached to the mobility of the transistor becomes ^{7 × 10 - 3 cm 2 /} Vs, On / Off ratio becomes was 1.5 × 10 ^7, it showed good properties. Furthermore, the voltage between the drain and source is -30V.

Through the above steps, the organic thin film transistor with a passivation film was successfully manufactured only by a wet process. In this process, the temperature given to the substrate P is a relatively low temperature region of about 100 ° C. For example, this process is performed while the substrate P is maintained at a temperature of 100 ° C or lower or 120 ° C or lower. Therefore, even when a PET substrate is used, thermal contraction of the substrate P can be avoided. In addition, as long as it is in this temperature range, degradation of the organic semiconductor constituting the organic semiconductor layer 30 is not caused, and therefore it can be expected to be applied to a roll-to-roll manufacturing system. In addition, since the organic semiconductor layer 30, the first protective layer 32, and the second protective layer 34 are formed only by a wet process, at least one of the organic semiconductor layer 30, the first protective layer 32, and the second protective layer 34 can be improved. The surface uniformity (flatness) can be patterned with high resolution of the organic semiconductor layer 30. That is, at least one of the organic semiconductor layer 30, the first protective layer 32, and the second protective layer 34 of the semiconductor element manufactured by this process has a flat surface.

[Second Embodiment]
In the above-mentioned first embodiment, as the organic thin film transistor, although the bottom gate and the bottom contact type are described as examples, the top gate and bottom contact types may also be used, and the bottom gate and top contact may also be used. type. In the second embodiment, as a semiconductor device, a method for manufacturing a top-gate, bottom-contact-type organic thin-film transistor with a passivation film is briefly described. The semiconductor element of the second embodiment has a structure in which a source, a drain electrode layer, an organic semiconductor layer, a first protective layer, a second protective layer, and a gate electrode layer are laminated on the substrate P in the above-mentioned order. The formation of each layer of the semiconductor element will be described below.

(About the formation of source and drain electrode layers)
The source and drain electrode layers can be manufactured through the same process as the manufacturing process of the source and drain electrode layers 26 described in the first embodiment. First, as shown in FIG. 18A, since a soft substrate P such as PET is a hard-to-plated member, an amine layer 50 is formed on the substrate P. Furthermore, as shown in FIG. 18B, a positive photoresist layer 52 is formed on the amine layer 50, and a mask M6 having a specific pattern is formed (there is an opening in the region where the source electrode S and the drain electrode D are formed) The mask M6 of the part ma6) is irradiated with UV light (light), and the photoresist layer 52 is exposed.

Thereafter, by immersing the photoresist layer 52 (substrate P) in a developing solution, as shown in FIG. 18C, after dissolving and removing the photoresist layer 52 in a portion irradiated with UV light (the exposed portion), it will contain A catalyst solution for the electroless plating catalyst (Pd) 54 is applied to the substrate P. By immersing the substrate P in a developing solution, a pattern corresponding to the source electrode S and the drain electrode D is formed on the photoresist layer 52. That is, a pattern having an opening portion 52a is formed in a region where the source electrode S and the drain electrode D are formed. In addition, since a photoresist layer 52 having a specific pattern is laminated on the amine layer 50, the catalyst 54 is provided on the amine layer 50 exposed through the opening portion 52a.

Then, by immersing the substrate P in an electroless plating solution such as nickel phosphorus, as shown in FIG. 19A, metal ions are reduced and precipitated on the surface of the catalyst 54. The deposited metal layer becomes the source and drain electrode layers 56. Therefore, a source and a drain electrode layer (metal layer) 56 having a source electrode S and a drain electrode D are selectively formed on the substrate P. Thereafter, the entire surface of the remaining photoresist layer 52 is exposed to UV light, and the photoresist layer 52 (substrate P) is immersed in a developing solution. As shown in FIG. 19B, the photoresist layer 52 is removed. Then, the substrate P is immersed in a plating-replacement gold bath and then immersed in a reduction-plating gold bath. As shown in FIG. 19C, the surfaces of the source and drain electrode layers 56 are covered with gold 58. Thereby, the source electrode S and the drain electrode D are covered with gold 58. Through the above steps, the source and drain electrode layers 56 are formed on the substrate P.

(About formation (film formation) of organic semiconductor layer)
The organic semiconductor layer 60 can be manufactured through the same process as the manufacturing steps of the organic semiconductor layer 30 described in the first embodiment. That is, an organic semiconductor liquid in which an organic semiconductor is dissolved in an organic solvent is applied to the substrate P, and then the solvent is evaporated (evaporated) by heating to form a film of the organic semiconductor layer 60. FIG. 20A shows the organic semiconductor layer 60 formed on the substrate P.

(About the formation of the first protective layer)
The first protective layer 62 as the first passivation film can be produced through the same process as the first protective layer 62 described in the first embodiment. First, as shown in FIG. 20B, a photopolymerization initiator (first photopolymerization initiator) containing a first resin, a first resin hardened by UV light is applied, and the first resin is dissolved and the photopolymerization initiator is applied The first protective layer solution, which is the first solvent of the solvent, forms a first protective layer 62 on the surface of the organic semiconductor layer 60. When the water-soluble resin is used as the first resin and water is used as the first solvent, the water contact angle of the first protective layer 62 is, for example, 62 degrees. When the first resin or the first solvent has the properties of a photopolymerization initiator, the first protective layer solution may not contain a photopolymerization initiator.

Then, as shown in FIG. 20C, the first protective layer 62 is irradiated with UV light through a mask M7 (a mask M7 having an opening ma7 in a region where the first protective layer 62 is to be formed) formed with a specific pattern. As a result, as shown in FIG. 21A, the first protective layer 62 in a region irradiated with UV light (a region where the first protective layer 62 is to be formed) is hardened. In FIG. 21A, the directions of the hatched lines in the hardened portion and the unhardened portion are shown as different. In this way, the first protective layer 62 can be selectively hardened by using the mask M7. Furthermore, at this time, it is more preferable to perform a heat treatment for promoting a chemical reaction in a region irradiated with UV light. Next, as shown in FIG. 21B, the first solvent (water, fluorine-based solvent, etc.) is used to dissolve and remove the portion that is not irradiated with UV light, thereby forming a first pattern having a specific pattern corresponding to the mask M7. Protective layer 62. That is, the first protective layer 62 remaining on the hardened portion irradiated with UV light remains. The region where the first protective layer 62 is to be formed includes a region between the source electrode S and the drain electrode D.

(Regarding the formation (patterning) of organic semiconductor layers)
The patterning of the organic semiconductor layer 60 can be performed through the same process as the patterning of the organic semiconductor layer 30 described in the first embodiment. That is, the substrate P on which the first protective layer 62 having a specific pattern is formed is immersed in an organic solvent capable of dissolving the organic semiconductor layer 60. As shown in FIG. 21C, the first protective layer 62 is dissolved as a mask and dissolved. The portion of the organic semiconductor layer 60 that is not covered by the first protective layer 62, that is, the exposed portion is removed. Thereby, the organic semiconductor layer 60 is formed between the source electrode S and the drain electrode D, and the target organic semiconductor layer 60 can be obtained. Furthermore, the organic semiconductor is recovered by purifying the organic solvent from the organic solvent in which the exposed part of the organic semiconductor layer 60 is dissolved, whereby the organic semiconductor can be reused.

(About the formation of the second protective layer)
The second protective layer 64 as the second passivation film can be produced through the same process as the production steps of the second protective layer 64 described in the first embodiment. First, as shown in FIG. 22A, a second protective layer solution in which a photosensitive resin is dissolved in a solvent is coated on the substrate P so as to cover the organic semiconductor layer 60 and the first protective layer 62, and the second protective layer 64 is formed into a film. . The second protective layer solution includes a second resin, a photopolymerization initiator (second photopolymerization initiator) that hardens the second resin by UV light, and a second resin that dissolves the second resin and the photopolymerization initiator. Solvent. The contact angle of the second protective layer 64 with respect to the first solvent is larger than the contact angle of the first protective layer 62 with respect to the first solvent. When water is used as the first solvent of the first protective layer solution, the water contact angle of the second protective layer 64 becomes a larger angle (for example, 73 degrees) than the water contact angle of the first protective layer (for example, 62 degrees). ). When the second resin or the second solvent has the properties of a photopolymerization initiator, the second protective layer solution may not contain a photopolymerization initiator.

Then, the second protective layer 64 is irradiated with UV light through a mask M8 (a mask M8 having an opening ma8 in a region where the second protective layer 64 is to be formed) formed with a specific pattern. As a result, as shown in FIG. 22B, the second protective layer 64 in the region irradiated with UV light (the region where the second protective layer 64 is to be formed) is hardened. In FIG. 22B, the directions of the hatched lines in the hardened portion and the unhardened portion are shown as different. In this way, the second protective layer 64 can be selectively hardened by using the mask M8. Furthermore, at this time, it is more preferable to perform a heat treatment for promoting a chemical reaction in a region irradiated with UV light.

Next, as shown in FIG. 22C, the second solvent (organic solvent, etc.) is used to dissolve and remove the portion (second protective layer 64) that is not irradiated with UV light, and to form a specific pattern corresponding to the mask M8. Of the pattern of the second protective layer 64. That is, the second protective layer 64 of the portion irradiated with UV light and hardened remains. The region where the second protective layer 64 is to be formed is a region necessary to cover the organic semiconductor layer 60 and the first protective layer 62. Therefore, the second protective layer 64 which is not necessary to cover the organic semiconductor layer 60 and the first protective layer 62 is removed. Since the second protective layer solution has a larger contact angle with respect to the first solvent than the first protective layer solution, the second protective layer 64 is more liquid-repellent to the first solvent than the first protective layer 62. . Therefore, compared with the first protective layer 62, the second protective layer 64 has lower solubility in the first solvent and lower liquid absorption. In the second embodiment, the second protective layer 64 also functions as an insulator layer.

(About the formation of the gate electrode layer)
The gate electrode layer can be manufactured through the same process as the manufacturing steps of the gate electrode layer 16 described in the first embodiment. First, as shown in FIG. 23A, an amine layer 66 is formed on the second protective layer 64. Further, as shown in FIG. 23B, a positive-type photoresist layer 68 is formed on the amine layer 66, and a mask M9 having a specific pattern is formed (a mask having an opening ma9 in a region where the gate electrode G is formed). M9) The photoresist layer 68 is exposed by irradiating UV light. Thereafter, as shown in FIG. 23C, the photoresist layer 68 (substrate P) is immersed in a developing solution (for example, TMAH, etc.) to dissolve and remove the photoresist layer in the portion exposed to the UV light (the exposed portion). 68. Thereby, a specific pattern corresponding to the gate electrode G is formed on the photoresist layer 68. That is, a pattern having an opening 68 a is formed in a region where the gate electrode G is formed.

Then, as shown in FIG. 24A, by applying a catalyst solution containing a catalyst (Pd) 70 for electroless plating to the amine layer 66 exposed through the opening 68a of the photoresist layer 68, The substrate P is immersed in a developing solution, and metal ions are reduced and precipitated on the surface of the catalyst 70. The deposited metal layer becomes the gate electrode layer 72. Therefore, a gate electrode layer 72 having a gate electrode G is selectively formed on the substrate P. Thereafter, the entire surface of the remaining photoresist layer 68 is exposed to UV light, and the photoresist layer 68 (substrate P) is immersed in a developing solution to remove the photoresist layer 68 as shown in FIG. 24B. Through the above steps, the gate electrode layer 72 is formed on the second protective layer 64.

By going through the above steps, it is possible to manufacture a top-gate, bottom-contact type organic thin-film transistor with a passivation film using only a wet process. In addition, since the organic semiconductor layer 60, the first protective layer 62, and the second protective layer 64 are formed only by a wet process, at least one of the organic semiconductor layer 60, the first protective layer 62, and the second protective layer 64 can be improved. The surface uniformity (flatness) of one of them is patterned with a high resolution of the organic semiconductor layer 60. Moreover, although the manufacturing method of the bottom gate and top contact type organic transistor with a passivation film is not explained in detail, it can be manufactured through the same process.

Furthermore, even in the case of manufacturing electronic devices such as electronic paper or organic EL displays having the semiconductor elements (organic thin film transistors with passivation films) described in the above embodiments, the manufacturing method of the electronic devices may include the above The manufacturing method of the semiconductor element described in each embodiment. That is, the manufacturing method of an electronic device can manufacture the semiconductor element of an electronic device using the manufacturing method demonstrated in each said embodiment.

In each of the above embodiments, the mask M (M1 to M9) is used to irradiate light to the photoresist layer or the protective layer to form a specific pattern. However, the mask M may not be used, and a specific pattern may be formed by scanning exposure. . For example, by using a seed light source or an electro-optic modulator to switch the light irradiated to the photoresist layer or the protective layer, a specific pattern can be formed on the photoresist layer or the protective layer. In addition, a digital micromirror device (DMD: Digital Micromirror Device) may be used to irradiate light to the photoresist layer (12, 22, 52, 68) or the protective layer (32, 34, 62, 64) to form a specific pattern.

10, 20, 50, 66‧‧‧amine layer

12, 22, 52, 68‧‧‧ photoresist layer

14, 24, 54, 70‧‧‧ catalyst

16, 72‧‧‧Gate electrode layer

18‧‧‧ insulator layer

26, 56‧‧‧ source and drain electrode layers

28, 58‧‧‧Gold

30, 60‧‧‧Organic semiconductor layer

32, 62‧‧‧ 1st protective layer

34, 64‧‧‧ 2nd protective layer

D‧‧‧ Drain electrode

G‧‧‧Gate electrode

M, M1 ～ M9‧‧‧Mask

P‧‧‧ substrate

S‧‧‧Source electrode

FIGS. 1A to 1C are diagrams showing steps of forming a gate electrode layer of a semiconductor element having a bottom gate and a bottom-contact type organic thin film transistor.

FIG. 2A to FIG. 2C are diagrams showing steps for forming a gate electrode layer of a semiconductor element having a bottom gate and a bottom-contact type organic thin film transistor.

FIG. 3A to FIG. 3C are diagrams showing steps of forming an insulator layer of a semiconductor element having a bottom gate and bottom contact type organic thin film transistor after forming a gate electrode layer.

FIGS. 4A to 4C are diagrams showing steps for forming a source electrode and a drain electrode layer of a semiconductor element having a bottom gate and a bottom-contact type organic thin film transistor after forming an insulator layer.

5A to 5C are diagrams showing steps of forming a source electrode and a drain electrode layer of a semiconductor element having a bottom gate and a bottom-contact type organic thin film transistor after forming an insulator layer.

6A to 6C are diagrams showing steps of forming an organic semiconductor layer and a first protective layer of a semiconductor element having a bottom-gate and bottom-contact type organic thin-film transistor after forming a source electrode and a drain electrode layer; .

7A to 7C are diagrams showing steps of forming an organic semiconductor layer and a first protective layer of a semiconductor element having a bottom-gate and bottom-contact type organic thin-film transistor after forming a source electrode and a drain electrode layer; .

FIGS. 8A to 8C are diagrams showing steps for forming a second protective layer of a semiconductor element having a bottom gate and a bottom-contact type organic thin film transistor after the organic semiconductor layer and the first protective layer are formed.

9A and 9B are respectively a diagram of an optical microscope image of a patterned first protective layer and a diagram of an optical microscope image of a patterned organic semiconductor layer in Example 1.

10A and 10B are respectively a diagram of a photograph of a gate electrode fabricated on a substrate and a diagram of an optical microscope image of the gate electrode in Example 2.

11A and 11B are respectively a photograph of an insulator layer patterned into a film on a gate electrode in Example 2, and a diagram of an optical microscope image of the insulator layer near the gate electrode.

12A and 12B are respectively a photograph of a source electrode and a drain electrode formed on an insulator layer, and a diagram of an optical microscope image near a gate electrode in Example 2.

13 is a diagram showing an optical microscope image of a substrate on which a TIPS thick pentabenzene organic semiconductor film was formed by dip coating in Example 2. FIG.

14 is a view showing an optical microscope image of a substrate on which a pattern is formed on a first protective layer in Example 2. FIG.

15 is a diagram showing an optical microscope image of a substrate after patterning an organic semiconductor layer in Example 2. FIG.

16 is a view showing an optical microscope image of a substrate on which a pattern is formed on the second protective layer in Example 2. FIG.

FIG. 17 is a graph showing evaluation results of characteristics of the organic thin film transistor with a passivation film produced in Example 2. FIG.

18A to 18C are diagrams showing the steps of forming the source and drain electrode layers of a semiconductor element having a top-gate and bottom-contact type organic thin-film transistor.

19A to 19C are diagrams showing steps of forming a source electrode and a drain electrode layer of a semiconductor element having a top-gate and bottom-contact type organic thin film transistor.

20A to 20C are diagrams showing steps of forming an organic semiconductor layer and a first protective layer of a semiconductor element having a top gate electrode and a bottom-contact type organic thin film transistor after forming a source electrode and a drain electrode layer; .

21A to 21C are diagrams showing the steps of forming an organic semiconductor layer and a first protective layer of a semiconductor element having a top-gate and bottom-contact type organic thin-film transistor after forming a source electrode and a drain electrode layer; .

22A to 22C are diagrams showing steps of forming a second protective layer of a semiconductor element having an organic thin film transistor of a top gate and a bottom contact type after the organic semiconductor layer and the first protective layer are formed.

23A to 23C are diagrams showing the steps of forming a gate electrode layer of a semiconductor element having a top-gate and bottom-contact type organic thin-film transistor after forming the second protective layer.

FIG. 24A and FIG. 24B are diagrams showing steps for forming a gate electrode layer of a semiconductor element having a top-gate and bottom-contact type organic thin-film transistor after forming a second protective layer.

Claims (16)

A method for manufacturing a semiconductor device includes: A first film forming step of forming an organic semiconductor layer on a substrate on which an electrode is formed; A second film forming step of forming a first protective layer on the surface of the organic semiconductor layer; A first pattern forming step of exposing the first protective layer to light by irradiating the first protective layer with light, and forming a specific pattern on the first protective layer; A second pattern forming step of forming the specific pattern on the organic semiconductor layer by using the first protective layer on which the specific pattern is formed as a mask and etching the organic semiconductor layer; and The third film forming step is to form a second protective layer after the second pattern forming step, and the second protective layer covers the first protective layer on which the specific pattern is formed. The method for manufacturing a semiconductor device according to claim 1, wherein: In the first pattern forming step, the first protective layer is irradiated with the light to harden the first protective layer. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The first pattern forming step is to dissolve a portion that is not irradiated with the light by using a first solvent, and form the specific pattern on the first protective layer. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein The second film forming step is to form a film of the first protective layer using a first solution, and the first solution includes a first resin and a first solvent that dissolves the first resin. The method for manufacturing a semiconductor device according to claim 4, wherein: The first solution further includes a first photopolymerization initiator that hardens the first resin by light, and The first solvent dissolves the first photopolymerization initiator. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein: The second pattern forming step is to dissolve the portion of the first pattern forming step that is not irradiated with the light, and then use an organic solvent capable of dissolving the organic semiconductor layer to dissolve the portion not covered by the first protective layer. The organic semiconductor layer is dissolved, and the organic semiconductor is recovered. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein: The third film forming step is to form the second protective layer, and the second protective layer has a lower solubility in the first solvent than the first protective layer. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein: The third film forming step is to form a second protective layer using a second solution, and the second solution includes a second resin and a second solvent that dissolves the second resin. The method for manufacturing a semiconductor device according to claim 8, wherein: The second solution further includes a second photopolymerization initiator that hardens the second resin by light, and The second solvent dissolves the second photopolymerization initiator. The method for manufacturing a semiconductor device according to any one of claims 1 to 9, It further includes a third pattern forming step of irradiating the second protective layer with light to expose the second protective layer to form a pattern on the second protective layer. The method for manufacturing a semiconductor device according to claim 10, wherein In the third pattern forming step, a portion of the second protective layer that is not irradiated with the light is dissolved and removed. A method for manufacturing an electronic device, It includes the manufacturing method of the semiconductor element as described in any one of Claims 1-11. A semiconductor element having: An organic semiconductor layer formed on a substrate on which an electrode is formed, A first protective layer formed on the surface of the organic semiconductor layer, and A second protective layer formed to cover the first protective layer, and The first protective layer is made of a first resin cured by light. The semiconductor device according to claim 13, wherein: The second protective layer is made of a second resin cured by light. A semiconductor element having: An organic semiconductor layer formed on a substrate on which an electrode is formed, A first protective layer formed on the surface of the organic semiconductor layer, and A second protective layer formed to cover the first protective layer, and The second protective layer has a lower solubility in the first solvent than the first protective layer. An electronic device, It has the semiconductor element as described in any one of Claims 13-15.