TW201937853A - Duty cycle converter - Google Patents

Abstract

A duty cycle conversion circuit portion (1) comprises N inverters (2, 4, 6, 8), wherein N is an integer greater than two. The duty cycle conversion circuit is arranged to receive N input signals (10a-d) each having a duty cycle between 1/N and 2/N. Each of the N input signals is applied to a respective input terminal (2a, 4a, 6a, 8a) of one of the N inverters such that each inverter receives a different input signal. Each of the N input signals is applied to a respective power terminal (2c, 4c, 6c, 8c) of one of the N inverters such that each inverter is powered by a different input signal. Each inverter receives different input signal at its respective input terminal to the input signal applied to its respective power terminal.

Description

Work cycle converter

The present invention relates to duty cycle converters, and more particularly to generating output signals having a duty cycle that depends on the rising or falling edges of the input signal.

Many modern electronic systems utilize control signals that exceed one phase and are referred to as "multi-phase" systems. An example of a multi-phase system may be a radio system that uses quadrature modulation and/or demodulation. Such radio systems typically require in-phase (I) and quadrature (Q) signals for I and Q mixing to perform proper modulation and/or demodulation. If input to the differential mixer, these I and Q signals are usually "differential", that is, these signals are "two-wire" signals, and the relative phases of the two "I lines" are 0° and 180°. The opposite phases of the two Q lines are 90° and 270°. Therefore, the radio system is a four-phase system. It will of course be understood that this is only one possible application and that there are many examples of such multiphase systems.

Such multiphase systems typically employ a number of (usually the same) periodic rectangular pulses that are phase shifted from each other. Each pulse has an associated "duty cycle", that is, the pulse is at a "logic high" in a given period compared to the digit "0" or "logic low" (ie, The proportion of time in the digit "1"). These multi-phase signals can be configured such that if there are N signals, each has a 1/N duty cycle and its individual logic high periods do not overlap. Therefore, in the above four-phase radio system example, the signals each have a 25% duty cycle.

When designing this multi-phase system, it produces such a large number of accurate duty cycles. Phase signals are a common challenge that engineers often face. One solution known in the art involves utilizing a series of Boolean NAND gates to produce an output signal that is set at one edge of the input signal (eg, a rising edge) and at another edge (eg, a falling edge) ) will reset (reset). However, this has severe duty cycle requirements for the input signal, but creates a new problem for the designer. It also has a relatively high power requirement when used in a radio frequency (RF) section because it requires several gates that operate at high RF frequencies.

When viewed from the first aspect, the present invention provides a duty cycle conversion circuit portion including N inverters, wherein N is an integer greater than two, and the duty cycle conversion circuit is configured to receive each having a ratio of 1/N and N input signals for a duty cycle between 2/N, wherein: each of the N input signals is applied to an individual input of one of the N inverters, such that each inverter receives a different one Inputting a signal; and applying each of the N input signals to an individual power supply of one of the N inverters such that each inverter is powered by a different input signal; wherein each inverter is The input signals received by their respective inputs are different from the input signals applied to their respective power terminals.

It will be appreciated by those skilled in the art that the present invention provides a duty cycle conversion circuit portion that requires only one edge (rising or falling) on the input to produce an output signal having a controlled duty cycle of 1/N. Since the input signals each have a duty cycle greater than 1/N, they can be used to power one of the inverters for receiving the next input signal for transition. In this configuration, even if only the rising (or falling) edge of the input signal used to trigger the transition in the output is clear, the output of each inverter can still produce an output signal with an accurate duty cycle of 1/N. Of course, depending on the desired application, a duty cycle of 1-1/N can be achieved, for example by reconfiguring the input to the inverter compared to what is required in the case of 1/N or by retaining for 1/1 N case input configuration but reverse Individual output. The former is preferred because it eliminates the extra current consumption associated with any additional inverters.

Therefore, from the second aspect, the present invention provides a duty cycle conversion circuit portion including N inverters, wherein N is an integer greater than two, and the duty cycle conversion circuit is configured to receive each having between 1-2 N input signals of a duty cycle between /N and 1-1/N, wherein: each of the N input signals is applied to an individual input of one of the N inverters, such that each The receiver receives a different input signal; and applies each of the N input signals to an individual power supply of one of the N inverters such that each inverter is powered by a different input signal; Each inverter receives an input signal at its respective input that is different from the input signal applied to its respective power supply.

Compared to conventional solutions, the duty cycle conversion circuit according to an embodiment of the present invention requires fewer nodes, reduces circuit complexity, reduces bill of materials and circuit cost, and reduces current consumption of the circuit, especially when operating in RF. Usually means that a higher current consumption will be required.

While a single output can be obtained from one of the inverters within the duty cycle conversion circuit, in a set of embodiments other than the above aspects of the invention, the duty cycle conversion circuit includes a plurality of outputs, each of which is different The output of the inverter is provided.

In a set of embodiments other than the above aspects of the invention, the input signals are provided by a divider circuit portion, such as an N-minute circuit portion. This divider can be driven by a voltage controlled oscillator to form part of, for example, a phase locked loop.

In a set of embodiments of the first aspect of the present invention, the power supply terminal of each of the N inverters is a positive power supply terminal, and the negative power supply terminal of each of the N inverters is grounded. . This allows the duty cycle conversion circuit portion to be triggered by the rising edge (positive transition) of the input signal.

However, in one set of embodiments of the second aspect of the invention, the N inverters Each of the power terminals described is a negative power supply terminal, and a positive power supply terminal of each of the N inverters is connected to a positive power supply rail. This allows the duty cycle conversion circuit portion to be triggered by the falling edge (negative transition) of the input signal.

In a set of embodiments other than the above aspects of the invention, the output signals are used to drive a plurality of individual amplifier circuit sections that share a common low noise amplifier (LNA). This prevents a short circuit in the LNA. However, many other applications are conceivable.

1‧‧‧Work cycle conversion circuit

2, 4, 6, 8‧‧ ‧ reverser

2a, 4a, 6a, 8a‧‧‧ inputs

2b, 4b, 6b, 8b‧‧‧ outputs

2c, 4c, 6c, 8c‧‧‧ positive power supply

2d, 4d, 6d, 8d‧‧‧ negative power supply

10a, 10b, 10c, 10d‧‧‧ input signals

12a, 12b, 12c, 12d‧‧‧ output signals

14‧‧‧ Radio Receiver

16‧‧‧Antenna

18‧‧‧Low Noise Amplifier (LNA)

20, 22‧‧‧Differential mixer

24‧‧‧Bandpass filter

28‧‧‧Divider

30‧‧‧Voltage Controlled Oscillator (VCO)

32‧‧‧Orthogonal output

34‧‧‧ Radio signals

36‧‧‧Output signal

38‧‧‧Oscillator signal

40‧‧‧In-phase (I) signal

42‧‧‧Orthogonal (Q) signal

44‧‧‧Filtered I signal

46‧‧‧Filtered Q signal

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A specific embodiment of the present invention will be described by way of example with reference to the accompanying drawings in which: FIG. 1 is a circuit diagram of a duty cycle conversion circuit in accordance with an embodiment of the present invention; and FIG. 2 is a diagram showing the operation shown in FIG. A timing diagram of a typical signal transition of a period conversion circuit; and FIG. 3 is a schematic diagram of a radio receiver configured to perform quadrature demodulation using the duty cycle conversion circuit of FIG.

Fig. 1 is a circuit diagram of a duty cycle conversion circuit 1 in accordance with an embodiment of the present invention. The duty cycle conversion circuit 1 includes four Boolean inverters 2, 4, 6, and 8. Each of the inverters 2, 4, 6, 8 includes: an input terminal 2a, 4a, 6a, 8a; an output terminal 2b, 4b, 6b, 8b; a positive power terminal 2c, 4c, 6c, 8c; and a negative power terminal 2d, 4d, 6d, 8d.

Each of the inverters 2, 4, 6, 8 is configured to receive a different input signal 10a, 10b, 10c, 10d at its respective input 2a, 4a, 6a, 8a and at its respective output 2b, 4b 6,b, 8b produces an output signal 12a, 12b, 12c, 12d, wherein the output signals 12a-d are logical negations of the individual input signals 10a-d as long as the respective inverters 2, 4, 6, 8 are energized.

While the negative power terminals 2d, 4d, 6d, 8d of each of the inverters 2, 4, 6, 8 are grounded, the positive power terminals 2c, 4c, 6c of each of the inverters 2, 4, 6, 8 are 8c is connected to apply to Input signals 10a-d of different inverters 2, 4, 6, 8. In this particular configuration, the positive power terminal 2c of the first inverter 2 is connected to the input signal 10d applied to the input 8a of the fourth inverter 8; the positive power terminal 4c of the second inverter 4 is connected to the application An input signal 10a to the input terminal 2a of the first inverter 2; a positive power terminal 6c of the third inverter 6 is connected to the input signal 10b applied to the input terminal 4a of the second inverter 4; The positive power terminal 8c of the directional device 8 is connected to the input signal 10c applied to the input terminal 6a of the third inverter 6. It can thus be seen that the inverters 2, 4, 6, 8 are arranged in a loop in which the input signals 10a-d applied to the inverters 2, 4, 6, 8 are used to supply the next reverse in the loop. 2, 4, 6, 8.

Fig. 2 is a timing chart showing typical signal transitions of the duty cycle conversion circuit 1 shown in Fig. 1. The input signals 10a-d have a duty cycle of between 25% and 50% as desired, and may only be derived from a quad splitter driven by a voltage controlled oscillator (not shown). In order to save power, these signals have a clear rising edge but the falling edge is less clear. This means that although each has a duty cycle of approximately 50%, it is not accurate. In the case of a four-phase clock with a 25% duty cycle - that is, in a radio receiver that requires I and Q signals to be modulated and/or demodulated as described below with reference to Figure 3 - cannot be directly Use this signal.

At an initial time t ₀ , the input signals 10a-c applied to the inverters 2, 4, 6 are at a logic low while the other input signal 10d applied to the inverter 8 is at a logic high. Since the fourth input signal 10d is used to supply power to the first inverter 2 due to the connection to the input terminal 2c of the first inverter 2, the first inverter 2 is powered and thus performs the first input signal 10a. The logic negates and produces a logic high at output 2a as indicated by the trace of output signal 12a. The other three inverters 4, 6, and 8 have no power at this time.

At time t ₁ , the first input signal 10a undergoes a positive transition to a logic high. Since the first inverter 2 still has power, this will change the first output signal 12a to a logic low. However, since the first input signal 10a is used to supply power to the second inverter 4 due to the relationship of the positive power supply terminal 4c connected to the second inverter 4, this causes the second inverter 4 to be powered, which performs the The logical negation of the two input signals 10b (which is still low) drives the second output signal 12b to a logic high. In t ₁ shortly after (but not specific time), a negative fourth input signal 10d undergoes transition to logic low, causing the first inverter 2 without electricity. However, this does not affect the first output signal 12a as it is already at logic low.

At time t ₂ , the second input signal 10b undergoes a positive transition to a logic high, causing the second output signal 12b generated by the second inverter 4 to undergo a negative transition to a logic low. The relationship between the second input signal 10b and the positive power supply terminal 6c of the third inverter 6 causes the third inverter 6 to become energized at this time. The third inverter 6 is energized to cause the third output signal 12c generated by the inverter 6 to undergo a positive transition to a logic high because the third input signal 10c is still at logic low. After a period of time (also not clear), the first input signal 10a undergoes a negative transition to a logic low, disabling the second inverter 4, the output of which has become low.

Then, at time t _3, the third input signal 10c subjected to positive transition to logic high. Since the second input signal 10b is still at logic high, the third inverter 6 is energized, which causes the second output signal 12c generated by the third inverter 6 to undergo a negative transition to a logic low at this time. Furthermore, since the third input signal 10c is used to supply power to the fourth inverter 8 and the fourth input signal 10d is now at logic low, the fourth inverter 8 performs a logical negation of the fourth input signal 10d and thus produces a logic high Output signal 12d.

At time t ₄ , the fourth input signal 10d undergoes its next positive transition to a logic high, which causes the fourth output signal 12d (of the fourth inverter 8 that is still powered) to undergo a negative transition to a logic low, and first The output signal 12a undergoes a positive transition to a logic high because the first inverter 2 is again powered. This loop is repeated, where time t _{5 is} equivalent to t ₁ , t _{6 is} equivalent to t ₂ , and the like.

It can be seen that as long as the rising edges of the input signals 10a-d are clear at the correct time interval, and each of the input signals 10a-d has a duty cycle between 25% and 50% (ie, between 1/N and Between 2/N, where N=4), then each output signal 12a-d will be input signal Just 25% of the duty cycle triggered by the rising edge.

FIG. 3 is a schematic diagram of a radio receiver 14 configured to perform quadrature demodulation using the duty cycle conversion circuit 1 of FIG. In addition to the aforementioned duty cycle conversion circuit 1, the radio receiver 14 includes an antenna 16, a low noise amplifier (LNA) 18, two differential mixers 20 and 22, a band pass filter 24, a binary divider 28, And voltage controlled oscillator (VCO) 30. It will be appreciated that while this radio receiver 14 is an exemplary application for one of the aforementioned duty cycle conversion circuits 1, the duty cycle conversion circuit 1 of Figure 1 may provide benefits in other applications.

Antenna receiver 14 is 16 receives radio signals 34 is the frequency f _RF receiver in the "(over-the-air) air" and input to the LNA 18, which amplifies the received signal and generates an output signal "Balance" amplified 36, which is input to each of the mixers 20 and 22.

The VCO 30 produces an oscillator signal 38 at the oscillator frequency f _VCO , which can be controlled in a manner known in the art. The oscillator signal 38 is input to a divide divider 28 which produces a four phase signal 10a-d at the local oscillator frequency f _LO as previously described, where f _LO is half of f _VCO (because the oscillator signal 38 is already differential Therefore, a divide-by-two divider is used instead of the quarter-divider described previously with reference to FIG. 1). However, each of the four-phase signals 10a-d produced by the binary divider 28 and previously described with reference to Figure 2 have any duty cycle in the range of 1/N to 2/N.

The duty cycle conversion circuit 1 converts the four-phase signals 10a-d having an arbitrary duty cycle (in the range of 1/N to 2/N) into the output signals 12a-d, each having exactly 25% (i.e., exactly 1/N). The duty cycle is as described above with reference to Figures 1 and 2. These signals 12a-d are input to mixers 20 and 22 which produce an in-phase (I) signal 40 and a quadrature (Q) signal 42 at intermediate frequencies f _IF , respectively. These I and Q signals 40 and 42 are input to a bandpass filter 24 which produces an orthogonal (I and Q) output 32 at an intermediate frequency f _{IF which} includes filtered by the bandpass filter 24. I signal 44 and filtered Q signal 46.

Thus, it can be seen that the described embodiments of the present invention provide an accurate control of multiple phases A duty cycle conversion circuit of a bit system that uses a single input signal edge type to define an output duty cycle by using a power supply terminal of a plurality of inverters as a control signal. Compared to using NAND or AND gates, the present invention minimizes noise and reduces power consumption without achieving severe duty cycle requirements for RF clock generation.

It will be appreciated by those skilled in the art that the above-described embodiments are merely exemplary and not limiting the scope of the invention.

Claims (12)

A duty cycle conversion circuit portion comprising N inverters, wherein N is an integer greater than two, the duty cycle conversion circuit configured to receive N inputs each having a duty cycle between 1/N and 2/N a signal, wherein: each of the N input signals is applied to an individual input of one of the N inverters, such that each inverter receives a different input signal; and the N input signals are Each is applied to an individual power supply of one of the N inverters such that each inverter is powered by a different input signal; wherein each inverter receives an input signal and application at its respective input The input signal is different to its individual power supply terminals. The duty cycle conversion circuit portion of claim 1 includes a plurality of outputs, each of which is provided by an output of a different inverter. The duty cycle conversion circuit portion of claim 1 or 2, wherein the input signals are provided by a divider circuit portion. The duty cycle conversion circuit unit of claim 3, wherein the divider circuit portion includes an N-minute circuit portion. The duty cycle conversion circuit portion of any one of the preceding claims, wherein the power supply terminal of each of the N inverters is a positive power supply terminal, and the negative power supply terminal of each of the N inverters is grounded . The duty cycle conversion circuit portion of any one of the preceding claims, wherein the output signals are used to drive a plurality of individual amplifier circuit portions sharing a common low noise amplifier. A duty cycle conversion circuit portion includes N inverters, wherein N is an integer greater than two, and the duty cycle conversion circuit is configured to receive a work week between 1-1/N and 1-2/N N input signals, wherein: each of the N input signals is applied to an individual input of one of the N inverters, such that each inverter receives a different input signal; Each of the N input signals is applied to an individual power supply of one of the N inverters such that each inverter is powered by a different input signal; each of the inverters receiving at its respective input The input signal is different from the input signal applied to its individual power supply terminals. The duty cycle conversion circuit portion of claim 7 of the patent application includes a plurality of outputs, each of which is provided by an output of a different inverter. The duty cycle conversion circuit portion of claim 7 or 8, wherein the input signals are provided by a divider circuit portion. The duty cycle conversion circuit unit of claim 9, wherein the divider circuit portion includes an N-minute circuit portion. The duty cycle conversion circuit unit of any one of clauses 7 to 10, wherein the power supply terminal of each of the N inverters is a negative power supply terminal, and each of the N inverters The positive power terminal is grounded. The duty cycle conversion circuit unit of any one of clauses 7 to 11, wherein the output signals are used to drive a plurality of individual amplifier circuit sections sharing a common low noise amplifier.