TW201937565A - 雙閘極ｌｄｍｏｓ及其形成的製程 - Google Patents

雙閘極ｌｄｍｏｓ及其形成的製程 Download PDF

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TW201937565A
TW201937565A TW107140575A TW107140575A TW201937565A TW 201937565 A TW201937565 A TW 201937565A TW 107140575 A TW107140575 A TW 107140575A TW 107140575 A TW107140575 A TW 107140575A TW 201937565 A TW201937565 A TW 201937565A
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region
well
gate
gate dielectric
substrate
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TW107140575A
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TWI710011B (zh
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李明
具政模
拉 夫爾瑪 普拉柯
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新加坡商格羅方德半導體私人有限公司
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Abstract

本發明揭露一種形成高壓裝置的方法。該方法包括設置定義有高壓裝置區的基板。形成裝置阱，以包圍該高壓裝置區。在該裝置阱內形成漂移區。在鄰近該漂移區的該裝置阱內形成本體阱。在該基板上形成變厚度閘極介電質。形成該變厚度閘極介電質包括圖案化犧牲多晶矽層以及氧化該圖案化犧牲多晶矽層，以定義具有傾斜側壁的厚閘極氧化物。在該變厚度閘極介電質上形成閘極電極，其中，該閘極電極部分疊蓋該厚閘極氧化物。鄰近該變厚度閘極介電質的第一及第二側形成第一及第二源/汲(S/D)區。

Description

雙閘極LDMOS及其形成的製程
本發明通常關於半導體裝置。尤其，本發明關於雙閘極LDMOS及其形成的製程。
具有高擊穿電壓及低開態電阻的高壓裝置例如高壓場效應電晶體在積體電路(IC)中用於高壓應用。此類高壓場效應電晶體包括橫向雙擴散金屬氧化物半導體(lateral double-diffused metal oxide semiconductor；LDMOS)電晶體。在一些高壓應用中，積體電路可包括並聯連接的多個LDMOS電晶體，以允許較高的電流處理能力。這要求各LDMOS電晶體一致形成，以確保各該電晶體之間電流的均勻分佈。不過，形成LDMOS電晶體的傳統製程難以控制，且在形成一致的LDMOS電晶體閘極方面不可靠。
而且，LDMOS電晶體的性能通常依賴於汲-源導通電阻(Rdson)以及擊穿電壓(Vbr)。對於高性能LDMOS電晶體，想要低汲-源導通電阻(Rdson)以最小化當其開啟時的功耗，以及高的Vbr以最大化其電壓能力。例如，較低的Rdson導致較高的開關速度，而較高的Vbr增加裝置可靠性。一般來說，較高的擊穿電壓可通過增加基板(substrate)上的汲-柵表 面面積來實現。不過，這增加柵-汲電容，導致較大的Rdson。因此，在性能優化期間在Rdson與Vbr之間常常存在折衷。
因此，需要提供具有較低Rdson及較高Vbr的改進高壓裝置。此外，也想要提供精確且可靠的方法來形成這些高壓裝置。
實施例通常涉及半導體裝置以及形成半導體裝置的方法。在一個實施例中，揭露一種形成高壓半導體裝置的方法。該方法包括設置基板並在該基板內形成多個隔離區。該隔離區包括圍繞第一及第二內部隔離區的裝置隔離區。該裝置隔離區定義該基板的高壓(high voltage；HV)裝置區。該第一及第二內部隔離區設於該HV裝置區中。在該HV裝置區中形成裝置阱(device well)。該裝置阱包圍該HV裝置區。在該裝置阱內形成漂移區。該漂移區鄰近該第一內部隔離區並部分重疊於該第一內部隔離區下方。在該裝置阱內形成本體阱(body well)。該本體阱鄰近該漂移區並圍繞該第二內部隔離區。在該第一與第二內部隔離區之間的該基板上形成雙閘極結構。該雙閘極結構包括氧化多晶矽材料。鄰近該雙閘極結構的第一及第二側形成第一及第二源/汲(S/D)區。該第一S/D區設於該本體阱內，且該第二S/D區設於該漂移區中。
在另一個實施例中，該方法包括設置定義有高壓裝置區的基板。形成裝置阱，以包圍該高壓裝置區。在該裝置阱內形成漂移區。在鄰近該漂移區的該裝置阱內形成本體阱。在該基板上形成變厚度閘極介電質。形成該變厚度閘極介電質包括圖案化犧牲多晶矽層以及氧化該圖案化犧牲多晶矽層，以定義具有傾斜側壁的厚閘極氧化物。在該變厚度閘極介電質 上形成閘極電極，其中，該閘極電極部分疊蓋該厚閘極氧化物。鄰近該變厚度閘極介電質的第一及第二側形成第一及第二源/汲(S/D)區。該第一S/D區設於該漂移區內，且該第二S/D區設於該HV裝置區的該本體阱中。
在又一個實施例中，揭露一種半導體裝置。該半導體裝置包括基板以及設於該基板中的裝置隔離區。該裝置隔離區定義高壓(high voltage；HV)裝置區。第一及第二阱設於HV裝置區中。第一阱包圍該HV裝置區，且該第二阱設於該第一阱內。漂移區設於鄰近該第二阱的該第一阱內。雙閘極結構設於該基板上，疊蓋該第二阱及該漂移區。該雙閘極結構包括閘極電極及變厚度閘極介電質。該變厚度閘極介電質包括氧化多晶矽材料。第一及第二源/汲(S/D)區鄰近該雙閘極結構的第一及第二側設置。
通過參照下面的說明及附圖，本文中所揭露的實施例的這些及其它優點和特徵將會變得更加清楚。而且，應當理解，本文中所述各種實施例的特徵並不相互排斥，而是可存在於各種組合和排列中。
100‧‧‧裝置
102‧‧‧高壓裝置區
105‧‧‧基板
110‧‧‧裝置阱
116‧‧‧漂移區
118‧‧‧本體阱
132、134‧‧‧S/D區、源汲區
136、138‧‧‧阱連接
140‧‧‧電晶體閘極、主閘極
142‧‧‧變厚度閘極介電質、雙閘極介電結構
144‧‧‧閘極電極
150‧‧‧次閘極、閘極場板
160‧‧‧雙閘極結構
180‧‧‧裝置隔離區
184‧‧‧第一內部隔離區
188‧‧‧第二內部隔離區
200‧‧‧製程
2021‧‧‧第一HV裝置區
2022‧‧‧第二HV裝置區
210‧‧‧裝置阱
216‧‧‧漂移區
218‧‧‧本體阱
232、234‧‧‧S/D區、源汲區
236、238‧‧‧阱連接
240‧‧‧電晶體閘極
242‧‧‧雙閘極介電結構
244‧‧‧閘極電極
250‧‧‧閘極場板
252‧‧‧襯墊介電層
254‧‧‧多晶矽層
254a、254b‧‧‧多晶矽結構
260‧‧‧雙閘極結構
262‧‧‧較薄的氧化物層
264‧‧‧較厚氮化物層
266‧‧‧介電堆疊
280‧‧‧厚閘極介電結構
282‧‧‧薄閘極介電質
290‧‧‧蝕刻掩膜
在該些附圖中，類似的附圖標記通常表示不同視圖中的相同部件。另外，該些附圖並不一定按比例繪製，而是通常著重說明各種實施例的原理。在下面的說明中，參照下面的附圖說明本揭露的各種實施例，其中：第1圖顯示裝置的實施例的剖視圖；以及第2a至2l圖顯示用於形成裝置的製程的實施例的剖視圖。
實施例通常涉及半導體裝置或積體電路(integrated circuit；IC)。尤其，實施例涉及高壓(high voltage；HV)裝置。例如，該HV裝置包括HV電晶體。該HV電晶體例如包括橫向雙擴散金屬氧化物半導體(LDMOS)電晶體。作為示例，本揭露的HV裝置可被用作電源管理應用的開關電壓調節器。該HV裝置也可被用於其它合適的應用中。該HV電晶體可被方便地集積於裝置或IC中。該裝置或IC可被納入或用於例如消費電子產品，尤其便攜式消費產品例如智能手機、移動電話、平板電腦、電視顯示器以及個人數字助理(personal digital assistant；PDA)。
第1圖顯示裝置100的實施例的部分的剖視圖。該裝置例如為IC。也可使用其它類型的裝置。該裝置包括基板105。該基板105例如為矽基板。也可使用其它類型的基板，例如矽鍺、鍺、砷化鎵，或絕緣體上矽(silicon-on-insulator；SOI)基板。該基板可為摻雜基板。例如，可用第二極性類型摻雜物例如p型或n型摻雜物輕摻雜該基板。也可設置具有其它類型摻雜物或摻雜物濃度的基板以及未摻雜基板。
該裝置可包括具有不同摻雜物濃度的摻雜區。例如，該裝置可包括重摻雜(x+)、中摻雜(x)及輕摻雜(x-)區，其中，x是極性類型，其可為p型或n型。輕摻雜區可具有約1E11至1E13cm-3的摻雜物濃度。中摻雜區可具有約1E13至1E15cm-3的摻雜物濃度。重摻雜區可具有約1E15至1E17cm-3的摻雜物濃度。該不同摻雜區也可具有其它合適的濃度。P型摻雜物可包括硼(B)、氟(F)、鋁(Al)、銦(In)或其組合，而n型摻雜物可包括磷(P)、砷(As)、銻(Sb)或其組合。
該基板包括周邊電路區。在一個實施例中，該周邊電路區包 括一個或多個高壓(HV)裝置區102。應當理解，基板105也可包括針對其它類型電路的其它裝置區。例如，該基板也可包括針對中壓(intermediate voltage；IV)及低壓(low voltage；LV)裝置的裝置區，以及針對多個互連記憶體裝置例如NVM(非易失性記憶體)裝置的陣列區。
在一個實施例中，裝置隔離區180圍繞HV裝置區102。裝置隔離區180例如將HV裝置區102與其它裝置區隔離。在一個實施例中，該裝置隔離區為淺溝槽隔離(shallow trench isolation；STI)區。也可採用其它類型的隔離區。例如，也可設置深溝槽隔離(deep trench isolation；DTI)區。該STI區例如自該基板的頂部表面延伸至約2000至5000埃的深度。在DTI區的情況下，深度可為約1至10微米。依據隔離要求，也可設置具有其它深度尺寸的隔離區。
HV裝置區102包括第一及第二內部隔離區184及188。在一個實施例中，該內部隔離區是與裝置隔離區180相同類型的隔離區。該內部隔離區例如為STI區。也可使用其它類型的內部隔離區184及188。內部隔離區184及188沿溝道長度方向(y軸)延伸以定義各內部隔離區的寬度。在一個實施例中，第一及第二內部隔離區184及188被配置有不同的寬度。例如，與第二內部隔離區188相比，第一內部隔離區184包括較大的寬度。該內部隔離區用以提供不同電晶體接觸區之間的電性隔離。電晶體接觸區例如包括源/汲(S/D)區以及阱連接區，後面將作詳細說明。該內部隔離區的尺寸可依賴於隔離要求。
HV裝置區102包括HV電晶體，例如LDMOS電晶體。在一個實施例中，該HV電晶體包括設於該基板的頂部表面上的雙閘極結構 160。雙閘極結構160例如包括部分疊蓋變厚度閘極介電質142(下文中稱為“雙閘極介電質”)的閘極電極144。該閘極電極可為多晶矽閘極電極。也可使用其它類型的閘極電極材料。例如，該閘極電極可包括金屬材料，如氮化鉭(TaN)或氮化鈦(TiN)。至於雙閘極介電質142，其可為氧化矽或氧化多晶矽。
如圖所示，雙閘極結構160設於第一與第二內部隔離區184與188之間。雙閘極介電質142包括通過薄閘極介電質及厚閘極介電質定義的不對稱結構。在一個實施例中，該薄閘極介電質包括平坦頂部表面及垂直側壁，而該厚閘極介電質包括平坦頂部表面及錐形(傾斜)側壁。該薄閘極介電質例如鄰接該厚閘極介電質的錐形側壁，以形成連續閘極介電結構。該厚閘極介電質的錐形側壁有利地提供從該較薄的閘極介電質向該較厚的閘極介電質的逐漸過渡。也可使用允許不同介電質厚度之間的逐漸過渡的其它合適的閘極介電質配置。閘極電極144共形設於雙閘極介電質142上方並整個包括均勻的厚度。
在一個實施例中，閘極電極144與雙閘極介電質142的外邊緣對齊並橫向延伸於雙閘極介電質142上方，以定義主閘極140及次閘極150。例如，疊蓋該薄閘極介電質的該閘極電極部分形成主動HV電晶體閘極140(下文中稱為“電晶體閘極”)，且疊蓋該厚閘極介電質的該閘極電極部分形成閘極場板150。閘極電極144自該薄閘極介電質的該垂直側壁連續延伸以部分疊蓋該厚閘極介電質的該平坦頂部表面。例如，電晶體閘極140與閘極場板150電性且實體連接。閘極場板150包括設於該厚閘極介電質的該錐形側壁上的傾斜部分以及設於該厚閘極介電質的該平坦頂部 表面上的水平部分。
在一個實施例中，在鄰近雙閘極結構160的第一及第二側的該基板中設置第一及第二擴散區132及134。例如，第一擴散區132鄰近該薄閘極介電質設置，且第二擴散區134鄰近該厚閘極介電質設置。在一個實施例中，針對第一極性類型電晶體用第一極性類型摻雜物重摻雜該擴散區。該極性類型定義該電晶體的類型。例如，該第一極性類型針對n型電晶體可為n型，且針對p型電晶體可為p型。與內部隔離區184及188相比，擴散區132及134具有較淺的深度。
在一個實施例中，該第一及第二擴散區可充當該電晶體的源/汲(S/D)區。例如，第一擴散區132可充當源區，且第二擴散區134可充當汲區。也可使用其它配置的S/D區。在一個實施例中，源區132與第二內部隔離區188對齊並稍微重疊於該薄閘極介電部分下方。例如，源區132與位於電晶體閘極140下方的電晶體溝道區連通。至於汲區134，它與第一內部隔離區184對齊並稍微重疊於該厚閘極介電部分的該錐形外側壁下方。如圖所示，該汲區偏離閘極場板150一定距離。使汲區134偏離閘極場板150減小HV擊穿操作的該電晶體溝道區附近的峰值電場。
在基板105中可設置裝置阱110。在一個實施例中，裝置阱110包圍HV裝置區102並重疊於裝置隔離區180的部分下方。在一個實施例中，該裝置阱為輕摻雜阱。裝置阱110的摻雜物濃度例如為約1E12至1E13cm-3。在一個實施例中，針對第一極性類型電晶體，用第二極性類型摻雜物摻雜裝置阱110。例如，裝置阱110針對n型電晶體包括p型摻雜物或者針對p型電晶體包括n型摻雜物。裝置阱110形成有足夠的深度 及寬度，以提供HV裝置區102與該基板的相鄰主動區之間的電性隔離。
在HV裝置區102中設置摻雜漂移區116。例如，該漂移區設於裝置阱110內。如圖所示，漂移區116包圍汲區134並重疊於雙閘極結構160的部分下方。例如，該裝置阱橫向延伸超出該厚閘極介電質以部分重疊於該薄閘極介電質下方。漂移區116連接汲區134與位於電晶體閘極140下方的電晶體溝道區。從汲區134至重疊於電晶體閘極140下方的漂移區116的內邊緣的距離可通過所需Rdson定義。
在一個實施例中，針對第一極性類型電晶體用第一極性類型摻雜物摻雜漂移區116。例如，該裝置阱可包括針對n型電晶體的n型摻雜物或針對p型電晶體的p型摻雜物。該漂移區可為輕或中摻雜。在一個實施例中，相對裝置阱110，漂移區116包括較高的摻雜物濃度。漂移區116的摻雜物濃度例如為約5E12至5E13cm-3。依據該HV電晶體的最大Vbr要求，也可使用其它摻雜物濃度。在一個實施例中，與內部隔離區184及188相比，漂移區116包括較深的深度。例如，該裝置阱延伸於第一內部隔離區184的部分下方並重疊於其下方。
在HV裝置區102中設置本體阱118。例如，該本體阱設於裝置阱110內並鄰近漂移區116。本體阱118包括針對第一極性類型電晶體的第二極性類型摻雜物。例如，本體阱118包括針對n型電晶體的p型摻雜物或針對p型電晶體的n型摻雜物。該本體阱的摻雜物濃度可低於源汲區132及134的摻雜物濃度。在一個實施例中，針對n型電晶體用p型摻雜物輕摻雜或中摻雜本體阱118。例如，該本體阱的摻雜物濃度可為約5E12至5E13cm-3。也可使用其它摻雜物濃度。該摻雜物濃度應當足以為 該HV電晶體提供所需的閾值電壓(Vth)，同時防止穿通電流。
與該內部隔離區相比，本體118包括較深的深度。在一個實施例中，本體阱118包圍第二內部隔離區188及源區132，並橫向延伸超出第二內部隔離區188，以重疊於裝置隔離區180的部分下方。在一個實施例中，本體阱118可沿溝道長度方向(y軸)延伸，以重疊於電晶體閘極140的部分下方。本體阱118可鄰接漂移區116的該內邊緣。儘管圖示本體阱118的深度淺於漂移區116的深度，但應當理解，該本體阱的深度也可與漂移區116相同或較深。在一個實施例中，在電晶體閘極140與本體阱118之間的該疊蓋部分確定該電晶體溝道區的長度。例如，該電晶體溝道長度約等於源區132與漂移區116之間的距離。
在裝置區102內的基板105中可設置阱連接。例如，在本體阱118內設置第一阱連接136並在裝置阱110內設置第二阱連接138。針對第一類型電晶體用第二極性類型摻雜物摻雜該第一及第二阱連接。該第二極性類型可為p型或n型。在一個實施例中，阱連接為重摻雜區。例如，阱連接具有約1E15至1E17cm-3的摻雜物濃度。在一個實施例中，該阱連接可通過與該S/D區相同的製程參數形成。例如，阱連接136及138的摻雜物濃度及深度可與電晶體S/D區132及134相同或類似。也可設置具有與該S/D區不同的深度及摻雜物濃度的阱連接。該阱連接用以減小接觸電阻並促進本體阱118及裝置阱110的偏置。第一阱連接136可被稱為本體阱接觸，且第二阱連接138可被稱為裝置阱接觸。
在一個實施例中，本體阱接觸136與第二內部隔離區188及裝置隔離區180對齊。例如，第二內部隔離區188將本體阱接觸136與 源區132隔離。此佈置允許本體阱118獨立於源區132偏置，以使該本體阱連接偏置電壓可不同於源極電壓。
在一個實施例中，裝置阱接觸138與第一內部隔離區184及裝置隔離區180對齊。例如，第一內部隔離區184將裝置阱接觸138與汲區134隔離。此佈置允許裝置阱110獨立於該汲區偏置，以使該裝置阱接觸偏置電壓可不同於汲極電壓。
在裝置100的接觸區上可設置金屬矽化物接觸(未顯示)。例如，該金屬矽化物接觸可設於S/D區132及134、阱連接136及138，以及閘極電極144上。該金屬矽化物接觸例如可為鎳或基於鎳的金屬矽化物接觸。也可使用其它合適類型的金屬矽化物接觸，包括鈷或基於鈷的金屬矽化物接觸。可採用該矽化物接觸以減小接觸電阻並促進與後端工藝(back-end-of-line；BEOL)金屬互連的接觸。
在該基板上方可設置BEOL介電堆疊(未顯示)。該BEOL介電堆疊例如包括層間介電(inter-level dielectric；ILD)層。應當理解，在ILD層之間可具有額外層，例如蝕刻停止層。該ILD層可包括位於金屬前介電(pre-metal dielectric；PMD)層上方的金屬內介電(intra-metal dielectric；IMD)層。該IMD層可充當其中形成金屬互連的金屬層級，或者充當其中形成接觸塞以連接下方金屬層級與上方金屬層級的接觸層級。該金屬互連例如提供不同裝置區之間的連接。PMD層可設於該IMD層與該基板之間，以連接前端工藝(front-end-of-line；FEOL)組件與BEOL互連。例如，該PMD層為第一接觸層級或CA層級。該ILD層可為例如氧化矽。也可使用其它類型介電材料來形成ILD層。在該接觸層級中可設置 接觸塞或過孔塞，例如鎢塞。該PMD層的接觸塞與該HV電晶體的端子或接觸區連通。
如第1圖中所述的實施例導致各種優點。如所述那樣，雙閘極結構160包括設於變厚度閘極介電結構142上的均勻閘極電極層144，以形成HV電晶體閘極140及閘極場板150。雙閘極結構160減小在閘極電極144的汲側多晶矽邊緣聚集的電場，因為該電場通過閘極介電質142的階梯電位變化被重新分佈。設置從HV電晶體閘極140至閘極場板150的錐形過渡減小在薄-厚閘極介電質過渡處的電場增強並允許更均勻的橫向電場分佈，從而增強雙閘極結構160的RESURF(reduced surface field；降低表面場)效應。因此，提升閘極介電Vbr並獲得較低的Rdson。而且，雙閘極介電質142也允許實現較短的漂移長度並潛在地縮小該裝置區的占晶面積(footprint)。而且，自同一閘極電極層形成HV電晶體閘極140及閘極場板150允許HV電晶體閘極140及場板150被共同偏置於合適的電位。
第2a至2l圖顯示用於形成半導體裝置的製程200的實施例的剖視圖。該半導體裝置例如為IC。也可使用其它類型的裝置。通過製程200形成的裝置與第1圖中所示的裝置100類似或相同。為簡潔起見，可能不說明或詳細說明具有相同附圖標記的共同元件及特徵。
請參照第2a圖，設置基板105。該基板可包括矽基板，例如輕摻雜p型或n型基板。也可使用其它類型的基板，包括矽鍺、鍺、砷化鎵，或SOI。也可設置具有其它類型摻雜物或摻雜物濃度的基板以及未摻雜基板。
如圖所示，基板105經製備而具有周邊電路區，在該周邊電路區中形成一個或多個HV電晶體。在一個實施例中，該周邊電路區包括第一HV裝置區2021以及第二HV裝置區2022。HV裝置區例如容置HV電晶體。在一個實施例中，第一HV裝置區2021及第二HV裝置區2022經設置以容置互補HV電晶體。例如，該第一HV裝置區容置第一極性類型電晶體，而該第二HV裝置區容置第二極性類型電晶體。該第一及第二極性類型電晶體為互補類型，例如n型及p型。例如，第一HV裝置區2021容置n型HV電晶體且第二裝置區2022容置p型HV電晶體。儘管僅顯示HV裝置區，但應當瞭解，依據裝置或IC的類型，該基板也可包括針對其它類型電路的其它區域(未顯示)。此外，應當理解，第一及第二HV裝置區2021及2022不需要彼此鄰近。
該基板經製備而具有隔離區，以隔開該不同的裝置區或主動基板區。隔離區可包括例如裝置隔離區180及內部隔離區188及184。裝置隔離區180圍繞該第一及第二HV裝置區。該裝置隔離區例如將各HV裝置區與其它區隔離。在一個實施例中，用於形成裝置隔離區180的製程也可在各HV裝置區內形成第一及第二內部隔離區184及188。例如，該不同隔離區可同時形成，離頂部基板表面具有相同的深度。或者，該不同隔離區可在獨立的製程步驟中形成。在這樣的情況下，該不同隔離區可形成有離頂部基板表面的不同深度。該隔離區例如為STI區。也可使用其它合適類型的隔離區，例如DTI區。
可採用各種製程以形成具有第1圖中所示並所述的配置的STI區。在一個實施例中，基板105經圖案化以對應要形成該不同隔離區 的位置形成溝槽。例如，利用蝕刻及掩膜技術可蝕刻該基板，以形成溝槽，接著用介電材料例如氧化矽填充該溝槽。可執行化學機械拋光(chemical mechanical polishing；CMP)，以移除多餘氧化物並提供基本平坦的頂部表面。也可使用其它製程或材料來形成該STI。該隔離區也可為其它類型的隔離區。
請參照第2b圖，在該基板中形成裝置阱110及210。該裝置阱用以將第一及第二HV裝置區2021及2022與該基板中的相鄰主動裝置區隔離。在一個實施例中，向該基板中離子注入第一及第二極性類型摻雜物，以形成第一裝置阱110及第二裝置阱210。該離子注入製程可包括在該基板上方形成注入掩膜(未顯示)。該注入掩膜例如為圖案化光阻層。在一個實施例中，通過光刻掩膜圖案化該光阻層，以在第一HV裝置區2021上方形成開口。該開口例如暴露該第一HV區並對應用於第一裝置阱注入的開口。通過使用該圖案化光阻作為該第一裝置阱注入掩膜，用第二極性類型摻雜物對該基板進行深度注入，以形成第二極性類型裝置阱110。例如，在第一HV裝置區2021中注入p型摻雜物，例如硼(B)、鋁(Al)、鎵(Ga)或其組合。也可注入其它p型摻雜物。該第一裝置阱注入掩膜保護第二HV裝置區2022免於接收該第一裝置阱注入。在形成第一裝置阱110以後，通過例如灰化製程可移除該第一裝置阱注入掩膜。也可採用其它合適的技術來移除軟掩膜層。
該製程接著形成第二裝置阱注入掩膜(未顯示)，以形成第二裝置阱210。該第二裝置阱注入掩膜可與該第一裝置阱注入掩膜類似地形成。例如，在該基板上方形成注入掩膜，例如圖案化光阻，以將第二HV 裝置區2022選擇性暴露於第二裝置阱注入。通過使用該第二裝置阱注入掩膜，用第一極性類型摻雜物對該基板進行離子注入，以形成第一極性類型裝置阱210。例如，在第二HV裝置區2022中注入n型摻雜物，例如磷(P)、砷(As)、銻(Sb)，或其組合。也可注入其它p型摻雜物。在形成第二裝置阱210以後，通過例如灰化製程可移除該第二裝置阱注入掩膜。也可採用其它合適的技術來移除軟掩膜層。
在一個實施例中，用於形成裝置阱110及210的注入製程包括相同的注入參數。該注入參數例如能量及劑量經調整以在所需位置產生具有所需效果的裝置阱。通過調節該注入的能量及劑量，可控制該裝置阱的摻雜物濃度及深度。也可採用其它技術來形成該裝置阱。
應當瞭解，該第一及第二裝置阱注入掩膜也可經形成以暴露需要以相同注入參數例如注入劑量及濃度注入相同極性類型摻雜物的該基板的其它主動區。例如，可形成多個第一及第二類型裝置阱，以容置多個互補HV電晶體。
請參照第2c圖，在該第一及第二HV裝置區中的各裝置阱110及210內形成漂移區116及216。在一個實施例中，針對p型裝置阱形成n型摻雜漂移區116，且針對n型裝置阱形成p型摻雜漂移區216。該漂移區可通過與形成該裝置阱所採用的注入製程類似的注入製程形成。該漂移區例如通過離子注入形成。在一個實施例中，使用相同的注入參數形成漂移區116及216。例如，漂移區116及216形成有大致相同的摻雜物濃度及深度。該漂移區也可具有其它配置。
請參照第2d圖，在該基板上形成襯墊介電層252。在一個 實施例中，採用熱氧化製程來形成襯墊介電層252。例如，襯墊介電層252可為通過乾式熱氧化製程形成的襯墊氧化物層。該襯墊介電層例如為高品質氧化矽材料。也可使用其它介電材料及製程來形成高品質襯墊介電層252。該熱氧化製程在該第一及第二HV裝置區中的頂部基板表面上生長薄襯墊氧化物層252。該襯墊氧化物層的厚度可為約50至100埃。也可使用其它厚度。
該製程接著在襯墊氧化物層252上形成多晶矽層254。該多晶矽層例如為未摻雜多晶矽層。該多晶矽層的厚度可為約1000至4000埃。可使用各種技術例如沉積製程來形成多晶矽層254。例如，通過化學氣相沉積(chemical vapor deposition；CVD)在襯墊氧化物層252上可沉積多晶矽材料，以形成該多晶矽層。多晶矽層254可充當犧牲多晶矽，以形成第1圖中所示的雙閘極介電質142。
請參照第2e圖，在犧牲多晶矽層254上方形成蝕刻掩膜290。蝕刻掩膜290例如為圖案化光阻。在一個實施例中，根據需要圖案化光阻290，以暴露要被移除的多晶矽層254的部分。光阻290保護位於第一及第二HV裝置區2021及2022中的漂移區116及216上方的多晶矽層254的部分免受蝕刻製程。多晶矽層254的該被保護部分對應將要形成的厚閘極介電結構的位置。如此，移除位於基板105上方的多晶矽層254的該暴露部分。在一個實施例中，利用乾式蝕刻製程例如反應離子蝕刻(reactive ion etching；RIE)實現該暴露多晶矽部分的移除。例如，執行等離子體蝕刻製程。也可使用其它乾式蝕刻製程，包括濺鍍蝕刻及氣相蝕刻。在一個實施例中，在多晶矽層254的該暴露部分上執行氧等離子體蝕刻製程，以 形成具有傾斜側壁的多晶矽結構254a及254b。可調節該氧等離子體蝕刻製程的參數，從而向該蝕刻氣體的受控氧添加導致多晶矽層254上的受控聚合物沉積，其影響該蝕刻製程的非等向性並形成具有傾斜側壁的多晶矽結構254a及254b。例如，多晶矽結構254a及254b包括相對襯墊氧化物層252約45度(45°)的側壁角度。也可設置具有其它側壁角度的多晶矽結構。在一個實施例中，襯墊氧化物層252充當該乾式蝕刻製程的蝕刻停止層。例如，用端點檢測執行該氧等離子體蝕刻製程，以提升蝕刻精度。該端點檢測方法可包括測量該蝕刻氣體的光譜，以監控該蝕刻並檢測該被蝕刻材料中的變化。也可採用其它端點檢測方法。
在形成多晶矽結構254a及254b以後，通過例如灰化製程可移除該蝕刻掩膜。也可採用其它合適的技術來移除蝕刻掩膜290。
請參照第2f圖，在基板105上方共形形成介電堆疊266。例如，該介電堆疊橫貫第一及第二HV裝置區2021及2022，以覆蓋襯墊介電層252及多晶矽結構254a及254b的該暴露表面。在一個實施例中，介電堆疊266通過在第一介電層266上方具有第二介電層264的介電雙層定義。該第一及第二介電層可由不同的介電材料形成並具有不同的厚度。該介電堆疊包括例如位於較薄的氧化物層262上方的較厚氮化物層264。介電堆疊266也可使用其它介電材料或配置。可使用各種技術來形成介電堆疊266。在一個實施例中，採用化學氣相沉積(CVD)。例如，在第一CVD製程中在該基板上方覆被沉積氧化矽層262，以加襯襯墊氧化物層252及多晶矽結構254a及254b的該暴露頂部表面。接著，第二CVD製程在氧化物層262上方覆被沉積氮化矽層264。
氮化物及氧化物層264及262可形成有不同的介電厚度，以定義介電堆疊266的厚度。例如，氧化物層262的厚度可為約100埃，且氮化物層263的厚度可為約600埃。該第一及第二介電層也可具有其它厚度配置。
請參照第2g圖，處理介電堆疊266，以部分暴露下方的多晶矽結構254a及254b。例如，移除該介電堆疊的部分以形成開口，該開口暴露多晶矽結構254a及254b的整個平坦頂部表面。在一個實施例中，處理介電堆疊266包括執行平坦化製程，例如化學機械拋光(CMP)，以移除疊蓋多晶矽結構254a及254b的氮化物層264的部分。該CMP製程在氮化物層264中形成開口，以暴露下方氧化物層262的最上平坦表面部分。氧化物層262例如充當拋光停止層。
執行蝕刻製程，以移除通過氮化物層264中的該開口所暴露的氧化物層262的部分。該蝕刻製程例如移除氧化物層262的暴露部分，以暴露多晶矽結構254a及254b的該平坦頂部表面。該蝕刻製程可包括對介電堆疊266的底部介電層(例如，氧化物層262)具有高選擇性的蝕刻化學，從而不凹入或損傷該下方多晶矽表面。
應當瞭解，也可稍微過蝕刻氧化物層262，以暴露多晶矽結構254a及254b的該傾斜側壁的最上部分。這確保多晶矽結構254a及254b的該平坦最上表面完全暴露於氧化製程。
請參照第2h圖，氧化多晶矽結構254a及254b，以在第一及第二HV裝置區2021及2022上方形成厚閘極介電結構280。在一個實施例中，通過爐氧化製程來完全氧化多晶矽結構254a及254b。例如，採用 該爐氧化製程以氧化被介電堆疊266中的該開口暴露的該多晶矽材料。氮化物層264例如充當針對該氧化製程的選擇性掩膜。該爐氧化製程完全消耗多晶矽結構254a及254b的該多晶矽材料，以形成高品質氧化矽(或爐氧化物)材料。也可使用其它合適的氧化製程來氧化多晶矽結構254a及254b。
應當瞭解，在該多晶矽結構內的氧化物材料的生長也可導致實體厚度的增加。例如，由於厚度尺寸的增加，相對多晶矽結構254a及254b的該平坦頂部表面，所得厚閘極介電結構280可包括較高的平坦頂部表面。厚閘極介電結構280包括例如約1000至4000埃的厚度。依據設計要求，也可使用其它厚度尺寸。
請參照第2i圖，處理該基板，以移除多餘介電材料。可採用各種蝕刻製程，以完全移除介電堆疊266及襯墊氧化物層252的暴露部分。例如，該蝕刻製程可包括高選擇性蝕刻化學，以移除不同的介電材料。該選擇性蝕刻製程可包括合適的製程參數，以最大限度地降低自厚閘極介電結構280的介電材料的移除。應當瞭解，在該蝕刻步驟以後保留重疊於厚閘極介電結構280下方的襯墊氧化物層252的部分，以在厚閘極介電結構280與基板105的該頂部表面之間提供高品質介電界面。
請參照第2j圖，在第一及第二HV裝置區2021及2022中的各裝置阱110及210內形成本體阱118及218。在一個實施例中，針對n型裝置阱116用p型摻雜物摻雜本體阱118，且針對p型裝置阱216用n型摻雜物摻雜本體阱218。隨後，通過與第2b圖中所述類似的離子注入製程可形成該本體阱。也可使用其它技術來形成該本體阱。形成各該本體阱 的該離子注入製程可同時形成具有與該基板105的其它裝置區中的本體阱118及218相同的深度及摻雜物濃度的相同極性類型阱。
在一個實施例中，在基板105上方形成薄閘極介電質282。薄閘極介電質282可通過沉積製程例如CVD形成。例如，在該基板上方共形形成覆被介電層。或者，可通過矽氧化技術生長介電層。接著，圖案化該介電層，以移除覆蓋該基板表面的多餘水平部分，從而形成所得的薄閘極介電質282。通過例如非等向性蝕刻如RIE可實現多餘介電材料的移除。薄閘極介電質282鄰接各厚閘極介電質280，以形成雙閘極介電結構142及242。例如，薄閘極介電質282及厚閘極介電質280由相同的介電材料形成，例如氧化矽。在一個實施例中，薄閘極介電質282包括與形成於基板105的其它裝置區中的MV(中壓)或LV(低壓)電晶體閘極的閘極介電質相同或類似的厚度。例如，在基板105的其它區域中形成電晶體的閘極介電質也形成薄閘極介電質282。
請參照第2k圖，該製程接著在雙閘極介電結構142及242上方形成閘極電極層。該閘極電極層例如可為多晶矽層。該多晶矽閘極層可通過例如CVD形成。可用電晶體類型摻雜物摻雜該多晶矽層，以形成摻雜多晶矽，從而使該閘極電極具有較高的導電性。也可使用其它材料及技術來形成該閘極電極層。通過掩膜及蝕刻技術圖案化該閘極電極層，以形成閘極電極144及244。如圖所示，各閘極電極144及244部分疊蓋各雙閘極介電結構142及242，以形成雙閘極結構160及260。例如，疊蓋該薄閘極介電質的該閘極電極部分形成主動電晶體閘極140(或240)且部分疊蓋該厚閘極介電質的該閘極電極部分形成閘極場板150(或250)。
請參照第2l圖，在基板105中形成重摻雜源汲(S/D)區132、134、232及234。該源汲區包括針對第一極性類型電晶體的第一極性類型摻雜物或針對第二極性類型電晶體的第二極性類型摻雜物。例如，在第一HV裝置區2021中形成n型S/D區，且在第二HV裝置區2022中形成p型S/D區。該源汲區可通過與第2b圖中所述類似的離子注入製程形成。例如，該注入製程可採用源/汲(S/D)注入掩膜(未顯示)，其具有暴露將要形成該源汲區之處的該基板的部分的開口。該S/D注入掩膜也可經圖案化以暴露將要形成阱連接136、138、236及238之處的該基板的部分。例如，具有相同極性類型的S/D區及阱連接可通過相同的注入步驟同時形成。依據注入種類及結要求，可使用合適的注入參數來形成該S/D區及阱連接。
應當理解，在形成該電晶體S/D區之前，可選擇性形成S/D延伸區(未顯示)。例如，該S/D區可包括輕摻雜(LD)延伸區，其延伸超出該重摻雜S/D區以重疊於雙閘極介電結構142及242的部分下方。形成該LD延伸區包括針對第一或第二極性類型電晶體向該基板中注入第一或第二極性類型摻雜物。該製程也可在基板105的其它裝置區中形成電晶體的S/D延伸區。
該製程可接著形成金屬矽化物接觸(未顯示)以及接觸或過孔塞。在位於基板105上的電晶體的端子或接觸區上適當形成矽化物接觸。例如，在HV電晶體閘極、S/D區及本體阱連接上形成矽化物接觸。例如，在矽化物形成以後可完成前端工藝(FEOL)製程。可採用該金屬矽化物接觸以減小接觸電阻並促進與後端工藝(BEOL)金屬互連的接觸。
在該基板上形成金屬前介電(PMD)層(未顯示)，以覆蓋雙閘 極結構160及260。該PMD層充當裝置或IC的第一層間介電(ILD)層，在其中形成接觸塞或過孔以耦接基板105上的各種接觸區或端子。在該PMD層上方可形成額外ILD層，以形成BEOL介電堆疊。該BEOL介電堆疊可包括金屬內介電(IMD)層，在其中形成導線或金屬互連。可執行額外的製程來完成該IC。此類製程可包括最後鈍化、切割、封裝及測試。
如第2a至2l圖中所述的實施例導致各種優點。如所述那樣，圖案化並隨後氧化犧牲未摻雜多晶矽層，以形成雙閘極介電結構142及242的該厚閘極介電部分。採用乾式蝕刻製程圖案化該犧牲多晶矽層避免了對極難以控制的濕式清洗製程的需要，從而改進在形成雙閘極介電結構142及242方面的控制及精度。在該圖案化犧牲多晶矽層上執行爐氧化製程形成具有高品質氧化物材料的厚閘極介電結構，以提升熱載流子注入(hot-carrier injection；HCI)可靠性。
可以其它特定形式實施本揭露的發明概念而不背離本發明的精神或基本特徵。因此，上述實施例在各方面被視為示例性質而非限制本文中所述的發明。因此，本發明的範圍由所附申請專利範圍而非上述說明表示，且意圖包括在該申請專利範圍的均同意義及範圍內的所有變更。

Claims (20)

  1. 一種形成高壓裝置的方法，包括：設置基板；在該基板內形成多個隔離區，其中，該隔離區包括裝置隔離區、以及第一及第二內部隔離區，其中，該裝置隔離區定義該基板的高壓(HV)裝置區，且該第一及第二內部隔離區設於該HV裝置區中；在該HV裝置區中形成裝置阱，其中，該裝置阱包圍該HV裝置區；在該裝置阱內形成漂移區，其中，該漂移區鄰近該第一內部隔離區並部分重疊於該第一內部隔離區下方；在該裝置阱內形成本體阱，其中，該本體阱鄰近該漂移區並圍繞該第二內部隔離區；在該第一與第二內部隔離區之間的該基板上形成雙閘極結構，其中，該雙閘極結構包括氧化多晶矽材料；以及鄰近該雙閘極結構的第一及第二側形成第一及第二源/汲(S/D)區，其中，該第一S/D區設於該本體阱內，且該第二S/D區設於該漂移區中。
  2. 如申請專利範圍第1項所述的方法，其中，該第一S/D區與該第一內部隔離結構對齊，且該第二S/D區與該第二內部隔離結構對齊。
  3. 如申請專利範圍第1項所述的方法，包括在該裝置阱內形成第一阱連接，且在該本體阱內形成第二阱連接。
  4. 如申請專利範圍第3項所述的方法，其中，該第一阱連接設於該第一內部隔離區與該裝置隔離區之間，且該第二阱連接設於該第二內部隔離區與該裝置隔離區之間。
  5. 如申請專利範圍第1項所述的方法，其中，形成該裝置阱及該本體阱包括注入p型摻雜物，以及形成該漂移區包括注入n型摻雜物。
  6. 如申請專利範圍第1項所述的方法，其中，該雙閘極結構包括通過薄閘極介電質鄰接厚閘極介電質定義的變厚度閘極介電質，其中，該厚閘極介電質包括該氧化多晶矽材料。
  7. 如申請專利範圍第6項所述的方法，其中，該厚閘極介電質包括傾斜側壁，其中，該厚閘極介電質的該側壁相對該基板的頂部表面形成約45度的角度。
  8. 如申請專利範圍第6項所述的方法，其中，形成該雙閘極結構包括圖案化犧牲多晶矽層，以及執行氧化製程以氧化該圖案化犧牲多晶矽層。
  9. 如申請專利範圍第6項所述的方法，其中，形成該雙閘極結構包括在該變厚度閘極介電質上形成閘極電極，其中，該閘極電極部分疊蓋該厚閘極介電質。
  10. 如申請專利範圍第9項所述的方法，其中，該第二S/D區鄰近該厚閘極介電質。
  11. 一種形成高壓電晶體的方法，包括：設置基板；在該基板內形成裝置隔離區，其中，該裝置隔離區圍繞該基板的高壓(HV)裝置區；在該第一HV裝置區中形成裝置阱，其中，該裝置阱包圍該HV裝置區； 在該裝置阱內形成漂移區；在該裝置阱內形成本體阱，其中，該本體阱鄰近漂移區；在該基板上形成變厚度閘極介電質，其中，形成該變厚度閘極介電質包括圖案化犧牲多晶矽層並氧化該圖案化犧牲多晶矽，以定義該變厚度閘極介電質的厚閘極氧化物，其中，該厚閘極氧化物包括傾斜側壁；在該變厚度閘極介電質上形成閘極電極，其中，該閘極電極部分疊蓋該厚閘極氧化物；以及鄰近該變厚度閘極介電質的第一及第二側形成第一及第二源/汲(S/D)區，其中，該第一S/D區設於該漂移區內，且該第二S/D區設於該HV裝置區的該本體阱中。
  12. 如申請專利範圍第11項所述的方法，包括在該裝置阱內形成第一及第二內部隔離區，其中，該變厚度閘極介電質位於該第一與第二內部隔離區之間。
  13. 如申請專利範圍第12項所述的方法，其中，該第一S/D區鄰近該第一內部隔離區，且該第二S/D區鄰近該第二內部隔離區。
  14. 如申請專利範圍第11項所述的方法，其中，該裝置阱與該本體阱包括相同極性類型摻雜物，其中，該漂移區包括與該裝置阱及本體阱不同的極性類型摻雜物。
  15. 如申請專利範圍第11項所述的方法，其中，形成該變厚度閘極介電質包括形成鄰接該厚閘極氧化物的傾斜側壁的薄閘極介電質。
  16. 如申請專利範圍第15項所述的方法，其中，該閘極電極延伸覆蓋該薄閘極介電質的整個頂部表面，且該閘極電極整個包括均勻的厚 度。
  17. 一種半導體裝置，包括：基板；裝置隔離區，設於該基板中，其中，該裝置隔離區定義高壓(HV)裝置區；第一及第二阱，設於該HV裝置區中，其中，該第一阱包圍該HV裝置區，且該第二阱設於該第一阱內；漂移區，設於該第一阱內，其中，該漂移區鄰近該第二阱；雙閘極結構，設於該基板上，疊蓋該第二阱及該漂移區，其中，該雙閘極結構包括閘極電極及變厚度閘極介電質，且該變厚度閘極介電質包括氧化多晶矽材料；以及第一及第二源/汲(S/D)區，鄰近該雙閘極結構的第一及第二側設置。
  18. 如申請專利範圍第17項所述的半導體裝置，復包括設於該漂移區中的第一內部隔離區以及設於該第二阱中的第二內部隔離區，其中，該雙閘極結構位於該第一與第二內部隔離區之間。
  19. 如申請專利範圍第17項所述的半導體裝置，其中，該雙閘極結構包括具有第一及第二傾斜側壁的厚閘極氧化物，其中，該厚閘極氧化物由該氧化多晶矽材料定義。
  20. 如申請專利範圍第19項所述的半導體裝置，其中，該雙閘極結構包括鄰接該厚閘極氧化物的傾斜側壁的薄閘極介電質，其中，該閘極電極層覆蓋該薄閘極介電質的頂部表面並部分疊蓋該厚閘極氧化物的平坦最上表面。
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