TW201935529A - Method for making a semiconductor device - Google Patents

Abstract

The present disclosure provides a method for making a semiconductor device. The method for making a semiconductor device comprises: providing a first semiconductor layer comprising a first area; forming a second semiconductor layer on the first area, wherein the second semiconductor layer comprising a dopant, and a doping concentration of the dopant in the second semiconductor layer is higher than a doping concentration of the dopant in the first semiconductor layer; introducing the dopant of the second semiconductor layer into the first area of the first semiconductor layer.

Description

Method for manufacturing semiconductor element

The present application relates to a method for manufacturing a semiconductor device, and more particularly to a method for allowing a dopant to enter a semiconductor layer.

In the process of manufacturing semiconductor devices, doping is a common step. In the prior art, if a dopant is to be doped to a desired region, a region that is not to be doped is masked by a shield to expose the desired region, and the exposed region is exposed to a full doping In the environment of impurities, the exposed area is brought into contact with the dopant, and the dopant is diffused into the exposed area.

The present application provides a method for manufacturing a semiconductor device, including: providing a first semiconductor layer including a first region; forming a second semiconductor layer on the first region; the second semiconductor layer including a dopant; and The concentration of the dopant in the second semiconductor layer is higher than the concentration of the dopant in the first semiconductor layer; and the dopant of the second semiconductor layer enters the first region of the first semiconductor layer to enhance the dopant The concentration in the first region.

The invention provides a method for manufacturing a semiconductor device, which includes: providing a first semiconductor layer including a first region; forming a second semiconductor layer on the first region; the second semiconductor layer including a dopant; and The concentration of the dopant in the second semiconductor layer is higher than the concentration of the dopant in the first semiconductor layer; the dopant of the second semiconductor layer is allowed to enter the first region of the first semiconductor layer to enhance the Concentration in the first region; and forming a light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an activity between the first conductive type semiconductor layer and the second conductive type semiconductor layer region.

The invention provides a method for manufacturing a semiconductor light emitting element, which includes: providing a first semiconductor structure, the first semiconductor structure including a first region; forming a semiconductor layer on the first semiconductor structure, the semiconductor layer including a dopant, And the concentration of the dopant in the semiconductor layer is higher than the concentration of the dopant in the first semiconductor structure; and the dopant in the semiconductor layer is diffused into the first region of the first semiconductor structure to improve the Concentration in a region.

The following embodiments will illustrate the concept of the present application along with drawings. In the drawings or description, similar or identical parts use the same reference numerals, and in the drawings, the shape or thickness of elements can be expanded or reduced. It should be particularly noted that components not shown in the figure or not described in the specification may be in a form known to those skilled in the art, and descriptions of the same technical features may be omitted between embodiments to avoid repetition.

In the content of this application, if there is no special description, the semiconductor material disclosed in this application may include a combination of various elements, for example, the general formula AlGaAs represents Al _x Ga _(1-x) As, where 0 ≦ x ≦ 1; general formula AlInP stands for Al _x In _(1-x) P, where 0 ≦ x ≦ 1; the general formula AlGaInP stands for (Al _y Ga _(1-y) ) _1-x In _x P, where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1; the general formula AlGaN represents Al _x Ga _(1-x) N, where 0 ≦ x ≦ 1; the general formula AlAsSb represents AlAs _(1-x) Sb _x , where 0 ≦ x ≦ 1; the general formula InGaAsP represents In _x Ga _1-x As _1-y P _y , where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1; the general formula AlGaAsP stands for Al _x Ga _1-x As _1-y P _y , where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1; InGaAsN representative of the general formula _{In x Ga 1-x As 1} -y N y,, where 0 ≦ x ≦ 1,0 ≦ y ≦ 1; InGaAs on behalf of the general formula _{In x Ga 1-x As,} , wherein 0 ≦ x ≦ 1; the general formula InGaN stands for In _x Ga _1-xN , where 0 ≦ x ≦ 1; and the general formula InGaP stands for In _x Ga _1-x P, where 0 ≦ x ≦ 1. Adjusting the content of the element can achieve different purposes, such as adjusting the energy level or adjusting the dominant or peak wavelength.

FIG. 1A to FIG. 1D are one embodiment of a method for manufacturing a semiconductor device according to the present application. In this embodiment, the method for manufacturing a semiconductor element includes steps:

a, as shown in FIG. 1A, a growth substrate 10 is provided, which has an upper surface 101;

b. As shown in FIG. 1A, a first semiconductor layer 20 is formed on the upper surface 101 of the growth substrate 10. The first semiconductor layer 20 includes a first region 21 and a second region 22, and a first semiconductor layer is formed therein. 20 ways include epitaxial growth;

c. As shown in FIG. 1A, a second semiconductor layer 30 is formed on the first semiconductor layer 20, wherein the second semiconductor layer 30 includes a first dopant, and the first dopant is on the second semiconductor layer 30. The concentration inside is higher than the concentration of the first dopant in the first semiconductor layer 20; in one embodiment, the concentration of the first dopant in the second semiconductor layer 30 is not less than 1´10 ¹⁸ / cm ³ , And preferably, it is between 1´10 ¹⁹ / cm ³ and 1´10 ²² / cm ³ (both are included), wherein the method of forming the second semiconductor layer 30 includes epitaxial growth; in one embodiment The thickness of the second semiconductor layer 30 may be greater than the thickness of the first semiconductor layer 20, preferably, the thickness of the second semiconductor layer 30 is not less than 300 angstroms (Å), and preferably, not more than 0.5 micrometers (um); In one embodiment, the thickness of the second semiconductor layer 30 may be smaller than the thickness of the first semiconductor layer 20;

d. As shown in FIG. 1B, the second semiconductor layer 30 is patterned so that the patterned second semiconductor layer 30 is located directly above the first region 21 of the first semiconductor layer 20, that is, the first semiconductor layer The first region 21 of 20 overlaps the patterned second semiconductor layer 30 in the vertical direction, and the second region 22 of the first semiconductor layer 20 is not covered with the second semiconductor layer 30. Specifically, the vertical direction means vertical In the direction of the upper surface 101 of the growth substrate 10, the manner of patterning the second semiconductor layer 30 includes, but is not limited to, a lithographic mask, embossing, electron beam, or laser beam; and

e. As shown in FIG. 1C, the first dopant of the patterned second semiconductor layer 30 is allowed to enter the first region 21 of the first semiconductor layer 20 to enhance the first dopant in the first region 21 The concentration, in which the manner in which the first dopant of the patterned second semiconductor layer 30 enters the first region 21 of the first semiconductor layer 20 includes, but is not limited to, heat treatment and / or pressure treatment.

After step e, the concentration of the first dopant in the first region 21 of the first semiconductor layer 20 is greater than the concentration of the first dopant in the second region 22. In an embodiment, the concentration of the first dopant in the second region 22 may be zero or near zero. In one embodiment, preferably, the difference between the concentration of the first dopant in the first region 21 and the concentration of the first dopant in the second region 22 is greater than 1´10 ¹⁶ / cm ³ , and more preferably Ground, greater than 1´10 ¹⁸ / cm ³ . In an embodiment, preferably, the concentration of the first dopant in the first region 21 of the first semiconductor layer 20 is greater than 1´10 ¹⁶ / cm ³ , and more preferably, greater than 1´10 ¹⁸ / cm ³ . In an embodiment of the foregoing step c, when the thickness of the second semiconductor layer 30 is greater than the thickness of the first semiconductor layer 20, performing step e can make the diffusion of the first dopant more efficient, and it is easier to make the first dopant more effective. The difference between the concentration of the dopant in the first region 21 and the concentration in the second region 22 is greater than 1´10 ¹⁶ / cm ³ .

Specifically, in step b, the first region 21 is a region predetermined to diffuse the first dopant into in step e.

In an embodiment, before step e, the first semiconductor layer 20 has a first conductivity type, that is, both the first region 21 and the second region 22 have a first conductivity type, and the second semiconductor layer 30 has a A second conductivity type different from the first conductivity type. For example, when the first semiconductor layer 20 is a p-type, the second semiconductor layer 30 is an n-type. In this aspect, the first dopant in the second semiconductor layer 30 is an n-type dopant, such as silicon (Si ) Or tellurium (Te). As another example, when the first semiconductor layer 20 is n-type, the second semiconductor layer 30 is p-type. In this state, the first dopant in the second semiconductor layer 30 is a p-type dopant, such as zinc ( Zn), magnesium (Mg) or carbon (C). Next, after step e, the first region 21 of the first semiconductor layer 20 is changed to have a third conductivity type, and the third conductivity type may be the same as the second conductivity type and different from the first conductivity type. The second region 22 of the first semiconductor layer 20 still has a first conductivity type. For example, after step e, the first region 21 of the first semiconductor layer 20 is n-type and the second region 22 of the first semiconductor layer 20 is p-type. For example, after step e, the first region 21 of the first semiconductor layer 20 One region 21 is p-type, and the second region 22 of the first semiconductor layer 20 is n-type. In detail, since the patterned second semiconductor layer 30 is located directly above the first region 21 of the first semiconductor layer 20 and indirectly or directly contacts the upper surface of the first region 21, the first semiconductor layer 20 The second region 22 is not covered with the second semiconductor layer 30. Therefore, in step e, the first dopant of the second semiconductor layer 30 enters the first region 21 of the first semiconductor layer 20, and the first semiconductor layer The second region 22 of 20 is not substantially affected. Therefore, after step e, the conductivity type of the first region 21 of the first semiconductor layer 20 will be changed to a third conductivity type, and this third conductivity type may be the same as the second conductivity type of the second semiconductor layer 30 State, and the second region 22 of the first semiconductor layer 20 still has a first conductivity type. The "indirect contact" referred to in this application means that there may be one or more buffer layers between the upper surface of the first region 21 and the first semiconductor layer 20, but the first dopant can still pass through the buffer layer into the first region twenty one. When an embodiment in which the third conductivity type of the first region 21 is different from the first conductivity type of the second region 22 is applied to a semiconductor element, the first semiconductor layer 20 can be used as a current limiting structure to allow a current to selectively flow in The first area 21 or the second area 22.

In an embodiment, before step e, the first semiconductor layer 20 has a first conductivity type, that is, both the first region 21 and the second region 22 have a first conductivity type, and the second semiconductor layer 30 has a The second conductivity type, which is the same as the first conductivity type, for example, both the first conductivity type and the second conductivity type are p-type or both are n-type. Since the patterned second semiconductor layer 30 is located directly above the first region 21 of the first semiconductor layer 20 and indirectly or directly contacts the upper surface of the first region 21, the second semiconductor layer 30 on the first semiconductor layer 20 It is not covered with the second semiconductor layer 30, so in step e, the first dopant of the second semiconductor layer 30 enters the first region 21 of the first semiconductor layer 20, and the second region of the first semiconductor layer 20 22 is essentially unaffected. The "indirect contact" referred to in this application means that there is one or more buffer layers between the upper surface of the first region 21 and the first semiconductor layer 20, but the first dopant can still pass through the buffer layer and enter the first region 21 . Therefore, after step e, the concentration of the first dopant in the first region 21 of the first semiconductor layer 20 will increase. For example, the concentration of the first dopant will be greater than 1´10 ¹⁶ / cm ³ . The concentration of the first dopant in the region 21 is greater than the concentration of the first dopant in the second region 22, where the concentration of the first dopant in the second region 22 may be zero or near zero, for example. Therefore, after step e, the first region 21 and the second region 22 of the first semiconductor layer 20 have different electrical resistance values. When an embodiment in which the first region 21 and the second region 22 have different electrical resistance values is applied to a semiconductor device, the first semiconductor layer 20 can be used as a current distribution structure, so that the current flowing into the first region 21 and the second region 22 can be reduced. The current value is different.

In an embodiment, before forming the first semiconductor layer 20 on the upper surface 101 of the growth substrate 10 in step b, the method of manufacturing a semiconductor device further includes forming a third semiconductor layer (not shown) by epitaxial growth on the On the upper surface 101 of the growth substrate 10, the third semiconductor layer has a fourth conductivity type, which is the same as the second conductivity type of the second semiconductor 30 formed in step c, and is different from the first semiconductor layer. 20 has a first conductivity type, for example, when the fourth conductivity type is an n-type, the first conductivity type is a p-type, and the second conductivity type is an n-type.

In an embodiment, after step e, the method for manufacturing a semiconductor device may further include a step f to remove the patterned second semiconductor layer 30, as shown in FIG. 1D. For example, the patterned second semiconductor layer 30 is removed by etching, grinding, or laser cutting.

FIG. 2 is a graph showing the relationship between the dopant concentration and the doping depth of one embodiment of a semiconductor device manufactured using the methods shown in FIGS. 1A to 1D. In this embodiment, the thickness of the growth substrate 10 is about 350 um. The growth substrate is an n-type conductive substrate having a dopant, and the thickness of the first semiconductor layer 20 is about 500 angstroms. The circle marks in FIG. 2 show the relationship between the dopant concentration and the doping depth of the growth substrate 10, and the triangle marks show the first dopant concentration and doping in the first region 21 of the first semiconductor layer 20. Relationship in depth. The position at a depth of 0 um is the upper surface of the first semiconductor layer 20. It can be seen from the figure that at least a part of the first region 21 of the first semiconductor layer 20 in this embodiment, preferably, the first region 21 In the region near the upper surface of the first semiconductor layer 20, the concentration of the first dopant increases with increasing doping depth, that is, at least a part of the first region 21 is further away from the first semiconductor layer 20 The higher the position of the surface, the higher the concentration of the first dopant.

In one embodiment, after the step of removing the patterned second semiconductor layer 30, the method for manufacturing a semiconductor device further includes forming a light emitting structure (not shown) on the first semiconductor layer 20. The light emitting structure includes a The first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active region between the first conductive type semiconductor layer and the second conductive type semiconductor layer. The first conductivity type semiconductor layer and the second conductivity type semiconductor layer have different conductivity types. For example, the first conductive type semiconductor layer is an n-type that provides electrons, the second conductive type semiconductor layer is a p-type that provides an electron hole, and the energy gap of the first conductive type semiconductor layer and the second conductive type semiconductor layer are greater than The energy gap of the active region.

In an embodiment, before the first semiconductor layer 20 is formed, the method for manufacturing a semiconductor device further includes forming a light emitting structure (not shown) on the growth substrate 10. The light emitting structure of this embodiment may be the same as that of the foregoing embodiment. The light emitting structures are the same or similar.

The active area of the present application may emit a radiation having a peak wavelength. In an embodiment, when the light-emitting element is a light-emitting diode, the radiation is non-homogeneous light with a far field angle greater than 60 degrees, preferably greater than 80 degrees. In another embodiment, when the light-emitting element is a laser light-emitting element, the radiation is homogeneous light with a far-field angle of less than 25 degrees, preferably less than 20 degrees, and even more preferably less than 15 degrees.

In an embodiment, in step c, the second semiconductor layer 30 is formed on the first semiconductor layer 20 at a first temperature. Preferably, the first temperature is not lower than 550 ° C and not higher than 700 ° C, and more preferably, the first temperature is not lower than 580 ° C and not higher than 670 ° C.

In an embodiment, the first dopant of the patterned second semiconductor layer 30 enters the first region 21 of the first semiconductor layer 20 by heating to operate at a second temperature, and the second temperature is lower than The first temperature of the second semiconductor layer 30. Preferably, the difference between the first temperature and the second temperature is not more than 50 ° C, and not less than 5 ° C, and more preferably, not more than 30 ° C. Specifically, the heat treatment method includes, but is not limited to, placing the structure formed in step d into a furnace tube for heat treatment, or placing the structure formed in step d into a metal organic chemical vapor deposition (Metalorganic Chemical Vapor Phase Deposition; MOCVD) is performed in the chamber of the machine.

The first semiconductor layer 20, the second semiconductor layer 30, and the third semiconductor layer include a group III semiconductor material, for example, a group III semiconductor material or a group III semiconductor material with a dopant, for example, a concentration Group ³ or 5 semiconductor materials with dopants greater than 1´10 ¹⁶ / cm ³ , or dopings with a concentration between 1´10 ¹⁸ / cm ³ and 1´10 ²² / cm ³ (both inclusive) Three or five semiconductor materials. As another example, the three or five semiconductor materials may include aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), gallium phosphide arsenide (GaAsP), InGaN (indium gallium nitride), or AlGaN (aluminum gallium nitride) Wait. In one embodiment, the first semiconductor layer 20 includes aluminum gallium indium phosphide (AlGaInP), the second semiconductor layer 30 includes aluminum gallium arsenide (AlGaAs), and the third semiconductor layer includes aluminum gallium arsenide (AlGaAs), wherein The first dopant in the second semiconductor layer 30 is zinc (Zn).

The semiconductor element in the present application may include, but is not limited to, a light emitting diode, a laser element, a light sensor, a solar cell, a field effect transistor or a power element, and the like. The method of the present application covers the first region 21 of the first semiconductor layer 20 with the patterned second semiconductor layer 30, and in step e, diffuses the first dopant in the patterned second semiconductor layer 30. Entering the first region 21 of the first semiconductor layer 20, so that the first region 21 of the first semiconductor layer 20 includes a first dopant after step e. The method of the present application utilizes a patterned semiconductor layer as a source of dopants, so that steps a to c and e can be performed in a chamber of a machine of a Metalorganic Chemical Vapor Phase Deposition (MOCVD). It can reduce the use of additional process equipment such as evaporation machines and high-temperature furnaces. Therefore, compared with the traditional doping process, the technology of this application includes at least a significant reduction in the cost of equipment for manufacturing semiconductor devices, while reducing the doping process. Benefits include transfer time between process equipment, increased process convenience and yield per unit of time.

3A to 3G are one embodiment of a method for manufacturing a semiconductor device in accordance with the present application. In this embodiment, the semiconductor element is a semiconductor light emitting element, such as a laser light emitting element. A method of manufacturing a semiconductor light emitting element includes steps:

a, as shown in FIG. 3A, a growth substrate 40 is provided, which has an upper surface 401;

b. As shown in FIG. 3A, an epitaxial structure 50 is formed on the upper surface 401, which includes a first reflector 60, a second reflector 70, and a first reflector 60 and a second reflector 70. The light-emitting structure 80 may be substantially the same as or similar to the light-emitting structure mentioned in the embodiment described earlier in this application. The first mirror 60 and the second mirror 70 each have a conductive type, and the conductive type of the first mirror 60 is different from the conductive type of the second mirror 70. For example, the first mirror 60 is an n-type, The second mirror 70 is a p-type;

c. As shown in FIG. 3A, a first semiconductor structure 90 is formed. The first semiconductor structure 90 includes a first region 91 and a second region 92. The method of forming the first semiconductor structure 90 includes epitaxial growth; Preferably, before the subsequent doping step f is performed, the conductivity type of the first semiconductor structure 90 is different from the conductivity type of the second reflector 70. For example, the second reflector 70 is p-type, and the The conductivity type is n-type, that is, the conductivity types of the first region 91 and the second region 92 of the first semiconductor structure 90 are both n-type;

d. As shown in FIG. 3A, a semiconductor layer 100 is formed on the first semiconductor structure 90. The semiconductor layer 100 includes a first dopant, and the concentration of the first dopant in the semiconductor layer 100 is higher than that of the first dopant. The concentration of the dopant in the first semiconductor structure 90. In an embodiment, the concentration of the first dopant in the semiconductor layer 100 is not less than 1´10 ¹⁸ / cm ³ , and preferably between 1´10 ¹⁹ / cm ³ and 1´10 ²² / cm ³ Between (both of them), wherein the method of forming the semiconductor layer 100 includes epitaxial growth; in one embodiment, the thickness of the semiconductor layer 100 may be greater than the thickness of the first semiconductor structure 90. Preferably, the The thickness is not less than 300 angstroms (Å), and more preferably, the thickness of the semiconductor layer 100 is not more than 0.5 micrometers (um); in an embodiment, the thickness of the second semiconductor layer 30 may be smaller than the thickness of the first semiconductor layer 20 ;

e. As shown in FIG. 3B, the semiconductor layer 100 is patterned so that the patterned semiconductor layer 100 is located directly above the first region 91 of the first semiconductor structure 90, that is, the first of the first semiconductor structure 90 The region 91 overlaps the patterned semiconductor layer 100 in the vertical direction, and the second region 92 of the first semiconductor structure 90 is not covered with the semiconductor layer 100. Specifically, the vertical direction means perpendicular to the upper surface of the growth substrate 40 plate. The direction of 401, in which the first semiconductor layer 100 is patterned includes, but is not limited to, a lithographic mask, an imprint, an electron beam, or a laser beam;

f. As shown in FIG. 3C, the first dopant of the patterned semiconductor layer 100 is diffused into the first region 91 of the first semiconductor structure 90 to increase the concentration of the first dopant in the first region 91. The manner in which the first dopant of the patterned semiconductor layer 100 enters the first region 91 of the first semiconductor layer includes, but is not limited to, heat treatment and / or pressure treatment;

g. As shown in FIG. 3D, selectively, but preferably, removing the patterned semiconductor layer 100, for example, removing the patterned semiconductor layer 100 by etching, grinding, or laser cutting, etc .;

h. As shown in FIG. 3E, a third reflector 110 is formed on the first semiconductor structure 90. The third reflector 110 has a conductive type that is the same as the conductive type of the second reflector 70. For example, In this embodiment, the third reflecting mirror 110 is a p-type, and the second reflecting mirror 70 is a p-type;

i. as shown in FIG. 3F, selectively, but preferably, forming a semiconductor contact layer 120 on the third reflector 110, wherein the method of forming the semiconductor contact layer 120 includes epitaxial growth; and

j. As shown in FIG. 3G, selectively, but preferably, forming a first electrode 130 on the semiconductor contact layer 120 and forming a second electrode on the other side of the growth substrate 40 opposite to the epitaxial structure 50 The electrode 140 includes a method for forming the first electrode 130 and the second electrode 140 by evaporation.

After step f, the concentration of the first dopant in the first region 91 of the first semiconductor structure 90 is greater than the concentration of the first dopant in the second region 92 of the first semiconductor structure 90. In an embodiment, the concentration of the first dopant in the second region 92 may be zero or near zero. In one embodiment, preferably, the difference between the concentration of the first dopant in the first region 91 and the concentration of the first dopant in the second region 92 is greater than 1´10 ¹⁶ / cm ³ , which is even better. Ground, greater than 1´10 ¹⁸ / cm ³ . In one embodiment, preferably, the concentration of the first dopant in the first region 91 of the first semiconductor structure 90 is greater than 1´10 ¹⁶ / cm ³ , and more preferably, greater than 1´10 ¹⁸ / cm ³ .

Specifically, in step c, the first region 91 is a region predetermined to diffuse the first dopant into in step f.

FIG. 4 is a relationship diagram between the first dopant concentration and the depth in the first semiconductor structure 90 according to the embodiment shown in FIG. 3D. The position at a depth of 0 um is the upper surface of the first semiconductor structure 90. As shown in FIG. 4, at least a part of the first region 91, preferably, the first region 91 is adjacent to the first semiconductor structure 90. In the region of the upper surface, the concentration of the first dopant increases as the doping depth increases, that is, at least a part of the first region 91, the further away from the upper surface of the first semiconductor structure 90, the first doping The higher the concentration of the substance.

In an embodiment, before step f, the conductive type of the patterned semiconductor layer 100 and the conductive type of the first semiconductor structure 90 are different. For example, the conductive type of the patterned semiconductor layer 100 is p-type. The first semiconductor structure 90 is n-type. In this aspect, the first dopant in the patterned semiconductor layer 100 is a p-type dopant, such as zinc (Zn), magnesium (Mg), and carbon (C). ) Or beryllium (Be), in this example, the first dopant is zinc (Zn). For another example, the conductive type of the patterned semiconductor layer 100 is n-type, and the first semiconductor structure 90 is p-type. In this aspect, the first dopant in the patterned semiconductor layer 100 is n-type doped. Materials, such as silicon (Si), tellurium (Te), or germanium (Ge). Next, in step f, since the patterned semiconductor layer 100 is located directly above the first region 91 of the first semiconductor structure 90 and indirectly or directly contacts the upper surface of the first region 91, the first semiconductor structure 90 The second region 92 is not covered with the semiconductor layer 100. Therefore, the first dopant in the patterned semiconductor layer 100 enters the first region 91 of the first semiconductor structure 90, and the second region of the first semiconductor structure 90 is second. Region 92 is essentially unaffected. The “indirect contact” referred to in this application means that there may be one or more buffer layers between the upper surface of the first region 91 and the semiconductor layer 100, but the first dopant can still pass through the buffer layer and enter the first region 91. Therefore, after step f, the conductivity type of the first region 91 of the first semiconductor structure 90 will be changed, which will be the same as the conductivity type of the second reflector 70, and the conductivity of the second region 92 of the first semiconductor structure 90 will be changed. The shape is still different from the conductive shape of the second mirror 70. Specifically, after step e, the conductive type of the first region 91 of the first semiconductor structure 90 is the same as the conductive type of the second mirror 70, and the conductive type of the first region 91 is different from that of the second region 92. Conductive type. For example, after step e, the conductivity type of the second reflector 70 is p-type, and the conductivity type of the first region 91 of the first semiconductor structure 90 is p-type. The conductive type is n-type. For another example, the conductivity type of the second reflector 70 is n-type, and the conductivity type of the first region 91 of the first semiconductor structure 90 is n-type, but the conductivity type of the second region 92 of the first semiconductor structure 90 is p-type.

In an embodiment, in step d, the semiconductor layer 100 is formed on the first semiconductor structure 90 at a first temperature. Preferably, the first temperature is not lower than 550 ° C and not higher than 700 ° C, and more preferably, the first temperature is not lower than 580 ° C and not higher than 670 ° C.

In an embodiment, the first dopant of the patterned semiconductor layer 100 enters the first region 91 of the first semiconductor structure 90 by being heated to operate at a second temperature, and the second temperature is lower than that of forming the semiconductor layer. First temperature of 100. Preferably, the difference between the first temperature and the second temperature is not more than 50 ° C, and not less than 5 ° C, and more preferably, not more than 30 ° C. Specifically, the method of heat treatment includes, but is not limited to, placing the structure formed in step e into a furnace tube for heat treatment, or placing the structure formed in step d into an organometallic chemical vapor deposition (Metalorganic Chemical Vapor Phase Deposition; MOCVD) is performed in the chamber of the machine.

In one embodiment, the light emitting structure may further include a spacer layer (not shown) located between the active region and the first conductive type semiconductor layer and / or between the active region and the second conductive type semiconductor layer to adjust light emission. The thickness of the structure is substantially close to or equal to a thickness of nλ / 2, where λ is the peak wavelength of the radiation emitted by the active region, and n is a positive integer. The material of the spacer layer is a semiconductor material including Group 1-3 semiconductors, such as aluminum gallium arsenide (AlGaAs).

FIG. 5 is an example of a semiconductor device manufactured by the methods of FIGS. 3A to 3G. When the laser light emitting element is driven as shown in FIG. 5, since the conductive type of the first region 91 of the first semiconductor structure 90 is the same as that of the second reflector 70 and the third reflector 90 located on both sides of the first semiconductor structure 90, respectively. The conductive type of the reflective mirror 110, and the conductive type of the second region 92 of the first semiconductor structure 90 is different from the conductive types of the second reflective mirror 70 and the third reflective mirror 110 located on both sides of the first semiconductor structure 90, respectively. Therefore, the current will be restricted by the second region 92 of the first semiconductor structure 90 and cannot pass through, and further concentrated to pass through the first region 91 of the first semiconductor structure 90 and flow into the light emitting structure 80. In other words, the first semiconductor structure 90 can be used as a current limiting structure in this embodiment to allow a current to pass through the predetermined first region 91.

The first reflecting mirror 60, the second reflecting mirror 70, and the third reflecting mirror 110 respectively include a plurality of alternating first refractive index semiconductor layers (not shown) and second refractive index semiconductor layers (not shown). The semiconductor layer has a first refractive index and the second refractive index. The semiconductor layer has a second refractive index, wherein the first refractive index is higher than the second refractive index. The material of the first mirror 60, the second mirror 70, and the third mirror 110 includes a group _1-3 semiconductor material, such as aluminum gallium arsenide Al _x Ga _(1-x) As / Al _y Ga _(1-y) As, where x is not equal to y, and the content of aluminum and gallium can be adjusted to reflect a wavelength range to be reflected. The first refractive index semiconductor layer and the second refractive index semiconductor layer have a thickness close to or equal to λ / 4n, where λ is a peak wavelength of radiation emitted by the active region 22, and n is a refractive index of the layer. The first mirror 60 has a reflectance of more than 99% at a peak wavelength. The second mirror 70 and the third mirror 110 have a reflectance of more than 98% at a peak wavelength. Preferably, for the peak wavelength, the reflectance of the first mirror 60 is greater than the reflectance of the second mirror 70 and the third mirror 110. The number of pairs of the first reflector 60 is greater than the sum of the number of pairs of the second reflector 70 and the third reflector 110, wherein a first refractive index semiconductor layer and a second refractive index semiconductor layer adjacent to the first refractive index semiconductor layer are regarded as A pair. In one embodiment, preferably, the logarithm of the first mirror 60 is greater than 15, and more preferably, greater than 30 and less than 80. In one embodiment, preferably, the sum of the logarithms of the second mirror 70 and the third mirror 110 is greater than 15, and more preferably, greater than 20 and less than 80.

In one embodiment, the first semiconductor structure 90 and the semiconductor layer 100 include three or five group semiconductor materials, such as aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), gallium phosphorous arsenide (GaAsP), InGaN ( Indium gallium nitride) or AlGaN (aluminum gallium nitride). In one embodiment, the first semiconductor structure 90 includes aluminum gallium indium phosphide (AlGaInP), and the semiconductor layer 100 includes aluminum gallium arsenide (AlGaAs). More preferably, in an embodiment, the first semiconductor structure 90 includes (Al _y Ga _(1-y) ) _1-x In _x P, where 0.4 ≦ x ≦ 1 and 0 ≦ y ≦ 1. In still another embodiment, the first semiconductor structure 90 includes (Al _y Ga _(1-y) ) _1-x In _x P, where 0.49 ≦ x ≦ 0.51 and 0 ≦ y ≦ 0.6. In one embodiment, the first dopant in the semiconductor layer 100 is zinc (Zn). In one embodiment, the first semiconductor structure 90 has a thickness close to or equal to λ / 4n, where λ is the peak wavelength of the radiation emitted by the active region 22, and n is the refractive index of the layer. In one embodiment, the first semiconductor structure 90 may replace one of the first refractive index semiconductor layer or the second refractive index semiconductor layer of the second reflector 70 or the third reflector 110.

In one embodiment, the first refractive index semiconductor layer in one pair of the second reflecting mirrors 70 is an aluminum-containing semiconductor layer, and the aluminum content thereof is compared to that of the aluminum in the first refractive index semiconductor layer in the other pairs. High content. Preferably, the aluminum-containing semiconductor layer includes Al _x Ga _(1-x) As, where 0.9 ≦ x ≦ 1.0. In this embodiment, before step j, the method for manufacturing a semiconductor light-emitting element further includes oxidizing an aluminum-containing semiconductor layer, so that the outermost and exposed part of the aluminum-containing semiconductor layer begins to oxidize, and gradually oxidize to the inside to make aluminum The semiconductor layer includes an unoxidized semiconductor portion and an oxide portion surrounding the semiconductor portion. The material of the oxide part includes alumina, and its chemical formula is Al _a O _b , where a and b are natural numbers other than 0. Specifically, the oxidation method includes a wet thermal oxidation method. When the laser light emitting element of this embodiment is driven, since the conductivity type of the first region 92 of the first semiconductor structure 90 is the same as that of the second reflector 70 and the third reflector 110 on both sides, The conductive type of the second region 92 of the first semiconductor structure 90 is different from the conductive types of the second and third mirrors 70 and 110 on both sides. Therefore, a current is passed through the second region 92 of the first semiconductor structure 90. It is restricted and cannot pass, and then enters the second reflecting mirror 70 through the first region 91 of the first semiconductor structure 90. Further, since the oxide portion is an insulating material, the current that enters the second reflecting mirror 70 is restricted by the oxide portion and cannot pass through, and further passes through the semiconductor portion in the aluminum-containing semiconductor layer to enter the light emitting structure 80. In other words, the first semiconductor structure 90 can be used as a current limiting structure in this embodiment to allow a current to pass through the predetermined first region 91.

In an embodiment, the first refractive index semiconductor layer of one pair of the third mirrors 110 is an aluminum-containing semiconductor layer, and the aluminum content thereof is compared with the aluminum content of the first refractive index semiconductor layer in the other pairs. high. Preferably, the aluminum-containing semiconductor layer includes Al _x Ga _(1-x) As, where 0.9 ≦ x ≦ 1.0. In this embodiment, before step j, the method for manufacturing a semiconductor light-emitting element further includes oxidizing an aluminum-containing semiconductor layer, so that the outermost and exposed part of the aluminum-containing semiconductor layer begins to oxidize, and gradually oxidize to the inside to make aluminum The semiconductor layer includes an unoxidized semiconductor portion and an oxide portion surrounding the semiconductor portion. The material of the oxide part includes alumina, and its chemical formula is Al _a O _b , where a and b are natural numbers other than 0. Specifically, the oxidation method includes a wet thermal oxidation method. When the laser light-emitting element of this embodiment is driven, since the oxide portion is an insulating material, the current that enters the third mirror 110 is restricted by the oxide portion and cannot pass through, and further passes through the semiconductor portion in the aluminum-containing semiconductor layer. And entering the first semiconductor structure 90, further, since the conductivity type of the first region 91 of the first semiconductor structure 90 is the same as that of the second reflector 70 and the third reflector 110 on both sides, the first The conductive type of the second region 92 of a semiconductor structure 90 is different from the conductive types of the second and third mirrors 70 and 110 on both sides. Therefore, the current is limited by the second region 92 of the first semiconductor structure 90. It cannot pass through, and further enters the light emitting structure 80 through the first region 91 of the first semiconductor structure 90.

The active region includes a single heterostructure (SH), a double heterostructure (DH), or a multiple quantum well (MQW). Preferably, the active region includes a multiple quantum well (MQW), which includes alternating well layers and barrier layers. The energy level of each barrier layer is greater than the energy level of one of the well layers. The peak wavelength emitted by the active region can be changed by changing the thickness or material of the well layer. Preferably, the material of the well layer includes Group 1-3 semiconductor materials, such as aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), gallium phosphide arsenide (GaAsP), or InGaN (indium gallium nitride). The material of the barrier layer includes Group III semiconductor materials, such as aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), or AlGaN (aluminum gallium nitride).

In one embodiment, the growth substrate 10 or 40 has a sufficient thickness to support a layer or structure that is grown on the substrate 10 or 40 afterwards. Preferably, the thickness of the growth substrate 10 or 40 is not less than 100 microns, and preferably not more than 250 microns. The growth substrate 10 or 40 is a single crystal and contains a semiconductor material, for example, a group III or 5 semiconductor material or a group 4 semiconductor material. In one embodiment, the growth substrate 10 or 40 includes a Group III semiconductor material having an n-type or a p-type. For example, the three or five semiconductor materials include n-type gallium arsenide (GaAs), and the n-type dopant is silicon (Si).

The first electrode 130 and the second electrode 140 are connected to an external power source and conduct a current between the two. The material of the first electrode 130 and the second electrode 140 includes a transparent conductive material or a metal material. Transparent conductive materials include transparent conductive oxides, and metallic materials include gold (Au), platinum (Pt), germanium gold nickel (GeAuNi), titanium (Ti), beryllium gold (BeAu), germanium gold (GeAu), and aluminum (Al) , Zinc gold (ZnAu) or nickel.

The first electrode 130 forms a low-resistance contact or an ohmic contact with the third reflector 110 through the semiconductor contact layer 120, wherein the resistance between the first electrode 130 and the third reflector 110 is lower than 10 ^-2 ohm-cm. The conductive type of the semiconductor contact layer 120 is the same as the conductive type of the third mirror 110. In an embodiment, the semiconductor contact layer 120 is p-type and has a high p-type doping concentration, such as higher than 1´10 ¹⁸ / cm ³ , and preferably higher than 1´10 ¹⁹ / cm ³ , and More preferably, it is between 1´10 ¹⁹ / cm ³ and 5´10 ²² / cm ³ (both included). The material of the semiconductor contact layer 120 includes one or three or five semiconductor materials, such as gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs).

The epitaxial growth method includes, but is not limited to, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), and molecular beam epitaxy (molecular beam epitaxy (MBE) or liquid-phase epitaxy (LPE).

It should be noted that the embodiments listed in this application are only used to illustrate this application, and are not intended to limit the scope of this application. Any obvious modification or change made by anyone to this application shall not depart from the spirit and scope of this application. The same or similar components in different embodiments, or the components with the same reference numerals in different embodiments have the same physical or chemical characteristics. In addition, the above-mentioned embodiments in this application may be combined or replaced with each other where appropriate, rather than being limited to the specific embodiments described. The connection relationship between the specific component and other components described in detail in one embodiment can also be applied to other embodiments, and all fall within the scope of the right protection scope of the present application as described later.

10, 40‧‧‧ Growth substrate

401, 101‧‧‧ upper surface

20‧‧‧First semiconductor layer

21, 91‧‧‧ first zone

22, 92‧‧‧ Second Zone

30‧‧‧Second semiconductor layer

50‧‧‧Epitaxial structure

60‧‧‧first mirror

70‧‧‧Second reflector

80‧‧‧light emitting structure

90‧‧‧First semiconductor structure

100‧‧‧ semiconductor layer

110‧‧‧third mirror

120‧‧‧Semiconductor contact layer

130‧‧‧first electrode

140‧‧‧Second electrode

FIG. 1A to FIG. 1D are one embodiment of a method for manufacturing a semiconductor device according to the present application;

FIG. 2 is a graph showing the relationship between the dopant concentration and the doping depth of one embodiment of a semiconductor device manufactured by using the methods shown in FIGS. 1A to 1D;

FIG. 3A to FIG. 3G are another embodiment of a method for manufacturing a semiconductor device according to the present application;

FIG. 4 is a graph showing a relationship between a first dopant concentration and a doping depth in a first semiconductor structure of an embodiment shown in FIG. 3D; and

FIG. 5 is an example of a semiconductor device manufactured by the methods of FIGS. 3A to 3G.

no.

Claims (10)

A method of manufacturing a semiconductor element includes: Providing an active area; Forming a first reflecting mirror and a second reflecting mirror, which are respectively located on both sides of the active region; Forming a first semiconductor structure including a first region and a second region; Forming a second semiconductor layer on the first semiconductor structure; Allowing a dopant to enter the first semiconductor structure; and The second semiconductor layer is completely removed. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the second semiconductor layer is formed on the first region. The method for manufacturing a semiconductor device according to item 2 of the scope of patent application, further comprising heat treatment and / or pressure treatment of the second semiconductor layer so that the dopant enters the first semiconductor structure from the second semiconductor into the first semiconductor structure. region. The method for manufacturing a semiconductor device according to item 3 of the scope of patent application, wherein the conductivity type of the first region is the same as that of the first reflector or the second reflector. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the concentration of the dopant in the first region is greater than the concentration of the dopant in the second region, and the The difference between the concentration of the dopant and the concentration of the dopant in the second region is greater than 1´10 ¹⁶ / cm ³ . The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the concentration of the dopant in the first region is greater than 1´10 ¹⁸ / cm ³ . The method for manufacturing a semiconductor device according to item 1 of the patent application scope further includes forming a third reflector on the first semiconductor structure. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the dopant comprises zinc (Zn), magnesium (Mg) or carbon (C). The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the first semiconductor structure comprises a group III-V semiconductor material. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the semiconductor device can emit non-homogeneous light with a far field angle greater than 60 degrees or coherent light with a far field angle less than 25 degrees.