TW487993B - Non-selectivity epitaxy deposition technique - Google Patents

Abstract

The present invention provides a bipolar transistor process using a non-selectivity epitaxy deposition technique to manufacturing the base. The process comprises depositing a polysilicon layer on the oxide layers and surface of the mono-crystalline silicon therebetween for use as a core-forming layer; and using photolithography and etching process to etch out an opening on the core-forming layer between the oxide layers (i.e., the opening is located above the N-buried layer). The non-selectivity epitaxy growth process is used to deposit the base of the bipolar transistor. The method can also forms a polysilicon layer at two sides of the intrinsic base for use as an extrinsic base, and the base metal electrode can be formed on the polysilicon layer. In addition, the process of manufacturing the bipolar transistor device is the same as the conventional process, including emitter polysilicon deposition, emitter polysilicon etching, dielectric layer deposition, contact etching and metal deposition and etching.

Description

487993 A7

V. Description of the Invention (j) Field of the Invention The present invention relates to the field of manufacturing process of bipolar transistor elements, and particularly relates to the fabrication of the base of the bipolar transistor elements. BACKGROUND OF THE INVENTION The development of semiconductor process technology is moving towards high-speed, low-power-consumption Very Large Scale Integration (vLSI). In order to achieve such a state, semiconductor elements must be made smaller and smaller, so In the design of the component, the junction of the vertical part (Junction) should be as shallow as possible, and the geometrical dimension of the component in the horizontal direction should be as small as possible. The junction depth of the traditional bipolar transistor is that ion implantation is used to implant ions into the stone lattice, and then the ions are activated and diffused to a certain depth by a high temperature process. The horizontal geometry of the component can be reduced by the continuous improvement of Lithography equipment, so that the parasitic effect of the component can be continuously reduced. There is a new technological development in the semiconductor manufacturing process currently being Low Temperature Epitaxy (LTE). This low-temperature epitaxial deposition process is generally performed using a chemical vapor deposition (CVD) system. Since this process cannot react at too high a temperature, in order to ensure better quality, Most will be deposited by Ultra High Vacuum Chemical Vapor Deposition System (UHV / CVD) because its deposition temperature is below 600 ° C; and because the background pressure is below 1 〇 · 1 () torr Therefore, the partial pressures of water vapor and oxygen in the reaction chamber are very low. Therefore, if the base layer of the bipolar transistor is manufactured by this process, not only the width of the base can be accurately controlled. 2 This paper size is applicable to China National Standard (CNS) A4 Specification (210 X 297 mm) (Please read the notes on the back before filling out this page) Order -------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ δ / 993 Α7 Β7 _________ 5. Description of the invention (2) and concentration, and there will be no tailing phenomenon using the ion implantation method in the past, because the width of the base can be smaller and the characteristics of the bipolar transistor element are improved, Therefore, the low temperature epitaxial deposition technology can make the bipolar transistor have a shallow junction depth, and improve the characteristics and uniformity of the device. However, the maintenance of the vacuum system, the throughput is too low (the system needs to be evacuated to 10'1 Qton: below), and the growth rate is too slow (because the growth temperature is too low) are the disadvantages of this system. Now, a selective epitaxial growth (SEG) process is developed using epitaxial growth technology. This selective epitaxial growth method uses silicon epitaxial growth technology to grow silicon worm crystals on bare silicon single crystals, but does not deposit any type on the dielectric layer of the dioxide or nitride. Silicon (single crystal, polySilicon or Amorphous). In the selective epitaxial deposition process, SiCl4 is often used as a source of silicon atoms, and the addition of hydrochloric acid (HC1) (or chlorine gas) in the reaction gas can increase the selectivity of selective deposition during growth. . The factors affecting selective deposition during the silicon epitaxial process include the surface conditions of the Shi Xi substrate, the size of the dielectric layer openings, the concentration of hydrochloric acid, the type of silicon gas source, the growth pressure and temperature. In this process, it is easy to observe some defects near the interface between the epitaxial layer and the dielectric layer. These defects include dislocation, stacking fault, and microtwins. These defects often cause electrical damage. On the issue of sex, although everyone tries very hard to reduce or even remove these defects, the final result is always unsatisfactory, and the process window is too small, which is another need for 3 paper standards for China National Standard (CNS) A4 Specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) ----- Order · ——.------. Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by Consumer Cooperatives ^ /

Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Co-operative Cooperatives, Inventions (Problems Faced. (Please read the precautions on the back before filling out this page) This invention proposes how to use non-selective deposition techniques to grow The selective epitaxial deposition process has the same results, but it has a larger process of 1¾ and can greatly reduce the above-mentioned defects. After inquiry, we have not found any relevant patent documents and the contents of the present invention. The contents of the mentioned invention are similar, and some slightly similar patent documents are specifically cited, respectively: Patent of Herbert et al. (US. 5,777, 3 50)-Method of forming a self-aligned bipolar junction transistor with silicide extrinsic base contacts and selective epitaxial grown intrinsic base, this patent proposes to use the epitaxial deposition technology to make the base layer in the process of the bipolar transistor, but the polycrystalline spar layer at the base contact (c ntact) requires It is produced separately, so it is not a self-aligned process.

The patent of Sato et al. (US5,599,723)-`` Method for manufacturing bipolar transistor having reduced b as e-collector parasitic capacitance '' This patent is the use of a photomask to make openings and the intention is to over-etch ) Method makes it generate suspension (Onerhang) at the boundary, so as to reduce the chance of silicon deposition to other areas during the deposition process.

The patent of Kimura et al. (US 5,6 1 4,425)-"Method of fabricating a bipolar transistor operable at high speed"-proposes that a silicon epitaxial crystal can be deposited in some places during the same epitaxial process, and The other part is the process technology for depositing polycrystals. The purpose and summary of the invention 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 5. Description of the invention (today) Α7 Β7 Process The subject of the present invention is to propose a legal system for making bipolar transistor elements This subject is a non-selective ... deposited square 沄 I is used as the base complex of fluorine as a bipolar transistor. Another subject is that the base metal of this process is connected to 2 cases. These topics can be used in the field oxygen The surface of eid Qxi and the silicon single crystal layer is sunk, and the silicon layer is used as a seed layer, and the technique is achieved. Then, the active device region (N +: (Above) to form the opening of the nucleation layer, and then use the non-selective epitaxial product to make the base of the bipolar transistor, so the contact area of the polycrystal can be formed on both sides of the base, and then the double Electrode production process-made by EmiUer (EmiUer, Υ emitter) engraved, Inter-layer dielectric deposited, metallized (% 6 (& 114 this 011 ) Process and so on, complete the bipolar transistor Simple illustration (please read the notes on the back before filling this page)

-· Ia-i ϋ · emmmmm t§ I 1 ^ ^ t 1_ · mi · — an fl_n ϋ · I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 1: Cross-sections before the new process proposed by the present invention Figures; Figure 2: The same structure as Figure * 1, but with the addition of a polycrystalline silicon layer as a nucleation M; Figure 3: A cross-sectional view showing the base region window made from the nucleation layer; Figure 4: Shows the use of non-nuclear layers Selective deposition method deposits the essential base layer and the size of the paper. Applicable to China National Standard (CNS) A4 (210 X 297 mm) A7

V. Description of the invention (f) A cross-sectional view after the crystal contact layer; FIG. 5: Refers to the process of the double-carrier transistor proposed in the present invention, and the final cross-sectional view thereof. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives for the detailed description of the invention The process proposed in the present invention uses a wafer as a substrate with a thickness of about 500 to 550 μηι and a resistance value of about 15-25Ω-cin, as shown in Figure 1. Shown at level 1. Then, a pattern of N + buried layer (level 2) is made on the surface of the wafer by the lithography process, and the donor ion is implanted into the crystal by ion implantation. The donor ion can be It is Shisen (Arsenic) or antimony (Antimony), the energy of ion implantation is about 65 to 10OKeV, and the ion dose used is 2 × 10ι5 to 5X1015 / cm2. After the photoresist is removed, a thermal annealing process is performed, and the thermal annealing temperature is about 1150 to 1250. C, annealing time is 50-100 minutes. Immediately after the Acceptor ion (generally boron ion) is implanted into the silicon wafer (the pattern is also made by lithography, which is not shown in the figure), the implanted energy is about 30 to 80 KeV, And the implanted dose is about ιχιο13 to lX1014 / cm2 to form a p-buried layer (level 3), the depth of this p-buried layer is about the same as the depth of the N-buried layer, and then between 850 and 950. The heat treatment is performed in the furnace tube of C, and the heat treatment time is about 40 to 100 minutes. Once both the P buried layer and the N buried layer have been fabricated, then a silicon epitaxial layer is formed by chemical vapor deposition. The deposition temperature is between about 1000 and 1200 ° C. About 0 to ι. 2 μιη. The 6 paper sizes used are in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm). Guang |: 1 "|| .— ^ ____________ (Please read the notes on the back before filling this page) Order—— 、、 ------ A7

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (The gas source includes SiHCl3, SiH2Cl2, PH3, H2 and HC1. The resistance of this Shi Xilei crystal layer is about 0.4 to 0.6 Ω-cm. Receptor ions (generally deleted ions) are then implanted by ion implantation to form a P-well region (P-weU). The implantation energy is about 150 to nOKeV, and the implantation dose is about 1X1013 / cm2, this p-type well area (level 4) uses these ions to diffuse down, and boron ions in the P-buried layer area (level 3) diffuse up and then join together to form a P-type well area. Then, the traditional LOCOS (Local oxidation of silicon) process is used to produce a field oxide layer (level 5) on the silicon wafer. At this time, the cross-sectional view of the structure is shown in Figure 1. Referring to FIG. 2, this step is a key part of the present invention. This process is to deposit a polycrystalline layer on a silicon wafer. The polycrystalline layer can be used as a nucleation layer, and the polycrystalline layer can also be amorphous silicon. Layer, the thickness of this layer is between about 450 and 550 angstroms. If polycrystalline silicon is used as the nucleation layer, SiH4 and Ar are used as the main gases, and the pressure is 62 (TC at 0.222torr). Deposition; if amorphous silicon is used as the nucleation layer, SiH4 and Ar are used as the main gases, and the cross-sectional view of the structure at this time is deposited at a temperature of 560 ° C, as shown in Figure 2. Refer to Figure 3, After a standard lithography process, the nucleation layer uses dry etching to etch an opening 37 in the nucleation layer (level 6). This opening is between the field oxide layer, that is, in the N + buried layer. Above (level 2), after this step, single crystal silicon will be exposed in the open area on the surface of the wafer (level 8). Next, a silicon epitaxial deposition method is used to grow silicon on the silicon wafer. Applicable to China National Standard (CNS) A4 (210 X 297 mm) --r ---: --------------- --------- (Please read the Notes on the back to fill out Page) 487 993

Technology is also the key point in this invention. As shown in Figure 4, this layer contains two parts, one is a single crystal silicon layer 41 (located on level 8), and the other is a polycrystalline layer 47 (located on level 6 and includes level 6). The thickness of 41/47 is between 600 and 2000 Angstroms. In this process, the wafer is first immersed in the RCA bath solution for cleaning and then immersed in the HF solution for about 5-10 seconds to remove the native oxide layer on the wafer, and then these pre-processed wafers are placed in a wafer transfer chamber (Load-lock In the chamber, the wafer transfer chamber needs to be kept in the air supply atmosphere, and then the wafer is transferred to the reaction chamber in a low temperature environment. The reaction chamber needs to be evacuated to 10-3torr and maintained at Deposition temperature, this gas source can be SiH2Cl2 or SiH4, the doping gas is B2H6, the pressure during deposition is 20 tor, the growth rate is maintained at 1-1.5pm / min. Read the notes on the back and fill in this page.) The cross-sectional structure of the wafer after these processes is shown in Figure 5. First, the active layer (level 41) is the use of ion implantation to implant P-type carriers into the wafer via a photoresist pattern (BF2 ion implantation, the implantation energy is about 40-60 KeV, and the implanted dose is about 1X1013 To 5X1013 cnT2). An insulating layer 52 (having a thickness of approximately 180 to 220 Angstroms) is deposited on the wafer and an opening is etched above the emitter 51. An emitter polycrystalline layer can be deposited in this opening. Next, an intermediate dielectric layer (level 54) is deposited on the wafer. This N-type emitter (level 51) can be formed by doping the dopant ions of the emitter complex layer (level 53) down to the single crystal silicon region. This diffusion is formed. The over-conversion is performed by a rapid thermal annealing (RTP) method, and the diffusion depth is about 300 to 2000 angstroms. Then use the traditional lithography process to form a pattern on the level 54, and then etch the level 54 by dry etching to form the contact window of the emitter, base and collector, respectively. The paper size is applicable to the Chinese National Standard (CNS) A4 specification. (210 × 297ϋ) ^ Five amendments to supplement A7 B7 Description of invention () 56, 57 and 58. Then deposit a suitable metal material layer as a conductive layer, and finally make the final metal wire layer by lithography and etching. The above description is only the best embodiment of the present invention, and is not intended to limit the scope of the application of the present invention; / L equivalent changes or modifications made in the spirit of the steps shown in this document are all It should be included in the scope of patent application described below. Wu —:-(Please read the precautions on the back before filling out this page} Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs

Claims (1)

1. Patent application scope 1-A method for manufacturing a bipolar transistor element by non-selective epitaxial deposition technology, including: providing a substrate, part of the surface of the substrate is a field oxide region, and part is a single crystal silicon region Deposit a thin stone layer on the surface of the wafer, including the field oxide layer; pattern the thin silicon layer, and etch the thin silicon layer to create an opening, the opening is located between the field oxide layer; grow The second silicon epitaxial layer is on the first thin silicon layer. The second silicon epitaxial layer includes a silicon epitaxial layer on the single crystal silicon layer at the opening and a compound on the first thin silicon layer.晶 层。 Crystal layer. 2. The method for manufacturing a bipolar transistor element by non-selective epitaxial deposition technology as described in item 1 of the scope of patent application, wherein the distance between the field oxide layers is 0.3 to 0 · 8μιη 〇3. The method for manufacturing a bipolar transistor device by non-selective epitaxial deposition technology described in the first item of the patent scope, wherein the thickness of the first thin silicon layer is between 450 and 550 angstroms. Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs (please read the notes on the back before filling out this page) 4. Make bipolar transistors using non-selective epitaxial deposition technology as described in item 1 of the scope of patent application The method of the device, wherein the first thin silicon layer described above may be a polycrystalline silicon layer. 5. The method for producing a bipolar transistor element by non-selective epitaxial deposition technology as described in item 4 of the scope of patent application, wherein the above-mentioned first thin silicon layer deposition process 10 paper standards are applicable to Chinese national standards (CNS ) Α4 size (210X 297 public directors) Printed by the Consumers' Cooperatives of the Ministry of Economic Affairs and Standards Bureau of the People's Republic of China 487993 A8 B8 C8 D8 6. The scope of patent application includes the use of chemical vapor deposition with SiH4 and Ar as the main gas sources. The deposition temperature is 600 to 640 QC, and the deposition pressure is 0.2 to 0.24 torr. 6. The method for producing a bipolar transistor element by non-selective epitaxial deposition technology as described in item 1 of the scope of patent application, wherein the first thin silicon layer may be amorphous 7. As described in item 6 of the scope of patent application Method for making bipolar transistor elements by non-selective epitaxial deposition technology, in which the above-mentioned first thin silicon layer can be deposited by chemical vapor deposition using SiH4 * Ar as the main gas source at a deposition temperature of 540 To 580QC. 8. The method for manufacturing a bipolar transistor device by using a non-selective epitaxial deposition technique as described in item 1 of the scope of patent application, wherein the thickness of the second silicon epitaxial layer is between 600 and 2000 angstroms. 9. The method for fabricating a bipolar transistor element by non-selective epitaxial deposition technology as described in item 1 of the scope of patent application, wherein the second silicon epitaxial layer can be fabricated by chemical vapor deposition method, using SiH2Cl2 and SiH4 is used as a gas source with a deposition pressure of 18 to 22 torr. 10. A process for making a bipolar transistor device, the process includes: providing a P-type silicon wafer as a substrate; using a lithography process to make a pattern of an N + buried layer on a specific area on the wafer, and using an ion implantation method to The donor ion is implanted under the surface of the wafer to form an N + buried layer; the silicon wafer is heated to diffuse the donor ion of the N + buried layer; 11 This paper size is applicable to China National Standard (CNS) A4 (210X 297 mm) (Please read the precautions on the back before filling out this page) Order WI. Α8 Β8 __ C8-· -------- 08, scope of patent application 1 ~-*-Please read the back first 5 ί The matter is refilled. This page uses a lithography process to make a pattern of the ρ + buried layer in a specific area on the wafer. The ion implantation method is used to implant the acceptor ions under the surface of the silicon wafer to form a ρ + buried layer. The depth of the N + buried layer is about the same as the depth of the N + buried layer. The silicon θθ sheet is heated to diffuse the ions of the P + buried layer. On the surface of the wafer; Receptor ions are implanted by the implantation method. The acceptor ions will diffuse downward at high temperatures, and the ions of the P + buried layer will diffuse upward to form a p-type well area; a field oxide layer is formed on the p-type well area; A second thin silicon layer is deposited on the silicon wafer; the lithography technique is used to make @samples on the second thin silicon layer, and the second thin silicon layer is etched on the N + buried layer in a lithographic manner, < Formation of officials An opening; π-product a second thin silicon layer, the third thin silicon layer includes a single crystal silicon formed on the opening, and a polycrystalline silicon layer is formed on the second thin silicon layer; η on the third thin silicon The pattern is created on the layer by lithography technology, and then the ion is implanted into the acceptor ion through the photoresist pattern to form the base layer; an insulating layer is deposited on the wafer; the staff of the Central Standards Bureau of the Ministry of Economic Affairs The consumer cooperative prints a pattern on the insulating layer using a lithography process, and etches this insulating layer to form a film I, and then deposits polycrystalline stone on the wafer, and then implants donor ions by ion implantation. And use the lithography and etching process to produce an emitter polycrystalline silicon layer Depositing an intermediate dielectric layer on silicon chips; The Ministry of Economic Affairs, China Bureau of Standards and Labor, Consumer Cooperatives printed the use of «and ㈣ dielectric layers to form contact windows for the emitter, base, and collector, and deposited metal layers on the Shi Xi wafer, and then used lithography and The metal wire of the bipolar transistor element is formed on the Shi Xi wafer in a free-cut manner. The process for making a bipolar transistor device according to item 1G of the Shenyue patent, wherein the thickness of the second thin stone layer is MO to MO angstrom. For example, the manufacturing process for manufacturing a bipolar transistor device described in item 1G of the patent scope, wherein the second thin silicon layer described above may be polycrystalline silicon. 13. The method for manufacturing a bipolar transistor device according to item 12 of the scope of the patent application, in which the second thin stone layer can be deposited by chemical vapor deposition method using SiH ^ Ar as the main gas source. The deposition temperature is 600 to 64 ° (^, the deposition pressure is 0.2 to 0.24 ton *). The manufacturing of a bipolar transistor device as described in item 1 () of the patent application scope, wherein The second thin silicon layer may be amorphous silicon. 15. The manufacturing method of producing a bipolar transistor device as described in item 14 of the patent application scope, wherein the above-mentioned second thin stone layer may be made of chemistry. The vapor deposition method uses • 4 spears Ar as the main gas source, and the deposition temperature is between 5 cents and $ 80. 匸. 16. The manufacturing of bipolar transistor elements as described in item 1G of the patent application scope, ^ The thickness of the above-mentioned second thin silicon layer may be between 600 and 2000 angstroms. 17. According to the scope of the application for patent, the process of making a bipolar transistor device described in the above 10, wherein the above-mentioned third thin stone layer Can be made using chemical vapor deposition to ____ 13 [paper . Otsuka Standard (CNS) A4 billion > < 297 public ^ (Please read the Notes on the back to fill out this page) 487993 A8 B8 C8 D8 Scope of patent application SiH2Cl2 and SiH4 are used as gas sources, and the deposition pressure is 18 to 22 toir. 18. The process for manufacturing a bipolar transistor device according to item 10 of the scope of the patent application, wherein the thickness of the base layer is about 800 to 4000 Angstroms. 19. The process for manufacturing a bipolar transistor device according to item 10 of the scope of patent application, wherein the thickness of the above-mentioned emitter complex layer is between 2000 and 4000 Angstroms. 20. The process for making a bipolar transistor device as described in item 10 of the scope of the patent application, wherein the above-mentioned emitter junction depth is about 300 to 2000 angstroms, and the thickness of the underlying insulating layer is about 180 to 220 angstroms. (Please read the notes on the back before filling in this I) Order Printed by the Consumers' Cooperative of the China Standards Bureau of the Ministry of Economic Affairs 14 This paper size applies to China National Standard (CNS) A4 (210X297 mm)