TW201932952A - Electrical connection structure and method for making same, TFT array substrate and method for making same - Google Patents

Abstract

A method for making an electrical connection structure includes: providing a substrate and forming a mating layer on the substrate, the mating layer being a stack of alternating niobium oxide films and silicon oxide films; forming a connection pad and a connection lines electrically connecting the connection pad, both the connection pad and the connection line are made of metal; forming an insulating coating layer covering the connection line; and exposing the insulating coating layer. The present invention also provides an electrical connection structure, a TFT array substrate and a manufacturing method thereof. The present invention can effectively reduce the light reflected by the metal layer in the insulating coating layer during exposure by providing the matching layer on the substrate so as to prevent the insulating coating layer from being overexposed and obtain a flat insulating coating layer.

Description

Electrical connection structure and manufacturing method thereof, TFT array substrate and preparation method thereof

The present invention relates to a method of fabricating an electrical connection structure, a method of fabricating a thin film transistor (TFT) array substrate, and an electrical connection structure and a TFT array substrate produced by the above method.

The liquid crystal display panel generally includes a TFT array substrate, a counter substrate, and a liquid crystal layer interposed between the TFT array substrate and the opposite substrate, and controls the rotation of the liquid crystal molecules in the liquid crystal layer to control the throughput of the light. In turn, the screen display is realized. The TFT array substrate includes structures such as a thin film transistor, a storage capacitor, and a connection pad, a connection line, and the like located around the periphery of the TFT array substrate. After the above structure is formed, an insulating cover layer covering the above structure is usually formed, for example, a planarization layer is formed, and the insulating cover layer is exposed. However, exposure of the insulating cover layer tends to make the surface of the insulating cover layer uneven, which affects the stability of the TFT array substrate.

In view of the above, it is necessary to provide a method for fabricating an electrical connection structure, comprising: providing a substrate on which a bonding layer is formed, the bonding layer being a laminate of alternating arrangement of a hafnium oxide film and a hafnium oxide film; Forming a connection pad and a connection line electrically connected to each other on the bonding layer, the connection pad and the connection line are both metal layers; forming an insulating cover layer covering the connection line; and exposing the insulation cover layer.

It is also necessary to provide a method of fabricating an array substrate, comprising: providing a substrate on which a bonding layer is formed, the bonding layer being a laminate in which yttrium oxide film and yttrium oxide film are alternately arranged; on the bonding layer Forming a thin film transistor, the thin film transistor comprising a source, a drain, a channel layer and a gate, wherein the source, the drain and the gate are both metal layers; forming an insulating coating covering the thin film transistor; And exposing the insulating cover layer by a mask.

An electrical connection structure comprising a substrate, a mating layer formed on the substrate, a connection pad and a connecting line electrically connected to each other on the mating layer, and a cover layer and the connecting line In the insulating cover layer, the connection pad and the connecting line are both metal layers, and the matching layer is a stack of alternating arrangement of a ruthenium oxide film and a ruthenium oxide film.

A TFT array substrate comprising a substrate, a bonding layer formed on the substrate, a thin film transistor formed on the bonding layer, and an insulating coating layer covering the thin film transistor, the thin film transistor including a source The pole, the drain, the channel layer and the gate, the source, the drain and the gate are both metal layers, and the mating layer is a stack of alternating arrangement of a ruthenium oxide film and a ruthenium oxide film.

Compared with the prior art, the method for fabricating the electrical connection structure and the array substrate provided by the embodiment of the present invention can effectively reduce the light reflected from the metal layer into the insulating cover layer during exposure due to the provision of the matching layer on the substrate, so as to cover the insulation. The layer is not easily overexposed, resulting in a flat insulating cover.

In the formation process of the array substrate in the liquid crystal display, an insulating coating layer, such as a passivation layer, is often formed on the electrical connection structure on the array substrate, and then the insulating cover layer is exposed to open a hole in the insulating cover layer. Or bleaching the insulating cover layer. However, exposure of the insulating cover layer in the prior art tends to make the surface of the insulating cover layer uneven. The inventors of the present invention have found that the reason for causing the insulating cover layer to be uneven is mainly that the electrical connection structure formed by the metal layer reflects the exposed light to the insulating cover layer when the insulating cover layer is exposed. The insulating cover layer is subjected to double exposure, so that the surface of the insulating cover layer facing the metal layer is uneven.

Therefore, in a specific embodiment of the present invention, the metal layer such as the electrical connection structure is reduced in reflection of light by providing a matching layer, and the insulating cover layer is prevented from being damaged by excessive exposure, thereby obtaining a flat insulating cover layer. The following is a detailed description.

Please refer to FIG. 1 , which is a flow chart of a method for fabricating an electrical connection structure according to an embodiment of the present invention. It should be noted that the method for fabricating the electrical connection structure of the present invention is not limited to the order of the following steps, and in other embodiments, the method for fabricating the electrical connection structure of the present embodiment may include only a part of the steps described below. , or some of the steps can be removed.

The method for fabricating the electrical connection structure provided by the specific embodiment of the present invention will be described in detail below with reference to the description of the various process steps of FIG.

Step S201, referring to FIG. 2, a substrate 100 is provided. A buffer layer 105 is formed on the substrate 100, a matching layer 106 is formed on the buffer layer 105, and a connection pad 118 is formed on the matching layer 106.

Specifically, a buffer layer 105 covering the substrate 100 is first formed on the substrate 100; then a matching layer 106 covering the buffer layer 105 is formed on the buffer layer 105; and then the matching layer 106 is A metal layer covering the bonding layer 106 is formed thereon; the metal layer is then patterned to form the connection pads 118.

In the present embodiment, the material of the substrate 100 is selected from a transparent substrate such as glass, quartz or an organic polymer. The material of the buffer layer 105 is selected from transparent insulating materials such as cerium oxide, cerium nitride, cerium oxynitride, and the like.

It can be understood that the buffer layer 105 is not necessary, and in other embodiments, the mating layer 106 can be directly formed on the substrate 100.

The mating layer 106 can be a multilayer film comprising a stack of alternating layers of yttria film and yttria film. The mating layer 106 can have a thickness of 100-1000 angstroms.

Step S202, referring to FIG. 3, an insulating layer 122 covering the matching layer 106 and the connection pad 118 is formed, and a connection pad hole 172 is formed at a position corresponding to the connection pad 118 of the insulating layer 122.

Specifically, an insulating layer 122 covering the bonding layer 106 and the connection pad 118 is first formed; then the insulating layer 122 is patterned to form a connection pad hole 172 at a position where the insulating layer 122 corresponds to the connection pad 118.

In the present embodiment, the material of the insulating layer 122 is selected from a transparent insulating material such as alumina, cerium oxide, cerium nitride, cerium oxynitride or the like.

Step S203, referring to FIG. 4, a connection line 146 is formed on the insulating layer 122. The connection line 146 is electrically connected to the connection pad 118 by the connection pad hole 172.

Specifically, a metal layer is first formed on the insulating layer 122, and the metal layer is also covered in the connection pad hole 172, and then the connection line 146 is formed by patterning the metal layer.

In the present embodiment, the material of the connecting wire 146 is selected from metals such as aluminum, titanium, molybdenum, niobium, and copper.

Through the above steps, the connection line 146 and the connection pad 118 are electrically connected via the connection pad hole 172, thereby forming an electrical connection structure. It will be understood that the electrical connection structure of the present invention is not limited to the ones listed in the present embodiment, and may include other layer structures such as other types of electrical connection structures having a semiconductor layer structure. For example, when the electrical connection structure is a TFT array substrate, the connection line 146 and the connection pad 118 can be a trace and a connection pad, respectively.

Step S204, referring to FIG. 5, an insulating cover layer 152 covering the connection line 146 and the insulating layer 122 is formed.

In the present embodiment, the material of the insulating cover layer 152 may be selected from organic materials that are often used as passivation layers, such as polycarbonate (PC) and benzocycloethylene (BCB).

Step S205, referring to FIG. 6, the insulating cover layer 152 is exposed by a mask 200 (eg, semi-transmissive). Upon illumination by the light, the insulating cover layer 152 is bleached by light, increasing the transmittance of the light, thereby forming a passivation layer.

As shown in FIG. 6, the portion of the light incident on the electrical connection structure is reflected by the connecting line 146 of the metal material, and is partially reflected by the matching layer 106, and interference between the two reflected lights is generated, thereby greatly reducing The light reflected to the insulating cover layer 152, thereby greatly reducing the double exposure of the insulating cover layer 152.

Therefore, the method for fabricating the electrical connection structure provided by the embodiment of the present invention can effectively reduce the light intensity of the corresponding position of the insulating cover layer 152 and the connecting line 146 by providing the matching layer 106, so that the insulating cover layer 152 It is not easily damaged by light, and a flat insulating cover layer 152 is obtained.

Referring to the electrical connection structure shown in FIG. 6 , the substrate 100 includes a buffer layer 105 formed on the substrate 100 , a matching layer 106 formed on the buffer layer 105 , and a matching layer 106 formed on the matching layer 106 . a connection pad 118, an insulating layer 122 formed on the bonding layer 106 and covering the connection pad 118, and a connection line formed on the insulating layer 122 and penetrating the insulating layer 122 to be connected to the connection pad 118 146. An insulating cover layer 152 formed on the insulating layer 122 and covering the connecting line 146. The connection pad 118 and the connection line 146 are both metal layers.

Please refer to FIG. 7 , which is a flowchart of a method for fabricating a TFT array substrate according to an embodiment of the present invention. It should be noted that the method for fabricating the TFT array substrate of the present invention is not limited to the order of the following steps, and in other embodiments, the method for fabricating the TFT array substrate of the present embodiment may include only a part of the steps described below. , or some of the steps can be removed. The method for fabricating the TFT array substrate provided by the specific embodiment of the present invention will be described in detail below with reference to the description of the flow steps of FIG.

Step S301, referring to FIG. 8, providing a substrate 100, forming a buffer layer 105 on the substrate 100, forming a matching layer 106 on the buffer layer 105, and forming a gate 114 and a connection pad on the matching layer 106. 118.

Specifically, a buffer layer 105 covering the substrate 100 is first formed on the substrate 100; then, a matching layer 106 covering the buffer layer 105 is formed on the buffer layer 105; and then the bonding layer is A metal layer covering the bonding layer 106 is formed on 106; the metal layer is then patterned to form the gate 114 and the connection pad 118.

In the present embodiment, the material of the substrate 100 is selected from a transparent substrate such as glass, quartz or an organic polymer. The material of the buffer layer 105 is selected from transparent insulating materials such as cerium oxide, cerium nitride, cerium oxynitride, and the like.

It can be understood that the buffer layer 105 is not necessary, and in other embodiments, the mating layer 106 can be directly formed on the substrate 100.

The mating layer 106 can be a multilayer film comprising a stack of alternating layers of yttria film and yttria film. The mating layer 106 can have a thickness of 100-1000 angstroms.

Step S302, referring to FIG. 9, forming an insulating layer 122 covering the matching layer 106, the gate 114, and the connection pad 118, and forming a channel layer 132 at a position corresponding to the gate 114 on the insulating layer 122. And connecting the pad hole 172 at a position corresponding to the connection pad 118 of the insulating layer 122 to expose the connection pad 118.

Specifically, first, an insulating layer 122 covering the bonding layer 106, the gate 114, and the connection pad 118 is formed; then, a semiconductor layer covering the insulating layer 122 is formed on the insulating layer 122; The semiconductor layer is patterned to form the channel layer 132. The position of the channel layer 132 corresponds to the position of the gate 114. While the semiconductor layer is patterned to form the channel layer 132, the insulating layer 122 is collectively patterned to form a connection pad hole 172 at a position where the insulating layer 122 corresponds to the connection pad 118.

In the present embodiment, the material of the insulating layer 122 is selected from a transparent insulating material such as alumina, cerium oxide, cerium nitride, cerium oxynitride or the like. The channel layer 132 is made of a semiconductor such as a metal oxide, an amorphous germanium or a polysilicon or the like.

Step S303, referring to FIG. 10, a source 142, a drain 144, and a connection line 146 are formed on the insulating layer 122. The source 142 and the drain 144 are disposed on the insulating layer 122 and respectively covered. The connecting line 146 is disposed on the insulating layer 122 and electrically connected to the connecting pad 118 through the connecting pad hole 172.

Specifically, a metal layer is first formed on the insulating layer 122 and the channel layer 132, and then the metal layer is patterned to form the source electrode 142, the drain 144, and the connection line 146.

In this embodiment, the material of the source 142, the drain 144, and the connecting line 146 may be selected from metals such as aluminum, titanium, molybdenum, niobium, and copper.

Through the above steps, the connection line 146 and the connection pad 118 are electrically connected via the connection pad hole 172, thereby forming an electrical connection structure.

At the same time, through the above steps, the gate 114, the source 142, the drain 144 and the channel layer 132 constitute a thin film transistor. It is to be understood that the thin film transistor of the present invention is not limited to the ones listed in the embodiment, and may be other structures such as a top gate type thin film transistor structure.

Step S304, referring to FIG. 11, an insulating cover layer 152 covering the source electrode 142, the channel layer 132, the drain 144, the connection line 146, and the insulating layer 122 is formed.

In the present embodiment, the material of the insulating cover layer 152 may be selected from organic materials that are often used as passivation layers, such as polycarbonate (PC) and benzocycloethylene (BCB).

Step S305, referring to FIG. 12, the insulating cover layer 152 is exposed by a mask 300. The mask 300 includes a first mask region 310 and a second mask region 320. The first mask region 310 corresponds to the position of the portion corresponding to the drain 144 for opening a contact hole 174 on the insulating cover layer 152, and the second mask region 320 corresponds to other regions. The light transmittance of the first mask region 310 is higher than the light transmittance of the second mask region 320 (semi-transmissive). Upon illumination by the light, the insulating cover layer 152 is bleached by light, increasing the transmittance of the light, thereby forming a passivation layer.

After the light is irradiated, the insulating cover layer 152 corresponding to the position of the first mask region 310 is irradiated most severely and can be removed by the photoresist developing solution; the insulating cover layer 152 corresponding to the position of the second mask region 320 is Light bleaching increases the transmission of light.

The portion of the light incident on the array substrate is reflected by the source 142, the drain 144, and the connecting line 146 of the metal material, and is partially reflected by the matching layer 106, and the interference between the two reflected rays is greatly increased. The light reflected to the insulating cover layer 152 is reduced, thereby greatly reducing the double exposure of the insulating cover layer 152.

Step S306, referring to FIG. 13, a pixel electrode 162 is formed on the insulating cover layer 152 to electrically connect the drain 144.

Specifically, a conductive layer is first formed on the insulating cover layer 152, and then the conductive layer is patterned to form the pixel electrode 162. The pixel electrode 162 is formed on the insulating cover layer 152 and extends into the contact hole 174 to be electrically connected to the drain 144.

Therefore, the method for fabricating the electrical connection structure provided by the embodiment of the present invention can effectively reduce the reflection of the source 142, the drain 144, and the connection line 146 into the insulating cover layer by providing the matching layer 106. The light intensity avoids overexposing the insulating cover layer 152, resulting in a flat insulating cover layer 152.

Referring to the TFT array substrate shown in FIG. 13 , the substrate 100 includes a buffer layer 105 formed on the substrate 100 , a matching layer 106 formed on the buffer layer 105 , and formed on the matching layer 106 . a gate electrode 114 and a connection pad 118 disposed at intervals, an insulating layer 122 formed on the bonding layer 106 and covering the gate electrode 114 and the connection pad, formed on the insulating layer 122 and corresponding to the gate 114 a channel layer 132, a source 142 and a drain 144 formed on the insulating layer 122 and electrically connected to both ends of the channel layer 132, respectively, formed on the insulating layer 122 and penetrating the insulating layer 122 A connection line 146 to which the connection pads 118 are connected, and an insulating cover layer 152 formed on the insulating layer 122 and covering the source 142, the channel layer 132, the drain 144, and the connection line 146. The gate 114, the source 142, the channel layer 132, and the drain 144 cooperate to form a TFT. The gate 114, the source 142, and the drain 144 are all metal layers.

The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to be limiting, and the above, the left, the right and the right directions appearing in the drawings are only for convenience of understanding, although the present invention is described in detail with reference to the preferred embodiments, A person skilled in the art should understand that the technical solutions of the present invention may be modified or equivalently substituted without departing from the spirit and scope of the technical solutions of the present invention.

100‧‧‧Substrate

105‧‧‧buffer layer

106‧‧‧Matching layer

114‧‧‧ gate

118‧‧‧Connecting mat

122‧‧‧Insulation

172‧‧‧Connecting hole

174‧‧‧Contact hole

132‧‧‧channel layer

142‧‧‧ source

144‧‧‧汲polar

152‧‧‧Insulating covering

162‧‧‧ pixel electrodes

146‧‧‧Connecting line

200, 300‧‧ ‧ mask

310‧‧‧First mask area

320‧‧‧second mask area

1 is a flow chart of a method of fabricating an electrical connection structure in accordance with a preferred embodiment of the present invention.

2 to 6 are step-by-step diagrams of the steps in Fig. 1.

FIG. 7 is a flow chart of a method for fabricating an array substrate according to a preferred embodiment of the present invention.

8 to 13 are step-by-step diagrams of the steps in Fig. 7.

Claims (10)

A manufacturing method of an electrical connection structure, comprising: providing a substrate, forming a matching layer on the substrate, wherein the matching layer is a stack of alternating arrangement of a ruthenium oxide film and a ruthenium oxide film; forming mutual electricity on the matching layer a connection pad and a connection line, the connection pad and the connection line are both metal layers; forming an insulating cover layer covering the connection line; and exposing the insulation cover layer. The method of manufacturing the electrical connection structure of claim 1, wherein: the connection pad is disposed on the mating layer, and the connecting line is disposed on the connection pad. The method of manufacturing the electrical connection structure of claim 1, wherein: an insulating layer is disposed between the matching layer and the insulating cover layer, and the insulating layer is located on the matching layer and covers the connection pad. The connecting line is disposed on the insulating layer and connected to the connection pad through the insulating layer, and the insulating cover layer is disposed on the insulating layer and covers the connecting line. The manufacturing method of the electrical connection structure according to claim 1, wherein the bonding layer has a thickness of 100 to 1000 angstroms. A manufacturing method of a TFT array substrate, comprising: providing a substrate, forming a matching layer on the substrate, wherein the matching layer is a stack of alternating arrangement of a ruthenium oxide film and a ruthenium oxide film; forming a thin film electricity on the matching layer a crystal, the thin film transistor comprising a source, a drain, a channel layer and a gate, the source, the drain and the gate being a metal layer; forming an insulating coating covering the thin film transistor; A mask is used to expose the insulating cover layer. The method of fabricating a TFT array substrate according to claim 5, wherein the mask comprises a first mask region and a second mask region, wherein a transmittance of the first mask region is greater than that of the second mask region The transmittance of the portion of the first mask region corresponding to the drain is used to open a contact hole on the insulating cover layer, and the second mask region is disposed corresponding to other regions. The method of fabricating a TFT array substrate according to claim 5, wherein: forming an electrical connection structure on the substrate while forming the thin film transistor, the electrical connection structure comprising a connection pad electrically connected to each other a connecting wire, the connecting pad and the connecting wire are both metal layers. The method of fabricating a TFT array substrate according to claim 7, wherein the connection pad is formed in the same process as the gate, and the connection line is formed in the same process as the source and the drain. An electrical connection structure comprising a substrate, a mating layer formed on the substrate, a connection pad and a connecting line electrically connected to each other on the mating layer, and a cover layer and the connecting line In the insulating cover layer, the connection pad and the connecting line are both metal layers, and the improvement is that the matching layer is a stack of alternating arrangement of a ruthenium oxide film and a ruthenium oxide film. A TFT array substrate comprising a substrate, a bonding layer formed on the substrate, a thin film transistor formed on the bonding layer, and an insulating coating layer covering the thin film transistor, the thin film transistor including a source The source, the drain layer, the gate layer and the gate are all metal layers, and the improvement is that the matching layer is a stack of alternating arrangement of a ruthenium oxide film and a ruthenium oxide film.