TW201928963A - Dynamic random access memory - Google Patents

Abstract

A dynamic random access memory including a memory cell array and a memory controller is provided. The memory cell array includes a plurality of bit lines, a plurality of word lines and a plurality of memory cells. The memory controller memory controller is coupled to the memory cells via the bit lines and the word lines. The memory controller is configured to perform a self-refresh operation on the memory cell array during a self-refresh period. Each of the bit lines includes a switch element. The memory controller controls a part of the switch elements to be conducted and a part of the switch elements not to be conducted.

Description

Dynamic random access memory

The present invention relates to a memory component, and more particularly to a dynamic random access memory (DRAM).

Due to the needs of the circuit architecture, the dynamic random access memory must perform a refresh operation at intervals to refresh the data stored in the memory cell. In general, DRAM will perform a self-refresh operation in a standby mode. However, if the self-refresh current is too high, the dynamic random access memory will generate excessive power consumption in the standby mode. In addition, the magnitude of the self-refresh current is typically dependent on the equivalent capacitance of the bit line during self-refresh. The larger the equivalent capacitance of the bit line, the larger the self-refresh current. Conversely, the smaller the equivalent capacitance of the bit line, the smaller the self-refresh current.

In order to solve the problem of excessive self-refresh current, in the prior art, the number of word lines coupled to the bit line can be reduced to reduce the equivalent capacitance of the bit line. However, this method reduces the equivalent capacitance of the bit line, but increases the area of the memory chip.

The present invention provides a dynamic random access memory having a low self-refresh current during self-refresh.

The dynamic random access memory of the present invention includes a memory cell array and a memory controller. The memory cell array includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. The memory controller is coupled to the memory cell via a bit line and a word line. The memory controller is configured to perform a self-refresh operation on the memory cell array during self-refresh. Each element line includes a switching element. The memory controller controls a part of the switching element to be turned on during self-refresh, and a part is not turned on.

In an embodiment of the invention, the switching element includes a plurality of first switching elements and a plurality of second switching elements. A bit line including the first switching element is coupled to the first sense amplifier circuit. A bit line including the second switching element is coupled to the second sense amplifier circuit. The memory controller controls the conduction state of the first switching element by using the first control signal. The memory controller controls the conduction state of the second switching element by using the second control signal.

In an embodiment of the invention, the self-refresh period includes a first period and a second period. During the first period, the memory controller controls the first switching element to be turned on, and the second switching element is not turned on. During the second period, the memory controller controls the first switching element to be non-conductive and the second switching element to be turned on.

In an embodiment of the invention, each of the switching elements includes a first end, a second end, and a control end. Each of the element lines includes a first node, a second node, a third node, and a fourth node. The first node of each bit line is coupled to the corresponding memory cell. A second node of each of the bit lines is coupled to the first end of each of the switching elements. The third node of each of the bit lines is coupled to the second end of each of the switching elements. A fourth node of each of the bit lines is coupled to a corresponding sense amplifier circuit of each of the switching elements. The control terminal of each switching element receives the control signal.

In an embodiment of the invention, the bit lines are coupled to the first number of memory cells between the first node and the second node, and coupled to the second number of nodes between the third node and the fourth node. Memory unit cell. The first quantity is equal to the second quantity.

In an embodiment of the invention, the bit lines are coupled to the first number of memory cells between the first node and the second node, and coupled to the second number of nodes between the third node and the fourth node. Memory unit cell. The first quantity is not equal to the second quantity.

The above described features and advantages of the invention will be apparent from the following description.

The invention is illustrated by the following examples, but the invention is not limited to the illustrated embodiments. Further combinations are also allowed between the embodiments.

FIG. 1 is a schematic diagram of a dynamic random access memory according to an embodiment of the invention. 2 is a schematic diagram showing the memory cell array and the sense amplifier circuit of the embodiment of FIG. 1. Referring to FIG. 1 and FIG. 2, the DRAM memory 100 of the present embodiment includes a memory controller 110, a memory cell array 120, and a sense amplifier circuit 130. The memory cell array 120 includes a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells 122. The memory controller 110 is coupled to the memory cell 122 via a bit line WL and a word line BL. In the present embodiment, the memory controller 110 is configured to perform a self-refresh operation on the memory cell array 120 during self-refresh, and the method of operation can be sufficiently taught, suggested, and implemented by the general knowledge in the art.

In the present embodiment, each bit line BL includes a switching element 210 or 220. The memory controller 110 controls a portion of the switching element 210 or 220 to be turned on during self-refresh, and a portion is not turned on. Specifically, in the present embodiment, the bit line 121 is coupled to the first sense amplifier circuit 132_1 and includes the first switching element 210. The control terminal of the first switching element 210 receives the first control signal SW0. The bit line 123 is coupled to the second sense amplifier circuit 132_2 and includes a second switching element 220. The control terminal of the second switching element 220 receives the second control signal SW1. In this embodiment, the memory controller 110 controls the conduction states of the first switching element 210 and the second switching element 220 by using the first control signal SW0 and the second control signal SW1, respectively.

FIG. 3 is a schematic diagram of a first control signal and a second control signal according to an embodiment of the invention. Referring to FIG. 1 to FIG. 3, the memory controller 110 of the present embodiment performs a self-refresh operation on the memory cell array 120 during self-refresh. In the present embodiment, the self-refresh period TSR includes the first period T1 and the second period T2. In the first period T1, the first control signal SW0 is at a high level, and the second control signal SW1 is at a low level. The memory controller 110 controls the first switching element 210 to be turned on by using the first control signal SW0, and controls the second switching element 220 to be non-conductive by using the second control signal SW1. Therefore, in the first period T1, the equivalent capacitance of the bit line 123 can be lowered. In the second period T2, the first control signal SW0 is at a low level, and the second control signal SW1 is at a high level. The memory controller 110 controls the first switching element 210 to be non-conducting by using the first control signal SW0, and controls the second switching element 220 to be turned on by using the second control signal SW1. Therefore, in the second period T2, the equivalent capacitance of the bit line 121 can be lowered.

In the present embodiment, although only the bit lines 121 and 123 and the switching elements 210 and 220 are exemplified, the operation of the remaining bit lines BL and the switching elements can be deduced by analogy. Therefore, in the present embodiment, during the self-refresh period TSR, the equivalent capacitance of the entire bit line BL can be lowered, thereby reducing the self-refresh current.

4 is a partial schematic view of the memory cell array and the sense amplifier circuit of the embodiment of FIG. 2. In this embodiment, the memory cell coupled between the first node N1 and the second node N2 of the bit line 121 is, for example, N (including a memory cell coupled to the first node N1), The memory cell coupled between the third node N3 and the fourth node N4 of the bit line 121 is, for example, M, where M and N are positive integers. In the present embodiment, the first number N is equal to the second number M. In an embodiment, the first number N and the second number M may also be unequal. The number of memory cells coupled to the bit line 123 can also be deduced by analogy.

In this embodiment, the switching elements can be divided into two groups, that is, the switching elements controlled by the first control signal SW0 (the first switching element 210) can be classified into the first group and controlled by the second control signal SW1. The switching elements (second switching element 220) can be classified as a second group. Therefore, the bit line BL can also be divided into two groups, that is, the bit line BL including the first switching element 210 and the bit line BL including the second switching element 220, but the present invention is not limited thereto. In an embodiment, the switching elements can be divided into three or more groups and controlled by three or more control signals. Therefore, during the self-refresh period, the amount of reduction in the equivalent capacitance of the bit line BL as a whole can be adjusted according to design requirements.

In summary, in an exemplary embodiment of the invention, each bit line includes a switching element. During the self-refresh, some of the switching elements are turned on, and some of the switching elements are not turned on. Therefore, the equivalent capacitance of the entire bit line can be lowered during self-refresh, thereby reducing the self-refresh current.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ Dynamic Random Access Memory

110‧‧‧ memory controller

120‧‧‧Memory cell array

130, 132_1, 132_2‧‧‧ sense amplifier circuit

122‧‧‧ memory cell

210, 220‧‧‧ Switching components

BL, 121, 123‧‧‧ bit line

WL‧‧‧ character line

SW0, SW1‧‧‧ control signals

TSR‧‧‧ self-refresh period

During T1, T2‧‧

N1, N2, N3, N4‧‧‧ nodes

FIG. 1 is a schematic diagram of a dynamic random access memory according to an embodiment of the invention. 2 is a schematic diagram showing the memory cell array and the sense amplifier circuit of the embodiment of FIG. 1. FIG. 3 is a schematic diagram of a first control signal and a second control signal according to an embodiment of the invention. 4 is a partial schematic view of the memory cell array and the sense amplifier circuit of the embodiment of FIG. 2.

Claims (6)

A dynamic random access memory comprising: a memory cell array comprising a plurality of bit lines, a plurality of word lines, and a plurality of memory cells; and a memory controller via which the bit lines are And the word lines are coupled to the memory cells, and are configured to perform a self-refresh operation on the memory cell array during a self-refresh; wherein each of the bit lines includes a switching element, and the The memory controller controls a portion of the switching elements to be turned on during the self-refresh, and a portion is not turned on. The dynamic random access memory of claim 1, wherein the switching elements comprise a plurality of first switching elements and a plurality of second switching elements, including the bit lines of the first switching elements The bit line of the second switching element is coupled to a second sense amplifier circuit, wherein the memory controller controls the first control signal by using a first control signal The on state of the first switching element, and the memory controller controls a conduction state of the second switching elements by using a second control signal. The dynamic random access memory according to claim 2, wherein the self-refresh period includes a first period and a second period, and the memory controller controls the first switching elements during the first period Turning on, the second switching elements are not turned on, and during the second period, the memory controller controls the first switching elements to be non-conductive, and the second switching elements are turned on. The dynamic random access memory according to claim 1, wherein each of the switching elements includes a first end, a second end, and a control end, each of the bit lines including a first node, a first a second node, a third node, and a fourth node, wherein the first node of each bit line is coupled to the corresponding memory cell, and the second node of each bit line is coupled to each of the switches The third end of each of the bit lines is coupled to the second end of each of the switching elements, and the fourth node of each of the bit lines is coupled to a corresponding sense amplifier circuit And the control terminal of each of the switching elements receives a control signal. The dynamic random access memory according to claim 4, wherein a first number of the memory cells are coupled between the first node and the second node of the bit line, A second number of the memory cells are coupled between the third node and the fourth node of the bit line, the first quantity being equal to the second quantity. The dynamic random access memory according to claim 4, wherein a first number of the memory cells are coupled between the first node and the second node of the bit line, A second number of the memory cells are coupled between the third node and the fourth node of the bit line, and the first number is not equal to the second number.