TW201926879A - Soft-switching power inversion or rectifier circuits - Google Patents

Abstract

The present invention is to provide a soft-switching power inversion circuits, wherein the inversion circuit is connected in parallel to an input DC voltage source, a middle network, and a clamping capacitor. The middle network includes a top block, a first switch-pair block, a middle block, a second switch-pair block and a bottom block and at least one transformer series-connected vertically. Both the first switch-pair block and the second switch-pair block include at least one switch-pair. Wherein three combinations of the middle block can be applied so that the semiconducting switches therein can be soft-switched alternately to reduce the switching loss. Moreover, the inversion circuit can be modified by adding more switch-pair in both the first switch-pair block and the second switch-pair block to reduce the voltage stress on the semiconductor switch. Consequently, low voltage rating semiconductor switch accompanied with lower RDS(on), conduction losses can be reduced to improve the converter efficiency. Similar topologies may be used to achieve soft-switching low output-current ripple for rectification instead of inversion.

Description

Inverter or rectifier circuit with soft switching

The invention relates to a power inversion or rectification circuit, in particular to a power switching or rectifying circuit with soft switching, in order to reduce the semiconductor switch due to the soft switching performance during the working switching period. (Semiconductor switch) exchange loss at the moment of instant or disconnection to effectively improve the efficiency of power conversion.

According to the DC-DC conversion circuit widely used in many electrical devices, there is an inverter circuit and a rectifier circuit, wherein the inverter circuit is always flowing. The voltage is inverted into an AC voltage, and the AC voltage is converted into a DC voltage through the rectifier circuit and a filter circuit to provide different DC levels required by the power device.

In general, many conventional DC-DC conversion circuits include topology circuits such as half-bridge, push-pull, and full-bridge, and such conventional conversions The circuit has the aforementioned inverter function, and the most widely used user is a Full-Bridge Converter (FBC), which is a buck-derived conversion circuit (Buck-derived), and its inverter circuit The input current has the disadvantage of a pulsating waveform, and often generates a relatively high noise due to the instantaneous current change (di/dt), and is accompanied by another kind of noise generated by the instantaneous voltage change (dv/dt). Electromagnetic interference (EMI) problems. Therefore, in such conventional conversion circuits, it is necessary to install an EMI filter to comply with the requirements of the electromagnetic interference specification, which not only increases the cost of the conventional conversion circuits, but also increases The space required for such conventional conversion circuits. In view of this, in order to reduce the noise generated by current chopping and instantaneous current fluctuation rate, the two groups of the same inverter circuit are widely interleaved and time-division work, however, this interleaved time-sharing operation is adopted. In addition to increasing the complexity and production cost of the circuit, the architects need to consider the inverter circuits because current ripple is reduced or eliminated. Depending on the duty cycle of each switch, if the duty cycle of the switches is less than 50%, the aforementioned electromagnetic interference (EMI) problem cannot be effectively alleviated.

In view of the foregoing problems, the inventors of the present invention have successively proposed several related inverter circuits capable of reducing current chopping, and have been granted patents, such as the US Patent No. 7,515,439 approved on April 7, 2009, US Patent No. 7,957,161 granted on June 7, 2011, US Patent No. 8,259,469 approved on September 4, 2012, US Patent No. 8,665,616 granted on March 4, 2014, October 2016 US Patent No. 9,473,045, which was approved on the 18th, and the protector claimed in Figure 2(c) and Figure 3(a) of US Patent No. 7,515,439, is a full-bridge inverter circuit with low input current chopping (below) Referred to as FBC-CRR), the full-bridge inverter circuit can effectively reduce the chopping of the input current, so only a small anti-electromagnetic interference filter is needed, which can meet the requirements of the specification.

However, because the aforementioned FBC-CRR system uses a symmetric pulse width modulation mechanism to regulate the output voltage, although it can obtain a stable output voltage under different input voltages and working loads, it will still be generated. Different dead time causes the semiconductor switch to operate in a hard switching state, and has a higher turn-on switching losses, which is proportional to the operating frequency. Therefore, the operating frequency of the full-bridge inverter circuit is limited, so that the inductive component value (such as inductance value or capacitance value) in the inverter circuit cannot be effectively reduced, thereby causing the full-bridge inverter circuit to be improved. The power density performance cannot be effectively achieved.

In order to enable the above-mentioned full-bridge inverter circuit to operate at a higher operating frequency, the inventors have, after many experiments and tests, believe that zero voltage switch (ZVS) using soft switching technology should be the only and necessary solution. Therefore, the high power density performance of the inverter circuit can be effectively realized without sacrificing the efficiency of the inverter circuit, which is an important subject to be discussed herein.

In view of the problems and shortcomings of the conventional inverter circuit described above, the inventors finally developed and designed the inverter circuit or rectifier circuit with soft switching according to years of practical experience and research experiments, in order to convert the circuit in power inverter (or rectification). In the process, the switching losses can be effectively reduced, and the overall performance can be effectively improved.

Another object of the present invention is to enable a leakage inductance and a parasitic capacitor to be a lossless snubber during power inversion (or rectification). The energy of the leakage inductance is effectively recycled and is used to effectively improve overall performance.

Still another object of the present invention is to use a semiconductor switch having a low on-resistance (Rdson) low voltage rating, or to use a low forward direction because the circuit can reduce the low voltage rating. Forward voltage drop Rectifier diodes of low voltage specifications to effectively reduce conduction losses and improve efficiency.

Accordingly, how to make the circuit made by a simple circuit design can effectively improve the efficiency of the circuit, which is the technical focus of the present invention.

For your convenience, the review committee can make a further understanding and understanding of the purpose, structure and efficacy of the present invention. The embodiments are described in conjunction with the drawings, which are described in detail as follows:

[study]

no

〔this invention〕

Z1‧‧‧Upper box

Z2‧‧‧ middle layer

Z3‧‧‧lower square

Z4n‧‧‧Clamping Network

Vin‧‧‧Input voltage

C1, Cr, Co1, Co2‧‧‧ capacitors

Switch-pair 1...switch-pair n‧‧‧switch to square

Switch-cell 1...switch-cell n‧‧‧switch pair unit

Q11, Q12, Q21, Q22, Q31, Q32, Qn1, Qn2, Qn3, Qn4‧‧‧ switch

Lr, Lr1, Lr2‧‧‧ inductance

T1, T2‧‧‧ transformer

P1, P2‧‧‧ primary winding

S1, S2‧‧‧ secondary winding

Ro‧‧‧ load

1(a) to 1(b), showing a first embodiment of the present invention, a DC-AC inverter circuit with a single transformer, a soft switching, and a multi-switch, and a mid-layer block circuit thereof Schematic diagram; shown in Figures 2(a) to 2(b), is a first embodiment of the present invention, a DC-AC inverter circuit with a double transformer, a soft switching, and a multi-switch, and a middle layer thereof Schematic diagram of the circuit; FIG. 3 is an inverter circuit diagram realized by a short circuit in the middle block circuit in the embodiment shown in FIG. 1(a); FIG. 4 is a view showing the embodiment shown in FIG. The switching circuit diagram of the switch pair, using the MOSFET to achieve the inverter circuit diagram; the fifth (a) ~ 5 (d) diagram, is the equivalent circuit diagram of the inverter circuit in the steady state operation shown in Figure 4; In Fig. 6, the inverter circuit shown in Fig. 4 is controlled by phase shift modulation, and the array operation waveform generated by the computer simulation software Simplis is shown in Fig. 7(a)~7(b). , comparing the input current Iin waveform of the traditional full bridge circuit with the inverter circuit shown in Fig. 3; As shown in FIG. 8, the middle layer block circuit realizes the inverter circuit of FIG. 1 by using a resonant inductor in series with a resonant capacitor; and in FIG. 9, the middle layer block circuit uses a resonant capacitor to realize the first figure. Inverter circuit; Figure 10 is the switch circuit diagram of the switch pair of the inverter circuit shown in Figure 9; the inverter circuit diagram realized by MOSFET; Figure 11(a)~11(d) is shown in Figure 10 The equivalent circuit diagram of each stage of the inverter circuit under steady state operation; shown in Fig. 12, the inverter circuit shown in Fig. 10 is controlled by variable frequency to control the array working waveform generated by the computer simulation software Simplis. Figure 13 is a schematic diagram of the inverter circuit of Figure 1 with a clamped network; Figure 14 is a schematic diagram of the inverter circuit of Figure 2 with a clamped network; The fly-through capacitor technique is used to realize the clamp network diagram of the inverter circuit of Fig. 13; the 16th figure shows the inverse of the 13th map by the diode clamping technique. Schematic diagram of the clamped network of the variable circuit; as shown in Figure 17, a resonant capacitor is used The application example of the inverter circuit diagram of Fig. 13 is realized by the flying over capacitor clamping technology; the 18th figure is the switching circuit diagram of the switching pair of the inverter circuit shown in Fig. 17, using the MOSFET to realize the inverter circuit diagram; The figure shows a second embodiment of the present invention, a schematic diagram of an AC-DC rectifier circuit with a single transformer, a soft switching, and a multi-switch; and a second embodiment of the present invention shown in FIG. Schematic diagram of an AC-DC rectification circuit with dual transformers, soft switching, and multi-switch; Figure 21 shows the AC-DC (AC-DC) of Figure 19 using a flying capacitor clamping technique. Schematic diagram of the rectifier circuit; Figure 22 shows a schematic diagram of the AC-DC rectifier circuit of Figure 20 using the overcapacity clamp technique; as shown in Figures 23(a) to 23(c), 21 and 22 of the second embodiment of the present invention As shown in the rectifier circuit diagram, one of the upper layer blocks Z1, one middle layer block Z2, the lower layer block Z3, and the clamp network Z4n is implemented in the middle layer network; and the rectifier circuit diagram shown in Fig. 19 is shown in Fig. 24. One of the first series of the upper layer block Z1, the middle layer block Z2, and the lower layer block Z3 is implemented in one of the middle layers shown in the middle layer network; and the switching circuit of the rectifier circuit shown in Fig. 24 is shown in Fig. 25. The switch, the inverter circuit diagram realized by the rectifying diode; FIG. 26 is the inverter circuit diagram of the switch pair of the rectifier circuit shown in FIG. 24, and the inverter circuit diagram realized by the MOSFET; In the rectification circuit diagram shown in the figure, the upper layer of the middle layer network Z1, the middle layer block Z2, and the second layer of the lower layer block Z3 are implemented in an application example; and in the figure 28, the switch of the rectifier circuit shown in Fig. 27 is shown. For the switch, the inverter circuit diagram realized by the rectifier diode is used; FIG. 29 is the switch circuit diagram of the switch pair of the rectifier circuit shown in FIG. 27, and the inverter circuit diagram realized by the MOSFET; The middle layer network shown in the rectification circuit diagram in Figure 19 One of the third series of the upper layer Z1, the middle layer Z2, and the lower layer Z3 is applied; and the third embodiment is shown in Fig. 30, which is the switch of the rectifier circuit shown in Fig. 30, using a rectifying diode The inverter circuit diagram realized by the body; FIG. 32 is the inverter circuit diagram of the switch pair of the rectifier circuit shown in FIG. 30, and the inverter circuit diagram realized by the MOSFET; FIG. 33(a)~(d), The equivalent circuit diagram of each stage of the rectifier circuit shown in Fig. 31 is shown in Fig. 34. The rectifier circuit shown in Fig. 31 is controlled by phase shift modulation, which is generated by the computer simulation software Simplis. Array working waveform diagram; FIG. 35 is a schematic diagram of an AC-DC double-voltage rectification circuit with a single transformer, soft switching, and multi-switch according to a third embodiment of the present invention; According to a third embodiment of the present invention, a schematic diagram of an AC-DC bipolar voltage rectification circuit with dual transformers, soft switching, and multiple switches is shown in FIG. 37, which is implemented by using a flying capacitor clamping technique. 35 Figure AC-DC (AC- DC) double-voltage rectifier circuit schematic; Figure 38 shows the schematic diagram of AC-DC (double-voltage) rectification circuit of Figure 36 using fly-by-capacitor clamping technology; 39(a)~39( c) shown in the figure, is the three implementation series of the upper layer network block Z1, the middle layer block Z2, the lower layer block Z3, and the clamp network Z4n shown in the double voltage rectifier circuit diagram shown in FIG. 35 and FIG. 37; Figure 40 shows an application example of one of the first series of the upper layer network Z1, the middle layer Z2, and the lower layer Z3 shown in the double-voltage rectification circuit diagram shown in Fig. 35; The switch of the switch pair of Fig. 40 uses a rectifying diode to realize a double voltage rectification circuit diagram; the 42nd figure is the switch of the switch pair of Fig. 40, using a MOSFET to realize a double voltage rectification circuit diagram; ) ~43 (d) shows the equivalent circuit diagram of the two-voltage rectifier circuit shown in Figure 41 under steady state operation; Figure 44 shows the double pressure shown in Figure 41 The rectifier circuit is controlled by phase shift, and the array operation waveform generated by the computer simulation software Simplis is used;

The inventor found in many experiments and tests that if the performance of the zero voltage operation is to be achieved in the inverter circuit, the following two necessary conditions must be met: 1. A fixed dead zone is required between the two groups of control drive signals ( Dead time interval; and 2, between the leakage inductance (or magnetizing inductance) and the output capacitance of the semiconductor switch, a large enough energy transfer is required.

In addition, the inventors have found in many control schemes that asymmetric Asymmetric Pulse-Width Modulation (APWM) control schemes are used, or phase shift modulation (Phase Shift Modulation, which is close to 50% duty cycle) is used. The control scheme of PS), or the control scheme of Variable Frequency (VF) which is close to 50% duty cycle, can obtain the required fixed dead time. Therefore, if the above control scheme is employed in the aforementioned circuit, the operating conditions of the zero voltage switch can be realized.

In addition to reducing the switching loss of the switch, in order to further improve the conversion efficiency of the aforementioned circuit, how to reduce the conduction loss of the semiconductor switches is also another motivation of the present invention. For the purpose of the present invention, the present invention utilizes two serial connections. A low-voltage MOSFET technology is designed to effectively reduce the equivalent on-resistance value R _DSon , thereby effectively reducing the conduction losses of the semiconductor switches to improve the conversion efficiency of the circuit. At the same time, the inventors use multiple connections. The technology of a low-voltage MOSFET can overcome the input voltage of up to several thousand volts, and under the bottleneck of the voltage specification technology of the semiconductor switch that can be used, the above problems to be solved by the present invention are achieved, and the power conversion is satisfied. Strict requirements.

In order to achieve the foregoing objectives, the inventors have considered the first embodiment of the present invention with a minimum of components, and a schematic diagram of a DC-AC inverter circuit of a single transformer, as shown in FIG. A soft-switching inverter circuit, the basic structure of the primary side of the inverter circuit is parallel-connected with the DC voltage, and the DC input voltage Vin of the input terminal is inverted into an AC voltage. And through the magnetic coupling of the transformer T1, the output to the output terminal including the at least one first secondary winding S1 generates a required AC voltage, and the first transformer T1 is composed of a first primary winding P1 and a second primary winding P2. At least one primary winding S1 is formed, wherein the first primary winding P1 and the second primary winding P2 have the same number of winding turns, and the inverter circuit comprises a middle network and a clamping capacitor (clamping) Capacitor and at least one transformer, all switches will be divided into four groups according to their operation: Q11-Q21-...-Qn1, Q12-Q22-...-Qn2, Q13-Q23-.. .-Qn3, and Q14-Q24-...-Qn4, switches belonging to the same group, will be the same It is turned on and off.

Please refer to FIG. 2(a), which is a schematic diagram of a soft-switching DC-AC inverter circuit with dual transformers according to the present invention, which is used for the single transformer of the inverter circuit of the first (a) diagram. The transformers T1 and T2 are replaced to increase the output power, wherein the transformer T1 includes at least a first primary winding P1 and a first secondary winding S1, and the transformer T2 includes at least a second primary winding P2 and at least a second secondary The winding S2, the first secondary winding S1 and the second secondary winding S2, can be connected in parallel or in series to generate a required AC output voltage. If a DC output voltage is required, an additional rectification and filtering must be added on the secondary side. a circuit (not shown), the first inductor Lr1 and the second inductor Lr2 will respectively represent the leakage inductance of the primary winding P1 of the first transformer T1 and the primary winding P2 of the second transformer T2, or two Independently applied inductor, or a coupled inductor sense.

Although the figures disclosed in Figures 1(a) and 2(a) are for providing different output powers, respectively, using two series of application examples of single transformer or dual transformer, but should have the same working principle, Therefore, the working principle of the first application example of Fig. 1(a) will be explained.

Referring to FIG. 1(a), the middle layer network includes a first primary winding P1 of a transformer and a first block Lr1 connected in a top block, and a first switch pair (switch-pair) Block), a middle block Z2 (middl block), a second switch-pair block, and a second primary winding P2 of the transformer and the second inductor Lr2 are connected in series to the bottom block, The serial connection composition, wherein the first switch pair block and the second switch pair block comprise an equal number of at least one switch pair, and if the voltage stress on the semiconductor switch is reduced, more first switches can be added at the same time The number of pairs of switches for the square and the second switch pair.

Referring to FIG. 1(a), the upper layer is composed of a first primary winding P1 of the transformer and a first inductor Lr1, and Lr1 may be a leakage inductance of the first primary winding P1 of the transformer or an additional A resonant inductor, or a leakage inductance combined with an external inductor, becomes a first resonant inductor, and the dot terminal of P1 and the right terminal of the Lr1 inductor are respectively connected to the positive terminal of the input voltage and the clamp capacitor.

Referring to FIG. 1(a), the first switch-pair block is connected in series by at least one switch pair Q11-Q13 or n switch pairs, wherein each switch pair includes two Each switch has two upper and lower terminals, which can be respectively connected to the corresponding switches of the two switches connected in series, such as the two lower terminals of Q21-Q23 and the two switches connected in series below Q11- Q13 two upper terminals are respectively connected, and the two upper terminals of Q21-Q23 and the two switches connected in series are connected to the two lower terminals of Q31-Q33, and so on, but the nth switch pair is Qn1-Qn3 The two upper terminals are respectively connected to the input voltage and the positive terminal of the clamp capacitor.

Referring to FIG. 1(a), the middle block Z2 has a first terminal and a second terminal.

Referring to FIG. 1(a), the second switch-pair block is connected in series by n switch pairs including at least one switch pair Q12-Q14, wherein each switch has a top-bottom switch. Two terminals, which can be connected to the corresponding switches of the two switches connected in series The junction, for example, the two lower terminals of Q22-Q24 and the switches connected in series are connected to the two upper terminals of Q32-Q34, and the two upper terminals of Q22-Q24 are connected with the two switches connected above. Q12- Q14 two lower terminals are connected, and so on, until the two upper terminals of the nth switch pair Qn2-Qn4 are respectively connected to the input voltage and the negative terminal of the clamp capacitor.

Referring to FIG. 1(a), the lower layer is composed of a second primary winding P2 of the transformer and a second inductor Lr2, and Lr2 may be the leakage inductance of the second primary winding P2 of the transformer or an additional The two resonant inductors, or a combination of leakage inductance and an external inductor, become a second resonant inductor, and the dot terminal of P2 and the right terminal of the Lr2 inductor are respectively connected to the input terminal and the negative terminal of the clamp capacitor.

Referring to Figure 1(a), the first terminal of the middle layer, the lower terminal of Q11, the upper terminal of Q12 are connected together, the second terminal of the middle layer, the lower terminal of Q13, and the upper terminal of Q14 are connected. together.

Please refer to Figure 1(b), the middle block Z2 (middl block) has three different circuit components; 1 short circuit, 2. a resonant inductor and a series connected resonant capacitor, 3. resonant capacitor, connected to its Between one terminal 1 and the second terminal 2, the first embodiment of the circuit of the invention can thus be derived from the following three implementation series.

Referring to FIG. 1(b), the middle layer block Z2 (middl block) is short-circuited between the first terminal 1 and the second terminal 2, which is the first embodiment of the circuit of the present invention. A series, as shown in Fig. 3, in which Lr1 and Lr2 are the leakage inductances of the first primary winding P1 and the second primary winding P2 of the transformer, respectively.

Referring to FIG. 1(a), a plurality of switch pairs connected in series by the first switch pair block and the second switch pair block can be applied to power conversion of a high voltage input to reduce voltage stress of each switch. All switches will be divided into four groups: Q11-Q21-...-Qn1, Q12-Q22-...-Qn2, Q13-Q23-...-Qn3, and Q14-Q24-...- Qn4, for the zero voltage operation, the switches belonging to the same group will be asymmetrical pulse width modulation (APWM) generated by a controller (not shown), or use nearly 50% of the work. Phase Shift Modulation (PS), or variable frequency (VF) control schemes close to 50% duty cycle, generate four sets of drive signals with fixed dead time interval, respectively, or Disconnect the switches of each group to make the inverter The secondary winding S1 of the circuit generates an AC output voltage. However, if the inverter circuit needs to provide a DC voltage to a load Ro, the corresponding output of the secondary winding S1 needs to be provided with a rectifier circuit. And filter circuit (not shown).

Referring to Figures 1(a) and 1(b), a different number of switch pairs connected in series by the first switch pair block and the second switch pair block can be used to derive many different switching stress circuits. The working principle is the same, so the working principle of the first series of the first embodiment of the present invention will be disclosed through the inverter circuit of one of the circuits of FIG.

Please refer to Fig. 4 and Fig. 5 for the inverter circuit diagram of Fig. 3 realized by MOSFET, and the equivalent circuit of the interval at steady state operation.

Referring to FIG. 5(a)-(d), the inverter circuit shown in the circuit of the first series of FIG. 4 of the first embodiment of the present invention uses a full bridge phase shift control method, in a fourth duty cycle. The equivalent circuit of a working phase.

Referring to Figure 5(a), the driver signal provided by the controller turns on Q11 and Q14, and the input voltage Vin provides the transformer through the loop of Vin(+)-Q11-Q14-P2-Lr2-Vin(-). The voltage of the second primary winding P2, while the voltage on the clamp capacitor C1, provides the voltage of the first primary winding P1 of the transformer via a loop of C1(+)-P1-Lr1-Q11-Q14-C1(-), For a time interval, the clamp capacitor C1 is in a discharged state.

Referring to Figure 5(b), the drive signal provided by the controller turns off Q11 and Q14. The time interval, the input voltage Vin and the energy stored in the leakage inductance are via Vin(+)-Lr1-P1-C1. -P2-Lr2-Vin(-) loop, charging the clamp capacitor C1, canceling each other due to the opposite polarity across the voltage across the first primary winding P1 of the transformer and the voltage across the second primary winding P2 of the transformer Therefore, the voltage on the clamp capacitor C1 is equal to the input voltage.

Referring to Figure 5(c), the driver signal provided by the controller turns on Q12 and Q13, and the input voltage Vin provides the transformer via the loop of Vin(+)-Lr1-P1-Q13-Q12-Vin(-). The voltage of the first primary winding P1, while the voltage on the clamp capacitor C1, provides the voltage of the second primary winding P2 of the transformer via a loop of C1(+)-Q13-Q12-Lr2-P2-C1(-). In the interval, the clamp capacitor C1 is in a discharged state.

Referring to Figure 5(d), the drive signal provided by the controller turns off Q12 and Q13. The time interval, the input voltage Vin and the energy stored in the leakage inductance are via The circuit of Vin(+)-Lr1-P1-C1-P2-Lr2-Vin(-) charges the clamp capacitor C1 due to the voltage across the first primary winding P1 of the transformer and the second primary across the transformer. The voltage of the winding P2, opposite in polarity, cancels each other, so the voltage on the clamp capacitor C1 is equal to the input voltage.

Please refer to FIG. 6 , which is a main working waveform of the inverter circuit of the first series of FIG. 5 according to the first embodiment of the present invention, including the driving signal provided by the controller and the voltage waveform of each MOSFET, as shown in the figure. The MOSFET operates at zero voltage conduction and has high efficiency due to reduced switching losses.

Please refer to the figure 7(a)-7(b) for the comparison of the input current waveforms of the traditional full-bridge inverter circuit and the inverter circuit of Figure 5, respectively, under the same specifications, indicating that the latter has lower The input current is chopped to allow the use of smaller components to meet the requirements of the electromagnetic interference specification.

Referring to FIG. 1(b), the middle layer block Z2 (middl block) is connected in series with a resonant inductor Lr and a resonant capacitor Cr, and is connected between the first terminal 1 and the second terminal 2 to become A second series of the first embodiment of the circuit of the present invention is shown in Fig. 8, wherein Lr1 and Lr2 are leakage inductances of the first primary winding P1 and the second primary winding P2 of the transformer, respectively.

Referring to FIG. 1(b), the middle layer block Z2 (middl block) is connected to the first terminal 1 and the second terminal 2 by using a resonant capacitor, which is the first embodiment of the circuit of the present invention. The third series, as shown in FIG. 9, wherein Lr1 and Lr2 are respectively connected to the leakage inductance of the first primary winding P1 of the transformer and a first resonant inductor, and the leakage inductance of the second primary winding P2 is connected in series with a second resonant inductor.

Please refer to FIG. 8 and FIG. 9. Although the positions of the resonant inductors are different, and the working principle is the same, the second series and the third series of the first embodiment of the present invention will pass through The inverter circuit of Figure 9 reveals its working principle.

Please refer to Fig. 10 and Fig. 11 for the inverter circuit diagram of Fig. 9 realized by MOSFET, and the equivalent circuit of the interval at steady state operation.

Referring to FIG. 11(a)-11(d), the inverter circuit shown in the second series of FIG. 10 of the first embodiment of the present invention uses the frequency conversion control method in four working phases of one duty cycle. The equivalent circuit.

Referring to Figure 11(a), the driver signal provided by the controller turns on Q11 and Q14, and through the loop of Q11-Q14, the input voltage Vin provides voltage transformation via Lr2-Cr resonance. The voltage of the second primary winding of the device, while the voltage on the clamp capacitor C1 provides the voltage of the first primary winding of the transformer via the Lr1-Cr resonance mode. In this interval, the clamp capacitor C1 is in a discharged state.

Referring to Figure 11(a), the driver signal provided by the controller turns on Q11 and Q14, and the input voltage Vin is via the loop of Vin(+)-Q11-Cr-Q14-P2-Lr2-Vin(-). The Cr-Lr2 resonance mode provides the voltage of the second primary winding P2 of the transformer, and the voltage on the clamp capacitor C1 is in the Cr-Lr2 resonance mode via C1(+)-P1-Lr1-Q11-Cr-Q14-C1 The circuit of (-) provides the voltage of the first primary winding P1 of the transformer. In this time interval, the clamp capacitor C1 is in a discharged state.

Referring to Figure 11(b), the driver signal provided by the controller turns off Q11 and Q14. The time interval, the input voltage Vin and the energy stored in the leakage inductance are via Vin(+)-Lr1-P1-C1. -P2-Lr2-Vin(-) loop, charging the clamp capacitor C1, canceling each other due to the opposite polarity across the voltage across the first primary winding P1 of the transformer and the voltage across the second primary winding P2 of the transformer Therefore, the voltage on the clamp capacitor C1 is equal to the input voltage.

Referring to Figure 11(c), the driver signal provided by the controller turns on Q12 and Q13, and the input voltage Vin is via the loop of Vin(+)-Lr1-P1-Q13-Cr-Q12-Vin(-). In the Cr-Lr1 resonance mode, the voltage of the first primary winding P1 of the transformer is provided, and the voltage on the clamp capacitor C1 is in the Cr-Lr2 resonance mode, via C1(+)-Q13-Cr-Q12-Lr2-P2- The circuit of C1(-) provides the voltage of the second primary winding P2 of the transformer. In this time interval, the clamp capacitor C1 is in a discharged state.

Referring to Figure 11(d), the driver signal provided by the controller turns off Q12 and Q13. The time interval, the input voltage Vin and the energy stored in the leakage inductance are via Vin(+)-Lr1-P1-C1. -P2-Lr2-Vin(-) loop, charging the clamp capacitor C1, canceling each other due to the opposite polarity across the voltage across the first primary winding P1 of the transformer and the voltage across the second primary winding P2 of the transformer Therefore, the voltage on the clamp capacitor C1 is equal to the input voltage.

Referring to FIG. 12, the main circuit working waveforms of the second and third series inverter circuits according to the first embodiment of the present invention include the driving signals provided by the controller and the voltage waveforms of the MOSFETs. It is shown that the MOSFETs on the primary side operate in a zero voltage conduction state, and the rectifier diodes on the primary side operate in a zero current off state, and have high efficiency performance due to a reduction in switching loss.

Please refer to the schematic diagram of the inverter circuit in Figure 1(a) and Figure 2(b). For high voltage input applications, it is necessary to use higher voltage components or series of more first switches. The number of switching pairs of the block and the second switch pair block to reduce the voltage stress on each semiconductor switch. However, the multi-switch series is connected, and the voltage stress of each component cannot be evenly distributed due to variations of components and circuit parameters. Therefore, it is necessary to use an inverter circuit with a clamp circuit as shown in Figs. 13(a) and 14(a).

Please refer to Figure 15 and Figure 16, for the addition of the clamp circuit as shown in Figures 13(a) and 14(a), using the flying capacitor clamping technique or the two poles respectively. The clamp circuit realized by the diode clamping technique, according to which the voltage stress of the switch is evenly shared.

Please refer to Fig. 17 and Fig. 18 for a schematic diagram of an application example of the inverter circuit of Fig. 1(a) using the fly-by-bit clamp technique, and an inverter circuit diagram of the switching element implemented by the MOSFET.

Referring to FIG. 19, which is a schematic diagram of a soft-switching AC-DC rectifier circuit of a single transformer according to a second embodiment of the present invention, the basic structure of the primary side of the circuit is At least one pair of switching circuits, such as push-pull, half-bridge, full-bridge inverter circuits (not shown), and at least one pair of control signals or complementary control signals that are close to 50% duty cycle (not shown) The basic structure of the secondary circuit of the circuit is composed of a middle network, a first output capacitor Co, and a load Ro. The first transformer T1 includes at least a first primary winding P1 and The first secondary winding S1 (included in the middle layer network), the switching pair of the foregoing inverter circuit is alternately turned on or off by receiving the aforementioned control signals, whereby the primary winding of the rectifier circuit is generated AC voltage, and electromagnetic coupling, AC voltage generated in the secondary winding, four group switches on the secondary side, Q11-Q21-...-Qn1, Q12-Q22-...-Qn2, Q13- Q23-...-Qn3, and Q14-Q24-...-Qn4, the same group of switches, simultaneously turned on Shut-off control, respectively of a DC voltage output load Ro. Due to the inverter circuit, the resonant frequency of the secondary side element is used as the operating frequency, and the current of the secondary side switch is reset to zero by resonance. Therefore, the switching elements of the primary side and the secondary side of the rectifier circuit are operated. The best working condition of soft switching.

Referring to FIG. 19, the middle network is a top block, a first switch-pair block, and a middle block Z2 (middle block). a second switch-pair block, and a lower layer Z3 (bottom block), which is composed of up and down serially, wherein the first switch pair block and the second switch pair block comprise an equal number of switch pairs. If the voltage stress on the semiconductor switch is reduced, the voltage balance can be increased simultaneously. More of the number of switch pairs of the first switch pair block and the second switch pair block.

Referring to FIG. 19, the upper layer Z1 has a first terminal and a second terminal. The first terminal, the positive terminal of the output capacitor, is connected to the positive terminal of the load.

Referring to FIG. 19, the first switch-pair block includes at least a first switch pair (Q11-Q13) until n switch pairs (Qn1-Qn3) are connected in series, wherein Each switch pair includes two switches, each of which has two upper and lower terminals, and the two switches connected in series with the upper and lower switches are connected with the corresponding switches, for example, the two lower terminals of the Q21-Q23 are connected in series with the lower one. The two switches are respectively connected to the two upper terminals of Q11-Q13, and the two upper terminals of Q21-Q23 are connected with the two lower terminals of Q31-Q33 respectively, and so on, until so on. The two upper terminals of the n-switch pair Qn1-Qn3 are respectively connected to the first terminal and the second terminal of the upper layer.

Referring to Figure 19, the middle block Z2 has a first terminal and a second terminal.

Referring to FIG. 19, the second switch-pair block includes at least one switch pair (Q12-Q14) until n switch pairs (Qn2-Qn4) are connected in series, wherein Each switch pair includes two switches, each of which has two upper and lower terminals, and the two switches connected in series with the upper and lower switches are connected with the corresponding switches, for example, the two lower terminals of the Q12-Q14 are connected in series with the lower end. The two switches are connected to the two upper terminals of Q22-Q24, and the two lower terminals of Q22-Q24 are connected to the two upper terminals of Q31-Q33 connected in series, and so on, until n The two lower terminals of the switch pair Qn1-Qn3 are respectively connected to the first terminal and the second terminal of the lower layer.

Referring to FIG. 19, the lower layer block has a first terminal and a second terminal, and the first terminal, the negative terminal of the output capacitor, is connected to the negative terminal of the load.

Please refer to Figure 19, the first terminal of the middle layer, the lower end of Q11 The upper terminals of Q12 are connected together, the second terminal of the middle layer, the lower terminal of Q13, and the upper terminal of Q14 are connected together.

Please refer to FIG. 20 , which is a schematic diagram of a soft-switching AC-DC rectifier circuit with dual transformers according to the present invention. In order to replace the single transformer of the rectifier circuit of FIG. 19 with two transformers T1 and T2, The output power is increased, wherein the transformer T1 includes at least a first primary winding P1 and a first secondary winding S1, and the transformer T2 includes at least a second primary winding P2 and at least a second secondary winding S2, the first primary winding P1 and the second primary winding P2 are connected in parallel or in series to produce a desired AC input voltage.

Referring to FIG. 21 and FIG. 22, for the application of high voltage output, the rectifier circuit of the 19th and 20th embodiments of the second embodiment of the present invention is improved, except that components of higher voltage specifications are used or must be simultaneously increased. The number of switching pairs of the first switch pair block and the second switch pair block is reduced to reduce the voltage stress on each semiconductor switch, and only the switches are connected in series, and the semiconductor switching elements are changed due to variations of components and circuit parameters. The voltage stress that can be withstood cannot be evenly distributed. The Z41 and Z42---Z4n1 blocks in Fig. 21 and Fig. 22 are therefore required to achieve the average voltage stress by using the flying capacitor clamping technology such as CF1, CF2---CFn.

Although the 19th and 20th figures disclose different output powers, the circuits of the two series of application examples of the single transformer or the double transformer are respectively used, and the persons disclosed in FIG. 21 and FIG. 22 are different. For the application of the output voltage, the first switch pair block and the second switch pair block must be connected in series with a larger number of switch pairs, thus deriving many different rectifier circuits, but the circuits described should have the same operational characteristics.

Referring to FIG. 19, the first terminal and the second terminal are connected between the upper block Z1 (top block), the middle block Z2 (middle block), and the lower block Z3 (bottom block). There are three different combinations of circuits, such as Figure 23(a), Figure 23(b), and Figure 23(c), so that the second embodiment of the circuit of the present invention can be derived from three series. Please refer to Fig. 24, for the Z1-Z2-Z3 in Fig. 19, the circuit combination connection of (short circuit)-(S1-Cr-Lr)-(short circuit) is shown in Fig. 23(a). Between the first terminal and the second terminal of each block, the first series of the second embodiment of the circuit of the present invention, wherein Lr and Cr are respectively a resonant inductor and a resonant capacitor.

Please refer to Figure 25 and Figure 26 for the rectifier diode and MOSFET respectively. The switching element in Fig. 24 is realized.

Referring to Fig. 27, in order to use Z1-Z2-Z3 in Fig. 19, the circuit combinations of (Lr1)-(S1-Cr)-(Lr2) are respectively connected to each other as shown in Fig. 23(b). Between the first terminal and the second terminal of the block, the second series of the second embodiment of the circuit of the present invention, wherein Lr1 and Lr2 are leakage inductances of the first primary winding P1 and the second primary winding P2, respectively, Lr and Cr is a resonant inductor and a resonant capacitor, respectively.

Referring to Figures 28 and 29, the switching elements of Figure 27 are implemented with a rectifying diode and a MOSFET, respectively.

Referring to Figure 30, in order to use Z1-Z2-Z3 in Figure 19, the circuit combination connection of (S1-Lr1)-(Cr)-(S2-Lr2) is shown in Figure 23(b). Between the first terminal and the second terminal of each block, the third series of the second embodiment of the circuit of the present invention, wherein Lr1, Lr2 and Cr are the first resonant inductor, the second resonant inductor and the resonant capacitor, respectively.

Referring to FIGS. 31 and 32, the switching elements in FIG. 30 are implemented by rectifying diodes and MOSFETs, respectively.

Referring to FIG. 19, there are three different circuit combinations respectively connected to the upper layer. The second embodiment of the circuit of the present invention can be derived into three series, but the circuit should have the same working characteristics. Accordingly, the operation of the second embodiment of the present invention will be disclosed with the rectifier circuit of Fig. 31.

Referring to Figures 33(a)-33(d), the rectifier circuit of the third series of the third embodiment of the second embodiment of the present invention uses a full-bridge inverter circuit using a phase shift control method on the primary side (Fig. Not shown in the equation), the equivalent circuit in four working phases of a duty cycle.

Referring to Figure 33(a), the drive signal provided by the controller turns on the first set of switches of the full-bridge inverter circuit on the primary side (not shown), and the winding P1 on the primary side of the transformer will generate The alternating voltage, through the electromagnetic coupling of the transformer, across the voltage of the first winding S1 on the secondary side of the transformer, via S1 (non-dot)-C1-Q14-Cr-Q11-Lr1-S1(dot) and the second winding S2 The voltage, through S2 (non-dot)-Q14-Cr-Q11-Ro-Lr2-S2 (dot), provides the forward bias of the rectifying diode, so Q11 and Q14 are turned on, and the current is based on Cr- The resonant mode of Lr1/Lr2 operates. In this one-time interval, the clamp capacitor C1 is in a charged state.

Please refer to Figure 33(b), the aforementioned resonant current is zero, so Q11 and Q14 is naturally turned off. In this interval, the voltage of the clamp capacitor C1, C1(+)-S1-Lr1-Ro-Lr2-S2-C1(-), provides the load current.

Referring to Figure 33(c), the drive signal provided by the controller turns on the second group of switch switches of the full-bridge inverter circuit on the primary side (not shown), and the winding P1 on the primary side of the transformer will generate The AC voltage, through the electromagnetic coupling of the transformer, across the voltage of the first winding S1 on the secondary side of the transformer, via S1(dot)-Lr1-Ro-Q12-Cr-Q13-S1(non-dot) and the second winding The voltage of S2, through S2(dot)-Lr2-Q12-Cr-Q13-C1-S2(non-dot), provides the forward bias of the rectifying diode, so that Q12 and Q13 are turned on, and the current is based on Cr -Lr1/Lr2 operates in a resonant mode. In this one-time interval, the clamp capacitor C1 is in a charged state.

Referring to Figure 33(d), the aforementioned resonant current is reset to zero, so Q12 and Q13 are naturally turned off. In this interval, the clamp capacitor C1 is placed.

Referring to FIG. 34, the operation waveform of the rectifier circuit of the third series and the application example of the third embodiment of the present invention includes the driving signal provided by the controller and the voltage waveform of each MOSFET, and each MOSFET operates at zero. The voltage is turned on, and at the same time, each of the rectifying diodes operates in a zero current off state, and the efficiency is improved due to a reduction in switching loss.

Referring to FIG. 35, a third embodiment of the present invention is a schematic diagram of a single transformer, soft-switched AC-DC voltage doubler rectifier circuit. The basic architecture of the primary side consists of at least one dual switching circuit, such as a push-pull, half-bridge, full-bridge inverter circuit (not shown), and at least one pair of control signals approaching 50% duty cycle Or a complementary control signal (not shown), the basic architecture of the secondary of the circuit is a middle network, a middle network, a first output capacitor Co1 and a The second output capacitor Co2 is connected in series with a load Ro. The first transformer T1 includes at least a first primary winding P1 and a first secondary winding S1 (included in the middle layer network), and the foregoing inverter The switching pair of the circuit is alternately turned on or off by receiving the aforementioned control signals, whereby the primary winding of the rectifier circuit will generate an alternating voltage, and electromagnetically coupled, the alternating voltage generated in the secondary winding, Two side group switches , Q11-Q21-...-Qn1, and the switch of the same group of Q12-Q22-...-Qn2, while applying the control of turning on or off, respectively outputting the DC voltage to a load Ro. Due to the inverter circuit, the secondary side component resonant frequency is used as the operating frequency, and the secondary side switching current is Returning to zero by resonance, therefore, the switching elements of the primary side and the secondary side of the rectifier circuit operate in the optimum operating condition of soft switching.

Referring to FIG. 35, the middle network is composed of a top block, a first switch block, and a middle block, a middle block, a middle block, a middle block, and a middle block. a second switch unit block (switch-cell block) and a lower layer block Z3 (bottom block) are connected in series, wherein the first switch unit block and the second switch unit block comprise an equal number of switch units, each The switch unit includes a switch. If the voltage stress on the semiconductor switch is reduced, the number of switch units of the first switch unit block and the second switch unit block can be increased at the same time.

Referring to FIG. 35, the upper layer Z1 has a first terminal and a second terminal. The first terminal, the positive terminal of the first output capacitor, is connected to the positive terminal of the load.

Referring to FIG. 35, the first switch unit block includes at least one switch unit Q11 until n switch units Qn1 are connected in series, wherein the switch unit includes a switch, wherein Each switch has two upper and lower terminals, which can be connected with the switches of the two switch units connected in series with each other. For example, the lower terminal of Q21 is connected with the Q11 upper terminal of the switch unit connected in series below, and the terminal of Q21 is connected in series with the upper end. The lower terminal of Q31 of the switch unit is connected, and so on, until the upper terminal of Qn1 of the n switch unit is connected with the second terminal of the upper layer block.

Referring to Figure 35, the middle block Z2 has a first terminal and a second terminal.

Referring to FIG. 35, the second switch unit block includes at least one switch unit Q12 until n switch units Qn2 are connected in series, wherein the switch unit includes a switch. Each switch has two upper and lower terminals, which can be connected with the switches of the two switch units connected in series with each other. For example, the lower terminal of Q22 is connected with the Q32 upper terminal of the switch unit connected in series, and the terminal of Q22 is connected in series with the upper end. The Q12 lower terminal of the switch unit is connected, and so on, until the Qn2 lower terminal of the n switch unit is connected to the second terminal of the lower layer block.

Referring to Figure 35, the lower layer Z3 has the first terminal and The second terminal, the first terminal, and the negative terminal of the second output capacitor are connected to the negative terminal of the load.

Referring to FIG. 35, the second terminal of the middle layer is connected with the lower terminal of Q11 and the upper terminal of Q12, and the first terminal of the middle layer and the summer terminal of the first output capacitor and the second output capacitor The terminals are connected together.

Please refer to FIG. 36, which is a schematic diagram of a soft-switching AC-DC rectifier circuit with dual transformers according to the present invention. In order to replace the single transformer of the rectifier circuit of FIG. 35 with two transformers T1 and T2, The output power is increased, wherein the transformer T1 includes at least a first primary winding P1 and a first secondary winding S1, and the transformer T2 includes at least a second primary winding P2 and at least a second secondary winding S2, the first primary winding P1 and the second primary winding P2 are connected in parallel or in series to produce a desired AC input voltage.

Referring to Figures 37 and 38, for the application of high voltage output, the rectifier circuit of the 35th and 36th embodiments of the second embodiment of the present invention is improved, except that components of higher voltage specifications are used or must be simultaneously increased. The number of switching pairs of the first switch pair block and the second switch pair block is reduced to reduce the voltage stress on each semiconductor switch, and only the switches are connected in series, and the semiconductor switching elements are changed due to variations of components and circuit parameters. The voltage stress that can be withstood cannot be evenly distributed. The Z41 and Z42---Z4n blocks in Fig. 35 and Fig. 36 are therefore required to achieve the average voltage stress by using the flying capacitor clamping technology such as CF1, CF2---CFn.

Although the figures disclosed in Figures 35 and 36 provide different output powers, the circuits of the two series of application examples of the single transformer or the dual transformer are respectively used, and the persons disclosed in Fig. 37 and Fig. 38 are different. For the application of the output voltage, the first switch pair block and the second switch pair block must be connected in series with a larger number of switch pairs, thus deriving many different rectifier circuits, but the circuits described should have the same operational characteristics.

Referring to FIG. 35, the first terminal and the second terminal are connected between the upper block Z1 (top block), the middle block Z2 (middle block), and the lower block Z3 (bottom block). There are three different combinations of circuits, such as Figure 39(a), Figure 39(b), and Figure 39(c), so the third embodiment of the circuit of the present invention can derive three different series, but The three should have the same working characteristics, and accordingly, the working principle of the third embodiment of the present invention will be disclosed with an application example of Fig. 35.

Please refer to Fig. 40, for the Z1-Z2-Z3 in Fig. 35, using the combination of (short circuit)-(S1-Cr-Lr)-(short circuit) as shown in Fig. 39(a) Between the first terminal and the second terminal of each block, the first series of the third embodiment of the circuit of the present invention, wherein Lr and Cr are respectively a resonant inductor and a resonant capacitor.

Referring to FIG. 41 and FIG. 42, the switching elements in FIG. 40 are implemented by rectifying diodes and MOSFETs, respectively.

Referring to FIG. 43(a)-43(d), the rectifier circuit of the first series 41 of the third embodiment of the present invention uses a full-bridge inverter circuit using a phase shift control method on the primary side ( The figure is not shown), the equivalent circuit in four working phases of a duty cycle.

Referring to Figure 43 (a), the drive signal provided by the controller turns on the first set of switches of the full-bridge inverter circuit on the primary side (not shown), and the winding P1 on the primary side of the transformer will generate The alternating voltage, through the electromagnetic coupling of the transformer, across the voltage of the first winding S1 on the secondary side of the transformer, providing a rectifying diode via S1(dot)-Q11-Co1-Cr-Lr-S1(non-dot) Forward bias, so Q11 is turned on, where the current operates in the resonant mode of Cr-Lr, while the second output capacitor Co2 is provided via Co2(+)-Cr-Lr-S1-Q11-Ro-Co2(-) Load current.

Referring to Figure 43(b), the aforementioned resonant current is reset to zero, so Q11 is naturally turned off. In this interval, the load current is provided by the first output capacitor Co1 and the second output capacitor Co2.

Referring to Figure 43 (c), the drive signal provided by the controller turns on the second set of switches of the full-bridge inverter circuit on the primary side (not shown), and the winding P1 on the primary side of the transformer will generate The alternating voltage, through the electromagnetic coupling of the transformer, across the voltage of the first winding S1 on the secondary side of the transformer, providing a rectifying diode via S1 (non-dot)-Lr-Cr-Co2-Q12-S1(dot) Forward bias, thus Q12 is turned on, where the current operates in the resonant mode of Cr-Lr, while the first output capacitor Co1 is provided via Co1(+)-Ro-Q12-S1-Lr-Cr-Co1(-) Load current.

Referring to Figure 43(d), the aforementioned resonant current is zeroed, so Q12 is naturally turned off. In this interval, the load current is provided by the first output capacitor Co1 and the second output capacitor Co2.

Please refer to FIG. 44, which is a working waveform of the double-voltage rectifier circuit of the first series of an application example according to the fourth embodiment of the present invention, including a driving signal provided by the controller and voltage waveforms of the MOSFETs. The MOSFET operates in a zero-voltage conduction state, and at the same time, each rectifying diode operates in a zero-current off state, and the efficiency is improved due to a reduction in switching loss.

However, in particular, in the foregoing embodiments of the present invention, the switches are not limited to the use of diodes, but may be adapted to other needs (if efficiency is desired), and other types of initiative may be used. A semiconductor switch (such as a MOSFET) that provides synchronous rectification or a combination of the two.

The above is only a few embodiments of the present invention. However, in the practice of the present invention, it is not limited thereto, and other equivalent elements may be substituted for corresponding components in the respective circuits according to actual needs, so any familiarity. The artist can easily think about the above equivalent in the field of the invention. Changes or modifications should be covered in the scope of the patent application in this case below.

Claims (12)

An inverter circuit with soft switching, the circuit is connected in parallel to an input voltage for converting a DC voltage of the input voltage into an AC voltage, comprising: an input voltage, a middle layer network, a clamp capacitor, And at least one transformer, the input voltage has a positive terminal and a negative terminal, the clamping capacitor has a positive terminal and a negative terminal, the transformer includes at least a first primary winding and a first secondary winding; the middle layer network, The method includes an upper layer block, a first switch pair block, a middle layer block, a second switch pair block and a lower layer block, which are vertically connected in series; the upper layer block includes a first primary winding of the transformer and a first inductor, the first An inductor has a right terminal and a left terminal, which may be a leakage inductance of the first primary winding of the transformer, or an external inductor, or a leakage inductance combined with an external inductor; the non-doped terminal of the first primary winding and the first The left terminals of the inductor are connected together, and the dot terminal of the first primary winding and the right terminal of the inductor are respectively connected to the positive terminal of the input voltage and the clamping capacitor; The switch pair block includes at least one or more switch pairs connected in series, wherein each switch pair includes two switches, each switch has two upper and lower terminals, and the corresponding switches of the two switch pairs connected in series with each other are respectively connected, However, the upper terminals of the uppermost switch pair are respectively connected with the input terminal and the positive terminal of the clamp capacitor; the middle layer block has a first terminal and a second terminal; The second switch pair block includes at least one or more switch pairs connected in series, wherein each switch pair includes two switches, each switch has two upper and lower terminals, and two switches corresponding to the upper and lower series are correspondingly connected to the switch Connected separately, but the lower two terminals of the lowermost switch are respectively connected with the input voltage and the negative terminal of the clamp capacitor; the lower block includes a second primary winding of a transformer connected in series with a second inductor, the second The inductor has a right terminal and a left terminal, which may be a leakage inductance of the second primary winding of the transformer, or an external inductor, or a leakage inductance combined with an external inductor; the non-drain terminal of the second primary winding and the second inductor The left terminals are connected together, and the dot terminals of the second primary winding and the right terminal of the inductor are respectively connected to the input terminal and the negative terminal of the clamp capacitor; the first switch pair block and the second switch pair block include an equal number And at least one switch pair; the first terminal and the second terminal of the middle layer block, and the second switch terminal of the first switch pair of the first switch pair block and the second switch pair block The two upper terminals of the switch pair are respectively connected together, and the transformer comprises at least one primary winding, each of the secondary windings being magnetically coupled with the corresponding primary winding in the middle layer network to become at least one magnetically coupled transformer To provide the AC voltage; thus, the inverter circuit can be borrowed during a switching cycle A soft switching mechanism that alternately turns on or off the switches to convert the DC voltage provided at the input to an AC voltage. The inverter circuit of claim 1, wherein the first terminal and the second terminal of the middle layer block are short circuited circuits. The inverter circuit of claim 1, wherein the first terminal and the second terminal of the middle layer block are a circuit in which a resonant inductor is connected in series with a resonant capacitor. The inverter circuit of claim 1, wherein the first terminal and the second terminal of the middle layer block are circuits of a resonant capacitor. A rectifying circuit with soft switching, the circuit is composed of a middle layer network, a first output capacitor, and a load, which are connected in parallel on a secondary side of a transformer, for converting the input AC voltage into a DC voltage. The system includes: a middle layer network, an output capacitor, and at least one transformer, the output capacitor has a positive terminal and a negative terminal, the transformer includes at least a first primary winding and a first secondary winding; the middle layer network includes An upper layer block, a first switch pair block, a middle layer block, a second switch pair block and a lower layer block are vertically connected in series; the upper layer block has a first terminal and a second terminal, and the upper layer block is first a terminal, the positive terminal of the output capacitor is connected to the positive terminal of the load; the first switch pair block includes at least one or more switch pairs connected in series, wherein each The switch pair includes two switches, each of which has two upper and lower terminals, and the two switches connected in series with the upper and lower switches are respectively connected to the corresponding switches, but the uppermost switch has two upper terminals and the upper square One terminal is respectively connected to the second terminal; the middle layer block has a first terminal and a second terminal; the second switch pair block includes at least one or more switch pairs connected in series, wherein each switch pair includes two Each switch has two upper and lower terminals, and the two switches connected in series with the upper and lower switches are respectively connected to the corresponding switches, but the lower end of the lower switch and the second terminal of the lower layer and the first The two terminals are respectively connected; the lower layer has a first terminal and a second terminal, and the first terminal of the lower layer, the negative terminal of the output capacitor is connected with the negative terminal of the load; the first switch The square block and the second switch pair block comprise an equal number of at least one switch pair; the first terminal and the second terminal of the middle layer block are opposite to the first switch of the first switch pair block The lower terminal and the second switch of the second switch pair of the second switch pair are respectively connected together, and the transformer comprises at least one primary winding, each of the secondary windings being magnetically coupled with the corresponding primary winding in the middle layer network And becoming at least one magnetically coupled transformer to provide the DC voltage; thus, during a switching duty cycle, the rectifier circuit can convert the AC voltage provided by the input terminal into a DC voltage by a soft switching mechanism . . The rectifier circuit of claim 5, wherein the first terminal and the second terminal of the lower layer are a short circuit, and the first terminal of the middle layer The two terminals are a first secondary winding of a transformer, a resonant inductor and a resonant capacitor connected in series. The rectifier circuit of claim 5, wherein the first terminal and the second terminal of the upper layer are a circuit of a first resonant inductance, and the first terminal of the middle layer The two terminals are a first secondary winding of a transformer, and a circuit in which a resonant capacitor is connected in series. The first terminal and the second terminal of the lower layer block are circuits of a second resonant inductor. The rectifier circuit of claim 5, wherein the upper layer is a circuit in which a first secondary winding of a transformer is connected in series with a first resonant inductor, and the first terminal of the middle layer is The second terminal is a resonant capacitor circuit, and the first terminal and the second terminal of the lower layer are a circuit in which a second secondary winding of the transformer is connected in series with a second resonant inductor. A rectification circuit with soft switching, the circuit is composed of a middle layer network, a first output capacitor, a second output capacitor, and a load, which are connected in parallel on a secondary side of a transformer for inputting the input AC voltage Converting to a DC voltage, comprising: a middle layer network, a first output capacitor and a second output capacitor connected in series, and at least one transformer, the first output capacitor and the second output capacitor each having a positive a terminal and a negative terminal, the transformer includes at least a first primary winding and a first secondary winding; the middle layer network includes an upper layer block, a first switch unit block, a middle layer block, and a second switch unit block The lower layer is composed of a top and bottom series; the upper layer has a first terminal and a second terminal, and the first terminal of the upper layer, the positive terminal of the first output capacitor is connected with the positive terminal of the load; The first switch unit block includes at least one or more switch units connected in series above and below, wherein each switch unit includes one switch, each switch has two upper and lower terminals, and the corresponding switches of the two switch units connected in series with the upper and lower sides are respectively connected , but the upper terminal of the upper switch unit is connected to the second terminal of the upper layer; the middle layer block has a first terminal and a second terminal; and the second switch unit block includes at least one or more switch units In series, each of the switch units includes a switch, each switch has two upper and lower terminals, and two switch units can be connected in series with the upper and lower The corresponding switches are respectively connected, but the lower terminal of the lower switching unit is connected with the second terminal of the lower layer; the lower layer has the first terminal and the second terminal, and the lower terminal first terminal, the first a negative terminal of the second output capacitor is connected to the negative terminal of the load; the first switch unit block and the second switch unit block include an equal number of at least one switch unit; The first terminal of the middle layer is connected with the negative terminal of the first output capacitor and the positive terminal of the second output capacitor, the second terminal of the middle layer block, the terminal of the first switch unit of the first switch unit block, and the first terminal The upper terminals of the first switch unit of the two switch unit blocks are connected together, and the transformer includes at least one primary winding, each of the secondary windings being magnetically coupled with the corresponding primary winding in the middle layer network to become at least one A magnetically coupled transformer is provided to provide the DC voltage; thus, the rectifier circuit can convert the AC voltage supplied from the input terminal into a DC voltage by a soft switching mechanism during a switching duty cycle. The rectifier circuit of claim 9, wherein the first terminal and the second terminal of the lower layer block are a short circuit, and the first terminal of the middle layer is The two terminals are a first secondary winding of a transformer, a resonant inductor and a resonant capacitor connected in series. The rectifier circuit of claim 9, wherein the first terminal and the second terminal of the upper layer are a circuit of a first resonant inductance, and the first terminal of the middle layer The two terminals are a first secondary winding of a transformer, and a circuit in which a resonant capacitor is connected in series. The first terminal and the second terminal of the lower layer block are circuits of a second resonant inductor. The rectifier circuit of claim 9, wherein the upper layer is a first secondary winding of a transformer and a first resonant inductor connected in series The first terminal and the second terminal of the middle layer block are a resonant capacitor circuit, and the first terminal and the second terminal of the lower layer block are a second secondary winding of a transformer and a first A circuit in which two resonant inductors are connected in series.