TW201926719A - 具有異質接面的垂直式功率電晶體 - Google Patents

具有異質接面的垂直式功率電晶體 Download PDF

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TW201926719A
TW201926719A TW107141481A TW107141481A TW201926719A TW 201926719 A TW201926719 A TW 201926719A TW 107141481 A TW107141481 A TW 107141481A TW 107141481 A TW107141481 A TW 107141481A TW 201926719 A TW201926719 A TW 201926719A
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power transistor
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里米亞 奧伯托 馬丁納茲
阿爾斐德 葛拉荷
霍格 巴爾托福
史堤方 史瓦格
沃夫岡 費勒
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德商羅伯特博斯奇股份有限公司
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Abstract

本發明提供一種垂直式功率電晶體(100)，其包含：一半導體基板(101)，至少一第一層(102)及一第二層(108)被配置於該半導體基板上，其中該第二層(108)被配置於該第一層(102)上且該第一層(102)包含一第一半導體材料、大量溝槽(103)，該等溝槽自該第二層(108)之一頂側延伸正入該第一層(102)中，使得各溝槽底部由該第一層(102)所封閉，其特徵在於該第一層(102)具有一第一摻雜且各溝槽具有自各別溝槽底部延伸直至一第一高度之一第一區域(112)，其中各第一區域(112)填充有具有一第二摻雜之一第二半導體材料(113)，其中該第一半導體材料與該第二半導體材料(113)不同，其中各第一區域(112)被電連接至該第二層(108)且該第二摻雜高於該第一摻雜，因此異質接面形成於該第一層(102)與各第一區域(112)之間，該等異質接面表現如同單極整流接面。

Description

具有異質接面的垂直式功率電晶體
本發明係關於一種包含大量溝槽之垂直式功率電晶體，其中異質接面形成於溝槽與第一層之間，且該等異質接面表現如同單極整流接面。
在垂直式功率電晶體之狀況下，在功率電晶體之關斷狀態操作中防護閘極氧化物以對抗高場強度係成問題的。此外，限制短路電流係困難的。
先前技術揭示構成閘極氧化物之防護的各種可能性，其方式為使得遵從組件之所設想使用壽命。一個可能性在於在功率電晶體之溝槽結構下方之磊晶層中引入或埋入p摻雜區域。此等p摻雜區域被電連接至功率電晶體之源極區域。由於其在MOS控制頭部下方之位置，該等區域防護MOS控制頭部以避免高場強度且關鍵地促成限制短路電流。其同樣地確保組件之關斷狀態下的最大電場強度被定位在半導體中深處。結果，閘極氧化物處之場強度顯著地被減小，使得組件之使用壽命顯著地得以改良。此外，藉助於深埋式區域，降低通道區域中之場強度，使得避免諸如汲極引發之障壁降低的短通道效應。
此處的缺點係需要額外磊晶層來產生埋式p型區域。此與高成本及其他處理風險相關聯，且亦與高處理複雜度相關聯。此之原因係MOS控制頭部必須精確地與已產生之埋層對準。此係成問題的，原因在於額外磊晶層使第 一磊晶層之在稍後時間點所產生之埋式p摻雜區域所提供的對準標記不可用。
另一可能性在於藉由相對於MOS控制頭部橫向地進行植入來產生深入延伸之p+區域。在此狀況下，此等區域之植入比MOS控制頭部更深，使得防護MOS控制頭部以對抗高場強度。因此，閘極氧化物處之場強度顯著地被降低。此顯著地改良組件之使用壽命。此外，通道區域中之場強度作為結果是被降低，使得避免短通道效應。
此處不利的係高能量及因此高植入遮罩必須使用深度植入，因此引起高成本，且電晶體之單元寬度由於所植入離子之側向擴散而非常大，且由於植入遮罩之高度而產生相對寬之結構。導通電阻由於大單元寬度而增大。
本發明之目標係改良垂直功率電晶體之效能。
一種垂直式功率電晶體包含一半導體基板，至少一第一層及一第二層被配置於該半導體基板上。該第二層被配置於該第一層上且該第一層包含一第一半導體材料。該垂直式功率電晶體包含大量溝槽，該等溝槽自該第二層之一頂側延伸正入該第一層中，使得各溝槽的底部由該第一層所封閉。根據本發明，該第一層具有一第一摻雜。各溝槽具有自各別溝槽的底部延伸直至一第一高度之一第一區域。各第一區域填充有具有一第二摻雜之一第二半導體材料。該第一半導體材料與該第二半導體材料不同。如此意謂具有一不同摻雜類型及一不同摻雜。各第一區域被電連接至該第二層。該第二摻雜高於該第一摻雜，使得異質接面形成於該第一層與各第一區域之間，該等異質接面表現如同單極整流接面。術語單極接面涵蓋蕭特基接面、異質接面、同型異質接面或非同型異質接面。在此狀況下，一傳統蕭特基接面應理解為一金屬半導體接面。在一異質接面之狀況下，兩種不同半導體材料接觸。一同型異質接面應理解為 在使用相同摻雜原子之兩種相同半導體材料之間的一接面。一非同型異質接面應理解為在使用不同摻雜原子之兩種相同半導體材料之間的一接面。在該等單極接面中，僅大部分電荷載子促成電荷載子電流。該等異質接面係整流性的，亦即，取決於所施加電壓之一極性，電流流經該接面，或其起到阻擋之作用，如此因為該第二半導體材料係高度摻雜的。換言之，相對於該第一層形成一能量障壁。該能量障壁取決於該第一層及該第二層之摻雜等級。該能量障壁之絕對值決定之組件之單極本體二極體的順向電壓。異質接面相比於傳統蕭特基接面之一個主要優點係不存在影像電荷，亦即，影像作用力降低。因此，該異質接面在一所施加場的情況下展現能量障壁的不減少。優點係甚至在該異質接面附近存在高阻擋電壓及因此高場強度之情況下，該洩漏電流亦保持獨立於阻擋電壓，因為該障壁不會由於不存在影像電荷而被降低。此外，該垂直式功率電晶體在其操作期間由於本體二極體之低順向電壓而具有低靜態損失。兩個其他技術優點起因於本體二極體之單極性質。首先，一單極本體二極體之接通損失及關斷損失與先前技術中使用之雙極二極體相比顯著地更低。其次，在雙極操作期間可能發生半導體之漂移區域中之電子與電洞的重組。精確地，在所謂寬帶隙半導體之WBG半導體中，此重組能量顯著地高於一傳統Si半導體材料中。因此，在WBG半導體之狀況下的雙極操作可能引起半導體晶體損壞，且因此危及組件之長期穩定性。尤其對於材料SiC，眾所周知在所謂基底面位錯處之電子電洞重組可能引起半導體晶體降級，即，所謂雙極降級。單極二極體因此具有不展現雙極降級之優點。單極二極體具有一低順向電壓及一低反向恢復。
因此，該異質接面具有三個出色屬性：在關斷狀態狀況下之功率電晶體頭部對抗高場強度之防護、在短路狀況下之導電路徑的夾斷，及該功率電晶體之反向操作期間的單極、無降級的本體二極體功能性。
在一個開發中，一第二區域被配置於該第一區域上。該第二區 域至少部分地填充有一金屬。在此狀況下，該金屬被配置於該第二區域之側壁上。
此處有利的係可經由選擇金屬而將肖特基障壁選擇為非常低。結果，可將在該第二區域與該第一層之間的接面處之順向電壓選擇為顯著地低於在該第一區域與該第一層之間的接面處之順向電壓。該第二區域經良好地防護以對抗高電場，使得肖特基障壁之障壁降低為可忽視地小。
在另一組態中，該第一半導體材料相比於該第二半導體材料具有一更大帶隙。此處之優點係反向電流較低。
在一個開發中，該第一摻雜具有小於10^16cm^-3之一摻雜濃度。
在另一組態中，該第二摻雜具有至少10^15cm^-3之一摻雜濃度。
此處之優點係可經由摻雜比率及半導體材料的選擇來產生單極二極體之一低順向電壓。
在一個開發中，該第一摻雜係一n摻雜，且該第二摻雜係一n摻雜或一p摻雜。
在另一組態中，該第二半導體材料包含聚Si、Si或3C-SiC。
在一個開發中，該第一半導體材料包含4H-SiC。
另一優點自以下例示性具體實例之描述或自附屬專利申請專利範圍中顯而易見。
100‧‧‧垂直式功率電晶體
101‧‧‧半導體基板
102‧‧‧第一層
103‧‧‧溝槽
104‧‧‧閘極介電質
105‧‧‧閘極電極
106‧‧‧層
107‧‧‧p+摻雜區域
108‧‧‧第二層
109‧‧‧金屬層
110‧‧‧絕緣層
111‧‧‧汲極金屬化物
112‧‧‧第一區域
113‧‧‧第二半導體材料
200‧‧‧垂直式功率電晶體
204‧‧‧閘極氧化物
212‧‧‧第一區域
213‧‧‧溝槽
214‧‧‧第二區域
300‧‧‧電流/電壓圖
301‧‧‧曲線
302‧‧‧曲線
400‧‧‧帶模型
401‧‧‧異質接面
402‧‧‧傳導帶
403‧‧‧價帶
404‧‧‧傳導帶
405‧‧‧價帶
406‧‧‧費米能階
407‧‧‧能量障壁
500‧‧‧垂直式功率電晶體
504‧‧‧閘極氧化物
505‧‧‧閘極電極
600‧‧‧垂直式功率電晶體
本發明基於較佳具體實例及隨附圖式在下文中加以解釋，其中： 圖1展示包含以電氣方式表現如同單極整流接面之異質接面的垂直式功率電晶體，圖2展示包含以電氣方式表現如同單極整流接面之異質接面的另一垂直式功率電晶體，圖3展示垂直式功率電晶體之IV圖式的第三象限，其中在MOS通道被關閉之情況下操作本體二極體，圖4展示在半導體材料n+ 3C-SiC與n- 4H-SiC之間的異質接面之帶模型，圖5展示包含在功率電晶體頭部旁邊被橫向地配置之異質接面的另一垂直式功率電晶體，且圖6展示包含在功率電晶體頭部旁邊且在功率電晶體頭部下方被橫向地配置之異質接面的另一垂直式功率電晶體。
圖1展示包含表現如同單極整流接面之異質接面的垂直式功率電晶體100。垂直式功率電晶體100包含半導體基板101，至少第一層102及第二層108。第一層102包含第一半導體材料，例如4H-SiC，且具有第一摻雜。第一摻雜包含具有n型電荷載子之低摻雜濃度。摻雜濃度通常小於10^16cm^-3。在此狀況下，第一層102表示磊晶層，且第二層108表示源極區域。表示通道區域之另一層106被配置於第一層102與第二層108之間。通道區域經植入或磊晶生長。舉例而言，源極區域經高度n摻雜，且通道區域經p摻雜。垂直式功率電晶體100包含大量溝槽103。溝槽103各自包含溝槽底部及側壁，且自第二層108之頂側延伸正入第一層102中。換言之，溝槽底部由第一層102所封閉。在此狀況下，溝槽可實質上自第二層108之頂側垂直延伸正入第一層102中。替代地，該等溝槽可相對於第二層108之頂側成非正角，或首先垂直地開始且接著合併至V 結構中。溝槽103具有介於0.5μm與10μm之間的深度。個別溝槽103之間的距離實質上等距且介於0.5μm與10μm之間。溝槽103具有長達5μm之寬度。各溝槽103具有自各別溝槽底部延伸直至第一高度之第一區域112。第一區域112填充有第二半導體材料113，其中第二半導體材料113具有第二摻雜。舉例而言，第二半導體材料係聚Si或3C-SiC。第二摻雜包含具有n型或p型電荷載子之高摻雜濃度。摻雜濃度係至少10^15cm^-3。換言之，填充第一區域112之第二半導體材料113經高度摻雜，且第一半導體材料經輕度摻雜。此外，垂直式功率電晶體100包含閘極介電質104，其將功率電晶體頭部與第二區域108隔絕開。閘極介電質104例如由SiO2所組成。此外，垂直式功率電晶體100包含閘極電極105、p+摻雜區域107、絕緣層110及金屬層109。汲極金屬化物111被配置於半導體基板101之後側上。閘極電極105包含例如摻雜聚Si。第一高度包含在溝槽深度之百分之十與百分之九十之間。排除製造容限，第一高度在個別溝槽103中相同。第一區域112例如藉助於歐姆接觸被電連接至第二層108、p+摻雜區域107及金屬化物109。
圖2展示包含表現如同單極整流接面之異質接面的另一垂直式功率電晶體200。來自圖2之與來自圖1之參考符號具有相同後數字的參考符號指派與圖1中相同之特徵。相比於來自圖1之垂直式功率電晶體100，另一垂直式功率電晶體200另外包含被配置於第一區域212上之第二區域214。亦即，第二區域214被定位於第一區域212與溝槽213中之閘極氧化物204之間。第二區域214至少部分地填充有金屬。在一個例示性具體實例中，金屬被配置於第二區域214之側壁上。在另一例示性具體實例中，第二區域214填充有金屬。舉例而言，金屬包含Ni或Ti。
圖3展示垂直式功率電晶體之電流/電壓圖300的第三象限。曲線301展示來自先前技術之具有雙極本體二極體之垂直式功率電晶體的IV特性。 曲線302展示包含單極異質接面之垂直式功率電晶體的IV特性。曲線302之特徵在於反向操作中之垂直式功率電晶體比來自曲線301之垂直式功率電晶體具有顯著更低之順向電壓。
圖4作為實例展示在半導體n+ 3C-SiC與n- 4H-SiC之間的異質接面401之帶模型400。由於不同晶體形式，該兩種材料可被視為不同半導體材料，使得自3C-SiC至4H-SiC之過渡可被稱作異質接面。在當前狀況下涉及同型異質接面。帶模型400包含半導體材料n+ 3C-SiC之價帶403及傳導帶402、半導體材料n- 4H-SiC之價帶405及傳導帶404，及費米能階406。在異質接面401處，相對於半導體晶體，即，在這裡是n- 4H-SiC，形成能量障壁407。該能量障壁407不展現障壁降低。
圖5展示包含在功率電晶體頭部旁邊經橫向地配置之異質接面的另一垂直式功率電晶體500。在此狀況下，功率電晶體頭部包含閘極氧化物504及閘極電極505。來自圖5之與來自圖1之參考符號具有相同後數字的參考符號指派與圖1中相同之特徵。在功率電晶體頭部之溝槽與具有異質接面之溝槽之間的距離介於0.1μm與10μm之間。
圖6展示包含在功率電晶體頭部旁邊且在功率電晶體頭部下方經橫向地配置之異質接面的另一垂直式功率電晶體600。因此，垂直式功率電晶體包含兩種溝槽類型，一種溝槽類型用於功率電晶體頭部，其具有在MOS控制頭部下方之其他異質接面，且另一種溝槽類型用於異質接面。在此狀況下，具有個別溝槽類型之溝槽深度可變化。溝槽可具有介於0.5μm與20μm之間的深度。來自圖6之與來自圖1之參考符號具有相同後數字的參考符號指派與圖1中相同之特徵。
垂直式功率電晶體包含表現如同單極整流接面的異質接面，而可被用於載具反相器、光伏反相器、牽引驅動器或HVDC傳輸系統中。

Claims (8)

  1. 一種垂直式功率電晶體(100)，其包含：半導體基板(101)，至少第一層(102)及第二層(108)被配置於該半導體基板上，其中該第二層(108)被配置於該第一層(102)上且該第一層(102)包含第一半導體材料，大量溝槽(103)，其自該第二層(108)之頂側延伸正入該第一層(102)中，使得各溝槽的底部由該第一層(102)所封閉，其特徵在於該第一層(102)具有第一摻雜且各溝槽具有自各別溝槽的底部延伸直至第一高度之第一區域(112)，其中各第一區域(112)填充有具有第二摻雜之第二半導體材料(113)，其中該第一半導體材料與該第二半導體材料(113)不同，其中各第一區域(112)被電連接至該第二層(108)且該第二摻雜高於該第一摻雜，因此異質接面形成於該第一層(102)與各第一區域(112)之間，該等異質接面表現如同單極整流接面。
  2. 如請求項1所述之垂直式功率電晶體(100)，其中第二區域(114)被配置於該第一區域(112)上，其中該第二區域(114)至少部分地填充有金屬，且該金屬被配置於該第二區域(114)之側壁上。
  3. 如請求項1及2中任一項所述之垂直式功率電晶體(100)，其中該第一半導體材料相比於該第二半導體材料(113)具有更大帶隙。
  4. 如請求項1及2中任一項所述之垂直式功率電晶體(100)，其中該第一摻雜具有小於10^16cm^-3之摻雜濃度。
  5. 如請求項1及2中任一項所述之垂直式功率電晶體(100)，其中該第二摻雜具有至少10^15cm^-3之摻雜濃度。
  6. 如請求項1及2中任一項所述之垂直式功率電晶體(100)，其中 該第一摻雜係n型摻雜，且該第二摻雜係n型摻雜或p型摻雜。
  7. 如請求項1及2中任一項所述之垂直式功率電晶體(100)，其中該第二半導體材料(113)包含Si或3C-SiC。
  8. 如請求項1及2中任一項所述之垂直式功率電晶體(100)，其中該第一半導體材料包含4H-SiC。
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