TW201919130A - Pixel structure, mathod for manufacturing semiconductor structure and mathod for manufacturing semiconductor element - Google Patents

Abstract

A method for manufacturing a semiconductor structure includes the following steps. An oxide semiconductor material layer including a main portion and an auxiliary portion connected to the main portion is formed. A first insulating material layer is formed on the oxide semiconductor material layer. A portion of the first insulating material layer and the auxiliary portion are removed to form a first insulating layer and an active layer, wherein the portion of the first insulating material layer that is removed at least overlaps the dummy portion.

Description

Pixel structure, manufacturing method of semiconductor structure, and manufacturing method of semiconductor element

The present invention relates to a pixel structure, a method for manufacturing a semiconductor structure, and a method for manufacturing a semiconductor element, and more particularly, to a pixel structure, a method for manufacturing a semiconductor structure, and a method for manufacturing a semiconductor element using an oxide semiconductor.

In recent years, the technology of manufacturing thin film transistors (TFTs) using oxide semiconductor films has attracted much attention. In the manufacturing process, a plasma process (such as PECVD) is often used to form a protective layer of the thin film transistors. However, the protective layer formed by the plasma process is often rich in hydrogen ions. Once excessive hydrogen ions diffuse into the oxide semiconductor thin film, the gate voltage of the thin film transistor will be shifted to a negative direction, thereby reducing the thin film transistor. Performance.

One of the objectives of the present invention is to prevent excessive diffusion of hydrogen ions into the channel region.

According to an aspect of the present invention, a method for manufacturing a semiconductor structure is provided, including the following steps. An oxide semiconductor material layer is formed. The oxide semiconductor material layer includes a main body portion and an auxiliary portion, and the auxiliary portion is connected to the main body portion. A first insulating material layer is formed on the oxide semiconductor material layer. A portion of the first insulating material layer and the auxiliary portion are removed to form a first insulating layer and an active layer, and the removed portion of the first insulating material layer at least overlaps the auxiliary portion.

According to an aspect of the present invention, a method for manufacturing a semiconductor device is provided, including the following steps. An oxide semiconductor material layer is formed. The oxide semiconductor material layer includes a main body portion and an auxiliary portion, and the auxiliary portion is connected to the main body portion. A gate electrode is formed to overlap the main body portion. A first insulating material layer is formed on the oxide semiconductor material layer. A portion of the first insulating material layer and the auxiliary portion are removed to form a first insulating layer and an active layer, and the removed portion of the first insulating material layer at least overlaps the auxiliary portion. A source and a drain are formed on the first insulating layer, and are electrically connected to a source region and a drain region of the active layer, respectively.

According to an aspect of the present invention, a pixel structure is provided, including an active layer, a first insulating layer, a gate insulating layer, a gate, a source and a drain, and a pixel electrode. The active layer includes a source region, a channel region, and a drain region. The first insulating layer is disposed on the active layer and is in contact with the active layer. The horizontal distance between the edge of the first insulating layer and the edge of the active layer is about 0 micrometers to 5 micrometers. The gate insulation layer is located between the gate and the active layer. The source electrode and the drain electrode are disposed on the first insulation layer, and are electrically connected to the source region and the drain region, respectively. The pixel electrode is electrically connected to the drain electrode.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail below in conjunction with the accompanying drawings:

The following is a detailed description of various embodiments. The present invention does not show all possible embodiments, and other implementation modes not provided in the present invention can also be applied. Moreover, the dimensional proportions in the drawings are not drawn according to the actual products. Therefore, the contents of the description and the drawings are only used to describe the embodiments, but not to limit the scope of protection of the present invention. In addition, some elements in the drawings in the embodiments are omitted to clearly show the technical features of the present invention. The following uses the same / similar symbols to indicate the same / similar elements or steps for explanation.

Please refer to FIG. 1, which is a partial plan view of an array substrate 1 according to an embodiment of the present invention. The array substrate 1 includes a substrate 10 and a pixel array PA. The pixel array PA includes a plurality of pixel structures P1 arranged in an array and formed on the substrate 10. Here, the 1 × 3 pixel structure P1 is taken as an example, but it is not necessary to limit the present invention.

FIG. 2A is a plan view of a first mask process in a method of manufacturing a pixel structure P1 according to an embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along a tangent line 2B-2B 'of FIG. 2A. Please refer to FIG. 2A and FIG. 2B at the same time. The manufacturing method of this embodiment may first form an oxide semiconductor material layer 110 on the substrate 10, and the oxide semiconductor material layer 110 may be manufactured by using a first mask process. . For example, a deposition process such as physical vapor deposition, chemical vapor deposition, sputtering, or the like may be performed first to form a whole layer of oxide semiconductor material on the substrate 10. Next, a first photomask (not shown) may be used to perform a lithographic etching process to pattern the entire oxide semiconductor material to form an oxide semiconductor material layer 110.

In this embodiment, the oxide semiconductor material layer may include a material selected from the group consisting of indium tin oxide (IZO), indium-tin-zinc oxide (ITZO), and indium gallium oxide. , IGO), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), zinc oxide (ZnO), tin oxide (SnO), gallium zinc oxide (Gallium-Zinc Oxide, GZO ), At least one of the group consisting of Zinc-Tin Oxide (ZTO) and Indium-Tin Oxide (ITO).

As shown in FIG. 2A, the oxide semiconductor material layer 110 includes a main body portion 112 and an auxiliary portion 114 connected to the main body portion 112. The area of the main body portion 112 may be an area where the active layer is finally formed. For example, in this embodiment, the oxide semiconductor material layer 110 can be patterned by the first photomask to define a single-channel active layer and its channel width W. In another embodiment, the oxide semiconductor material layer can be patterned by the first mask to define a multi-channel active layer and its channel width.

FIG. 3A is a plan view of a second mask process in the method of manufacturing the pixel structure P1 according to an embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along a tangent line 3B-3B ′ of FIG. 3A. Please refer to FIG. 3A and FIG. 3B at the same time. After the above-mentioned first mask process, a second mask process may be used to form a gate insulating layer 120 and a first metal layer 130 on the oxide semiconductor material layer 110. . First, a gate insulating material layer can be formed on the oxide semiconductor material layer 110 by a deposition process commonly used in the art, and a first metal material layer can be formed on the gate insulating material layer. Then, a second photomask (not shown) can be used to perform a lithographic etching process to pattern the gate insulating material layer and the first metal material layer together to form the gate insulating layer 120 and the first metal layer 130. In this embodiment, the first metal layer 130 may include a gate electrode 132 and a scan line 134. The gate electrode 132 may extend from the scanning line 134 and overlap the main body portion 112.

4A-1 are plan views of a third mask process in the method of manufacturing the pixel structure P1 according to an embodiment of the present invention, and FIG. 4B is a cross-sectional view of the structure in which the first insulating material layer 140 is formed in FIG. 3B. Figure 4C is a cross-sectional view taken along the line 4C-4C 'of Figures 4A-1. Please refer to FIG. 4A-1, FIG. 4B, and FIG. 4C at the same time. After the above-mentioned second mask process, the third mask process may be used to form the first insulating layer 140 'and the active layer 112'. First, an entire first insulating material layer 140 can be formed on the oxide semiconductor material layer 110 and the first metal layer 130 by a deposition process (such as PECVD) commonly used in the art, as shown in FIG. 4B. Next, a lithographic etching process may be performed through a third photomask (not shown) to pattern the first insulating material layer 140 and the oxide semiconductor material layer 110 together, thereby removing a portion of the first insulating material layer 140 and the oxide. The auxiliary portion 114 of the semiconductor material layer 110 forms a first insulating layer 140 'and an active layer 112'. Here, the formed first insulating layer 140 'and the active layer 112' can be substantially aligned with each other in the channel length direction D1. Further, the edge of the first insulating layer 140 'and the edge of the active layer 112' may be separated from each other by a horizontal distance of about 0 micrometers to 5 micrometers, preferably 0 micrometers, that is, the edge of the active layer 112 'and the adjacent layer. The edges of the first insulating layer 140 'are aligned.

In this embodiment, a portion of the first insulating material layer 140 that overlaps with the auxiliary portion 114 but does not overlap with the first metal layer 130 is removed. As shown in FIG. 4A-1, after the third mask process is performed, the first insulating layer 140 'is still covered on the scan lines 134 and the gate electrodes 132. Thereby, the gate electrode 132 can be protected by the first insulating layer 140 'to prevent the gate electrode 132 from being damaged in the subsequent manufacturing process.

In another embodiment, please refer to FIGS. 4A-2, which are top views of a third mask process in a method of manufacturing a pixel structure P2 according to another embodiment of the present invention. In addition, the sectional views of FIGS. 4B and 4C can also be applied to the embodiments of FIGS. 4A-2. As shown in Figs. 4A-2, the removed portion of the first insulating material layer 140 'overlaps with the auxiliary portion 114 before the removal, and also overlaps with the scanning line 134, that is, after the third mask process is performed, The first insulating layer 140 ′ may not cover the scan lines 134.

In this embodiment, a material of the first insulating material layer 140 may be silicon nitride (SiNx). Since the first insulating material layer 140 formed by the PECVD process is rich in hydrogen ions, these hydrogen ions will diffuse into the oxide semiconductor material layer 110, so that the area of the oxide semiconductor material layer 110 that is in contact with the first insulating material layer 140 The resistance value is reduced to form n + low-conductivity doping (ie, the doped auxiliary portion 114 'and the body portion are doped regions). These low-conductivity doped regions can be used as the active layer 112'. The source region 112'a and the drain region 112'b are used. However, once excessive hydrogen ions are further laterally diffused into the channel region 112'c, it may have an adverse effect on the semiconductor structure. Referring to FIG. 4C, by further removing the doped auxiliary portion 114 ′ and a portion of the first insulating material layer 140 overlapping the doped auxiliary portion 114 ′, it is possible to effectively prevent excessive hydrogen ions from diffusing into the channel region 112. 'c. In this step, the remaining doped regions of the main body are used as the source region 112'a and the drain region 112'b of the active layer 112 ', respectively.

In this embodiment, the auxiliary portion 114 can absorb excess hydrogen ions, so that the overall hydrogen content of the first insulating material layer 140 is reduced. Therefore, after part of the first insulating material layer 140 and the doped auxiliary portion 114 'are removed, excessive hydrogen ions can be prevented from further diffusing into the channel region 112'c.

FIG. 5A is a plan view of a fourth mask process in the method of manufacturing the pixel structure P1 according to an embodiment of the present invention, and FIG. 5B-1 is a cross-sectional view taken along a tangent line 5B-5B ′ of FIG. 5A. Please refer to FIG. 5A and FIG. 5B-1 at the same time. After the third mask process described above, a fourth mask process may be adopted to form two first openings H1 in the first insulating layer 140 ', and the first openings H1. The source region 112'a and the drain region 112'b of the active layer 112 'are respectively exposed.

5B-2 are cross-sectional views of a pixel structure P3 of another embodiment using the fourth mask process in the manufacturing method of FIG. 5A. Please refer to FIG. 5B-2. In other embodiments, the fourth mask process may include forming a second insulating layer 142 to cover the first insulating layer 140 ', the active layer 112' and the substrate 10, and by using the first Four photomasks (not shown) perform a lithographic etching process to form two first openings H1 in the first insulating layer 140 'and the second insulating layer 142, and the first openings H1 respectively expose the source of the active layer 112'. The polar region 112'a and the drain region 112'c.

In this embodiment, the material of the second insulating layer 142 may be silicon oxide (SiOx), wherein the hydrogen concentration of the second insulating layer 142 may be lower than the hydrogen concentration of the first insulating layer 140 ′ to prevent the excess hydrogen ions from further Diffusion into the channel region 112'c.

FIG. 6A is a plan view of a fifth mask process in the method of manufacturing the pixel structure P1 according to an embodiment of the present invention, and FIG. 6B-1 is a cross-sectional view taken along a tangent line 6B-6B ′ of FIG. 6A. Please refer to FIG. 6A and FIG. 6B-1 at the same time. After the fourth mask process, the fifth mask process may be used to form the second metal layer 150 on the first insulating layer 140 '. In this embodiment, the second metal layer 150 may include a source electrode 152, a data line 154, a common electrode 156, and a common electrode line 158. The extending direction of the data line 154 and the common electrode line 158 may be perpendicular to the extending direction of the scanning line 134. The source electrode 152 may extend from the data line 154 and is electrically connected to the source region 112'a of the active layer 112 'through the first opening H1. The common electrode 156 is electrically connected to the common electrode line 158.

6B-2 are cross-sectional views of a pixel structure P3 of another embodiment using the fifth mask process in the manufacturing method of FIG. 6A. Please refer to FIG. 6B-2, which is an embodiment continuing from 5B-2. Here, the fifth mask process may include forming a source electrode 152 and a common electrode 156 on the second insulating layer 142, and the source electrode 152 is electrically connected to the source region 112'a of the active layer 112 'through the first opening H1. connection.

FIG. 7A is a plan view of a sixth mask process in a method of manufacturing a pixel structure P1 according to an embodiment of the present invention, and FIG. 7B-1 is a cross-sectional view taken along a tangent line 7B-7B 'of FIG. 7A. Please refer to FIG. 7A and FIG. 7B-1 at the same time. After the fifth mask process, a flat layer 160 can be formed to cover the substrate 10, the first insulating layer 140 ', the source electrode 152, and the common electrode 156. A sixth photomask process is used to form a second opening H2 in the flat layer 160, wherein the second opening H2 corresponds to the first opening H1 to expose the drain region 112'b of the active layer 112 '.

7B-2 are cross-sectional views of a pixel structure P3 of another embodiment using the sixth mask process in the manufacturing method of FIG. 7A. Please refer to FIG. 7B-2, which is an embodiment continuing from FIG. 6B-2. Here, the sixth mask process may include forming a flat layer 160 to cover the second insulating layer 142, the source electrode 152, and the common electrode 156, and a lithography etching process through a sixth mask (not shown). In order to form a second opening H2 in the flat layer 160, the second opening H2 corresponds to the first opening H1 to expose the drain region 112'b of the active layer 112 '.

FIG. 8A is a plan view of a seventh mask process in the method of manufacturing the pixel structure P1 according to an embodiment of the present invention, and FIG. 8B-1 is a cross-sectional view taken along a tangent line 8B-8B 'of FIG. 8A. Please refer to FIG. 8A and FIG. 8B-1 at the same time. After the sixth photomask process, a seventh photomask process may be used to form a pixel electrode 170 on the flat layer 160. The pixel electrode 170 may be electrically connected to the drain region 112'b of the active layer 112 'through the second opening H2 and the first opening H1 to complete the pixel structure P1. In addition, the pixel electrode 170 may at least partially overlap the common electrode 156 to form a storage capacitor between the pixel electrode 170 and the common electrode 156. In addition, the drain region 112'b may at least partially overlap the common electrode 156 to Form another storage capacitor.

8B-2 are cross-sectional views of a pixel structure P3 of another embodiment using the seventh mask process in the manufacturing method of FIG. 8A. Please refer to FIG. 8B-2, which is an embodiment continuing from FIG. 7B-2. Here, the seventh mask process may include forming a pixel electrode 170 on the flat layer 160, and the pixel electrode 170 further penetrates the second opening H2 and the first opening H1 and communicates with the drain region 112'b of the active layer 112 '. Electrically connected to complete the pixel structure P3. In addition, the pixel electrode 170 may at least partially overlap the common electrode 156 to form a storage capacitor between the pixel electrode 170 and the common electrode 156. In addition, the drain region 112'b may at least partially overlap the common electrode 156 to Form another storage capacitor.

In the above embodiment, the pixel electrode 170 can be used as a drain at the same time, and is directly electrically connected to the drain region 112'b of the active layer 112 '. However, in other embodiments, the drain electrode and the drain region of the active layer may be electrically connected first, and then the pixel electrode and the drain electrode may be electrically connected. For example, in the embodiments shown in FIGS. 6A, 6B-1, and 6B-2, the second metal layer 150 manufactured by the fifth photomask process may further include a drain electrode, and the drain electrode is active through the first opening H1. The drain region 112'b of the layer 112 'is electrically connected.

The manufacturing method of the above embodiment uses the pixel structures P1, P2, and P3 of the thin-film transistor designed by the top gate as an example. The auxiliary portion 114 can absorb excess hydrogen ions, and the auxiliary portion 114 is absorbing excess After that, the hydrogen ions can be further removed to prevent excessive hydrogen ions from diffusing into the channel region 112'c. However, the present invention is not limited to this. In other embodiments, the same concept can also be applied to the pixel structure of a thin-film transistor with a bottom gate design, which will be further described below.

FIG. 9A is a plan view of a first mask process in a method of manufacturing a pixel structure P4 according to another embodiment of the present invention, and FIG. 9B is a cross-sectional view taken along a line 9B-9B ′ of FIG. 9A. Please refer to FIG. 9A and FIG. 9B at the same time. In the manufacturing method of this embodiment, a first mask process can be used to form a first metal layer 130 on the substrate 10. In this embodiment, the first metal layer 130 may include a gate electrode 132 and a scan line 134. The gate electrode 132 may extend from the scan line 134.

FIG. 10A is a plan view of a second mask process in a method of manufacturing a pixel structure P4 according to another embodiment of the present invention, and FIG. 10B is a cross-sectional view taken along a tangent line 10B-10B ′ of FIG. Please refer to FIG. 10A and FIG. 10B at the same time. After the above-mentioned first mask process, a gate insulating layer 120 may be formed on the substrate 10 first, and then an oxide semiconductor material layer 110 may be formed on the gate insulating layer 120. In addition, the oxide semiconductor material layer 110 can be fabricated by a second mask process.

As shown in FIG. 10A, the oxide semiconductor material layer 110 includes a main body portion 112 and an auxiliary portion 114 connected to the main body portion 112. The area of the main body portion 112 may be an area where the active layer is finally formed.

11A-1 are plan views of a third mask process in a method of manufacturing a pixel structure P4 according to another embodiment of the present invention, and FIG. 11B is a cross-sectional view taken along a line 11B-11B ′ of FIG. 11A-1. Please refer to FIGS. 11A-1 and 11B at the same time. After the above-mentioned second mask process, a third mask process may be used to form a protective layer 180 on the oxide semiconductor material layer 110. The protective layer 180 is formed on the main body portion 112 and contacts the main body portion 112, and overlaps the gate electrode 132.

12A-1 are plan views of a fourth photomask process in a method of manufacturing a pixel structure P4 according to another embodiment of the present invention, and FIG. 12B is a cross-sectional view of the structure in which the first insulating material layer 140 is formed in FIG. 11B. Fig. 12C is a sectional view taken along line 12C-12C 'of Fig. 12A-1. Please refer to FIGS. 12A-1, 12B, and 12C at the same time. After the third photomask process, a fourth photomask process may be used to form a first insulating layer 140 'and an active layer 112'. First, an entire first insulating material layer 140 can be formed on the oxide semiconductor material layer 110 and the protective layer 180 by a deposition process (such as PECVD) commonly used in the art. Then, a lithography etching process may be performed through a fourth photomask (not shown) to collectively pattern the first insulating material layer 140 and the oxide semiconductor material layer 110, and then partially remove the first insulating material layer 140 and the oxide. The auxiliary portion 114 of the semiconductor material layer 110 forms a first insulating layer 140 'and an active layer 112'. Here, the formed first insulating layer 140 'and the active layer 112' can be substantially aligned with each other in the channel length direction D1. Further, the edge of the first insulating layer 140 'and the edge of the active layer 112' may be separated from each other by a horizontal distance of about 0 micrometers to 5 micrometers, preferably 0 micrometers, that is, the edge of the active layer 112 'and the adjacent layer. The edges of the first insulating layer 140 'are aligned.

In this embodiment, a material of the first insulating material layer 140 may be silicon nitride (SiNx). Please refer to FIG. 12B. Since the first insulating material layer 140 formed by the PECVD process is rich in hydrogen ions, these hydrogen ions can diffuse into the oxide semiconductor material layer 110, so that the oxide semiconductor material layer 110 and the first insulating material The resistance of the areas where the layer 140 is in contact is reduced to form n + low-conductivity doped regions (ie, the regions where the doped auxiliary portion 114 'and the body portion are doped). These low-conductivity doped regions may be sufficient. The source region 112'a and the drain region 112'b are used as the active layer 112 '. Moreover, referring to FIG. 12C, by further removing the doped auxiliary portion 114 'and a portion of the first insulating material layer 140 overlapping the doped auxiliary portion 114', it is possible to effectively prevent excessive hydrogen ions from diffusing into the channel. Within zone 112'c. In this step, the remaining doped regions of the main body are used as the source region 112'a and the drain region 112'b of the active layer 112 ', respectively.

In this embodiment, the auxiliary portion 114 can absorb excess hydrogen ions, so that the overall hydrogen content of the first insulating material layer 140 is reduced. Therefore, after part of the first insulating material layer 140 and the doped auxiliary portion 114 ′ are removed, the hydrogen concentration of the first insulating layer 140 ′ may be lower than that of the first insulating material layer 140 to avoid excessive The hydrogen ions further diffuse into the channel region 112'c. In addition, the material of the protective layer 180 may be silicon oxide (SiOx), wherein the hydrogen concentration of the protective layer 180 may be lower than the hydrogen concentration of the first insulating layer 140 'to prevent the excess hydrogen ions from further diffusing into the channel region 112'c .

In the embodiments shown in FIGS. 10A, 11A-1, and 12A-1, the oxide semiconductor material layer 110 is patterned first, and then a protective layer 180 is formed on the oxide semiconductor material layer 110. However, the present invention is not limited to this.

Please refer to FIGS. 11A-2 and 12A-2 at the same time, which are top views of the second mask process and the third mask process in the manufacturing method of the pixel structure P5 according to another embodiment of the present invention, respectively. In addition, FIG. 11B is applicable to the embodiment of FIGS. 11A-2, and the cross-sectional views of FIGS. 12B and 12C are also applicable to the embodiment of FIGS. 12A-2. In this embodiment, the oxide semiconductor material layer 110 may not be patterned by the second mask process first, and the second mask process is only used to form a protective material layer 181 on the oxide semiconductor material layer 110 and communicate with the gate. The poles 132 overlap. Next, in the third mask process step, a third mask (not shown) is used to pattern the first insulating material layer 140, the oxide semiconductor material layer 110, and the protective material layer 181 to form a first insulating layer. 140 ', an active layer 112', and a protective layer 180. Therefore, compared with the manufacturing method of the pixel structure P4, the manufacturing method of the pixel structure P5 in this embodiment can reduce at least one photomask manufacturing process.

FIG. 13A is a plan view of a fifth mask process in a method of manufacturing a pixel structure P4 according to another embodiment of the present invention, and FIG. 13B-1 is a cross-sectional view taken along a tangent line 13B-13B ′ of FIG. 13A. After the fourth photomask process described above, a fifth photomask process may be used to form two first openings H1 in the first insulating layer 140 '. The first openings H1 respectively expose the source regions 112' of the active layer 112 '. a and the drain region 112'b.

13B-2 are cross-sectional views of a pixel structure P6 of another embodiment using a fifth mask process in the manufacturing method of FIG. 13A. Please refer to FIG. 13B-2. In other embodiments, the fifth mask process may include forming a second insulating layer 142 to cover the first insulating layer 140 ', the active layer 112' and the gate insulating layer 120, and borrowing A lithographic etching process is performed by a fifth photomask (not shown) to form two first openings H1 in the first insulating layer 140 'and the second insulating layer 142, and the first openings H1 respectively expose the active layer 112'. Source region 112'a and drain region 112'c.

In this embodiment, the material of the second insulating layer 142 may be silicon oxide (SiOx), wherein the hydrogen concentration of the second insulating layer 142 may be lower than the hydrogen concentration of the first insulating layer 140 ′ to prevent the excess hydrogen ions from further Diffusion into the channel region 112'c.

FIG. 14A is a plan view of a sixth mask process in a method of manufacturing a pixel structure P4 according to another embodiment of the present invention, and FIG. 14B-1 is a cross-sectional view taken along a tangent line 14B-14B ′ of FIG. 14A. Please refer to FIG. 14A and FIG. 14B-1 at the same time. After the fifth photomask process, a sixth photomask process may be used to form a second metal layer 150 on the first insulating layer 140 '. In this embodiment, the second metal layer 150 may include a source electrode 152, a data line 154, a common electrode 156, and a common electrode line 158. The extension direction of the data line 154 and the common electrode line 158 is perpendicular to the extension direction of the scan line 134. The source electrode 152 may extend from the data line 154 and is electrically connected to the source region 112'a of the active layer 112 'through the first opening H1. The common electrode 156 is electrically connected to the common electrode line 158.

14B-2 are cross-sectional views of a pixel structure P6 of another embodiment using a sixth mask process in the manufacturing method of FIG. 14A. Please refer to FIG. 14B-2, which is an embodiment continuing from 13B-2. Here, the sixth mask process may include forming a source electrode 152 and a common electrode 156 on the second insulating layer 142, and the source electrode 152 is electrically connected to the source region 112'a of the active layer 112 'through the first opening H1. connection.

FIG. 15A is a plan view of a seventh mask process in a method of manufacturing a pixel structure P4 according to another embodiment of the present invention, and FIG. 15B-1 is a cross-sectional view taken along a tangent line 15B-15B ′ of FIG. 15A. Please refer to FIGS. 15A and 15B-1 at the same time. After the sixth photomask process, a flat layer 160 may be formed to cover the gate insulating layer 120, the first insulating layer 140 ′, the source electrode 152, and the common electrode 156. Then, a seventh photomask process is used to form a second opening H2 in the flat layer 160, wherein the second opening H2 corresponds to the first opening H1 to expose the drain region 112'b of the active layer 112 '.

15B-2 are cross-sectional views of a pixel structure P6 of another embodiment using the seventh mask process in the manufacturing method of FIG. 15A. Please refer to FIG. 15B-2, which is an embodiment continuing from FIG. 14B-2. Here, the seventh mask process may include forming a flat layer 160 to cover the second insulating layer 142, the source electrode 152, and the common electrode 156, and a lithography etching process by a seventh mask (not shown). In order to form a second opening H2 in the flat layer 160, the second opening H2 corresponds to the first opening H1 to expose the drain region 112'b of the active layer 112 '.

FIG. 16A is a plan view of an eighth mask process in a method of manufacturing a pixel structure P4 according to another embodiment of the present invention, and FIG. 16B-1 is a cross-sectional view taken along a tangent line 16B-16B ′ of FIG. 16A. Please refer to FIG. 16A and FIG. 16B-1 at the same time. After the seventh mask process, the eighth mask process may be used to form a pixel electrode 170 on the flat layer 160. The pixel electrode 170 may be electrically connected to the drain region 112'b of the active layer 112 'through the second opening H2 and the first opening H1 to complete the pixel structure P4. In addition, the pixel electrode 170 may at least partially overlap the common electrode 156 to form a storage capacitor between the pixel electrode 170 and the common electrode 156. In addition, the drain region 112'b may at least partially overlap the common electrode 156 to Form another storage capacitor.

16B-2 are cross-sectional views of a pixel structure P6 of another embodiment using the eighth mask process in the manufacturing method of FIG. 16A. Please refer to FIG. 16B-2, which is an embodiment continuing from FIG. 15B-2. Here, the eighth mask process may include forming a pixel electrode 170 on the flat layer 160, and the pixel electrode 170 further passes through the second opening H2 and the first opening H1 and communicates with the drain region 112 'of the active layer 112'. b is electrically connected to complete the pixel structure P6. In addition, the pixel electrode 170 may at least partially overlap the common electrode 156 to form a storage capacitor between the pixel electrode 170 and the common electrode 156. In addition, the drain region 112'b may at least partially overlap the common electrode 156 to Form another storage capacitor.

In the above various embodiments, the pixel electrode 170 is used as a drain electrode, and is directly electrically connected to the drain region 112'b of the active layer 112 '. However, in other embodiments, the drain electrode and the drain region of the active layer may be electrically connected first, and then the pixel electrode and the drain electrode may be electrically connected. For example, in the embodiments shown in FIGS. 6A, 6B-1, and 6B-2, the second metal layer 150 manufactured by the fifth photomask process may further include a drain electrode, and the drain electrode is active through the first opening H1. The drain region 112'b of the layer 112 'is electrically connected. In the embodiment shown in FIGS. 14A, 14B-1, and 14B-2, the second metal layer 150 manufactured by the sixth mask process may further include a drain electrode, and the drain electrode communicates with the active layer through the first opening H1. The drain region 112'b of 112 'is electrically connected.

In the manufacturing method of the pixel structure P1 to P6 provided in the above embodiment, the gate electrode 132, the source electrode 152, the drain electrode (or the pixel electrode 170), and the active layer 112 'constitute a thin film transistor, which is used as the pixel structure. Active element driving a display medium. However, the present invention is not limited to an active element with a pixel structure, and may also be an active element of a gate driver on array (GOA) in a circuit area.

Further, the gate electrode 132 formed in the above embodiment can also be electrically connected to the source electrode 152, so the same concept can be applied to the diode element.

In various embodiments provided above, through the arrangement of the auxiliary portion, excess hydrogen ions can be absorbed, and the auxiliary portion can be further removed after absorbing the excess hydrogen ions to prevent excessive hydrogen ions from diffusing into the channel area.

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

1‧‧‧ array substrate

10‧‧‧ substrate

110‧‧‧oxide semiconductor material layer

112‧‧‧Main body

112’‧‧‧Active layer

112’a‧‧‧ source region

112’b‧‧‧ Drain

112’c‧‧‧passage zone

114‧‧‧Auxiliary Department

114’‧‧‧ Auxiliary Department

120‧‧‧Gate insulation

130‧‧‧first metal layer

132‧‧‧Gate

134‧‧‧scan line

140‧‧‧first insulating material layer

140’‧‧‧first insulation layer

142‧‧‧Second insulation layer

150‧‧‧Second metal layer

152‧‧‧Source

154‧‧‧data line

156‧‧‧Common electrode

158‧‧‧Common electrode wire

160‧‧‧ flat layer

170‧‧‧pixel electrode

180‧‧‧ protective layer

181‧‧‧ protective material layer

D1‧‧‧Channel length direction

H1‧‧‧First opening

H2‧‧‧Second opening

P1, P2, P3, P4, P5, P6 ‧‧‧ pixel structure

PA‧‧‧Pixel Array

W‧‧‧channel width

FIG. 1 is a partial plan view of an array substrate according to an embodiment of the present invention. FIG. 2A is a top view of a first mask process in a method of manufacturing a pixel structure according to an embodiment of the present invention. Fig. 2B is a cross-sectional view taken along a tangent line 2B-2B 'in Fig. 2A. FIG. 3A is a plan view of a second mask process in a method of manufacturing a pixel structure according to an embodiment of the present invention. Fig. 3B is a cross-sectional view taken along a tangent line 3B-3B 'in Fig. 3A. FIG. 4A-1 is a top view of a third mask process in a method of manufacturing a pixel structure according to an embodiment of the present invention, and FIG. 4A-2 is a third diagram of a light process in a method of manufacturing a pixel structure according to another embodiment of the present invention Top view of the hood process. FIG. 4B is a cross-sectional view of the structure in which the first insulating material layer is formed in FIG. 3B. Fig. 4C is a cross-sectional view taken along a tangent line 4C-4C 'in Figs. 4A-1 or 4A-2. FIG. 5A is a plan view of a fourth mask process in a method of manufacturing a pixel structure according to an embodiment of the present invention. Fig. 5B-1 is a sectional view taken along a tangent line 5B-5B 'in Fig. 5A. 5B-2 are cross-sectional views of a pixel structure of another embodiment using a fourth mask process in the manufacturing method of FIG. 5A. FIG. 6A is a plan view of a fifth mask process in a method of manufacturing a pixel structure according to an embodiment of the present invention. Fig. 6B-1 is a sectional view taken along a tangent line 6B-6B 'in Fig. 6A. 6B-2 are cross-sectional views of a pixel structure of another embodiment using the fifth mask process in the manufacturing method of FIG. 6A. FIG. 7A is a plan view of a sixth mask process in a method of manufacturing a pixel structure according to an embodiment of the present invention. Fig. 7B-1 is a cross-sectional view taken along the line 7B-7B 'of Fig. 7A. 7B-2 are cross-sectional views of a pixel structure of another embodiment using a sixth mask process in the manufacturing method of FIG. 7A. FIG. 8A is a plan view of a seventh mask process in a method of manufacturing a pixel structure according to an embodiment of the present invention. Fig. 8B-1 is a sectional view taken along line 8B-8B 'of Fig. 8A. 8B-2 are cross-sectional views of a pixel structure of another embodiment using a seventh mask process in the manufacturing method of FIG. 8A. FIG. 9A is a top view of a first mask process in a method of manufacturing a pixel structure according to another embodiment of the present invention. Fig. 9B is a cross-sectional view taken along the line 9B-9B 'of Fig. 9A. FIG. 10A is a top view of a second mask process in a method of manufacturing a pixel structure according to another embodiment of the present invention. Fig. 10B is a cross-sectional view taken along the line 10B-10B 'of Fig. 10A. 11A-1 is a top view of a third mask process in a method of manufacturing a pixel structure according to another embodiment of the present invention, and FIG. 11A-2 is a second view of a method of manufacturing a pixel structure according to another embodiment of the present invention Top view of the mask process. Fig. 11B is a cross-sectional view taken along the line 11B-11B 'of Figs. 11A-1 or 11A-2. 12A-1 is a plan view of a fourth mask process in a method of manufacturing a pixel structure according to another embodiment of the present invention, and FIG. 12A-2 is a third view of a method of manufacturing a pixel structure according to another embodiment of the present invention Top view of the mask process. FIG. 12B is a cross-sectional view of the structure in which the first insulating material layer is formed in FIG. 11B. Fig. 12C is a cross-sectional view taken along a tangent line 12C-12C 'in Figs. 12A-1 or 12A-2. FIG. 13A is a plan view of a fifth mask process in a method of manufacturing a pixel structure according to another embodiment of the present invention. Fig. 13B-1 is a sectional view taken along the tangent line 13B-13B 'of Fig. 13A. 13B-2 are cross-sectional views of a pixel structure of another embodiment using a fifth mask process in the manufacturing method of FIG. 13A. FIG. 14A is a plan view of a sixth mask process in a method of manufacturing a pixel structure according to another embodiment of the present invention. Fig. 14B-1 is a cross-sectional view taken along line 14B-14B 'of Fig. 14A. 14B-2 are cross-sectional views of a pixel structure of another embodiment using a sixth mask process in the manufacturing method of FIG. 14A. FIG. 15A is a top view of a seventh mask process in a method of manufacturing a pixel structure according to another embodiment of the present invention. Fig. 15B-1 is a cross-sectional view taken along line 15B-15B 'of Fig. 15A. 15B-2 are cross-sectional views of a pixel structure of another embodiment using a seventh mask process in the manufacturing method of FIG. 15A. FIG. 16A is a plan view of an eighth mask process in a method of manufacturing a pixel structure according to another embodiment of the present invention. Fig. 16B-1 is a sectional view taken along the tangent line 16B-16B 'of Fig. 16A. 16B-2 are cross-sectional views of a pixel structure of another embodiment using the eighth mask process in the manufacturing method of FIG. 16A.

Claims (18)

A method for manufacturing a semiconductor structure includes: forming an oxide semiconductor material layer, the oxide semiconductor material layer including: a main body portion; and an auxiliary portion connected to the main body portion; forming a first insulating material layer on the oxide A semiconductor material layer; and removing a portion of the first insulating material layer and the auxiliary portion to form a first insulating layer and an active layer, wherein the removed portion of the first insulating material layer at least overlaps the auxiliary portion . The manufacturing method according to item 1 of the scope of patent application, wherein a hydrogen concentration of the first insulating layer is lower than a hydrogen concentration of the first insulating material layer. The manufacturing method according to item 1 of the patent application scope, wherein the oxide semiconductor material layer comprises a material selected from the group consisting of indium tin oxide (IZO), indium-tin-zinc oxide (ITZO) , Indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), zinc oxide (ZnO), tin oxide (SnO), gallium oxide At least one of the group consisting of Gallium-Zinc Oxide (GZO), Zinc-Tin Oxide (ZTO) and Indium-Tin Oxide (ITO). A method for manufacturing a semiconductor element includes: forming an oxide semiconductor material layer, the oxide semiconductor material layer including: a main body portion; and an auxiliary portion connected to the main body portion; forming a gate electrode to overlap the main body portion; Forming a first insulating material layer on the oxide semiconductor material layer; removing a part of the first insulating material layer and the auxiliary part to form a first insulating layer and an active layer, wherein a part of the first insulating layer is removed The material layer overlaps at least the auxiliary portion; and a source and a drain are formed on the first insulating layer, and are electrically connected to a source region and a drain region of the active layer, respectively. The manufacturing method according to item 4 of the scope of patent application, wherein a hydrogen concentration of the first insulating layer is lower than a hydrogen concentration of the first insulating material layer. The manufacturing method according to item 4 of the scope of patent application, further comprising: forming a second insulating layer on the first insulating layer, wherein the source electrode and the drain electrode are formed on the second insulating layer. The manufacturing method according to item 6 of the patent application, wherein a hydrogen concentration of the second insulating layer is lower than a hydrogen concentration of the first insulating layer. The manufacturing method according to item 4 of the scope of patent application, wherein the oxide semiconductor material layer comprises a material selected from the group consisting of indium tin oxide (IZO), indium-tin-zinc oxide (ITZO) , Indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), zinc oxide (ZnO), tin oxide (SnO), gallium oxide At least one of the group consisting of Gallium-Zinc Oxide (GZO), Zinc-Tin Oxide (ZTO) and Indium-Tin Oxide (ITO). The manufacturing method according to item 4 of the scope of patent application, wherein the step of forming the oxide semiconductor material layer precedes the step of forming the gate, and the method further includes forming a gate insulating layer on the gate and the oxidation. Between the semiconductor material layers. According to the manufacturing method described in item 4 of the patent application, the step of forming the gate is preceded by the step of forming the oxide semiconductor material layer. The method further includes forming a gate insulating layer on the gate and the oxide. Between semiconductor material layers. The manufacturing method according to item 10 of the patent application scope, further comprising: before the step of forming the first insulating material layer, forming a protective layer on the main body portion and contacting the main body portion to contact one of the active layers The channel areas overlap. The manufacturing method according to item 11 of the scope of the patent application, wherein a hydrogen concentration of the protective layer is lower than a hydrogen concentration of the first insulating layer. The manufacturing method according to item 4 of the scope of patent application, wherein the gate is electrically connected to the source. A pixel structure includes: an active layer including a source region, a channel region, and a drain region; a first insulating layer disposed on the active layer and in contact with the active layer, the first insulating layer A horizontal distance between the edge of the edge and the edge of the active layer is 0 micrometers to 5 microns; a gate insulating layer; a gate, wherein the gate insulating layer is located between the gate and the active layer; a source and A drain electrode is disposed on the first insulating layer and is electrically connected to the source region and the drain region respectively; and a pixel electrode is electrically connected to the drain electrode. The pixel structure according to item 14 of the patent application scope further includes: a second insulating layer disposed on the first insulating layer, wherein the source electrode and the drain electrode are disposed on the second insulating layer. The pixel structure according to item 15 of the application, wherein the hydrogen concentration of the second insulating layer is lower than that of the first insulating layer. The pixel structure according to item 14 of the patent application scope, wherein the oxide semiconductor material layer comprises a material selected from the group consisting of indium tin oxide (IZO), indium-tin-zinc oxide (ITZO) ), Indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), zinc oxide (ZnO), tin oxide (SnO), oxide At least one of the group consisting of Gallium-Zinc Oxide (GZO), Zinc-Tin Oxide (ZTO) and Indium-Tin Oxide (ITO). The pixel structure according to item 14 of the scope of the patent application, wherein the horizontal distance is 0 micrometers.