TW201917820A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201917820A
TW201917820A TW107132669A TW107132669A TW201917820A TW 201917820 A TW201917820 A TW 201917820A TW 107132669 A TW107132669 A TW 107132669A TW 107132669 A TW107132669 A TW 107132669A TW 201917820 A TW201917820 A TW 201917820A
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Taiwan
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semiconductor
layer
seed
section
semiconductor substrate
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TW107132669A
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English (en)
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雲惟勝
林佑儒
余紹銘
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台灣積體電路製造股份有限公司
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Publication of TW201917820A publication Critical patent/TW201917820A/zh

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    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract

本發明實施例提供一種用於製造一半導體裝置之方法。接納一半導體基板。圖案化該半導體基板以形成彼此間隔之複數個突出部，其中該突出部包括一基底區段，及堆疊在該基底區段上之一晶種區段。形成複數個第一絕緣結構，從而覆蓋該等基底區段側壁且暴露該等晶種區段之側壁。形成複數個間隔件，從而覆蓋該等晶種區段之該等側壁。部分移除該等第一絕緣結構以部分暴露該等基底區段之該等側壁。移除自該等第一絕緣結構暴露之該等基底區段。在該等晶種區段下方形成複數個第二絕緣結構。

Description

半導體裝置及其製造方法
本發明實施例係有關半導體裝置及其製造方法。
近年來，應變鬆弛緩衝器(SRB)經生長在一塊體半導體基板(諸如矽基板)上，且用作一虛擬基板(VS)以磊晶生長具有不同於該塊體基板之一晶格常數之另一半導體材料。然而，SRB經受缺陷問題，且經磊晶生長半導體材料之厚度受其理論臨界厚度限制。
本發明的一實施例係關於一種用於製造一半導體裝置之方法，其包括：接納一半導體基板； 圖案化該半導體基板以形成彼此間隔之複數個突出部，其中該突出部包括一基底區段，及堆疊在該基底區段上之一晶種區段；形成複數個第一絕緣結構，從而覆蓋該等基底區段之側壁且暴露該等晶種區段之側壁；形成複數個間隔件，從而覆蓋該等晶種區段之該等側壁；部分移除該等第一絕緣結構以部分暴露該等基底區段之該等側壁；移除自該等第一絕緣結構暴露之該等基底區段；及在該等晶種區段下方形成複數個第二絕緣結構。
本發明的一實施例係關於一種用於製造一半導體裝置之方法，其包括：接納一半導體基板；圖案化該半導體基板以形成彼此間隔開之複數個突出部；覆蓋該複數個突出部之頂部部分及底部部分之側壁，而暴露該複數個突出部之中間部分；移除該複數個突出部之該等中間部分；在該複數個突出部之該等底部部分與該等頂部部分之間形成一絕緣層；及在該等突出部之該等頂部部分上生長複數個半導體結構。
本發明的一實施例係關於一種半導體裝置，其包括：一半導體基板，其包含一表面，及自該半導體基板之該表面突出之複數個突出部；一絕緣層，其在該半導體基板上方；及複數個堆疊式半導體通道，其等在該絕緣層上方，其中該複數個堆疊式半導體通道實質上與該複數個突出部對準，且藉由該絕緣層與該複數個突出部隔開。
以下揭露內容提供用於實施本揭露之不同特徵之許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等僅為實例且不旨在限制。舉例而言，在下列描述中之一第一構件形成於一第二構件上方或上可包含其中該第一構件及該第二構件經形成直接接觸之實施例，且亦可包含其中額外構件可形成在該第一構件與該第二構件之間，使得該第一構件及該第二構件可不直接接觸之實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複出於簡化及清楚之目的，且本身不指示所論述之各項實施例及/或組態之間之一關係。
此外，為便於描述，可在本文中使用諸如「在…下面」、「在…下方」、「下」、「在…上方」、「上」、「在…上」及類似者之空間相對術語來描述一個元件或構件與另一(些)元件或構件之關係，如圖中繪示。空間相對術語旨在涵蓋除在圖中描繪之定向以外之使用或操作中之裝置之不同定向。設備可以其他方式經定向(旋轉90度或按其他定向)且本文中使用之空間相對描述符同樣可相應地解釋。
如本文中所使用，術語(諸如「第一」、「第二」及「第三」)描述各種元件、組件、區、層及/或區段，此等元件、組件、區、層及/或區段不應受此等術語限制。此等術語可僅用於區分一個元件、組件、區、層或區段與另一元件、組件、區、層或區段。術語(諸如「第一」、「第二」及「第三」)在本文中使用時並不意指一序列或順序，除非上下文另有明確指示。
如本文中使用，術語「近似」、「實質上」、「實質」及「大約」用於描述且考量較小變動。當結合事件或狀況使用時，該等術語可係指其中確切地發生該事件或狀況之例項以及其中近似發生該事件或狀況之例項。例如，當結合數值使用時，該等術語可係指小於或等於該數值之±10%之一變動範圍，諸如小於或等於±5%，小於或等於±4%，小於或等於±3%，小於或等於±2%，小於或等於±1%，小於或等於±0.5%，小於或等於±0.1%或小於或等於±0.05%。例如，若兩個數值之間的差小於或等於該等值之一平均數之±10%，諸如小於或等於±5%，小於或等於±4%，小於或等於±3%，小於或等於±2%，小於或等於±1%，小於或等於±0.5%，小於或等於±0.1%或小於或等於±0.05%，則該等值可被視為「實質上」相同或相等。例如，「實質上」平行可係指相對於0°小於或等於±10°之一角度變動範圍，諸如小於或等於±5°，小於或等於±4°，小於或等於±3°，小於或等於±2°，小於或等於±1°，小於或等於±0.5°，小於或等於±0.1°或小於或等於±0.05°。例如，「實質上」垂直可係指相對於90°小於或等於±10°之一角度變動範圍，諸如小於或等於±5°，小於或等於±4°，小於或等於±3°，小於或等於±2°，小於或等於±1°，小於或等於±0.5°，小於或等於±0.1°或小於或等於±0.05°。
可藉由任何適當方法圖案化鰭片。例如，可使用一或多個光微影程序(包含雙重圖案化或多重圖案化程序)來圖案化鰭片。一般言之，雙重圖案化或多重圖案化程序組合光微影及自對準程序，從而容許產生(例如)具有小於原本可使用一單一、直接光微影程序獲得之節距之節距之圖案。例如，在一項實施例中，一犧牲層經形成在一基板上方且使用一光微影程序圖案化。使用一自對準程序與經圖案化犧牲層並排形成間隔件。接著移除犧牲層，且接著可使用剩餘間隔件以圖案化鰭片。
如本文使用，術語「半導體基板」可係指一塊體半導體基板或包含一半導體基底及堆疊於半導體基底上之一半導體晶種層之一複合半導體基板。
在本揭露之一或多項實施例中，具有小於其臨界厚度之一厚度之一半導體晶種層用作一晶種層及一應變轉移介質。實質上不含缺陷之半導體晶種層容許磊晶生長在其上之另一半導體層應變。半導體晶種層亦容許磊晶生長在其上之半導體層甚至在其厚度超過其理論臨界厚度時實質上不含缺陷。半導體晶種層可為一塊體半導體基板之一部分，或生長在一半導體基底上之一半導體層。
圖1係繪示根據本揭露之一或多項實施例之各種態樣之用於製造一半導體裝置之一方法之一流程圖。方法100開始於操作110，其中接納一半導體基板。方法100繼續操作120，其中圖案化半導體基板以形成彼此間隔開之複數個突出部。突出部之各者包含一基底區段及堆疊在該基底區段上之一晶種區段。方法100繼續操作130，其中形成複數個第一絕緣結構以覆蓋基底區段之側壁且暴露晶種區段之側壁。方法100繼續操作140，其中形成複數個間隔件，從而覆蓋晶種區段之側壁。方法100繼續操作150，其中部分移除第一絕緣結構以部分暴露基底區段之側壁。方法100繼續操作160，其中移除自第一絕緣結構暴露之基底區段。方法100繼續操作170，其中在晶種區段下方形成複數個第二絕緣結構。
方法100僅係一實例，且並不旨在將本揭露限制在發明申請專利範圍中明確陳述之範圍以外。可在方法100之前、期間及之後提供額外操作，且所描述之一些操作可針對方法之額外實施例替換、消除或移動。
圖2係繪示根據本揭露之一或多項實施例之各種態樣之用於製造一半導體裝置之一方法之一流程圖。方法200開始於操作210，其中接納一半導體基板。方法200繼續操作220，其中圖案化半導體基板以形成彼此間隔開之複數個突出部。方法200繼續操作230，其中覆蓋複數個突出部之頂部部分及底部部分之側壁，而暴露複數個突出部之中間部分。方法200繼續操作240，其中移除複數個突出部之中間部分。方法200繼續操作250，其中在複數個突出部之底部部分與頂部部分之間形成一支撐層。方法200繼續操作260，其中在突出部之頂部部分上生長複數個半導體結構。
方法200僅係一實例，且並不旨在將本揭露限制在發明申請專利範圍中明確陳述之範圍以外。可在方法200之前、期間及之後提供額外操作，且所描述之一些操作可針對方法之額外實施例替換、消除或移動。
圖3A、圖3B、圖3C、圖3D、圖3E、圖3F、圖3G、圖3H、圖3I、圖3J、圖3K、圖3L及圖3M係根據本揭露之一或多項實施例之製造一半導體裝置之各種操作之一或多者處之示意圖。如在圖3A中展示，接納一半導體基板10。在一些實施例中，半導體基板10可包含一半導體基底12及半導體基底12上方之一半導體晶種層14。藉由實例，半導體基底12可包含一半導體基底，諸如矽基底或類似物。在一些實施例中，半導體基底12可為自一半導體晶錠切割之一半導體晶圓。藉由實例，半導體晶種層14可包含形成在半導體基底12上之一半導體材料。在一些實施例中，半導體晶種層14之材料可包含矽、鍺、矽鍺、其他半導體材料(諸如III族、IV族或V族元素或化合物)或類似物。在一些實施例中，半導體晶種層14磊晶生長在半導體基底12上，且半導體晶種層14之厚度小於其臨界厚度。
如在圖3B中展示，圖案化半導體基板10以在半導體基板10中形成複數個凹槽10R及藉由凹槽10R彼此間隔之複數個突出部16。突出部16之各者包含一基底區段101及堆疊在基底區段101上之一晶種區段102。在一些實施例中，基底區段101可為半導體基底12之部分，且晶種區段102可為半導體晶種層14之部分。
在一些實施例中，可由光微影及蝕刻技術形成凹槽10R及突出部16。在一些實施例中，在半導體基板10之一表面10A上方形成一經圖案化遮罩層20作為一硬遮罩。經圖案化遮罩層20包含部分暴露半導體基板10之表面10A之複數個開口20A。在一些實施例中，經圖案化遮罩層20可為一單層遮罩或一多層遮罩。在一些實施例中，經圖案化遮罩層20可包含一墊層22及堆疊在墊層22上之一硬遮罩層24。藉由實例，墊層22可包含墊氧化物層(諸如氧化矽層)，且經組態以增強硬遮罩層24與半導體基板10之間的黏著性。藉由實例，硬遮罩層24可包含氮化物層(諸如氮化矽層)。接著可(例如)藉由蝕刻穿過經圖案化遮罩層20之開口20A而移除半導體基板10之部分以在半導體基板10中形成凹槽10R及藉由凹槽10R彼此間隔開之突出部16。晶種區段102之各者介於各自基底區段101與經圖案化遮罩層20之間。
在一些實施例中，分別在凹槽10R中形成複數個第一絕緣結構。在一些實施例中，第一絕緣結構可藉由下列操作形成，但不限於此等。如在圖3C中展示，在複數個凹槽10R中形成一第一絕緣層26。在一些實施例中，第一絕緣層26可形成在經圖案化遮罩層20上方且填充於凹槽10R及開口20A中。在一些實施例中，第一絕緣層26之材料可包含氧化物化合物(諸如氧化矽)或其他適當絕緣或介電材料。在一些實施例中，一襯層絕緣層(未展示)可在形成第一絕緣層26之前形成於經圖案化遮罩層20上方及凹槽10R中，但不限於此。
如在圖3D中展示，在一些實施例中，可執行一平坦化操作(諸如化學機械拋光(CMP)、研磨或類似物)以移除開口20A外部之第一絕緣層26。在一些實施例中，可部分移除第一絕緣層26以分別在凹槽10R中形成第一絕緣結構28。在一些實施例中，第一絕緣結構28覆蓋基底區段10之側壁101S且暴露晶種區段102之側壁102S。
在一些實施例中，形成覆蓋晶種區段102之側壁102S之複數個間隔件。在一些實施例中，間隔件可藉由下列操作形成，但不限於此等。如在圖3E中展示，可形成一襯層間隔件層30以覆蓋經圖案化遮罩層20之一上表面20U及側壁20S以及晶種區段102之側壁102S及第一絕緣結構28。在一些實施例中，襯層間隔件層30之材料可包含氮化物化合物(諸如氮化矽)或類似物。
如在圖3F中展示，可移除經圖案化遮罩層20之上表面20U及第一絕緣結構28上方之襯層間隔件層30，而保留覆蓋經圖案化遮罩層20之側壁20S及晶種區段102之側壁102S之襯層間隔件層30。在一些實施例中，襯層間隔件層30可藉由一各向異性蝕刻(諸如一電漿蝕刻)移除，但不限於此。因此，可形成覆蓋晶種區段102之側壁102S之間隔件32。在一些實施例中，間隔件32可進一步覆蓋經圖案化遮罩層20之側壁20S。
如在圖3G中展示，部分移除第一絕緣結構28之各者以至少部分暴露基底區段101之側壁101S。在一些實施例中，第一絕緣結構28可藉由一各向異性蝕刻(諸如一電漿蝕刻)部分移除，但不限於此。
如在圖3H及圖3I中展示，移除自第一絕緣結構28暴露之基底區段101。在一些實施例中，突出部16之晶種區段102自半導體基底12懸掛，但晶種區段102之兩端102E經組態為連接至半導體基板10之錨定部分。在一些實施例中，第一絕緣結構28可藉由蝕刻(諸如側向蝕刻)移除。在一些實施例中，自第一絕緣結構28暴露之基底區段101可在蝕刻自第一絕緣結構28暴露之基底區段101之前氧化。經氧化基底區段101可變為半導體氧化物化合物(諸如氧化矽)，且因此可具有相對於用於蝕刻基底區段101之一蝕刻劑不同於晶種區段102及半導體基板10之其他部分之蝕刻率。藉由實例，當晶種區段102係矽且暴露之基底區段101係氧化矽時，可使用一蝕刻劑溶液(諸如氫氧化銨(NH4 OH)溶液、氫氧化四甲基銨(TMAH)溶液、氫氧化鉀(KOH)溶液或類似物)以濕式蝕刻暴露之基底區段101。在一些實施例中，相對於蝕刻劑溶液之基底區段101與晶種區段102之間的蝕刻選擇性可大於約10。在一些實施例中，可藉由乾式蝕刻移除暴露之基底區段101。用於乾式蝕刻基底區段101之蝕刻劑可包含但不限於氫氯化物(HCl)、鹵素間化合物(諸如ClF3 或類似物)、鹵素(諸如F2 )、鹵素化合物(諸如XeF2 、SF6 、NF3 或類似物)。
此蝕刻率差可在蝕刻基底區段101時減輕對晶種區段102及半導體基板10之損害。在已經移除基底區段101之後，突出部16之剩餘部分自半導體基底12之表面突出且對準於晶種區段102。
圖3J係根據本揭露之一些實施例之在蝕刻基底區段101之後之突出部16之一放大圖。如在圖3J中展示，在蝕刻基底區段101之後，一些突出部16之上表面16U可為一不平坦表面(諸如一凹表面、一凸表面或其等之一組合)。不平坦上表面16U可歸因於蝕刻基底區段101之不均勻性而產生。
如在圖3K中展示，分別在凹槽10R中形成複數個第二絕緣結構34。在一些實施例中，第二絕緣結構34側向延伸以放置於晶種區段102下方及半導體基底12之突出部16與晶種區段102之間。第二絕緣結構34可將半導體基底12之突出部16與晶種區段102隔離，使得突出部16及晶種區段102彼此不接觸。在一些實施例中，第二絕緣結構34之材料可與第一絕緣結構28之材料相同，但不限於此。第二絕緣結構34之材料之實例可包含氧化物化合物(諸如氧化矽)，但不限於此。
如在圖3L中展示，移除經圖案化遮罩層20以暴露晶種區段102及間隔件32。在一些實施例中，晶種區段102及間隔件32可由第二絕緣結構34側向圍繞，而晶種區段102及間隔件32之上表面暴露。在一些實施例中，在移除經圖案化遮罩層20之後，第二絕緣結構34自晶種區段102及間隔件32向上突出，以便在晶種區段102及間隔件32上方形成複數個腔34C。在一些實施例中，可部分移除第二絕緣結構34以調整腔34C之深度。在一些替代性實施例中，可諸如藉由CMP或研磨移除第二絕緣結構34之部分，使得第二絕緣結構34、間隔件32及第二晶種區段102可實質上共面。
如在圖3M中展示，在形成第二絕緣結構34之後在晶種區段102上方磊晶生長複數個第一半導體結構40以形成本揭露之一些實施例之一半導體裝置1。晶種區段102及堆疊於其上之第一半導體結構40形成一堆疊式半導體結構。在一些實施例中，第一半導體結構40之材料可與晶種區段102相同或不同。第一半導體結構40及晶種區段102可一起形成一電晶體裝置之一通道。第一半導體結構40之材料之實例可包含但不限於矽、鍺、矽鍺、其他半導體材料(諸如III族、IV族或V族元素或化合物)或類似物。在一些實施例中，晶種區段102經組態為磊晶生長第一半導體結構40之一晶種層。晶種區段102之厚度小於晶種區段102之材料之臨界厚度，即，晶種區段102處於一實質上不含缺陷之狀態中。因此，當第一半導體結構40磊晶生長在處於實質上不含缺陷之狀態中之晶種區段102上時，缺陷將被抑制。在一些實施例中，晶種區段102亦經組態為用於應變轉移之一介質。第一半導體結構40之厚度不受其臨界厚度限制，且第一半導體結構40可在不具有缺陷或具有較少缺陷的情況下變厚，此係由於應變能量達成飽和。第一半導體結構40可經組態為一反轉虛擬基板。磊晶生長在晶種區段102上之第一半導體結構40可應變，且因此可增強裝置效能。
在本揭露之一些實施例中，在一半導體晶種材料上生長一半導體材料，且半導體材料及半導體晶種材料具有失配晶格常數。術語「臨界厚度」經定義為實質上不具有缺陷(諸如錯配位錯及穿透位錯)之一應變半導體材料之一最大穩定厚度。圖4係繪示臨界厚度與不同組合物中之矽鍺之間的一關係之一圖。垂直軸係厚度。水平軸係矽鍺材料(Si1-x Gex ，其中x=0-1)中之鍺之組合物。如在圖4中展示，兩個曲線A及B定義具有不同組合物之矽鍺材料之穩定區、亞穩定區及伴隨缺陷之鬆弛區。在曲線B上方係處於伴隨缺陷之鬆弛條件之矽鍺材料。在曲線A下方係處於穩定條件(即，實質上不含缺陷且處於一「完全應變」條件)之矽鍺材料。在兩個曲線A與B之間的區定義其中矽鍺材料處於準穩定條件之區。處於亞穩定條件之矽鍺材料不穩定，但在恰當條件下生長時仍可完全應變且實質上不含缺陷。在本揭露之一些實施例中，一半導體材料之臨界厚度經定義為當半導體材料處於穩定條件或亞穩定條件時之厚度。在穩定條件或亞穩定條件下，半導體材料實質上不含缺陷，且因此甚至在生長於不含缺陷之半導體材料上之具有失配晶格常數之另一半導體材料之厚度超過其理論臨界厚度時，最新生長之半導體材料亦可實質上不含缺陷。
參考圖3M。在本揭露之一些實例中，若晶種區段102之材料係具有小於3 nm之一厚度之矽，則第一半導體結構40 (諸如磊晶生長在晶種區段102上之鍺層)之厚度可超過其理論臨界厚度而無缺陷。在本揭露之一些其他實例中，若晶種區段102之材料係具有小於10 nm之一厚度之Si0.5 Ge0.5 ，則第一半導體結構40 (諸如磊晶生長在晶種區段102上之鍺層)之厚度可超過其理論臨界厚度而無缺陷。
本揭露之半導體裝置及其製造方法不限於上文提及之實施例，且可具有其他不同實施例。為了簡化描述且為便於比較本揭露之實施例之各者，使用相同數字標記下列實施例之各者中之相同組件。為更易於比較實施例之間的差異，下列描述將詳述不同實施例間的相異性且不會冗餘地描述相同構件。
圖5A、圖5B及圖5C係根據本揭露之一或多項實施例之製造一半導體裝置之各種操作之一或多者處之示意圖。如在圖5A中展示，接納一半導體基板10。與半導體裝置1相反，半導體基板10係一塊體半導體基板。可執行類似於在圖3A至圖3F中描述之操作之連續操作以形成複數個突出部16。基底區段101可為塊體半導體基板之一些部分，且晶種區段102可為塊體半導體基板之一些其他部分。在一些實施例中，突出部16可包含彼此堆疊之一底部部分103、一中間部分(例如，基底部分101)及一頂部部分(例如，晶種區段102)，如在圖5B中展示。可由第一絕緣結構28覆蓋底部部分103之側壁，且可由間隔件32覆蓋頂部部分(晶種區段102)之側壁。部分移除第一絕緣結構28以至少部分暴露基底區段101之側壁101S (例如，中間部分)。可執行類似於在圖3H至圖3K中描述之操作之連續操作。如在圖5C中展示，在形成第二絕緣結構34之後在晶種區段102上方磊晶生長複數個第一半導體結構40以形成本揭露之一些實施例之一半導體裝置2。在一些實施例中，第一半導體結構40之材料可與晶種區段102相同或不同。第一半導體結構40之材料之實例可包含但不限於矽、鍺、矽鍺、其他半導體材料(諸如III族、IV族或V族元素或化合物)或類似物。在一些實施例中，晶種區段102經組態為磊晶生長第一半導體結構40之一晶種層。晶種區段102之厚度小於晶種區段102之材料之臨界厚度，即，晶種區段102處於實質上不含缺陷之狀態中。
圖6A、圖6B及圖6C係根據本揭露之一或多項實施例之製造一半導體裝置之各種操作之一或多者處之示意圖。在一些實施例中，可在圖3J中繪示之操作之後執行在圖6A中繪示之操作。如在圖6A中展示，晶種區段102之各者可經部分氧化以在晶種區段102之各者中形成氧化部分102X。例如，氧化部分102X可經放置鄰近於晶種區段102之上表面。在一些實施例中，可藉由引入氧氣或其他氧化技術形成氧化部分102X。在一些實施例中，晶種區段102之材料可包含半導體化合物(諸如矽鍺)，且氧化可有助於冷凝晶種區段102。具體言之，由於不同材料之氧化能力係不同的，故可使用晶種區段102之氧化來改質晶種區段102之組合物。藉由實例，由於矽比鍺更易於氧化，故若晶種區段102之原始材料係Si0.7 Ge0.3 ，則晶種區段102之材料可在氧化之後冷凝至Si0.5 Ge0.5 。
如在圖6B中展示，(例如)藉由蝕刻移除晶種區段102之氧化部分102X。如在圖6C中展示，在晶種區段102上方磊晶生長複數個第一半導體結構40以形成本揭露之一些實施例之一半導體裝置3。
圖7A、圖7B及圖7C係根據本揭露之一或多項實施例之製造一半導體裝置之各種操作之一或多者處之示意圖。在一些實施例中，可在圖3M、圖5C或圖6C中繪示之操作之後執行在圖7A中繪示之操作。如在圖7A中展示，在第一半導體結構40上方形成一遮罩層50 (諸如一光阻層)。遮罩層50覆蓋第一半導體結構40之一第一部分401，且暴露第一半導體結構40之一第二部分402。
如在圖7B中展示，(例如)藉由蝕刻部分移除自遮罩層50暴露之第一半導體結構40之第二部分402。如在圖7C中展示，在第一半導體結構40之剩餘第二部分402上方磊晶生長複數個第二半導體結構42，且移除遮罩層50以形成本揭露之一些實施例之一半導體裝置4。在一些實施例中，晶種區段102、第一半導體結構40及第二半導體結構42之材料具有不同晶格常數。晶種區段102及堆疊於其上之第一半導體結構40形成一堆疊式半導體結構。彼此堆疊之晶種區段102、第一半導體結構40及第二半導體結構42形成另一堆疊式半導體結構。在一些實施例中，第一半導體結構40可經組態為P型半導體裝置(諸如PMOS)之通道，且第二半導體結構42可經組態為N型半導體裝置(諸如NMOS)之通道。晶種區段102之材料之實例可包含矽鍺(SiGe)，諸如Si0.5 Ge0.5 。第一半導體結構40之材料之實例可包含鍺(Ge)，且第二半導體結構42之材料之實例可包含砷化鎵銦(InGaAs)。在一些實施例中，可個別地選擇第一半導體結構40及第二半導體結構42之材料以形成不同半導體裝置之應變通道及鬆弛通道。
圖8A、圖8B、圖8C、圖8D及圖8E係根據本揭露之一或多項實施例之製造一半導體裝置之各種操作之一或多者處之示意圖。在一些實施例中，可在圖3M、圖5C、圖6C或圖7C中繪示之操作之後執行在圖8A中繪示之操作。如在圖8A中展示，在第一半導體結構40上方形成一遮罩層50 (諸如一光阻層)。遮罩層50覆蓋第一半導體結構40之一第一部分401，且暴露第一半導體結構40之一第二部分402。
如在圖8B中展示，(例如)藉由蝕刻部分移除自遮罩層50暴露之第一半導體結構40之第二部分402。如在圖8C中展示，在第一半導體結構40之剩餘第二部分402上方磊晶生長複數個第二半導體結構42。在一些實施例中，第二半導體結構42及第一半導體結構40之材料具有不同晶格常數。
如在圖8D中展示，移除遮罩層50。在第二半導體結構42上方形成另一遮罩層52 (諸如一光阻層)。遮罩層52覆蓋第二半導體結構42，且暴露第一半導體結構40。(例如)藉由蝕刻部分移除自遮罩層52暴露之第一半導體結構40。
如在圖8E中展示，在第一半導體結構40之剩餘第一部分上方磊晶生長複數個第三半導體結構44，且移除遮罩層52以形成本揭露之一些實施例之一半導體裝置5。在一些實施例中，晶種區段102、第一半導體結構40、第二半導體結構42及第三半導體結構44之材料具有不同晶格常數。彼此堆疊之晶種區段102、第一半導體結構40及第二半導體結構42形成一堆疊式半導體結構。彼此堆疊之晶種區段102、第一半導體結構40及第三半導體結構44形成另一堆疊式半導體結構。在一些實施例中，第一半導體結構40可經組態為緩衝區，第二半導體結構42可經組態為N型半導體裝置(諸如NMOS)之通道，且第三半導體結構44可經組態為P型半導體裝置(諸如PMOS)之通道。晶種區段102之材料之實例可包含矽(Si)。第一半導體結構40之材料之實例可包含矽鍺(SiGe)，諸如Si0.5 Ge0.5 。第二半導體結構42之材料之實例可包含矽。第三半導體結構44之材料之實例可包含鍺。在一些實施例中，可選擇第一半導體結構40、第二半導體結構42及第三半導體結構44之材料以形成不同半導體裝置之應變通道及鬆弛通道。
圖9A、圖9B、圖9C、圖9D、圖9E、圖9F、圖9G及圖9H係根據本揭露之一或多項實施例之製造一半導體裝置之各種操作之一或多者處之示意圖。如在圖9A中展示，接納一半導體基板10。在一些實施例中，半導體基板10係一塊體半導體基板。在半導體基板10之一表面10A上方形成一經圖案化遮罩層20作為一硬遮罩。接著，(例如)藉由蝕刻穿過經圖案化遮罩層20之開口20A而圖案化半導體基板10以形成彼此間隔之複數個突出部16。在一些實施例中，可在半導體基板10、突出部16及經圖案化遮罩層20上方形成一襯層絕緣層25。
如在圖9B中展示，分別在凹槽10R中形成複數個第一絕緣結構28。在一些實施例中，第一絕緣結構28部分覆蓋突出部16之側壁。在一些實施例中，形成複數個間隔件32，從而部分覆蓋突出部16之側壁。在一些實施例中，間隔件32可進一步覆蓋經圖案化遮罩層20之側壁。
如在圖9C中展示，形成一第一抗蝕層27 (諸如一光阻層)以覆蓋突出部16及第一絕緣結構28之一第一群組G1，且暴露突出部16及第一絕緣結構28之一第二群組G2。接著，(例如)藉由蝕刻部分移除透過第一抗蝕層27暴露之第二群組G2之第一絕緣結構28以降低第一絕緣結構28之厚度。亦可移除暴露之襯層絕緣層25。因此，第二群組G2之突出部16之中間部分162暴露，而第二群組G2之底部部分161及頂部部分163被覆蓋。
如在圖9D中展示，移除第一抗蝕層27及間隔件32。移除暴露之中間部分162，而保留底部部分161及頂部部分163。在移除中間部分162之後，頂部部分163之兩端仍連接至半導體基板10且經組態為錨定部分，使得頂部部分163並不掉落。在移除中間部分162之後，頂部部分163及底部部分161彼此分離。第二群組G2之頂部部分163經組態為一晶種區段，且具有一厚度H2。底部部分161經連接至半導體基板10，且經組態為一突出部。第二群組G2之底部部分161具有一厚度K2。
如在圖9E中展示，在半導體基板10上方形成一絕緣層29。接著，部分移除絕緣層29，且保留第二群組G2之突出部16之上部分163與底部部分161之間的絕緣層29。在一些實施例中，部分移除第一絕緣結構28以及絕緣層29，使得第一群組G1之絕緣層29及第一絕緣結構28可實質上共面。在一些實施例中，形成複數個第二間隔件33，從而部分覆蓋突出部16之側壁。在一些實施例中，第二間隔件33可進一步覆蓋經圖案化遮罩層20之側壁。在一些實施例中，絕緣層29可用於支撐上部分163。一旦形成絕緣層29，上部分163之兩端便可在連續操作中移除且與半導體基板10斷開連接。在一些實施例中，絕緣層29之材料可與第一絕緣結構28相同。
如在圖9F中展示，形成一第二抗蝕層31 (諸如一光阻層)以覆蓋突出部16及絕緣層29之第二群組G2，且暴露突出部16及第一絕緣結構28之第一群組G1。接著，(例如)藉由蝕刻部分移除透過第二抗蝕層31暴露之第一群組G1之第一絕緣結構28以降低第一絕緣結構28之厚度。亦可移除暴露之襯層絕緣層25。因此，第一群組G1之突出部16之中間部分162暴露，而第一群組G1之底部部分161及頂部部分163被覆蓋。第一群組G1之第一絕緣結構28之厚度不同於第二群組G2之第一絕緣結構28之厚度。藉由實例，第二群組G2之第一絕緣結構28之厚度小於第一群組G1之第一絕緣結構28之厚度。因此，第一群組G1之突出部16之底部部分161、中間部分162及頂部部分163之厚度不同於第二群組G2之突出部16之底部部分161、中間部分162及頂部部分163之厚度。
如在圖9G中展示，移除第二抗蝕層31及第二間隔件33。移除暴露之中間部分162，而保留底部部分161及頂部部分163。在移除中間部分162之後，頂部部分163及底部部分161彼此分離。第一群組G1之頂部部分163經組態為一晶種區段，且具有不同於第二群組G2之頂部部分163之厚度H2之一厚度H1。例如，厚度H1大於厚度H2。第一群組G1之底部部分161經連接至半導體基板10，且經組態為一突出部。第一群組G1之底部部分161具有不同於第二群組G2之底部部分161之厚度K2之一厚度K1。例如，厚度K1小於厚度K2。
如在圖9H中展示，在半導體基板10上方形成另一絕緣層35。絕緣層35之材料可與絕緣層29相同。例如，絕緣層35之材料可包含氧化物化合物(諸如氧化矽)或其他適當絕緣或介電材料。移除經圖案化遮罩層20以暴露突出部16之頂部部分163。在一些實施例中，在頂部部分163上方磊晶生長複數個第一半導體結構40以形成本揭露之一些實施例之一半導體裝置6。頂部部分163及第一半導體結構40可形成一堆疊式半導體通道，其中頂部部分163經組態為一底部半導體通道，且第一半導體結構40經組態為一上半導體通道。在一些實施例中，第一半導體結構40之材料可與頂部部分163相同或不同。第一半導體結構40之材料之實例可包含但不限於矽、鍺、矽鍺、其他半導體材料(諸如III族、IV族或V族元素或化合物)或類似物。在一些實施例中，頂部部分163經組態為磊晶生長第一半導體結構40之一晶種層。頂部部分163之厚度小於頂部部分163之材料之臨界厚度，即，頂部部分163處於一實質上不含缺陷之狀態中。因此，當在處於實質上不含缺陷之狀態中之頂部部分163上磊晶生長第一半導體結構40時，缺陷將被抑制。在一些實施例中，頂部部分163亦經組態為用於應變轉移之一介質。第一半導體結構40之厚度不受其臨界厚度限制，且第一半導體結構40可在不具有缺陷或具有較少缺陷的情況下變厚，此係由於應變能量達成飽和。第一半導體結構40可經組態為一反轉虛擬基板。磊晶生長在頂部部分163上之第一半導體結構40可應變，且因此可增強裝置效能。在一些實施例中，第一群組G1之頂部部分163與第二群組G2之頂部部分之間的差異容許形成具有不同性質之半導體結構。
在一些實施例中，第一群組G1及/或第二群組G2之一些或全部第一半導體結構40可經移除，且由如在圖7A至圖7C或圖8A至圖8C之一些實施例中描述之另一半導體結構替換。
圖10係根據本揭露之一或多項實施例之一半導體裝置之一示意圖。如在圖10中展示，半導體裝置7可為一finFET裝置。在一些實施例中，形成在突出部16之頂部部分163上之半導體結構(諸如第一半導體結構40、第二半導體結構42及/或第三半導體結構44可經組態為finFET裝置之一鰭片。半導體裝置7可進一步包含一閘極介電質60、一閘極電極62 (諸如閘極介電質60上方之一金屬閘極電極)及與閘極電極62並排之一對間隔件64。半導體裝置7可進一步包含電連接至鰭片之兩個相對端之一對源極/汲極區66及電連接至該對源極/汲極區66之一對接觸通路68。圖11係根據本揭露之一或多項實施例之一半導體裝置之一示意圖。如在圖11中展示，半導體裝置8可為一環繞式閘極(GAA)電晶體裝置。在一些實施例中，可使用半導體結構(諸如第一半導體結構40、第二半導體結構42及/或第三半導體結構44)來形成GAA電晶體裝置之奈米線70。半導體裝置8可進一步包含圍繞奈米線70之介面層72，及覆蓋介面層72之高K介電層74。半導體裝置8可進一步包含圍繞奈米線70之一閘極電極76及源極/汲極區(未展示)。
在本揭露之一些實施例中，具有小於其臨界厚度之一厚度之一半導體晶種層用作一晶種層及一應變轉移介質。實質上不含缺陷之半導體晶種層容許磊晶生長在其上之另一半導體層應變。半導體晶種層亦容許磊晶生長在其上之半導體層甚至在半導體層之厚度超過其理論臨界厚度時實質上不含缺陷。在本揭露之一些實施例中，使用另一不同半導體材料來替換半導體層之一些部分或全部，且替換半導體材料之厚度實質上亦不含缺陷且不受其理論臨界厚度限制。在本揭露之一些實施例中，經應變、厚且實質上不含缺陷(或無缺陷)磊晶生長半導體材料可增強半導體裝置之效能(諸如電子遷移率)，且可應用於各種類型之半導體裝置，諸如邏輯MOSFET裝置、光電子積體電路(OEIC) (諸如CMOS感測器)或基於III至V族半導體裝置(諸如高電子遷移率電晶體(HEMT)、光電二極體或雷射裝置)。
在一個例示性態樣中，提供一種用於製造一半導體裝置之方法。接納一半導體基板。圖案化半導體基板以形成彼此間隔之複數個突出部，其中突出部包括一基底區段，及堆疊在基底區段上之一晶種區段。形成複數個第一絕緣結構，從而覆蓋基底區段之側壁且暴露晶種區段之側壁。形成複數個間隔件，從而覆蓋晶種區段之側壁。部分移除第一絕緣結構以部分暴露基底區段之側壁。移除自第一絕緣結構暴露之基底區段。在晶種區段下方形成複數個第二絕緣結構。
在另一態樣中，提供一種用於製造一半導體裝置之方法。接納一半導體基板。圖案化半導體基板以形成彼此間隔開之複數個突出部。覆蓋複數個突出部之頂部部分及底部部分之側壁，而暴露複數個突出部之中間部分。移除複數個突出部之中間部分。在複數個突出部之底部部分與頂部部分之間形成一絕緣層。在突出部之頂部部分上生長複數個半導體結構。
在另一態樣中，一種半導體裝置包含一半導體基板、一絕緣層及複數個堆疊式半導體結構。半導體基板包含一表面，及自半導體基板之表面突出之複數個突出部。絕緣層係在半導體基板上方。堆疊式半導體結構係在絕緣層上方，其中複數個突出部實質上與複數個突出部對準，且藉由絕緣層與複數個突出部隔開。
前文概述若干實施例之結構，使得熟習此項技術者可更好理解本揭露之態樣。熟習此項技術者應瞭解，其等可容易地使用本揭露作為設計或修改用於實行本文中介紹之實施例之相同目的及/或達成相同優點之其他製程及結構之一基礎。熟習此項技術者亦應認識到，此等等效架構並不脫離本發明實施例之精神及範疇，且其等可在不脫離本發明實施例之精神及範疇之情況下在本文中作出各種改變、替代及更改。
1‧‧‧半導體裝置
2‧‧‧半導體裝置
3‧‧‧半導體裝置
4‧‧‧半導體裝置
5‧‧‧半導體裝置
7‧‧‧半導體裝置
8‧‧‧半導體裝置
10‧‧‧半導體基板
10A‧‧‧表面
10R‧‧‧凹槽
12‧‧‧半導體基底
14‧‧‧半導體晶種層
16‧‧‧突出部
16U‧‧‧上表面
20‧‧‧經圖案化遮罩層
20A‧‧‧開口
20S‧‧‧側壁
20U‧‧‧上表面
22‧‧‧墊層
24‧‧‧硬遮罩層
25‧‧‧襯層絕緣層
26‧‧‧第一絕緣層
27‧‧‧第一抗蝕層
28‧‧‧第一絕緣結構
29‧‧‧絕緣層
30‧‧‧襯層間隔件層
31‧‧‧第二抗蝕層
32‧‧‧間隔件
33‧‧‧第二間隔件
34‧‧‧第二絕緣結構
34C‧‧‧腔
35‧‧‧絕緣層
40‧‧‧第一半導體結構
42‧‧‧第二半導體結構
44‧‧‧第三半導體結構
50‧‧‧遮罩層
52‧‧‧遮罩層
60‧‧‧閘極介電質
62‧‧‧閘極電極
64‧‧‧間隔件
66‧‧‧源極/汲極區
68‧‧‧接觸通路
70‧‧‧奈米線
72‧‧‧介面層
74‧‧‧高K介電層
76‧‧‧閘極電極
100‧‧‧方法
101‧‧‧基底區段
101S‧‧‧側壁
102‧‧‧晶種區段
102E‧‧‧端
102S‧‧‧側壁
102X‧‧‧氧化部分
103‧‧‧底部部分
110‧‧‧操作
120‧‧‧操作
130‧‧‧操作
140‧‧‧操作
150‧‧‧操作
160‧‧‧操作
161‧‧‧底部部分
162‧‧‧中間部分
163‧‧‧頂部部分
170‧‧‧操作
200‧‧‧方法
210‧‧‧操作
220‧‧‧操作
230‧‧‧操作
240‧‧‧操作
250‧‧‧操作
260‧‧‧操作
401‧‧‧第一部分
402‧‧‧第二部分
A‧‧‧曲線
B‧‧‧曲線
G1‧‧‧第一群組
G2‧‧‧第二群組
H1‧‧‧厚度
H2‧‧‧厚度
K1‧‧‧厚度
K2‧‧‧厚度
當結合附圖閱讀時，自以下實施方式最佳理解本發明實施例之態樣。應注意，根據行業中之標準實踐，各種結構不按比例繪製。實際上，為清晰論述，各種結構之尺寸可任意增大或減小。
圖1係繪示根據本揭露之一或多項實施例之各種態樣之用於製造一半導體裝置之一方法之一流程圖。
圖2係繪示根據本揭露之一或多項實施例之各種態樣之用於製造一半導體裝置之一方法之一流程圖。
圖3A、圖3B、圖3C、圖3D、圖3E、圖3F、圖3G、圖3H、圖3I、圖3J、圖3K、圖3L及圖3M係根據本揭露之一或多項實施例之製造一半導體裝置之各種操作之一或多者處之示意圖。
圖4係繪示臨界厚度與不同組合物中之矽鍺之間的一關係之一圖。
圖5A、圖5B及圖5C係根據本揭露之一或多項實施例之製造一半導體裝置之各種操作之一或多者處之示意圖。
圖6A、圖6B及圖6C係根據本揭露之一或多項實施例之製造一半導體裝置之各種操作之一或多者處之示意圖。
圖7A、圖7B及圖7C係根據本揭露之一或多項實施例之製造一半導體裝置之各種操作之一或多者處之示意圖。
圖8A、圖8B、圖8C、圖8D及圖8E係根據本揭露之一或多項實施例之製造一半導體裝置之各種操作之一或多者處之示意圖。
圖9A、圖9B、圖9C、圖9D、圖9E、圖9F、圖9G及圖9H係根據本揭露之一或多項實施例之製造一半導體裝置之各種操作之一或多者處之示意圖。
圖10係根據本揭露之一或多項實施例之一半導體裝置之一示意圖。
圖11係根據本揭露之一或多項實施例之一半導體裝置之一示意圖。

Claims (1)

  1. 一種用於製造一半導體裝置之方法，其包括： 接納一半導體基板； 圖案化該半導體基板以形成彼此間隔之複數個突出部，其中該突出部包括一基底區段，及堆疊在該基底區段上之一晶種區段； 形成複數個第一絕緣結構，從而覆蓋該等基底區段之側壁且暴露該等晶種區段之側壁； 形成複數個間隔件，從而覆蓋該等晶種區段之該等側壁； 部分移除該等第一絕緣結構以部分暴露該等基底區段之該等側壁； 移除自該等第一絕緣結構暴露之該等基底區段；及 在該等晶種區段下方形成複數個第二絕緣結構。
TW107132669A 2017-10-30 2018-09-17 半導體裝置及其製造方法 TW201917820A (zh)

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