US20190131423A1 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- US20190131423A1 US20190131423A1 US15/799,385 US201715799385A US2019131423A1 US 20190131423 A1 US20190131423 A1 US 20190131423A1 US 201715799385 A US201715799385 A US 201715799385A US 2019131423 A1 US2019131423 A1 US 2019131423A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 268
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000010410 layer Substances 0.000 claims description 103
- 238000000034 method Methods 0.000 claims description 82
- 239000000463 material Substances 0.000 claims description 52
- 238000002955 isolation Methods 0.000 claims description 38
- 238000000407 epitaxy Methods 0.000 claims description 37
- 239000011229 interlayer Substances 0.000 claims description 16
- 230000008569 process Effects 0.000 description 66
- 238000005530 etching Methods 0.000 description 27
- 229920002120 photoresistant polymer Polymers 0.000 description 20
- 125000006850 spacer group Chemical group 0.000 description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 13
- 239000007789 gas Substances 0.000 description 12
- 230000009969 flowable effect Effects 0.000 description 9
- 238000000059 patterning Methods 0.000 description 9
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 239000011241 protective layer Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- HEDRZPFGACZZDS-UHFFFAOYSA-N Chloroform Chemical compound ClC(Cl)Cl HEDRZPFGACZZDS-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- DQBAOWPVHRWLJC-UHFFFAOYSA-N barium(2+);dioxido(oxo)zirconium Chemical compound [Ba+2].[O-][Zr]([O-])=O DQBAOWPVHRWLJC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 2
- 229910052794 bromium Inorganic materials 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000011630 iodine Substances 0.000 description 2
- 229910052740 iodine Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 210000002381 plasma Anatomy 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- FZHAPNGMFPVSLP-UHFFFAOYSA-N silanamine Chemical compound [SiH3]N FZHAPNGMFPVSLP-UHFFFAOYSA-N 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- -1 zirconium aluminate Chemical class 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010073306 Exposure to radiation Diseases 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- GEIAQOFPUVMAGM-UHFFFAOYSA-N Oxozirconium Chemical compound [Zr]=O GEIAQOFPUVMAGM-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- OBZUDFAHIZFVHI-UHFFFAOYSA-N [La].[Si]=O Chemical compound [La].[Si]=O OBZUDFAHIZFVHI-UHFFFAOYSA-N 0.000 description 1
- DBOSVWZVMLOAEU-UHFFFAOYSA-N [O-2].[Hf+4].[La+3] Chemical compound [O-2].[Hf+4].[La+3] DBOSVWZVMLOAEU-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 150000004645 aluminates Chemical class 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- DIKBFYAXUHHXCS-UHFFFAOYSA-N bromoform Chemical compound BrC(Br)Br DIKBFYAXUHHXCS-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 1
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 1
- KUVFGOLWQIXGBP-UHFFFAOYSA-N hafnium(4+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Hf+4] KUVFGOLWQIXGBP-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000012705 liquid precursor Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001709 polysilazane Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium(II) oxide Chemical compound [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
- 229910000326 transition metal silicate Inorganic materials 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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Definitions
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- FIG. 3A is a top view of the local semiconductor device 10 .
- FIG. 3B is cross-sectional views along sections A-A in FIG. 3A .
- a flowable dielectric material is deposited to form an isolation material 110 at least in the recess 106 around the semiconductor fins 108 and 109 .
- a flowable dielectric material overfills the recess 106 and the mask layer 210 to form a flowable dielectric layer.
- the tri-layer photoresist 120 may be used, including a photoresist (PR) layer 121 as the top or uppermost portion, a middle layer 122 , and a bottom layer 124 .
- the tri-layer photoresist 120 is disposed on the substrate 100 and the isolation material 110 .
- the middle layer 122 of the tri-layer photoresist 120 which may include anti-reflective layers or backside anti-reflective layers to aid in the exposure and focus of the PR processing, and the bottom layer 124 which may be a hard mask material; for example, an oxide.
- the interlayer dielectric 140 is formed to cover the isolation structure 110 ′, the etched semiconductor fin 108 ′, and the semiconductor fin 109 .
- the interlayer dielectric 140 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or other methods known and used in the art for forming a gate dielectric.
- the interlayer dielectric 140 may include, for example, a high-k dielectric material such as metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, or combinations thereof.
- FIG. 11 is a cross-sectional view of the local semiconductor device 10 .
- the dummy layer 150 of FIG. 10 disposed on the top semiconductor fin 130 is then patterned to form a dummy gate electrode 152 by using the mask 214 (see FIG. 10 ).
- the dummy gate electrode 152 is disposed between the first sidewall structure 1082 a and the second sidewall structure 1082 b , is disposed on and straddles across the top semiconductor fin 130 .
- the dummy layer 150 may be patterned by an etching process, such as a dry plasma etching process or a wet etching process.
- At least one parameter, such as etchant, etching temperature, etching solution concentration, etching pressure, source power, radio frequency (RF) bias voltage, etchant flow rate, of the patterning (or etching) recipe can be tuned.
- RF radio frequency
- the lithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof.
- the lithography process is implemented or replaced by other methods, such as maskless photolithography, electron-beam writing, and ion-beam writing.
- the lithography process could implement nanoimprint technology.
- a pre-cleaning process may be performed to clean the recesses 232 and 234 with HF or other suitable solution.
- the epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes.
- the epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the recesses 232 and 234 of the top semiconductor fin 130 and the semiconductor fin 109 (e.g., silicon).
- a strained channel can be achieved to increase carrier mobility and enhance device performance.
- the epitaxy structures 172 and 174 may be in-situ doped.
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Abstract
Description
- As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (Fin FET). Fin FET devices include semiconductor fins with high aspect ratios and in which channel and source/drain regions of semiconductor transistor devices are formed. A gate is formed over and along the sides of the fin structure (e.g., wrapping) utilizing the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. In some devices, strained materials in source/drain (S/D) portions of the FinFET utilizing, for example, silicon germanium (SiGe), silicon phosphide (SiP) or silicon carbide (SiC), may be used to enhance carrier mobility. Further, channel on oxide structures have been proposed to improve carrier mobility and to maintain a straight fin profile.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIGS. 1A-8A are top views of a local semiconductor device at various stages of fabrication in accordance with some embodiments of the present disclosure; -
FIGS. 1B-8B are cross-sectional views along sections A-A inFIGS. 1A-8A respectively; and -
FIGS. 9-19 are cross-sectional views of a local semiconductor device at various stages of fabrication in accordance with some embodiments of the present disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.
- Illustrative embodiments for forming a semiconductor device will be described below with reference to
FIGS. 1A-19 . The structures illustrate operations which may be used in the process of forming a semiconductor device.FIGS. 1A-8A are top views of alocal semiconductor device 10 at various stages of fabrication in accordance with some embodiments of the present disclosure.FIGS. 1B-8B are cross-sectional views along sections A-A inFIGS. 1A-8A respectively.FIGS. 9-19 are cross-sectional views of alocal semiconductor device 10 at various stages of fabrication in accordance with some embodiments of the present disclosure. - Reference is made to
FIGS. 1A and 1B .FIG. 1A is a top view of alocal semiconductor device 10.FIG. 1B is cross-sectional views along sections A-A inFIG. 1A . Asubstrate 100 is provided. Thesubstrate 100 has atop surface 102. A patterned mask layer 200 (may be a hard mask layer) is disposed on thetop surface 102 of thesubstrate 100. In some embodiments, thesubstrate 100 may include silicon (Si). Alternatively, thesubstrate 100 may include germanium (Ge), silicon germanium, gallium arsenide (GaAs) or other appropriate semiconductor materials. Also alternatively, thesubstrate 100 may include an epitaxial layer. For example, thesubstrate 100 may have an epitaxial layer overlying a bulk semiconductor. Further, thesubstrate 100 may be strained for performance enhancement. For example, the epitaxial layer may include a semiconductor material different from those of the bulk semiconductor such as a layer of silicon germanium overlying a bulk silicon or a layer of silicon overlying a bulk silicon germanium formed by a process including selective epitaxial growth (SEG). Furthermore, thesubstrate 100 may include a semiconductor-on-insulator (SOI) structure such as a buried dielectric layer. Also alternatively, thesubstrate 100 may include a buried dielectric layer such as a buried oxide (BOX) layer, such as that formed by a method referred to as separation by implantation of oxygen (SIMOX) technology, wafer bonding, SEG, or other appropriate method. In various embodiments may include any of a variety of substrate structures and material. - The
mask layer 200 maintains the integrity of the patterns during etching of a recess 106 (seeFIGS. 2A and 2B ) formed in thesubstrate 100. In some embodiments, themask layer 200 is used as a planarization stop layer during the removal of excess flowable dielectric layer that fills the recess 106 (discussed in the process ofFIGS. 3A and 3B ). In some embodiments, themask layer 200 includes nitride. For example, themask layer 200 is made of silicon nitride (SiN). However, other materials, such as SiON, silicon carbide, or a combination thereof, may also be used. Themask layer 200 may be formed by a process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). Alternatively, themask layer 200 may be first made of a silicon oxide and then converted to SiN by nitridation. - In some embodiments, a
protective layer 210 is formed over thetop surface 102 of thesubstrate 100 and between themask layer 200 and thesubstrate 100. Theprotective layer 210 protects thetop surface 102 from direct contact with themask layer 200. For example, for a portion of thesubstrate 100 next to the recess 106 (seeFIGS. 2A and 2B ) which is filled by the isolation material 110 (seeFIGS. 3A and 3B ), theprotective layer 210 can protectactive regions substrate 100. Theactive regions isolation material 110 are formed. Depending upon the devices to be formed, theactive regions protective layer 210 is made of a thermal oxide. Once formed, themask layer 200 and theprotective layer 210 are patterned through suitable photolithographic and etching processes to formopenings top surface 102 for therecess 106 ofFIGS. 2A and 2B . - Reference is made to
FIGS. 2A and 2B .FIG. 2A is a top view of thelocal semiconductor device 10.FIG. 2B is cross-sectional views along sections A-A in FIG. 2A. Thesubstrate 100 ofFIGS. 1A and 1B are patterned to formsemiconductor fins semiconductor fins substrate 100 along a direction D2. The direction D1 intersects with the direction D2. In some embodiments, the direction D1 is orthogonal to the direction D2. The exposed portions of thesubstrate 100 through theopenings recess 106 in thesubstrate 100. Therecess 106 faces thetop surface 102 of thesubstrate 100 and separates theactive regions top surface 102 of thesubstrate 100. In some embodiments, the semiconductor device can be a Fin field effect transistor (FinFET), and therecess 106 is configured to separate adjacent twosemiconductor fins substrate 100. - Reference is made to
FIGS. 3A and 3B .FIG. 3A is a top view of thelocal semiconductor device 10.FIG. 3B is cross-sectional views along sections A-A inFIG. 3A . After the forming of thesemiconductor fins isolation material 110 at least in therecess 106 around thesemiconductor fins recess 106 and themask layer 210 to form a flowable dielectric layer. The flowable dielectric layer can be formed by using a spin on dielectric (SOD) formation process, or by depositing a flowable dielectric by a chemical vapor deposition (CVD) process, such as radical-component CVD. The examples of flowable silicon oxide precursors, include a silicate, a siloxane, a methyl SilsesQuioxane (MSQ), a hydrogen SisesQuioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS), a perhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silyl-amine (SA). Then, a planarization process is performed to remove the flowable dielectric layer outside therecess 106 to form theisolation material 110. That is, a top surface of theisolation material 110 and top surfaces of thesemiconductor fins recess 106. In some embodiments, the planarization process also removes themask layer 210 and the protective layer 210 (seeFIGS. 2A and 2B ). In some other embodiments, the planarization process removes themask layer 210, however, theprotective layer 210 is removed by an etching process. - Reference is made to
FIGS. 4A and 4B .FIG. 4A is a top view of thelocal semiconductor device 10.FIG. 4B is cross-sectional views along sections A-A inFIG. 4A . After the forming of theisolation material 110, atri-layer photoresist 120 is formed on thesubstrate 100 and theisolation material 110. - In some embodiments, the
tri-layer photoresist 120 may be used, including a photoresist (PR)layer 121 as the top or uppermost portion, amiddle layer 122, and abottom layer 124. Thetri-layer photoresist 120 is disposed on thesubstrate 100 and theisolation material 110. Themiddle layer 122 of thetri-layer photoresist 120 which may include anti-reflective layers or backside anti-reflective layers to aid in the exposure and focus of the PR processing, and thebottom layer 124 which may be a hard mask material; for example, an oxide. To pattern thetri-layer photoresist 120, thePR layer 121 is patterned using a mask, exposure to radiation, such as light or an excimer laser, for example, a bake or cure operation to harden the resist, and use of a developer to remove either the exposed or unexposed portions of the resist, depending on whether a positive resist or a negative resist is used, to form the pattern from the mask in thePR layer 121. ThePR layer 121 is patterned to form anopening 128 above thesemiconductor fin 108. Specifically, the vertically projection of theopening 128 is locates on thesemiconductor fin 108 and outside thesemiconductor fin 109. Theopening 128 has a width W2 along the direction D1. Thesemiconductor fin 108 has a width W1 along the direction D1, and the width W1 is larger than the width W2. Thispatterned PR layer 121 is then used to etch the underlyingmiddle layer 122 andbottom layer 124 to form an etch mask for the target layer; here, thesemiconductor fin 108 from theopening 128. - Reference is made to
FIGS. 5A and 5B .FIG. 5A is a top view of thelocal semiconductor device 10.FIG. 5B is cross-sectional views along sections A-A inFIG. 5A . After the forming of thetri-layer photoresist 120, themiddle layer 122 ofFIGS. 4A and 4B are patterned to form anopening 228. A trench etching is performed to form a patternedmiddle layer 122′ having the opening 228 therein. Theopening 228 has a width W3 along the direction D1 substantially equal to the width W2 of opening 128 and smaller than the width W1 of thesemiconductor fin 108. InFIGS. 5A and 5B , the patternedPR layer 121 is used as a mask during the trench etching. The term “substantially” as used herein may be applied to modify any quantitative representation which could permissibly vary without resulting in a change in the basic function to which it is related. In the trench etching, the middle layer 122 (seeFIGS. 4A and 4B ) may be etched by various methods, including a dry etch, a wet etch, or a combination of dry etch and wet etch. The dry etching process may implement fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCH), bromine-containing gas (e.g., HBr and/or CHBR3), oxygen-containing gas, iodine-containing gas, other suitable gases and/or plasmas, or combinations thereof. The etching process may include a multiple-step etching to gain etch selectivity, flexibility and desired etch profile. - Reference is made to
FIGS. 6A and 6B .FIG. 6A is a top view of thelocal semiconductor device 10.FIG. 6B is cross-sectional views along sections A-A inFIG. 6A . After the patterned of the middle layer 122 (seeFIG. 5B ), thebottom layer 124 ofFIG. 5B is patterned to form anopening 127. After themask layer 124 is patterned, the patternedPR layer 121 and the patternedmiddle layer 122′ are removed, and then thesemiconductor fin 108 is etched to form atrench 129 through theopening 127. That is, using the patternedbottom layer 124′ as a mask, thesemiconductor fin 108 is etched to form an etchedsemiconductor fin 108′ having thetrench 129 therein. - In other words, the etched
semiconductor fin 108′ is formed by removing the portion thereof, thereby forming abottom semiconductor fin 1080, and forming afirst sidewall structure 1082 a and asecond sidewall structure 1082 b disposed over thebottom semiconductor fin 1080. Specifically, thebottom semiconductor fin 1080 is disposed on thesubstrate 100, and extends along the direction D1 as thesemiconductor fin 108. Thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b protrude from thebottom semiconductor fin 1080 facing away thesubstrate 100, and define thetrench 129 with thebottom semiconductor fin 1080 therebetween. That is, thetrench 129 is formed by inner surfaces of thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b and a top surface thebottom semiconductor fin 1080. In addition, thefirst sidewall structure 1082 a and asecond sidewall structure 1082 b are covered by the patternedbottom layer 124′. Theopening 127 of the patternedbottom layer 124′ and thetrench 129 of thesemiconductor fin 108 have a width W4 and a width W5 along the direction D1 respectively. The width W4 and the width W5 is substantially the same and both smaller than the width W1 of thesemiconductor fin 108. - In some embodiments, the
trench 129 is formed by various methods, including a dry etch, a wet etch, or a combination of dry etch and wet etch. The dry etching process may implement fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), bromine-containing gas (e.g., HBr and/or CHBr3), oxygen-containing gas, iodine-containing gas, other suitable gases and/or plasmas, or combinations thereof. The etching process may include a multiple-step etching to gain etch selectivity, flexibility and desired etch profile. - Reference is made to
FIGS. 7A and 7B .FIG. 7A is a top view of thelocal semiconductor device 10.FIG. 7B is cross-sectional views along sections A-A inFIG. 7A . After the etched of thesemiconductor fin 108 to form thetrench 129, atop semiconductor fin 130 as the active region 104 (seeFIGS. 1B and 2B ) is formed in thetrench 129. An epitaxial growth process is performed on exposed parts of thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b, and performed on exposed parts of thebottom semiconductor fin 1080 from theopening 127. Then, an epitaxy material is formed in thetrench 129. - Specifically, the epitaxy material epitaxial grows at least from the
first sidewall structure 1082 a, thesecond sidewall structure 1082 b, and thebottom semiconductor fin 1080. Then, a portion of the epitaxy material above a top surface of theisolation material 110 is removed to form thetop semiconductor fin 130 in thetrench 129 and over thebottom semiconductor fin 1080. Therefore, thetop semiconductor fin 130 is formed between thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b and on thebottom semiconductor fin 1080. As such, opposite sidewalls of thetop semiconductor fin 130 are in contact with thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b, and a bottom portion of thetop semiconductor fin 130 is in contact with thebottom semiconductor fin 1080. On the other hand, thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b are located on two opposite ends of thetop semiconductor fin 130, respectively disposed between and extends pass thetop semiconductor fin 130 and theisolation material 110, and arranged in the direction D1. - In some embodiments, at least one of the
first sidewall structure 1082 a and thesecond sidewall structure 1082 b is made of a material that is the same as thebottom semiconductor fin 1080, and thetop semiconductor fin 130 is made of a material that is different from that of thebottom semiconductor fin 1080. In some embodiments, thetop semiconductor fin 130 is made of the material whose lattice constant is greater than that of the at least one thefirst sidewall structure 1082 a, thesecond sidewall structure 1082 b, and thebottom semiconductor fin 1080. In some embodiments, thebottom semiconductor fin 1080, thefirst sidewall structure 1082 a, and thesecond sidewall structure 1082 b may include a material such as Si, and thetop semiconductor fin 130 may include a material such as SiGe. - With such configuration, the
first sidewall structure 1082 a, thesecond sidewall structure 1082 b, and thebottom semiconductor fin 1080 are positioned such that subsequent epitaxial growth processes that forming thetop semiconductor fin 130 during device fabrication do not in contact with theisolation material 110 on ends of thebottom semiconductor fin 1080. Here, if thetop semiconductor fin 130 is not formed on thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b, defects such as voids or dislocations may be formed at an interface of theisolation material 110 and thetop semiconductor fin 130, because theisolation material 110 is less easily grown on the oxide surface. In contrast, since thetop semiconductor fin 130 is in contact with thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b, the epitaxial growth of thetop semiconductor fin 130 is enhanced. - Reference is made to
FIGS. 8A and 8B .FIG. 8A is a top view of thelocal semiconductor device 10.FIG. 8B is cross-sectional views along sections A-A inFIG. 8A . After the forming of thetop semiconductor fin 130, the patternedbottom layer 124′ is removed and theisolation material 110 is recessed to form anisolation structure 110′. An anisotropic etch is used to recess theisolation material 110 into thesubstrate 100 to form theisolation structure 110′. Theisolation structure 110′ surrounds the etchedsemiconductor fin 108′ and thesemiconductor fin 109. The etchedsemiconductor fin 108′ and thesemiconductor fin 109 are exposed above theisolation structure 110′. That is, a top portion of the etchedsemiconductor fin 108′ and thesemiconductor fin 109 are not covered by theisolation structure 110′, and a bottom surface of thetop semiconductor fin 130 is higher than atop surface 11 of theisolation structure 110′. - Specifically, as shown in
FIGS. 8A and 8B , theisolation structure 110′ is disposed on thesubstrate 100, and from the top surface of theisolation structure 110′, a total of thefirst sidewall structure 1082 a, thesecond sidewall structure 1082 b, and thetop semiconductor fin 130 are exposed. Thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b cap thetop semiconductor fin 130. Thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b are respectively located between theisolation structure 110′ and thetop semiconductor fin 130. Furthermore, a bottom portion of at least one of thefirst sidewall structure 1082 a, thesecond sidewall structure 1082 b, and thetop semiconductor fin 130 is higher than atop surface 11 of theisolation structure 110′. - Reference is made to
FIG. 9 .FIG. 9 is a cross-sectional view of thelocal semiconductor device 10. After the removing the patternedbottom layer 124′ and the recessed of theisolation structure 110, aninterlayer dielectric 140 and adummy layer 150 are disposed on theisolation structure 110′, the etchedsemiconductor fin 108′, and thesemiconductor fin 109. - The
interlayer dielectric 140 is formed to cover theisolation structure 110′, the etchedsemiconductor fin 108′, and thesemiconductor fin 109. Theinterlayer dielectric 140 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or other methods known and used in the art for forming a gate dielectric. Theinterlayer dielectric 140 may include, for example, a high-k dielectric material such as metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, or combinations thereof. Some embodiments may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HMO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitrides (SiON), and combinations thereof. Theinterlayer dielectric 140 may have a multilayer structure such as one layer of silicon oxide (e.g., interfacial layer) and another layer of high-k material. Theinterlayer dielectric 140 may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxide, ozone oxidation, other suitable processes, or combinations thereof. - The
dummy layer 150 is formed on theinterlayer dielectric 140. Thedummy layer 150 may be deposited by chemical vapor deposition (CVD), by sputter deposition, or by other techniques known and used in the art for depositing conductive materials. Thedummy layer 150 may include polycrystalline-silicon (poly-Si) or poly-crystalline silicon-germanium (poly-SiGe). Further, thedummy layer 150 may be doped poly-silicon with uniform or non-uniform doping. - Reference is made to
FIG. 10 .FIG. 10 is a cross-sectional view of thelocal semiconductor device 10. After the forming theinterlayer dielectric 140 and thedummy layer 150, a patterned mask layer is formed on thedummy layer 150. The patterned mask layer includesmasks mask 214 defines a profile of a gate electrode disposed on thetop semiconductor fin 130, and themask 215 covers thedummy layer 150 disposed on thesemiconductor fin 109. - Reference is made to
FIG. 11 .FIG. 11 is a cross-sectional view of thelocal semiconductor device 10. After the forming of themasks dummy layer 150 ofFIG. 10 disposed on thetop semiconductor fin 130 is then patterned to form adummy gate electrode 152 by using the mask 214 (seeFIG. 10 ). Thedummy gate electrode 152 is disposed between thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b, is disposed on and straddles across thetop semiconductor fin 130. Thedummy layer 150 may be patterned by an etching process, such as a dry plasma etching process or a wet etching process. At least one parameter, such as etchant, etching temperature, etching solution concentration, etching pressure, source power, radio frequency (RF) bias voltage, etchant flow rate, of the patterning (or etching) recipe can be tuned. - After the patterning process, the
masks FIG. 10 may then be removed. The portion of theinterlayer dielectric 140 disposed on thetop semiconductor fin 130 and not covered by thedummy gate electrode 152 may or may not be removed during the etching process. In the case where someinterlayer dielectric 140 remains on thetop semiconductor fin 130 not covered by thedummy gate electrode 152, theinterlayer dielectric 140 may be subsequently removed by dry or wet etching to form agate dielectric 142. Thegate dielectric 142 and thedummy gate electrode 152 can refer to as agate structure 302. Thus, thegate structure 302 is disposed between thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b, and is disposed on and straddles across thetop semiconductor fin 130. - Reference is made to
FIG. 12 .FIG. 12 is a cross-sectional view of thelocal semiconductor device 10. After the forming thedummy gate electrode 152 and thegate dielectric 142, another patterned mask layer is formed on the remainingdummy layer 150 and thedummy gate electrode 152. The patterned mask layer includesmasks mask 217 defines a profile of a dummy gate electrode 154 (seeFIG. 13 ) disposed on thesemiconductor fin 109, and themask 216 covers thedummy gate electrode 152, thetop semiconductor fin 130, the etchedsemiconductor fin 108′, and theisolation structure 110′. - Reference is made to
FIG. 13 .FIG. 13 is a cross-sectional view of thelocal semiconductor device 10. After the forming the other patterned mask layer, the remainingdummy layer 150 ofFIG. 12 disposed on thesemiconductor fin 109 is then patterned to form adummy gate electrode 154 by using the mask 217 (seeFIG. 12 ). The remainingdummy layer 150 may be patterned by an etching process, such as a dry plasma etching process or a wet etching process. At least one parameter, such as etchant, etching temperature, etching solution concentration, etching pressure, source power, radio frequency (RF) bias voltage, etchant flow rate, of the patterning (or etching) recipe can be tuned. - After the patterning process, the
masks FIG. 12 may then be removed. The portion of theinterlayer dielectric 140 not covered by thedummy gate electrode 154 may or may not be removed during the etching process. In the case where someinterlayer dielectric 140 remains on thesemiconductor fin 109 not covered by thedummy gate electrode 154, theinterlayer dielectric 140 may be subsequently removed by dry or wet etching to form agate dielectric 144. Thegate dielectric 144 and thedummy gate electrode 154 can refer to as agate structure 304. - It is noted that although in
FIGS. 10 to 13 , thegate structures gate structures FIG. 10 , two patterned mask layers can be formed over thedummy layer 150 and respectively over thetop semiconductor fin 130 and thesemiconductor fin 109. Thedummy layer 150 is then patterned using the patterned mask layers as masks and form thegate structures top semiconductor fin 130 and thesemiconductor fin 109. - Reference is made to
FIG. 14 .FIG. 14 is a cross-sectional view of thelocal semiconductor device 10. After the forming of thegate structures gate spacers 162 is formed on thetop semiconductor fin 130 and along thedummy gate electrode 152, and a pair ofgate spacers 164 is formed on thesemiconductor fin 109 and along thedummy gate electrode 164. In some embodiments, thegate spacers gate spacers top semiconductor fin 130 and thesemiconductor fin 109 by CVD, PVD, ALD, or other suitable technique. Then, an anisotropic etching is performed on the blanket layer to form thegate spacers dummy gate electrodes - Furthermore, the
top semiconductor fin 130 includes a channel portion (may also refer to as a channel region) 132 and source/drain portions (may also refer to as source/drain regions) 134 and 136 disposed therein. Thechannel portion 132 is disposed in thetop semiconductor fin 130, below thegate structure 302 and the pair ofgate spacers 162, and between thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b. On the other hand, thegate structure 302 covers thechannel portion 132 of the top semiconductor fin. In addition, the source/drain portions dummy gate electrode 152 and uncovered by thegate structure 302. The source/drain portions 134 is disposed between thechannel portion 132 and thefirst sidewall structure 1082 a, and the source/drain portions 136 is disposed between thechannel portion 132 and thesecond sidewall structure 1082 b. - With such configuration, the
top semiconductor fin 130 is in contact with thefirst sidewall structure 1082 a, thesecond sidewall structure 1082 b, and thebottom semiconductor fin 1080, whereby enabling thechannel portion 132 of thetop semiconductor fin 130 to improve fully strain channel (FSC) due to the two opposite ends of thetop semiconductor fin 130 strain with thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b of the etchedsemiconductor fin 108′ respectively, thus to improve performance of said two opposite ends. As such, a stress relaxation occurring at the two opposite ends of thetop semiconductor fin 130 reduces epitaxial defects, such as, voids or dislocations, at an interface of thesidewall structure 1082 a (1082 b) and thetop semiconductor fin 130. Further, the epitaxial defects of the two opposite ends of thetop semiconductor fin 130 will be reduced. Hence, the epitaxial quality of thechannel portion 132 oftop semiconductor fin 130 will also be enhanced, such that the performance of thechannel portion 132 will be improved. - Reference is made to
FIG. 15 .FIG. 15 is a cross-sectional view of thelocal semiconductor device 10. After the forming the pairs of thegate spacers top semiconductor fin 130 and thesemiconductor fin 109 exposed both by thedummy gate electrodes gate spacers recesses top semiconductor fin 130, thetop semiconductor fin 130forms protruding portions first sidewall structure 1082 a and thesecond sidewall structure 1082 b, and arranged in the direction D1. - Removing portions of the
top semiconductor fin 130 and thesemiconductor fin 109 may include forming a photoresist layer or a capping layer (such as an oxide capping layer) over the structure ofFIG. 14 , patterning the photoresist or capping layer to have openings that expose a portion of thetop semiconductor fin 130 and thesemiconductor fin 109, and etching back material from thetop semiconductor fin 130 and thesemiconductor fin 109. In some embodiments, thetop semiconductor fin 130 and thesemiconductor fin 109 can be etched using a dry etching process. Alternatively, the etching process is a wet etching process, or combination dry and wet etching process. Removal may include a lithography process to facilitate the etching process. The lithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. Alternatively, the lithography process is implemented or replaced by other methods, such as maskless photolithography, electron-beam writing, and ion-beam writing. In yet some other embodiments, the lithography process could implement nanoimprint technology. In some embodiments, a pre-cleaning process may be performed to clean therecesses - Reference is made to
FIG. 16 .FIG. 16 is a cross-sectional view of thelocal semiconductor device 10. After the forming therecesses epitaxy structures recesses top semiconductor fin 130 and thesemiconductor fin 109. Theepitaxy structures 172 are at least partially embedded in the source/drain portions top semiconductor fin 130, and disposed between thefirst sidewall structure 1082 a and thegate structure 302 and between thesecond sidewall structure 1082 b and thegate structure 302 respectively. - On the other hand, the
first sidewall structure 1082 a and thesecond sidewall structure 1082 b are separated from theepitaxy structures 172. In other words, protrudingportion 130 a of thetop semiconductor fin 130 is disposed between and in contact with thefirst sidewall structure 1082 a and theepitaxy structures 172, and protrudingportion 130 b is disposed between and in contact with thesecond sidewall structure 1082 b and theepitaxy structures 172. In some embodiments, a bottom portion of thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b is lower than a bottom surface of theepitaxy structures 172. In some other embodiments, however, a bottom surface of theepitaxy structures 172 and a bottom surface of thetop semiconductor fin 130 are coplanar. - The
epitaxy structures recesses top semiconductor fin 130 and thesemiconductor fin 109. In some embodiments, the lattice constant of theepitaxy structures top semiconductor fin 130 and thesemiconductor fin 109, and theepitaxy structures recesses top semiconductor fin 130 and the semiconductor fin 109 (e.g., silicon). Thus, a strained channel can be achieved to increase carrier mobility and enhance device performance. Theepitaxy structures epitaxy structures epitaxy structures epitaxy structures - Then, an interlayer dielectric (ILD) 170 is formed at outer sides of the
gate spacers top semiconductor fin 130 and thesemiconductor fin 109. TheILD 170 includes silicon oxide, oxynitride or other suitable materials. TheILD 170 includes a single layer or multiple layers. TheILD 170 is formed by a suitable technique, such as CVD or ALD. A chemical mechanical planarization (CMP) process may be applied to removeexcessive ILD 170 and expose the top surface of thedummy gate electrodes - Reference is made to
FIG. 17 .FIG. 17 is a cross-sectional view of thelocal semiconductor device 10. After the forming theepitaxy structures ILD 170, thedummy gate electrodes 152 and 154 (seeFIG. 16 ) are removed to form anopening 156 with thegate spacers 162 as its sidewall and anopening 158 with thegate spacers 164 as its sidewall. In some other embodiments, thegate dielectrics dummy gate electrodes gate dielectrics dummy gate electrodes 152 and 154 (and thegate dielectrics 142 and 144) may be removed by dry etch, wet etch, or a combination of dry and wet etch. For example, a wet etch process may include exposure to a hydroxide containing solution (e.g., ammonium hydroxide), deionized water, and/or other suitable etchant solutions. - Reference is made to
FIG. 18 .FIG. 18 is a cross-sectional view of thelocal semiconductor device 10. After the removing of thedummy gate electrodes metal gate electrodes openings 156 and 158 (seeFIG. 17 ). Thegate electrodes openings gate dielectric 142 and thegate electrode 182 can refer to as agate structure 402, and thegate dielectric 144 and thegate electrode 184 can refer to as agate structure 404. - As shown in
FIG. 18 , afirst device 12 and asecond device 14 are formed. Thefirst device 12 includes thetop semiconductor fin 130, thefirst sidewall structure 1082 a and thesecond sidewall structure 1082 b, theepitaxy structures 172, the gate structure 402 (or thegate structure 302 ofFIG. 16 ), and thegate spacers 162. Thesecond device 14 includes thesemiconductor fin 109, theepitaxy structures 174, the gate structure 404 (or thegate structure 304 ofFIG. 16 ), and thegate spacers 164. In the embodiments where thefirst device 12 is p-channel metal-oxide-semiconductor field-effect transistors (p-channel MOSFETs), and thesecond device 14 is n-channel MOSFETs. - Reference is made to
FIG. 19 .FIG. 19 is a cross-sectional view of thelocal semiconductor device 10. After the forming of themetal gate electrodes trenches ILD 170. Thetrenches 186 expose theepitaxy structures 172, and thetrenches 188 expose theepitaxy structures 174. Metal such as tungsten is then deposited into thetrenches epitaxy structures drain contacts drain contacts epitaxy structures - According to some embodiments, the top semiconductor fin is in contact with the first sidewall structure, the second sidewall structure, and the bottom semiconductor fin, whereby enabling the channel portion of the top semiconductor fin to improve fully strain channel (FSC) due to the two opposite ends of the top semiconductor fin strain with the first sidewall structure and the second sidewall structure of the etched semiconductor fin respectively, thus to improve performance of said two opposite ends. As such, a stress relaxation occurring at the two opposite ends of the top semiconductor fin reduces epitaxial defects, such as, voids or dislocations, at an interface of the sidewall structure and the top semiconductor fin. Further, the epitaxial defects of the two opposite ends of the top semiconductor fin will be reduced. Hence, the epitaxial quality of the channel portion of top semiconductor fin will also be enhanced, such that the performance of the channel portion will be improved.
- According to some embodiments, a semiconductor device includes a substrate, a bottom semiconductor fin, at least one sidewall structure, a top semiconductor fin, and a gate structure. The bottom semiconductor fin is disposed on the substrate. The sidewall structure protrudes from the semiconductor fin. The top semiconductor fin is disposed on the bottom semiconductor fin. The top semiconductor fin includes a channel portion and at least one source/drain portion. The source/drain portion is disposed between the channel portion and the sidewall structure. The gate structure covers the channel portion of the top semiconductor fin.
- According to some embodiments, a semiconductor device includes a substrate, a bottom semiconductor fin, atop semiconductor fin, a first sidewall structure and a second sidewall structure, and a gate structure. The bottom semiconductor fin is disposed on the substrate and extending along a direction. The top semiconductor fin is disposed on the bottom semiconductor fin. The first sidewall structure and a second sidewall structure are disposed on two opposite ends of the top semiconductor fin and arranged in the direction, in which the top semiconductor fin is made of a material that is different from that of the first sidewall structure and the second sidewall structure. The gate structure is disposed between the first sidewall structure and the second sidewall structure and straddles across the top semiconductor fin.
- According to some embodiments, a method for manufacturing a semiconductor device includes forming fin structure on a substrate; forming an isolation material surrounding the fin structure; removing a portion of the fin structure to form a bottom semiconductor fin and sidewall structures over the bottom semiconductor fin, in which the sidewall structures are in contact with the isolation material, and the bottom semiconductor fin and the sidewall structures define a trench therebetween; forming a top semiconductor fin in the trench, between the sidewall structures, and over the semiconductor fin; and forming a gate structure on the top semiconductor fin.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
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US20130011986A1 (en) * | 2011-07-08 | 2013-01-10 | Huajie Zhou | Method for Manufacturing Full Silicide Metal Gate Bulk Silicon Multi-Gate Fin Field Effect Transistors |
US8815712B2 (en) | 2011-12-28 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for epitaxial re-growth of semiconductor region |
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US9136106B2 (en) | 2013-12-19 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
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