TW201916106A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.

Description

 Method of forming a semiconductor device  

Embodiments of the present invention relate to a method of forming a semiconductor device, and more particularly to forming an oxide layer by depositing a precursor of an allotrope containing no oxygen.

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. The semiconductor device is generally fabricated by sequentially depositing an insulating or dielectric layer, a conductive layer, and a material of the semiconductor layer on the semiconductor substrate, and patterning a plurality of material layers by using a lithography and etching process to form a circuit member and a unit thereof. on.

The semiconductor industry continues to reduce the minimum structural size and continuously improve the bulk density of various electronic components such as transistors, diodes, resistors, capacitors, or the like to integrate more components into a given area. However, as the minimum size of the structure shrinks, each process used will present additional problems and these additional issues need to be addressed.

A method of forming a semiconductor device according to an embodiment of the present invention includes: placing a substrate into a deposition chamber; depositing a layer on the substrate; and depositing an oxide layer on the layer, comprising: making the first precursor material Flowing into the deposition chamber; forming a portion of the oxide layer from the first precursor material in the deposition chamber; igniting the second precursor material into a plasma, and the second precursor material is free of oxygen allotropes And forming a portion of the oxide layer from the plasma in the deposition chamber.

A method of forming a semiconductor device according to an embodiment of the present invention includes: depositing a dielectric layer on a substrate; performing a first patterning step to form a recess in the dielectric layer; and depositing an oxide film on the dielectric layer In the recess of the dielectric layer, and the oxide film contacts the dielectric layer, wherein the oxide film is formed of a plurality of precursors, wherein the precursor does not contain oxygen, and wherein the step of depositing the oxide film comprises forming a first precursor of the precursor Plasma of matter.

A method for forming a semiconductor device according to an embodiment of the present invention includes: forming a dielectric layer on a semiconductor substrate; patterning a photoresist on the dielectric layer; placing the semiconductor substrate and the photoresist into the process chamber; using an etching process, Transferring the pattern of photoresist to the dielectric layer; sequentially providing a plurality of precursors into the process chamber, wherein the precursor contains an oxygen-free allotrope; and forming an oxide layer in the process chamber to dielectric On the layer, the oxide layer contacts the dielectric layer, and the step of forming the oxide layer includes igniting at least one precursor of the precursor into a plasma.

A-A', B-B', 6C-6C', 6F-6F', 6I-6I'‧‧‧

ER1, ER2‧‧‧ edge roughness

DT1, DT3‧‧‧ thickness variation

T1, T2, T3, T4, T5, T6‧‧‧ thickness

WR1, WR2‧‧‧ width roughness

W1, W2, W3, W4, W5‧‧‧ width

100, 500, 600, 700‧‧‧ semiconductor devices

102‧‧‧Semiconductor substrate

112, 612, 702‧‧ ‧ interlayer dielectric layer

114, 514, 614‧‧‧ below

116, 516, 616, 736, 862‧‧‧ low temperature dielectric film

118, 518, 618‧‧‧ upper layer

120, 632‧‧‧ conductive lines

200‧‧‧Deposition system

203‧‧‧Sedimentation chamber

205‧‧‧First Precursor Delivery System

206‧‧‧Second precursor transport system

207‧‧‧ gas supply

209‧‧‧Flow Controller

213‧‧‧Precursor gas controller

215‧‧‧Control unit

216‧‧‧Management

217‧‧‧sprinkler head

219‧‧‧Shell

221‧‧‧Installation platform

223‧‧‧vacuum pump

225‧‧‧Exhaust outlet

230‧‧‧First electrode

231‧‧‧Upper electrode

232, 233‧‧‧RF generator

301‧‧‧ processor

303‧‧‧ display

305‧‧‧Input/output components

306‧‧‧Central Processing Unit

308‧‧‧ memory

310‧‧‧Many storage devices

312‧‧ ‧ busbar

314‧‧‧ display card

316‧‧‧Input/Output Interface

318‧‧‧Internet interface

320‧‧‧LAN or WAN

400‧‧‧ Chart

410, 420, 430‧‧‧ curves

512‧‧‧ bottom layer

502, 602, 704, 850‧‧‧ substrates

522, 622, 624, 734, 750 ‧ ‧ openings

612‧‧‧Target layer

630, 764‧‧‧ conductive materials

724‧‧‧Mask area

728, 854‧‧‧ mask layer

770‧‧‧Line Cutting Department

772‧‧‧First conductive line

774‧‧‧Second conductive line

802‧‧‧Source/Bungee Zone

818‧‧‧ gate dielectric layer

820‧‧‧ gate

850B‧‧‧First District

850C‧‧‧Second District

852‧‧‧Anti-reflective coating

856‧‧‧ core layer

858‧‧ core

864‧‧‧ spacers

868, 874‧‧‧Fins

872‧‧‧Shallow trench isolation zone

1A through 1H are cross-sectional views of various intermediate stages of a method of forming a conductive line in a semiconductor device employing a low temperature dielectric film in some embodiments.

2 is a deposition system for depositing a low temperature dielectric film in some embodiments.

Figure 3 is a control unit for a deposition system in some embodiments.

Figure 4 is an experimental result of the relationship between underlying layer damage and low temperature dielectric film thickness in some embodiments.

5A through 5C are cross-sectional views of various intermediate stages of a semiconductor device employing a low temperature dielectric film in some embodiments.

Figures 6A through 6J are cross-sectional or plan views of various intermediate stages of the formation process for conductive traces in a semiconductor device employing a low temperature dielectric film in some embodiments.

7A-7B, 8, 9A-9C, 10A-10C, 11, 12A-12B, 13A-13C, 14A-14B, 15A-15B are conductive lines in a semiconductor device using a low temperature dielectric film in some embodiments , a cross-sectional view, a plan view, or a perspective view of various intermediate stages of the forming method.

16 through 25 are cross-sectional views of various intermediate stages of a fin field effect transistor semiconductor device employing a low temperature dielectric film in some embodiments.

Different embodiments provided below can implement the different structures of the present disclosure. The specific components and arrangements of the embodiments are intended to simplify the disclosure and not to limit the disclosure. For example, the description of forming the first member on the second member includes direct contact between the two, or the other is spaced apart from other direct members rather than in direct contact. In addition, the various embodiments of the disclosure may be repeated, and the description is only for the sake of simplicity and clarity, and does not represent the same correspondence between units having the same reference numerals between different embodiments and/or arrangements.

In addition, spatial relative terms such as "below", "below", "below", "above", "above", or similar terms may be used to simplify the description of one element and another element in the illustration. Relative relationship. Spatial relative terms may be extended to elements used in other directions, and are not limited to the illustrated orientation. The component can also be rotated by 90° or other angles, so the directional terminology is only used to illustrate the orientation in the illustration.

Various embodiments described herein are directed to forming a low temperature dielectric film for use in the fabrication of semiconductor devices. The low temperature dielectric films, processes, methods, or materials described herein can be used in a variety of applications, including fin field effect transistors. For example, embodiments of the present invention are well suited for patterning fins to provide a tighter space between the structures. Furthermore, the spacers used to form the fins of the fin field effect transistors are also referred to as cores, and the methods of formation thereof may employ the techniques or materials described herein. In another example, the low temperature dielectric film can be used as part of a multilayer photoresist in a multiple patterning process, or as a film that reduces the size of the structure when patterned. However, embodiments of the invention are not limited to these applications. The term "low temperature dielectric film" as used herein refers to a dielectric layer deposited using a lower process temperature, such as less than or equal to 200 °C. In some instances, depositing a dielectric material at a lower process temperature may reduce possible damage to the underlying layer of dielectric material during deposition.

The low temperature dielectric films described herein can be used to form different processes for different types of semiconductor devices. In the first exemplary embodiment, FIGS. 1A through 1J show cross-sectional views of intermediate stages in forming an electrically conductive line 120 in an interlayer dielectric layer 112 on a semiconductor substrate 102.

In the embodiment of FIGS. 1A through 1H, the low temperature dielectric film 116 serves as an etch mask for patterning the interlayer dielectric layer 112 when the conductive traces 120 are formed. For example, the embodiment illustrated in Figures 1A through 1H is part of a method of forming a conductive trace in a post-stage process. In FIG. 1A, an interlayer dielectric layer 112 and an underlying layer 114 are formed in the semiconductor device 100. In some embodiments, the interlayer dielectric layer 112 can be formed on the semiconductor substrate 102. The composition of the semiconductor substrate 102 can be a semiconductor material such as doped or undoped germanium, or an active layer of a semiconductor substrate on the insulating layer. The semiconductor substrate 102 may include other semiconductor materials such as germanium, semiconductor compounds (including germanium carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide), and semiconductor alloys (including germanium and phosphorus). Gallium arsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide, or a combination thereof. Other substrates such as a multilayer substrate or a compositionally graded substrate may also be used. Devices (not shown) such as transistors, diodes, capacitors, resistors, or the like may be formed in and/or on the active surface of the semiconductor substrate 102. The device may comprise a variety of active devices such as transistors or the like, and a variety of passive devices such as capacitors, resistors, inductors, or the like. The active device and the passive device may be formed in or on the semiconductor substrate 102 by any suitable method. In some examples, the semiconductor substrate 102 can be omitted.

The interlayer dielectric layer 112 may comprise a dielectric material, which may be formed by spin coating, chemical vapor deposition, flowable chemical vapor deposition, plasma enhanced chemical vapor deposition, or other deposition methods. The composition of the interlayer dielectric layer 112 may be a phosphonate glass, a borosilicate glass, a boron-doped phosphosilicate glass, an undoped tellurite glass, an oxide of tetraethoxydecane, or analog.

FIG. 1A also shows that the underlying layer 114 is formed on the interlayer dielectric layer 112. In some examples, other layers may be formed between the interlayer dielectric layer 112 and the underlying layer 114. In some embodiments, the lower layer 114 can be a photoresist layer or a polymer layer. The method of forming the lower layer 114 can be spin coating or another suitable process. As with some examples shown in FIG. 1A, the thickness T1 of the lower layer 114 can be between about 10 nm and about 600 nm. However, these thicknesses are for illustrative purposes only and are not intended to limit the scope of the embodiments, and the precise thickness of the deposited layer can be any suitable desired thickness.

Although FIGS. 1A through 1G show that the interlayer dielectric layer 112 physically contacts the semiconductor substrate 102, or the underlying layer 114 physically contacts the interlayer dielectric layer 112, any number of interposers may be located between the interlayer dielectric layer 112 and the semiconductor substrate 102. The interposer may include another interlayer dielectric layer (including a low-k dielectric and a contact plug formed therein), an inter-metal dielectric layer (having conductive lines and/or vias formed therein), one or more An intermediate layer (such as an etch stop layer, an adhesive layer, an anti-reflective coating, or the like), a combination of the above, or the like. For example, an etch stop layer (not shown) may be formed directly under the interlayer dielectric layer 112. The etch stop layer can stop subsequent etching processes performed on the interlayer dielectric layer 112. The materials and processes used to form the etch stop layer may depend on the material of the interlayer dielectric layer 112.

As shown in FIG. 1B, a low temperature dielectric film 116 is formed on the lower layer 114. In some embodiments, the low temperature dielectric film 116 can be part of a multilayer photoresist. For example, the low temperature dielectric film 116 can be an intermediate layer of a multilayer photoresist stack, while the lower layer 114 can be a bottom layer of a multilayer photoresist stack. In some embodiments, the composition of the low temperature dielectric film 116 may be tantalum nitride, hafnium oxynitride, niobium carbonitride, tantalum carbide, tantalum carbonitride, tantalum oxide, titanium oxide, oxides, other dielectrics, the above a combination, or the like. The method of forming the low temperature dielectric film 116 may be a deposition process such as plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, physical vapor deposition, plasma enhanced atomic layer deposition, or the like. In some embodiments, the low temperature dielectric film 116 can have a thickness between about 10 Å and about 50 nm. However, these thicknesses are for illustrative purposes only and are not intended to limit the scope of the embodiments of the invention, and the precise thickness of the deposited layer may be any suitable desired thickness.

2 and 3 show a deposition system 200 for forming a low temperature dielectric film such as a low temperature dielectric film 116. In some embodiments, deposition system 200 forms a low temperature dielectric film using a plasma enhanced atomic layer deposition process. In some embodiments, deposition system 200 receives a first precursor material from first precursor delivery system 205 and a second precursor material from second precursor delivery system 206 to form a layer of material on a semiconductor substrate 102. In an embodiment, the first precursor delivery system 205 and the second precursor delivery system 206 can be coupled to each other to deliver a plurality of different precursor materials into the deposition chamber 203, wherein the semiconductor substrate 102 is located in the deposition chamber 203 . In some examples, first precursor delivery system 205 and second precursor delivery system 206 may have similar physical components to each other. In some embodiments, other precursor delivery systems can be part of deposition system 200 and can be similar to first precursor delivery system 205 or second precursor delivery system 206.

In some embodiments, the first precursor delivery system 205 and the second precursor delivery system 206 can each include a gas supply 207 and a flow controller 209 (for clarity of illustration, only the first precursor is labeled in FIG. 2) Delivery system 205 is not labeled in second precursor delivery system 206). In an embodiment, the first precursor material is stored in a gaseous state, and the gas supply 207 can provide a first precursor material to the deposition chamber 203. The gas supply 207 can be a vessel such as a gas reservoir that can be located adjacent to or away from the deposition chamber 203. On the other hand, the gas supply 207 facilitates independently preparing and delivering the first precursor material to the flow controller 209. Any source suitable for the first precursor material can be used as the gas supply 207, and these sources are fully included in the scope of the embodiments of the present invention.

Gas supply 207 can deliver the desired first precursor material to flow controller 209. The flow controller 209 can be used to control the flow of the first precursor material to the precursor gas controller 213 and thereafter to the deposition chamber 203 to help control the pressure in the deposition chamber 203. The flow controller 209 can be a proportional valve, a trim valve, a needle valve, a pressure regulator, a mass flow controller, combinations of the above, or the like. However, any suitable method can be employed to control and adjust the flow of carrier gas to the precursor canister, and all of these components and methods are well within the scope of embodiments of the present invention.

However, as is known to those of ordinary skill in the art, the first precursor delivery system 205 and the second precursor delivery system 206 described herein have the same components, which are merely illustrative and not limiting to the embodiments of the present invention. Any form. Any suitable type of precursor delivery system can be used, which can have any number and number of individual components, and these components can be the same or different than the components of any other precursor delivery system in deposition system 200. These precursor systems are well within the scope of embodiments of the invention.

Additionally, the first precursor material in some embodiments is stored in a solid or liquid state. The gas supply 207 can store a carrier gas, and the carrier gas can be introduced into a precursor canister (not shown separately), and the precursor canister stores a first precursor material in a solid or liquid state. The first precursor material is then pushed and carried by the carrier gas prior to feeding the first precursor material to the precursor gas controller 213, such as evaporating or sublimating the first precursor material into the gas portion of the precursor can. In some embodiments, the carrier gas can be an inert gas such as argon, helium, or another gas. Any suitable combination of methods and units can be used to provide the first precursor material, and all combinations of units are fully encompassed within the scope of embodiments of the invention.

The first precursor delivery system 205 and the second precursor delivery system 206 can deliver individual precursor materials to the precursor gas controller 213. Precursor gas controller 213 is coupled from deposition chamber 203 and separates first precursor delivery system 205 from second precursor delivery system 206 to deliver the desired precursor material to deposition chamber 203. The precursor gas controller 213 can include means such as a valve member, flow meter, sensor, or the like to control the delivery rate of each precursor and can be received from the control unit 215 (described further below in conjunction with FIG. 3) The instructions are to control the precursor gas controller 213.

The precursor gas controller 213 receives an instruction from the control unit 215 to open or close the valve member to connect one or more of the first precursor delivery system 205 and the second precursor delivery system 206 to the deposition chamber 203, and via the manifold Tube 216 will direct the desired precursor material into deposition chamber 203 and sprinkler head 217. Sprinkler head 217 can be used to disperse the selected precursor material into deposition chamber 203 and is designed to evenly disperse the precursor material to minimize undesirable process conditions resulting from uneven dispersion. In some embodiments, the showerhead 217 has a circular design with openings that are evenly distributed around the showerhead 217 to allow the desired precursor to be dispersed into the deposition chamber 203.

However, those of ordinary skill in the art will appreciate that the foregoing introduction of the precursor material into the deposition chamber 203 via a single showerhead 217 or a single point of introduction is merely illustrative and not limiting of the embodiments of the invention. Any number of separate individual showerheads 217 or other openings can be used to introduce the precursor material into the deposition chamber 203. All combinations of sprinkler heads and other points of introduction are fully encompassed within the scope of embodiments of the present invention.

The deposition chamber 203 can accept the desired precursor material and expose the underlying layer 114 to the precursor material. The deposition chamber 203 can be of any desired shape suitable for dispersing the precursor material and contacting the precursor material with the underlying layer 114. In the embodiment shown in Figure 2, the deposition chamber 203 has a cylindrical side wall and a bottom. However, the deposition chamber 203 is not limited to a cylindrical shape, and any other shape such as a hollow square tube, an octahedron, or the like may be employed. Additionally, the outer casing 219 can surround the deposition chamber 203 and the material composition of the outer casing 219 is inert to a variety of process materials. As such, the outer casing 219 can be any suitable material that withstands the chemicals and pressures in the deposition process, such as steel, stainless steel, nickel, aluminum, alloys of the foregoing, combinations of the foregoing, or the like.

In the deposition chamber 203, the semiconductor substrate 102 can be placed on the mounting platform 221 to place and control the semiconductor substrate 102 and the underlying layer 114 in a deposition process. The mounting platform 221 can be located on the bottom of the deposition chamber 203 and can include a heating mechanism to heat the semiconductor substrate 102 during the deposition process. Moreover, although FIG. 2 shows a single mounting platform 221, any number of mounting platforms 221 may be additionally included in the deposition chamber 203.

In some embodiments, the mounting platform 221 can also include a first electrode 230 coupled to the RF generator 232. Under the control of the control unit 215, the RF generator 232 when a deposition process (such as plasma enhanced atomic layer deposition) can apply a bias voltage of the RF voltage to the first electrode 230. Since the first electrode 230 has a bias voltage, it can be used to provide a bias to the incoming gas (such as the precursor material and/or carrier gas) and assist in igniting the gas into a plasma. In some embodiments, the carrier gas can be ignited into a plasma with the precursor material. On the other hand, the bias of the first electrode 230 can also be maintained during deposition to maintain the plasma.

The deposition chamber 203 also includes an upper electrode 231 as a plasma generator. In an embodiment, the plasma generator can be a transformer coupled plasma generator and can be a coil. The coil can be attached to a radio frequency generator 233 that provides power to the upper electrode 231 under control of the control unit 215 to ignite the gas into a plasma.

Although the aforementioned upper electrode 231 is a transformer coupled plasma generator, the embodiment is not limited to a transformer coupled plasma generator. Conversely, any suitable method of producing a plasma, such as an inductively coupled plasma system, a magnetically enhanced reactive ion etching, an electron cyclotron resonance, a remote plasma generator, or the like, can be used instead. For example, the gas entering in some embodiments may be ignited into a plasma, and the ignition method may employ a plasma generator connected to a separate chamber of the deposition chamber 203, or may be uncoupled to the deposition chamber 203. The plasma generator of the mounting platform 221 is installed. These methods are fully encompassed within the scope of embodiments of the invention.

Additionally, deposition chamber 203 and mounting platform 221 can be part of a cluster tool system (not shown). The cluster tool system can be combined with an automated processing system to position the semiconductor substrate 102 into the deposition chamber 203 prior to the deposition process, fix the semiconductor substrate 102 during the deposition process, and remove the semiconductor substrate 102 from the deposition chamber 203 after the deposition process.

The deposition chamber 203 may also have an exhaust outlet 225 to pump gas out of the deposition chamber 203. A vacuum pump 223 can be coupled to the exhaust outlet 225 of the deposition chamber 203 to assist in exhausting the exhaust. Under the control of the control unit 215, the vacuum pump 223 can reduce and control the pressure in the deposition chamber 203 to the desired pressure, and can discharge the precursor material from the deposition chamber 203 to prepare the precursor material after introduction.

FIG. 3 shows an embodiment of control unit 215 that may be used to control precursor gas controller 213, vacuum pump 223, or radio frequency generators 232 and 233. Control unit 215 can be any type of computer processor that can be used in industrial settings to control the process machine. In an embodiment, control unit 215 can include a processor 301 such as a desktop computer, workstation, notebook, analog, or special purpose unit customized for special purposes. Control unit 215 can be equipped with display 303 and one or more input/output members 305 (eg, command output, sense input, mouse, keyboard, printer, combination of the above, or the like). The processor 301 can include an input/output interface 316 connected to the bus 312, a central processing unit 306, a memory 308, a mass storage device 310, and a display card 314.

The bus bar 312 can also be a plurality of bus bar structures of one or more arbitrary forms, including a memory bus bar or a memory controller, a peripheral bus bar, or an image bus bar. The central processing unit 306 can include any type of electronic data processor, and the memory 308 can include any type of system memory such as static random access memory, dynamic random access memory, or read only memory. The mass storage device 310 can include any type of storage device configured to store data, programs, or other information and is configured to be accessible by the bus 312 for accessing data, programs, or other information. For example, mass storage device 310 can include one or more hard drives, disks, or optical disks.

Display card 314 and input/output interface 316 provide an interface to couple external input and output devices to processing unit 301. As shown in FIG. 3, examples of input and output devices include a display 303 coupled to display card 314, and an input/output member 305 coupled to input/output interface 316 such as a mouse, keyboard, printer, or the like. Things. Other devices may be coupled to the processor 301 and additional or fewer interface cards may be employed. For example, a serial interface card (not shown) can provide a serial interface for a printer. The processor 301 can also include a network interface 318, which can be a wired connection and/or a wireless connection to a local area network or wide area network 320. It is noted that the control unit 215 can include other components. For example, control unit 215 can include a power source, a cable, a motherboard, a removable storage medium, a housing, and the like. Although not shown in FIG. 3, these other components can be considered as part of the control unit 215.

In some instances, the presence of oxygen plasma may damage the surface of the underlying layer when the material is deposited on the underlying layer of the photoresist or polymer. In some instances, oxygen radicals (O*) formed in the plasma can destroy the carbon-carbon bonds (CC or C=C) or carbon-hydrogen bonds (CH) in the underlying layer, damaging or consuming the underlying layers. For example, the oxygen plasma may react with the lower layer as follows: C=C+O* → CO ₂ or CO C-H+O* → CO ₂ +H ₂ O In addition to the above formula, other reaction.

In the plasma enhanced atomic layer deposition process, an oxygen-containing film is deposited using an oxygen-containing precursor material, which may generate oxygen plasma during deposition to damage the underlying layer. In some instances, the oxygen plasma consumes or etches portions of the underlying layer, causing the thickness of the underlying layer to be less than the thickness at the time of deposition. For example, by depositing the underlying layer 114 of oxygen plasma of the low temperature dielectric film 116, the thickness T1 of the underlying layer 114 from deposition is reduced to a thickness T2. As shown in FIG. 1B, the lower layer 114 has a thickness variation DT1. In some examples, the amount of thickness change DT1 depends on the material of the underlying layer 114, as well as the characteristics of the oxygen plasma and plasma enhanced atomic layer deposition process. These damages may reduce process consistency or reproducibility, and damage in some instances may affect the size of the patterned structure or other structures.

In some instances, an oxygen-containing precursor, rather than an oxygen-containing allotrope (such as gaseous oxygen, ozone, or the like) to deposit a low temperature dielectric film 116 can reduce oxygenation during deposition of the low temperature dielectric film 116. Pulp. In some embodiments, a precursor such as carbon dioxide, nitrous oxide, or dinitrogen dioxide can be used to replace or otherwise add to the allotrope precursor of oxygen. In some embodiments, a combination of one or more alcohols such as ethanol, other alcohols, or alcohols can serve as a precursor. In some embodiments, more than one precursor can be employed. In some embodiments, more than one precursor may or may not bind to an allotrope of oxygen (as another precursor material). The precursor has less oxygen content (e.g., the precursor is free of gaseous oxygen, ozone, or the like) and may be less damaging to the underlying layer 114 when the oxygen-containing low temperature dielectric film 116 is formed on the underlying layer 114.

The graph 400 of FIG. 4 shows experimental results of depositing a low temperature dielectric film on the underlying layer to produce a multilayer structure similar to that shown in FIG. 1B. The curves 410, 420, and 430 shown in the graph 400 are the thickness variations of the underlying layers caused by different low temperature dielectric films deposited directly on the underlying layers, respectively. In some examples, the amount of thickness variation of the underlying layer can be considered as the amount of damage caused by the oxygen plasma to the underlying layer. In the experiment shown in graph 400, the curves for depositing different low temperature dielectric films are represented by curves 410, 420, and 430, respectively. Curves 410, 420, and 430 show the reduced underlying layer thickness of the deposited low temperature dielectric film. In general, as the thickness of the deposited low temperature dielectric film increases, the thickness of the underlying layer also changes. Curves 410 and 420 employ oxygen as a precursor to deposit a low temperature dielectric film. Curve 430, however, uses carbon dioxide instead of oxygen as a precursor to deposit a low temperature dielectric film, and curve 430 deposits a lower layer of damaged low temperature dielectric film that is less than curves 410 and 420. For example, the curve 430 of the underlying layer thickness variation is almost one-half of the curve 410 of the underlying layer thickness variation. Thus, graph 400 shows how the techniques of some embodiments described herein reduce the damage photoresist or underlying layers of the polymer when directly depositing the oxygen-containing dielectric film on the underlying layer.

As shown in FIG. 1B, a deposition system, such as deposition system 200, can be employed to deposit a low temperature dielectric film 116 on the underlying layer 114. In some embodiments, the method of forming the low temperature dielectric film 116 can first introduce the precursor material into the first precursor delivery system 205 or the second precursor delivery system 206. In some embodiments, the first precursor material comprises carbon dioxide, nitrous oxide, dinitrogen dioxide, mono or eastern alcohols, other materials, or combinations thereof. In some embodiments, the second precursor material comprises tris(diethylamino)decane, tetrakis(dimethylamino)titanium, bis(t-butylamino)decane, bis(diethylamino) ) decane, other materials, or a combination of the above. In some embodiments, the oxygen allotrope precursor can be used as a third precursor material to combine with another first precursor material.

Once the first precursor material and the second precursor material are placed in the first precursor delivery system 205 and the second precursor delivery system 206, the control unit 215 can transmit an instruction to the precursor gas controller 213, in order The first precursor delivery system 205 and the second precursor delivery system 206 are alternately connected to the deposition chamber 203 to begin forming the low temperature dielectric film 116. Once the above connections are completed, the first precursor delivery system 205 and the second precursor delivery system 206 can deliver the first precursor material and the second precursor material to the showerhead 217 via the precursor gas controller 213 and the manifold 216. The showerhead 217 can then disperse the first precursor material and the second precursor material into the deposition chamber 203, wherein the first precursor material and the second precursor material can form the low temperature dielectric film 116 on the underlying layer 114. Control unit 215 can also ignite the precursor material to plasma into deposition chamber 203. For example, the above ignition may employ RF generators 232 and 233. In some embodiments, the first precursor material can be ignited to form a plasma when the low temperature dielectric film 116 is deposited. In some examples, the low temperature dielectric film 116 can be deposited in the same deposition chamber 203 with other processing steps (such as a deposition process or an etch process). For example, a plasma etching process or another plasma enhanced deposition process may also be performed on the semiconductor device 100 in the deposition chamber 203.

In some embodiments, the flow rate of the first precursor material used to form the low temperature dielectric film 116 into the deposition chamber 203 is between about 10 sccm and about 5000 sccm, and the flow rate of the second precursor material flows into the deposition chamber 203. Between about 10 sccm and about 5000 sccm. For example, the flow rate of carbon dioxide as the first precursor material into the deposition chamber 203 is between about 10 sccm and about 5,000 sccm. Further, the pressure of the deposition chamber 203 can be maintained between about 0.1 Torr and about 10 Torr, and the temperature can be maintained between about 0 ° C and about 200 ° C (eg, about 90 ° C). In some embodiments, the RF power used to form the low temperature dielectric film 116 is between about 1 watt and about 2000 watts. In some embodiments, the DC power used to form the low temperature dielectric film 116 is between about 1 watt and about 2000 watts. However, as is known to those of ordinary skill in the art, these process conditions are for illustrative purposes only, and any suitable process conditions are still within the scope of embodiments of the invention.

As shown in FIG. 1C, an upper layer 118 is formed on the low temperature dielectric film 116. In some embodiments, the upper layer 118 can be photoresist. In some examples, the upper layer 118 can be part of a multilayer photoresist stack. For example, the upper layer 118 can be the uppermost layer of the multilayer photoresist stack, and the low temperature dielectric film 116 can be the intermediate layer of the multilayer photoresist stack. The formation of the upper layer 118 can be a spin coating process or another suitable process. In some embodiments, an additional layer, such as an adhesive layer, may be formed on the low temperature dielectric film 116 prior to forming the upper layer 118. In FIG. 1D, the upper layer 118 is patterned using a photolithography process to form openings in the upper layer 118.

As shown in FIG. 1E, the patterned upper layer 118 acts as an etch mask when patterning the low temperature dielectric film 116. The pattern of the upper layer 118 can be transferred to the low temperature dielectric film 116 via an etching process. In some examples, the etch process is non-isotropic, such that the opening in the upper layer 118 extends through the low temperature dielectric film 116 and the opening size in the low temperature dielectric film 116 is substantially the same as the opening size in the upper layer 118. In some embodiments, one or more etching processes can be performed in the same chamber (eg, deposition chamber 203) where the low temperature dielectric film 116 is deposited.

As shown in FIG. 1F, the patterned low temperature dielectric film 116 acts as an etch mask for patterning the underlying layer 114. The pattern of the low temperature dielectric film 116 can be transferred to the underlying layer 114 via an etching process. In some examples, the etch process is non-isotropic, such that openings in the low temperature dielectric film 116 will extend through the underlying layer 114, and the openings in the lower layer 114 have the same dimensions as the openings in the low temperature dielectric film 116. In some examples, some or all of the upper layer 118 may be consumed when etching the underlying layer 114. As shown in FIG. 1G, the patterned underlying layer 114 is then used as an etch mask for patterning the interlayer dielectric layer 112. The pattern of the lower layer 114 can be transferred to the interlayer dielectric layer 112 via an etching process. In some examples, some or all of the low temperature dielectric film 116 or underlying layer 114 may be consumed when etching the interlayer dielectric layer 112. In embodiments where the step of etching the interlayer dielectric layer 112 does not completely consume the underlying layer 114, an ashing process can be performed to remove the remaining underlying layer 114.

In FIG. 1H, a conductive material may be filled into the portion of the interlayer dielectric layer 112 that is etched. Any suitable conductive material such as copper, aluminum, or another metal may be employed, and the conductive material may be formed by an electroplating process or another suitable process. In some embodiments, one or more additional layers such as a barrier layer, an adhesion layer, a seed layer, or other layer may be deposited over the etched portion of the interlayer dielectric layer 112 prior to forming the conductive material. After the etched portion is filled, a planarization process such as chemical mechanical polishing can be performed to remove an additional portion of the conductive material on the interlayer dielectric layer 112, i.e., the conductive traces 120 are formed.

Although the low temperature dielectric film 116 in the embodiment of FIGS. 1A through 1H is used to pattern the interlayer dielectric layer 112, the interlayer dielectric layer 112 of other embodiments may be another layer. For example, the interlayer dielectric layer 112 can be a semiconductor substrate used to form a device such as a fin field effect transistor, rather than an interlayer dielectric layer. In some examples, interlayer dielectric layer 112 includes one or more layers, such as additional interlayer dielectric layers, other types of dielectric layers, semiconductor layers, conductive layers, or the like. As such, the interlayer dielectric layer 112 is merely an exemplary layer of one or more different types of layers when the semiconductor device 100 is formed.

In some examples, the presence of the low temperature dielectric film 116 may improve the adhesion of the upper layer (e.g., the upper layer 118). In some examples, the presence of the low temperature dielectric film 116 may reduce the chance of flaking of the patterned structure on the upper layer 118. For example, the use of the low temperature dielectric film 116 can increase the adhesion of the patterned upper layer 118 shown in FIG. 1D.

The technique described herein employs a lower temperature and less oxygen plasma deposition process that deposits a low temperature dielectric film of oxide on the underlying layer with less damage to the underlying layer. In particular, damage to the photoresist or underlying layers of the polymer can be reduced by the oxygen plasma. In some instances, the use of a low temperature dielectric film such as described above can reduce the critical dimensions of the patterned structure to achieve a smaller structural size. Deposition of a low temperature dielectric film such as described above results in a fine patterned structure with greater process control, smaller structural size, and higher yield.

In other embodiments, the low temperature dielectric film described herein can be used as a gap filler material in a gap or opening in the fabrication of a semiconductor device. Taking an exemplary embodiment as an example, FIGS. 5A to 5C are cross-sectional views showing a middle stage of a method of forming a semiconductor device 500 using a low temperature dielectric film 516 as a gap filling material. In FIG. 5A, a bottom layer 512 can be formed on the substrate 502 as appropriate. In some embodiments, substrate 502 can be similar to the aforementioned semiconductor substrate 102 illustrated in FIGS. 1A through 1G, while bottom layer 512 can be similar to the aforementioned interlayer dielectric layer 112 illustrated in FIGS. 1A through 1G.

FIG. 5A also shows that the lower layer 514 is formed on the bottom layer 512. In some embodiments, the lower layer 514 is a photoresist or polymeric material, and the lower layer 514 can be similar to the aforementioned lower layer 114 shown in Figures 1A through 1G. In some embodiments, the underlying layer 514 is deposited to have a thickness T3 between about 5 nm and about 1000 nm. The method of forming the lower layer 514 can be a spin coating process or another suitable process.

FIG. 5A also shows that the upper layer 518 is formed on the lower layer 514. As shown in FIG. 5A, the upper layer 518 is patterned using a photolithography process to form openings in the upper layer 518. In some embodiments, the upper layer 518 is an oxygen-containing dielectric material similar to the low temperature dielectric film 116. In other embodiments, the upper layer 518 can be another dielectric material. As shown in FIG. 5B, the upper layer 518 acts as an etch mask when patterning the underlying layer 514. The pattern of the upper layer 518 can be transferred to the underlying layer 514 via an etch process to form openings 522 in the underlying layer 514. In some examples, the etch process is non-isotropic, such that the opening in the upper layer 518 will extend through the underlying layer 514, such as the opening 522, and the opening 522 in the lower layer 514 has substantially the same dimensions as the opening in the upper layer 518. . In some examples, some or all of the upper layer 518 may be consumed while etching the underlying layer 514, as shown in Figure 5B. FIG. 5B also shows that the pattern 522 in the lower layer 514 can have a width W1. In some embodiments, the width W1 can be between about 5 nm to about 100 nm. In some embodiments, the opening 522 can be considered a depression in the underlying layer 514.

In FIG. 5C, a low temperature dielectric film 516 is deposited as an interstitial material on the underlying layer 514 and in the opening 522. In some embodiments, a low temperature dielectric film 516 is also deposited on the remaining portion of the upper layer 518. In some embodiments, the low temperature dielectric film 516 can function as a gap filler material, a sacrificial material, or a reverse material. In some embodiments, the low temperature dielectric film 516 can be conformally deposited on the sidewalls and the lower surface of the opening 522. In other embodiments, however, the low temperature dielectric film 516 is not conformally deposited. As deposition continues, the low temperature dielectric film 516 on both side walls of the opening 522 can merge and fill the opening 522. In some embodiments, the upper surface of the low temperature dielectric film 516 may not be flat, as shown in Figure 5C.

In some embodiments, the low temperature dielectric film 516 can be similar to the aforementioned low temperature dielectric film 116 of FIGS. 1A through 4. For example, the deposition method of the low temperature dielectric film 516 may be a plasma enhanced atomic layer deposition process that does not use oxygen as a precursor material to reduce possible damage to the underlying layer 514. As described herein, the use of one or more precursors that reduce oxygen plasma during deposition of the low temperature dielectric film 516 can reduce damage to the underlying layer 514 when forming the low temperature dielectric film 516. For example, forming the low temperature dielectric film 516 on the lower layer 514 may reduce the thickness of the lower layer 514 from the thickness T3 to the thickness T4, and the thickness variation DT3 therebetween is as shown in FIG. 5C. The thickness variation DT3 caused by the deposition of the low temperature dielectric film 516 by the techniques described herein can be less than the thickness variation caused by other techniques in which more oxygen plasma is present during deposition. In some examples, depositing the low temperature dielectric film 516 may also consume portions of the underlying layer 514 on the sidewalls of the opening 522. Taking FIG. 5C as an example, after depositing the low temperature dielectric film 516, the width W1 of the opening 522 can be increased to the width W2. In some embodiments, the increase in width W1 to width W2 may be less than about 5 nm, such as about 3 nm, when forming low temperature dielectric film 516. In some examples, the width variation after deposition of the low temperature dielectric film described herein is at most about 5 nm, which is less than the width variation caused by the deposition of the dielectric film with the oxygen precursor.

In some embodiments, the subsequent process can be performed on the semiconductor device 500 illustrated in FIGS. 5A through 5C. For example, the low temperature dielectric film 516 can then be planarized using a chemical mechanical polishing process. The remaining portion of the underlying layer 514 can then be removed and the portion of the low temperature dielectric film 516 on the bottom layer 512 retained. The remaining portion of the low temperature dielectric film 516 can then serve as an etch mask when patterning the bottom layer 512. A conductive material can be deposited over the patterned underlayer 512 to form conductive traces, contacts, vias, or the like. This is an example of a process, and other processes using a low temperature dielectric film as a gap filler are also within the scope of embodiments of the present invention.

The low temperature dielectric film described herein can also be used to reduce the structural size in the back end process of a semiconductor device. In another exemplary embodiment, FIGS. 6A through 6J show cross-sectional views of intermediate stages of forming conductive traces in semiconductor device 600. Specifically, in the embodiment shown in FIGS. 6A through 6J, the low temperature dielectric film 616 is used as a compliant material to reduce the patterned structure size of the process of the semiconductor device 600. In FIG. 6A, an interlayer dielectric layer 612 may be formed on the substrate 602. In some embodiments, the substrate 602 can be similar to the substrate 102 or substrate 502 shown in FIGS. 1A through 1H or 5A through 5C, and the interlayer dielectric layer 612 can be between the layers shown in FIGS. 1A through 1H or 5A through 5C. Dielectric layer 112 or bottom layer 512 is similar. In some examples, substrate 602 can be a semiconductor device that performs a partial process. For example, the embodiment shown in Figures 6A through 6J can be part of a later stage process or part of another process.

FIG. 6A also shows that the underlying layer 614 is formed over the interlayer dielectric layer 612. In some embodiments, the lower layer 614 is a photoresist material and the lower layer 614 can be similar to the aforementioned lower layer 114 or lower layer 514 shown in FIGS. 1A through 1H or 5A through 5C. In some embodiments, the underlayer 614 formed by deposition has a thickness T5 between about 5 nm and about 1000 nm. The formation of the lower layer 614 can be a spin coating process or another suitable process.

FIG. 6A also shows that the upper layer 618 is formed on the lower layer 614. As shown in FIG. 6A, the upper layer 618 is patterned using a photolithography process to form openings in the upper layer 618. In some embodiments, the upper layer 618 is an oxygen-containing dielectric material similar to the low temperature dielectric film 116, although the upper layer 618 in other embodiments can be another dielectric material. As shown in Figure 6B, the patterned upper layer 618 acts as an etch mask when patterning the underlying layer 614. The pattern of the upper layer 618 can be transferred to the underlying layer 614 via an etch process to form an opening 622 in the underlying layer 614. In some examples, the etch process is non-isotropic, such that the opening in the upper layer 618 extends through the underlying layer 614, such as the opening 622, and the opening 622 can be approximately the same size as the opening in the upper layer 618. In some examples, some or all of the upper layer 618 may be consumed when etching the underlying layer 614, as shown in Figure 6B. FIG. 6B also shows that opening 622 patterned into lower layer 614 can have a width W3. In some embodiments, the opening 622 can be considered a depression in the underlying layer 614.

In some examples, the sidewalls of the patterned opening 622 can have a rough surface. For example, Figure 6C shows a cross-sectional view of an example of opening 622, like opening 622 shown in Figure 6B. Figure 6D shows a plan view of the opening 622 of Figure 6C, and the cross-sectional view of Figure 6C is taken along line 6C-6C' of the plan view of Figure 6D. As shown in Fig. 6D, the side walls of the opening 622 in plan view also have roughness. In some examples, the roughness may be defined by one or more measurements of the deviation between the sidewall edge of the opening 622 and the fixed position, such as edge roughness ER1 in Figure 6D. In some examples, the roughness may be defined by one or more measurements across a distance of the opening 622, such as the width roughness WR1 in Figure 6D. In some examples, the use of a low temperature dielectric film 616 may improve the width roughness or edge roughness of the openings, patterned layers, or subsequently formed structures. The above examples will be described below in conjunction with Figs. 6F to 6J.

As shown in FIG. 6E, a low temperature dielectric film 616 is deposited over the lower layer 614 and into the opening 622. In some embodiments, a low temperature dielectric film 616 is also deposited on the remaining portion (if present) of the upper layer 618. As shown in FIG. 6C, a low temperature dielectric film 616 can be conformally deposited on the sidewalls and the lower surface of the opening 622. In some embodiments, the low temperature dielectric film 616 can have a thickness between about 0.1 nm and about 100 nm. In some embodiments, the low temperature dielectric film 616 can be similar to the aforementioned low temperature dielectric film 116 or low temperature dielectric film 516 shown in FIGS. 1A through 4 or 5A through 5C. For example, the deposition method of the low temperature dielectric film 616 may be a plasma enhanced atomic layer deposition process that does not use oxygen as a precursor material to reduce possible damage to the underlying layer 614.

A low temperature dielectric film 616 is deposited conformally in the opening 622 to form an opening 624. Due to the presence of the low temperature dielectric film 616, the width W5 of the opening 624 is smaller than the width W3 of the opening 622. This method uses a low temperature dielectric film 616 that allows for a smaller size of the structure patterned into the target layer 612, which will be described in more detail below in conjunction with Figure 6D.

In addition, the use of one or more precursors to reduce oxygen plasma during deposition of the low temperature dielectric film 616 can reduce damage to the underlying layer 614 when forming the low temperature dielectric film 616 as described herein. For example, the step of forming the low temperature dielectric film 616 on the underlying layer 614 may reduce the thickness T5 of the underlying layer 614 to a thickness T6, which is similar to the aforementioned lower layer 514 shown in Figures 5A through 5C. In some examples, the step of depositing the low temperature dielectric film 616 may also consume portions of the underlying layer 614 on the sidewalls of the opening 622. Taking FIG. 6C as an example, after depositing the low temperature dielectric film 616, the width of the opening 622 can be increased to the width W4. In some embodiments, the increase in width W3 to width W4 may be less than about 50 nm (such as about 3 nm) when forming a low temperature dielectric film 616 having a thickness of about 3 nm. In some embodiments, the thickness of the low temperature dielectric film 616 deposited on the surface of the underlying layer 614 can be less than, greater than, or equal to the thickness of the surface of the underlying layer 614 when the low temperature dielectric film 616 is deposited. By reducing possible damage to the sidewalls of the opening 622, the opening 624 can have a smaller width W5 that can reduce subsequent patterned structural dimensions and improve process control.

In some examples, forming a low temperature dielectric film 616 on the underlying layer 614 and opening 622 may improve sidewall roughness. In the illustrative example, FIGS. 6F and 6G are cross-sectional and plan views of the formed opening 624 after forming the low temperature dielectric film 616 in the opening 622 shown in FIGS. 6C and 6D. The opening 624 shown in Figures 6F and 6G is similar to the opening 624 shown in Figure 6E. The cross-sectional view of Fig. 6F is along the line 6F-6F' in the plan view of Fig. 6G. The low temperature dielectric film 616 can be filled into small depressions in the rough sidewalls of the underlying layer 614, and its deposited surface is smoother than the rough sidewalls of the underlying layer 614. As such, as shown in FIG. 6F, the roughness of the low temperature dielectric film 616 of the sidewall of the opening 624 can be less than the sidewall roughness of the lower layer 614. In some examples, the edge roughness ER2 of the sidewall of the opening 624 can be less than the edge roughness ER1 of the sidewall of the opening 622. In some examples, the width roughness WR2 of the sidewall of the opening 624 can be less than the width roughness WR1 of the sidewall of the opening 622. In this manner, the use of a low temperature dielectric film reduces sidewall roughness and allows for a more consistent or lesser roughness of subsequently formed structures.

As shown in FIG. 6H, opening 624 can be transferred to target layer 612 via an etch process. In some examples, the etch process is non-isotropic, such that the opening 624 extends through the target layer 612 and the size of the opening in the target layer 612 is substantially the same as the size of the opening 624. The etching process can also stop at the upper surface of the low temperature dielectric film 616 on the lower layer 614, as shown in FIG. 6H. In some examples, using the low temperature dielectric film deposition process described herein, the size of the opening formed in the previous patterning step can be reduced to form a smaller structural size. A planarization process (such as chemical mechanical polishing, dry etching, combinations of the above, or the like) may be performed as appropriate to remove portions of the low temperature dielectric film 616 that cover the underlying layer 614. In some examples, the planarization process can also remove the upper portion of the underlying layer 614.

In some embodiments, an additional process can be performed. For example, some embodiments may then fill a conductive material into opening 624 in target layer 612 to form vias, conductive traces, or other conductive structures. As shown in FIGS. 6I through 6J, the opening 624 in the target layer 612 is filled with a conductive material 630 to form a conductive trace 632. The cross-sectional view of Fig. 6I is taken along the line 6I-6I' in the plan view of Fig. 6J. After forming the conductive material 630, a planarization process (such as chemical mechanical polishing) or an etching process may be employed to remove the low temperature dielectric film 616, the underlying layer 614, and excess portions of the conductive material 630. In some embodiments, the low temperature dielectric film 616 is removed prior to forming the conductive material 630. In this manner, the low temperature dielectric film 616 can be used to form smaller sized structures such as conductive traces 632. The embodiments shown in Figures 6A through 6J are for illustrative purposes only, while other embodiments may include additional layers, structures, or process steps.

The use of the low temperature dielectric film 616 can improve the roughness of the opening 622 and also reduce the structural roughness patterned from the opening 622. For example, the use of the low temperature dielectric film 616 can reduce the sidewall roughness of the opening 622, and can also reduce the line edge roughness or line width roughness of the conductive line 632, as shown in FIG. 6J. In this manner, the use of a low temperature dielectric film can reduce the roughness of the patterned structure, and can also make the subsequently formed structure more uniform or have less roughness.

The low temperature dielectric film described herein can serve as a gap fill material that can be deposited in a gap or opening in a back end process of a semiconductor device. In the exemplary embodiment, FIGS. 7A-15B show cross-sectional and/or plan views of intermediate stages in forming an electrically conductive structure in interlayer dielectric 702 of semiconductor device 700. The process shown in FIGS. 7A to 15B is an embodiment in which a low temperature dielectric film 736 is used as a gap filling material, and the low temperature dielectric film 736 as a gap filling material can be combined with the aforementioned low temperature dielectric film shown in FIGS. 5A to 5C. 516 is similar. The semiconductor device 700 is shown in FIG. 7A (cross-sectional view) and FIG. 7B (plan view). The cross-sectional view of Fig. 7A is along the line A-A' in the plan view of Fig. 7B. In FIGS. 7A and 7B, an interlayer dielectric layer 702 is formed on the substrate 704. In some embodiments, the substrate 704 can be similar to the other substrates described above, or the interlayer dielectric layer 702 can be similar to the other layers described above (such as the interlayer dielectric layer 112 shown in FIG. 1A), or can be another Layer. For example, the embodiment shown in Figures 7A through 15B can be part of a later stage process or part of another process.

7A and 7B show the formation of a mask region 724 on the interlayer dielectric layer 702. For example, the masking region 724 can be formed by patterning a dielectric layer blanket, and the patterning method can employ a photolithography process. In plan view, the area defined by the gap between the mask regions 724 can then form a conductive structure in the interlayer dielectric 702. In FIG. 8, a mask layer 728 is formed over the mask region 724 and the interlayer dielectric layer 702. In some embodiments, the mask layer 728 is a photoresist or a polymeric material and may be associated with the aforementioned lower layer 114, lower layer 514, or below as shown in Figures 1A through 1G, Figures 5A through 5C, or Figures 6A through 6J. Layer 614 is similar. In some embodiments, the mask layer 728 comprises multiple layers and a variety of materials.

In FIGS. 9A through 9C, the mask layer 728 is patterned using a photolithography process to form openings 734. The cross-sectional view of Fig. 9A is along the line AA' of the plan view of Fig. 9B and the perspective view of Fig. 9C. In the perspective view of FIG. 9C, the portion of the mask layer 728 is presented in a transparent manner, and the opening 734 can be more clearly displayed.

In FIGS. 10A through 10C, a low temperature dielectric film 736 is formed in the opening 734 and on the mask layer 728. The cross-sectional view of Fig. 10A is along the line AA' of the plan view of Fig. 10B and the perspective view of Fig. 10C. In the perspective view of FIG. 10C, portions of the mask layer 728 are presented in a transparent manner to more clearly show the low temperature dielectric film 736 formed in the opening 734. In some embodiments, the low temperature dielectric film 736 can function as a gap fill material or a sacrificial material. In some embodiments, the low temperature dielectric film 736 can be the aforementioned low temperature dielectric film 116, low temperature dielectric film 516, or low temperature dielectric film 616 as shown in FIGS. 1A through 4, 5A through 5C, or FIGS. 6A through 6J. similar. For example, the deposition method of the low temperature dielectric film 736 may be a plasma enhanced atomic layer deposition process that does not use oxygen as a precursor material to reduce possible damage to the mask layer 728. In some embodiments, a low temperature dielectric film 736 can be deposited to compliantly fill the opening 734.

The low temperature dielectric film 736 can be further patterned in a subsequent process, and the patterned low temperature dielectric film 736 can be used to define a line cut between two adjacent conductive lines that will be formed in the interlayer dielectric layer 702. As detailed below. Although FIG. 10 shows the formation of a low temperature dielectric film 736 in a single opening 734, some embodiments may have a single or more than two openings 734, and a low temperature dielectric film 736 may be formed in one or more than two openings 734 (to form a Less line cuts or extra line cuts).

Next, in FIG. 11, a planarization process (such as chemical mechanical polishing, dry etching, combinations thereof, or the like) may be performed to remove excess portions of the low temperature dielectric film 736 outside the opening 734. Next, in FIGS. 12A and 12B, the remaining portion of the mask layer 728 is removed. Fig. 12A is a cross-sectional view taken along line A-A' in the plan view of Fig. 12B. In some embodiments, the ashing process can be used to remove the mask layer 728. After the mask layer 728 is removed, the low temperature dielectric film 736 can be left to cover a portion of the interlayer dielectric layer 702 and the mask region 724.

Next, as shown in FIGS. 13A to 13C, a planarization process is performed to remove excess portions of the low temperature dielectric film 736, and the upper surface of the low temperature dielectric film 736 is planarized to be flush with the upper surface of the mask region 724. The cross-sectional view of Fig. 13A is along the line AA' of the plan view of Fig. 13B and the perspective view of Fig. 13C. In some embodiments, the planarization process includes one or more etching processes. For example, a dry etching process or a wet etching process can be employed. In other embodiments, a grinding process such as chemical mechanical polishing can be employed. The structure formed by the above steps is as shown in Figs. 13A and 13B. As shown in FIGS. 13A and 13B, the planarized low temperature dielectric film 736 can create a separation portion of the low temperature dielectric film 736, and each of the separation portions is located on a gap between two adjacent mask regions 724. In some embodiments, each spaced portion of the region is a line cut between two adjacent portions of the conductive trace to be formed.

In FIGS. 14A and 14B, a low temperature dielectric film 736 and a mask region 724 are then used as an etch mask to form openings 750 into the interlayer dielectric layer 702. The method of etching the interlayer dielectric layer 702 may include an anisotropic dry etching process or a wet etching process. The pattern of the remaining portions of the interlayer dielectric layer 702 may be the same as the pattern of the mask region 724 and the low temperature dielectric film 736 of FIGS. 14A and 14B.

Next, as shown in FIGS. 15A and 15B, conductive material 764 can be filled into the remaining portion of opening 750. The conductive material 764 can be copper, aluminum, or another metal, and the conductive material 764 can be formed by an electroplating process or another suitable process. In some examples, conductive material 764 may be deposited to overfill opening 750. After filling the opening 750, a planarization process such as chemical mechanical polishing can be performed to remove excess portions of the conductive material 764. In some embodiments, a liner material can be formed in opening 750 prior to forming conductive material 764.

As shown in Figures 15A and 15B, a planarization process can be performed to remove excess portions of conductive material 764 on interlayer dielectric layer 702. As such, a conductive structure can be formed in the interlayer dielectric layer 702. In some embodiments, the conductive structures in the interlayer dielectric layer 702 are electrically conductive lines. When the interlayer dielectric layer 702 is patterned, the region under the portion of the low temperature dielectric film 736 is a position where the conductive line has a gap or a "line cutting portion". For example, the line cut 770 can separate the first conductive trace 772 from the second conductive trace 774 by the low temperature dielectric film 736. The use of the low temperature dielectric film 736 described above can improve line width variation or line edge roughness, which allows the conductive structure to be smaller and allows the line cut between the conductive structures to be smaller.

The low temperature dielectric film described herein can be used to form structures in the front-end process of a semiconductor device. In the exemplary embodiment, FIGS. 16 through 25 illustrate an intermediate stage of a front-end process employing a low temperature dielectric film 862 that forms a fin 868 of a fin field effect transistor device. Figure 16 shows a three-dimensional view of an example of a fin field effect transistor in some embodiments. 17 through 25 show cross-sectional views of intermediate stages of a method of forming a fin of a fin field effect transistor in some embodiments. 17 to 25 are sectional views taken along line B-B' in the three-dimensional view of Fig. 16. An example of a fin field effect transistor shown in FIG. 16 includes a fin 874 on a substrate 850. Shallow trench isolation regions 872 are located on substrate 850 and fins 874 are raised upwardly between adjacent shallow trench isolation regions 872. Gate dielectric layer 818 is along the sidewall of fin 874 and is located on the upper surface of fin 874. Gate 820 is located on gate dielectric layer 818. The source/drain regions 802 are located on opposite sides of the fins 874 with respect to the gate dielectric layer 818 and the gate 820. Some embodiments described herein form a fin field effect transistor using a gate post process. In other embodiments, a gate priority process can be employed. Moreover, some embodiments may be used in planar devices such as planar field effect transistors. For example, the embodiment shown in Figures 16 through 25 can be part of the front-end process or part of another process.

Figure 17 shows a substrate 850 of some embodiments. The substrate 850 has a first region 850B and a second region 850C. The first region 850B can be used to form an n-type device such as an n-type MOS transistor (eg, an n-type fin field effect transistor). The second region 850C can be used to form a p-type device such as a p-type MOS transistor (e.g., a p-type fin field effect transistor). In some embodiments, both the first zone 850B and the second zone 850C are used to form the same type of device, such as both zones for forming an n-type device (or p-type device). The first zone 850B and the second zone 850C may be physically separated from one another, and any number of structures (eg, isolation zones or active zones, etc.) may be located between the first zone 850B and the second zone 850C. Substrate 850 can be a semiconductor substrate such as a base semiconductor, a semiconductor substrate on an insulating layer, or the like, which can be undoped or doped (p-type or n-type dopant). The substrate 850 can be a wafer such as a germanium wafer. In general, the semiconductor substrate on the insulating layer is a layer of semiconductor material formed on the insulating layer. For example, the insulating layer can be a buried oxide layer, a hafnium oxide layer, or the like. The insulating layer may be on the substrate, and the substrate is typically a germanium substrate or a glass substrate. Other substrates such as a multilayer substrate or a compositionally graded substrate may also be used. In some embodiments, the semiconductor material of the substrate 850 may comprise germanium, germanium, a semiconductor compound (including tantalum carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide), a semiconductor alloy. (Including bismuth, gallium arsenide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide), or a combination thereof.

In FIG. 18, a film is formed stacked on a substrate 850. The film stack is used to form structures in the substrate 850, and the structural dimensions can be a fraction of the minimum photolithographic spacing. In some embodiments, the process is a self-aligned dual lithography process wherein the structure size is one-half of the minimum photolithographic pitch. In other embodiments, the process can be a self-aligned quadruple patterning process in which the structure size is one quarter of the minimum photolithographic pitch. The film stack includes an anti-reflective coating 852, a mask layer 854, and a core layer 856. In other embodiments, the film stack can include more or fewer layers.

An anti-reflective coating 852 is formed on the substrate 850 and assists in exposing and focusing the photoresist layer above (as described below) when patterning the photoresist layer. In some embodiments, the composition of the anti-reflective coating 852 can be yttrium oxynitride, tantalum carbide, a material doped with oxygen and nitrogen, or the like. In some embodiments, the anti-reflective coating 852 is substantially free of nitrogen and the composition can be an oxide.

A mask layer 854 is formed on the anti-reflective coating 852. In some embodiments, the mask layer 854 is a low temperature dielectric film that can be combined with the aforementioned low temperature dielectric film 116 shown in FIGS. 1A through 4, FIGS. 5A through 5C, FIGS. 6A through 6E, and FIGS. 7A through 15B, low temperature. The dielectric film 516, the low temperature dielectric film 616, or the low temperature dielectric film 736 is similar. In some examples, the use of a low temperature dielectric film as the mask layer 854 improves the adhesion of the upper or lower structure. In some examples, the mask layer 854 uses a low temperature dielectric film rather than another material, which reduces the chance of the patterned structure peeling off the mask layer 854. For example, the use of a low temperature dielectric film as the mask layer 854 can improve the adhesion of the core layer 856 or the core 858, as described below. In other embodiments, the composition of the mask layer 854 can be a hard mask material that can include metals and/or dielectrics. In embodiments where the mask layer 854 comprises a metal, the composition may be titanium nitride, titanium, tantalum nitride, tantalum, or the like. In embodiments where the mask layer 854 comprises a dielectric, the composition can be an oxide, a nitride, or the like. The mask layer 854 can be formed by physical vapor deposition, radio frequency physical vapor deposition, atomic layer deposition, or the like. Patterns may be formed in the mask layer 854 in subsequent processing steps, such as a portion of a self-aligned double patterning process. The mask layer 854 is then used as an etch mask to transfer the pattern of the mask layer 854 to the substrate 850.

Core layer 856 is a sacrificial layer formed on mask layer 854. In some embodiments, core layer 856 is a photoresist or polymeric material and may be as described above with respect to FIGS. 1A through 1G, FIGS. 5A through 5C, FIGS. 6A through 6F, or FIGS. 7A through 14B. 514, lower layer 614, or mask layer 728 are similar. In some embodiments, the material composition of core layer 856 has a high etch selectivity relative to the underlying layer (e.g., mask layer 854). In some embodiments, the material composition of the core layer 856 may be amorphous germanium, polycrystalline germanium, tantalum nitride, hafnium oxide, the like, or a combination thereof, and the formation process may be chemical vapor deposition, plasma enhanced chemistry. Vapor deposition, or a similar method. In one embodiment, the core layer 856 is composed of polysilicon.

In FIG. 19, core layer 856 is patterned to form core 858. The patterning method of core layer 856 can employ any suitable photolithography technique. For example, the patterning method of core layer 856 can form a three layer photoresist (not shown) on the film stack. The three-layer photoresist may include a bottom layer, an intermediate layer, and an upper layer. The composition of the upper layer may be a photosensitive material such as a photoresist, which may comprise an organic material. The bottom layer can be a bottom anti-reflective coating. The composition of the intermediate layer may be or include an inorganic material such as a nitride such as tantalum nitride, an oxynitride such as bismuth oxynitride, an oxide such as cerium oxide, or the like. The intermediate layer has high etching selectivity with respect to the upper layer and the bottom layer. In this way, the upper layer serves as an etch mask for patterning the intermediate layer, and the intermediate layer serves as an etch mask for patterning the underlayer.

After the pattern is transferred to the underlayer, an etch process can be performed to transfer the underlying pattern to the core layer 856. The etching process removes portions of the core layer 856 exposed by the intermediate layer and the bottom layer. In an embodiment, the etch process can be a dry etch that exposes the core layer 856 to the plasma source and one or more etchant gases. The etch can be an inductively coupled plasma etch, a transformer coupled plasma etch, an electron cyclotron resonance etch, a reactive ion etch, or the like. The remaining portion of the core layer 856 forms the core 858. In some embodiments, an etch process for transferring the pattern to the core layer 856 can remove the intermediate layer and partially remove the underlying portion. An ashing process can be performed to remove residual intermediate layers and/or underlayers.

In Fig. 20, a low temperature dielectric film 862 is formed over the mask layer 854 and the core 858. After forming the low temperature dielectric film 862, it may extend along the upper surface of the mask layer 854 and the core 858 and along the sidewalls of the core 858. In some embodiments, the low temperature dielectric film 862 can be the aforementioned low temperature dielectric film 116, low temperature dielectric film 516, low temperature as shown in FIGS. 1A to 4, 5A to 5C, FIGS. 6A to 6E, or 7A to 14B. Dielectric film 616, or low temperature dielectric film 736 is similar. For example, the deposition method of the low temperature dielectric film 862 may be a plasma enhanced atomic layer deposition process that does not use oxygen as a precursor material to reduce possible damage to the core 858. In the method of forming the fins 874 described below, reducing the damage core 858 can improve process uniformity.

In FIG. 21, a suitable etching process can be performed to remove the horizontal portion of the low temperature dielectric film 862. In some embodiments, the etchant used to etch the horizontal portion of the low temperature dielectric film 862 is chlorine, methane, nitrogen, argon, the like, or a combination thereof. After the etching process, the vertical portion of the low temperature dielectric film 862 may remain along the sides of the core, which may be referred to as spacers 864 thereafter. The etching process can be non-isotropic, so the width of the spacer 864 is not significantly reduced.

In Figure 22, the core 858 is removed. The removal method of the core 858 may be a suitable etching process (such as an etching process including an etchant such as carbon tetrafluoride, methyl fluoride, hydrogen, nitrogen, argon, the like, or a combination thereof), an ashing process, Or any other suitable etching process that removes the core 858 without substantially damaging the spacers 864. Additionally, the substrate 850 can be subjected to a wet cleaning process to remove residual spacers and core material. In some embodiments, the process of etching the spacers and removing the core can be performed in the same deposition chamber.

In FIG. 23, spacer 864 acts as an etch mask for patterned mask layer 854. A suitable etching process, such as non-isotropic etching, can be employed in conjunction with any suitable chemical such as carbon tetrafluoride, hydrogen bromide, chlorine, oxygen, argon, the like, or combinations thereof. The pattern of spacers 864 can thus be transferred to the mask layer 854 to form openings in the mask layer 854.

In FIG. 24, a fin 868 is formed in the substrate 850. The method of forming the fins 868 may employ a patterned mask layer 854 as an etch mask and etch the anti-reflective coating 852 and the substrate 850 to form trenches in the substrate 850. The semiconductor strips between the trenches form fins 868. The etching can be any acceptable etching process, and an etchant such as chlorine, nitrogen, methane, the like, or a combination thereof can be employed. The etching can be non-isotropic. This process can consume spacers 864, patterned mask layer 854, and patterned anti-reflective coating 852. In some embodiments, a cleaning process can be performed to remove any residual material of the spacer 864, the patterned mask layer 854, or the patterned anti-reflective coating 852.

In FIG. 25, an insulating material is formed between the substrate 850 and the adjacent fins 868. The insulating material may be an oxide such as yttria, a nitride, the like, or a combination thereof. The insulating material is then recessed to form shallow trench isolation regions 872. Due to the recess of the insulating material, the fins 874 in the first region 850B and the second region 850C will bulge from between the adjacent shallow trench isolation regions 872. The insulating material may be recessed using an acceptable etching process to form shallow trench isolation regions 872. This etching process is selective to the insulating material. The fins 874 can be similar to the fins 874 shown in Figure 16 above. After the fins 874 are formed, other processing steps can be performed to form fin field effect transistors (such as the fin field effect transistors shown in FIG. 16). For example, gate dielectric layer 818 and gate 820 can be formed on each fin 874, and source/drain regions 802 can be formed on both sides of each fin 874. This is an illustrative example, and other embodiments for forming a fin field effect transistor may employ additional or other process steps and fall within the scope of embodiments of the present invention.

Although the processes illustrated in Figures 17 through 25 are used to form the fins 874, it should be understood that the process steps illustrated in Figures 17 through 25 can be used in other processes. For example, spacers formed from a low temperature dielectric film may be formed on other semiconductor device units to pattern other semiconductor device units, and other semiconductor device units may be polysilicon gates, metal gates, dummy gates, isolation A region, an interconnect structure, a gate spacer, a contact etch stop layer, or the like.

The various embodiments described above provide a process for depositing a low temperature dielectric film. The low temperature dielectric film described above can be deposited on the photoresist or polymer layer without damaging the photoresist or polymer layer. In some embodiments, the low temperature dielectric film described above can be used as an etch mask for photoresists, polymers, or other materials. In some embodiments, the low temperature dielectric film described above can be used as a backing layer for improving adhesion. For example, the adhesion of a layer (such as a photoresist, dielectric layer, or other kind of layer) deposited on a low temperature dielectric film can be higher than that of a layer deposited on a different material. Sex. The use of low temperature dielectric films can improve the width variation or edge roughness of some structures, such as metal lines or other structures. The low temperature dielectric film can be used for a part of the front stage process or a part of the back end process.

In one embodiment, a method of forming a semiconductor device includes: placing a substrate into a deposition chamber; depositing a layer on the substrate; and depositing an oxide layer on the layer. The step of depositing an oxide layer includes: flowing a first precursor material into a deposition chamber; forming a portion of the oxide layer from the first precursor material in the deposition chamber; igniting the second precursor material into a plasma, And the second precursor material is free of oxygen allotropes; and in the deposition chamber, a portion of the oxide layer is formed from the plasma. In an embodiment, the method further includes patterning the opening in the layer. In one embodiment, the step of depositing an oxide layer includes depositing an oxide layer in the opening in the layer. In an embodiment, the above method further includes patterning the oxide layer to extend the opening into the oxide layer. In one embodiment, the process temperature at which the oxide layer is deposited is less than about 200 °C. In an embodiment, the second precursor material is free of gaseous oxygen. In an embodiment, the second precursor material comprises carbon dioxide. In an embodiment, the oxide layer comprises tantalum, carbon, or a combination thereof. In an embodiment, the oxide layer comprises tantalum carbonitride.

In another embodiment, a method of forming a semiconductor device includes: depositing a dielectric layer on a substrate; performing a first patterning step to form a recess in the dielectric layer; and depositing an oxide film on the dielectric layer In the recess of the electrical layer, and the oxide film contacts the dielectric layer, wherein the oxide film is formed of a plurality of precursors, wherein the precursor does not contain oxygen, and wherein the step of depositing the oxide film comprises forming a first precursor of the precursor Plasma. In one embodiment, the oxide film deposits a recess that fills the dielectric layer. In one embodiment, the recess has a first inner width, and the step of depositing an oxide film in the recess forms a trench in the recess, the trench having a second inner width, and the second inner width being less than the first inner width. In an embodiment, the oxide film is conformally deposited in the recess. In an embodiment, the dielectric layer is a photoresist material or a polymer material. In an embodiment, the oxide film comprises tantalum, carbon, nitrogen, or a combination thereof. In one embodiment, the oxide film is tantalum carbonitride. In one embodiment, the first precursor of the precursor is nitrous oxide. In an embodiment, the first precursor of the precursor is carbon dioxide.

In another embodiment, a method of forming a semiconductor device includes: forming a dielectric layer on a semiconductor substrate; patterning a photoresist on the dielectric layer; placing the semiconductor substrate and the photoresist into the process chamber; using an etching process to Transferring the pattern of the photoresist to the dielectric layer; sequentially providing a plurality of precursors into the process chamber, wherein the precursor contains an oxygen-free allotrope; and forming an oxide layer in the dielectric layer in the process chamber The oxide layer contacts the dielectric layer, and the step of forming the oxide layer includes igniting at least one precursor of the precursor into a plasma. In one embodiment, the method includes performing an etching process in the process chamber to etch the oxide layer. In an embodiment, the precursor comprises carbon dioxide, nitrous oxide, or ethanol. In an embodiment, the oxide layer comprises tantalum, carbon, nitrogen, or a combination thereof. In an embodiment, the oxide layer comprises bismuth oxynitride. In one embodiment, the step of forming an oxide layer includes using a plasma enhanced atomic layer deposition process.

The features of the above-described embodiments are advantageous to those of ordinary skill in the art in understanding the embodiments of the invention. Those having ordinary skill in the art should understand that the embodiments of the present invention can be used to design and change other processes and structures to achieve the same objectives and/or advantages of the above embodiments. It is also to be understood by those of ordinary skill in the art that the invention may be modified, substituted, or modified without departing from the spirit and scope of the invention.

Claims (20)

 A method of forming a semiconductor device, comprising: placing a substrate in a deposition chamber; depositing a layer on the substrate; and depositing an oxide layer on the layer, comprising: making a first precursor Material flows into the deposition chamber; in the deposition chamber, a portion of the oxide layer is formed from the first precursor material; a second precursor material is ignited into a plasma, and the second precursor material is not An oxygen-containing allotrope; and a portion of the oxide layer formed from the plasma in the deposition chamber.    The method of forming a semiconductor device according to claim 1, further comprising patterning an opening in the layer.    The method of forming a semiconductor device according to claim 2, wherein the step of depositing the oxide layer comprises depositing the oxide layer in an opening in the layer.    The method of forming a semiconductor device according to claim 3, further comprising patterning the oxide layer to extend the opening into the oxide layer.    The method of forming a semiconductor device according to claim 1, wherein a process temperature for depositing the oxide layer is less than about 200 °C.    The method of forming a semiconductor device according to claim 1, wherein the second precursor material is free of gaseous oxygen.    The method of forming a semiconductor device according to claim 1, wherein the second precursor material comprises carbon dioxide.    The method of forming a semiconductor device according to claim 1, wherein the oxide layer comprises tantalum, carbon, or a combination thereof.    A method of forming a semiconductor device, comprising: depositing a dielectric layer on a substrate; performing a first patterning step to form a recess in the dielectric layer; and depositing an oxide film on the dielectric layer In the recess of the dielectric layer, and the oxide film contacts the dielectric layer, wherein the oxide film is formed of a plurality of precursors, wherein the precursors are free of oxygen, and wherein the oxide film is deposited The step includes forming a plasma of a first precursor of the precursors.    The method of forming a semiconductor device according to claim 9, wherein the oxide film deposits the recess filled in the dielectric layer.    The method of forming a semiconductor device according to claim 9, wherein the recess has a first inner width, and the step of depositing the oxide film in the recess forms a trench in the recess, the trench having a second inner width, and the second inner width is less than the first inner width.    The method of forming a semiconductor device according to claim 9, wherein the oxide film is conformally deposited in the recess.    The method of forming a semiconductor device according to claim 9, wherein the dielectric layer is a photoresist material or a polymer material.    The method of forming a semiconductor device according to claim 9, wherein the oxide film comprises germanium, carbon, nitrogen, or a combination thereof.    The method of forming a semiconductor device according to claim 9, wherein the first precursor of the precursors is nitrous oxide.    A method of forming a semiconductor device includes: forming a dielectric layer on a semiconductor substrate; patterning a photoresist on the dielectric layer; placing the semiconductor substrate and the photoresist into a process chamber; using an etch a process of transferring the pattern of the photoresist to the dielectric layer; sequentially providing a plurality of precursors into the process chamber, wherein the precursors are oxygen-free allotropes; and in the process chamber Forming an oxide layer on the dielectric layer, the oxide layer contacting the dielectric layer, and forming the oxide layer comprises igniting at least one precursor of the precursors into a plasma.    The method of forming a semiconductor device according to claim 16, further comprising performing an etching process in the process chamber to etch the oxide layer.    The method of forming a semiconductor device according to claim 16, wherein the precursors comprise carbon dioxide, nitrous oxide, or ethanol.    The method of forming a semiconductor device according to claim 16, wherein the oxide layer comprises germanium, carbon, nitrogen, or a combination thereof.    The method of forming a semiconductor device according to claim 16, wherein the step of forming the oxide layer comprises using a plasma enhanced atomic layer deposition process.