TW201916037A - Operating method of resistive memory storage apparatus - Google Patents

Abstract

A operating method of a resistive memory storage apparatus includes applying a forming voltage to a memory cell and obtaining a cell current of the memory cell; and determining whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell according to an amount relationship of the cell current and a reference current. The memory cell that the forming voltage is applied operates in a heavy forming and serves as an one-time programmable memory device.

Description

Operation method of resistive memory storage device

The present invention relates to a method of operating a memory storage device, and more particularly to a method of operating a resistive memory storage device.

In recent years, resistive memory (such as Resistive Random Access Memory (RRAM)) has developed extremely rapidly and is currently the most attractive structure of future memory. Resistive memory is ideal for low-power, high-speed operation, high density, and compatibility with Complementary Metal Oxide Semiconductor (CMOS) process technology, making it ideal for next generation non-volatile Memory component.

Current resistive memories typically include opposing upper and lower electrodes and a dielectric layer between the upper and lower electrodes. When setting the current resistive memory, we first need to perform the filament forming procedure. A positive bias is applied to the resistive memory to cause a current to flow from the upper electrode to the lower electrode such that an oxygen vacancy or oxygen ion is formed in the dielectric layer to form a current path, and the filament is formed at this time. In the formed filament, the diameter of the portion adjacent to the upper electrode may be larger than the diameter of the portion adjacent to the lower electrode. Further, when the current resistive memory is reset, a negative bias is applied to the resistive memory to cause current to flow from the lower electrode to the upper electrode. At this point, oxygen vacancies or oxygen ions exit the current path adjacent the lower electrode, causing the filament to break adjacent to the lower electrode.

However, in the prior art, after the current resistive memory is set, although a low resistance state (LRS) memory cell can be obtained, and the read current is large, The large read current does not know whether the filament of the low-resistance memory cell is robust enough to meet the high temperature data retention (HTDR) and endurance detection. On the contrary, after the current resistive memory is reset, although a high resistance state (HRS) memory cell can be obtained, and the read current is small, the small read current cannot be known. Whether the filament of the high-resistance memory cell is strong enough to meet the detection of high-temperature data retention and durability. A memory cell that does not meet the high-temperature data retention capability and durability detection is not reliable and is not suitable as a one-time programmable (OTP) memory component.

The invention provides a method for operating a resistive memory storage device, wherein the memory cell has high reliability and is suitable as a one-time programmable memory device.

The writing method of the resistive memory storage device of the present invention includes: applying a forming voltage to the memory cell, and obtaining a first cell current of the memory cell; and according to the first cell current and the first reference current The size relationship determines whether the voltage is formed and an adjusted forming voltage is applied to the memory cell. The memory cell after the voltage is applied is operated in a heavy forming mode and as a one-time programmable memory element.

In an embodiment of the present invention, the operating method of the resistive memory storage device further includes: determining whether the first unit cell current is less than the first reference current; and adjusting the first unit current if the first unit current is less than the first reference current And applying an adjusted forming voltage to the memory cell; and ending the method of operation if the first cell current is greater than or equal to the first reference current.

In an embodiment of the invention, the method for operating the resistive memory storage device further includes: repeating the step of adjusting the forming voltage and applying the adjusted forming voltage to the memory cell until the first cell current is greater than or Equal to the first reference current.

In an embodiment of the invention, the forming voltage includes a gate voltage and a bit line voltage. The step of applying a forming voltage to the memory cell includes applying a gate voltage and a bit line voltage to the gate of the memory cell and the bit line to which it is coupled, respectively. The voltage of the gate voltage and the bit line voltage is determined by the material of the dielectric layer of the memory cell.

In an embodiment of the invention, the method for operating the resistive memory storage device further includes: performing a reset operation on the memory cell operating in the reforming mode. The memory cell after the reset operation is operated in the reforming mode and is a memory element of multiple-time programmable (MTP).

In an embodiment of the present invention, the method for operating the resistive memory storage device further includes: obtaining a second unit cell current of the memory unit cell; and determining a magnitude relationship between the second unit current and the second reference current Determine whether to perform a reset operation on the memory cell operating in the reforming mode. Determining whether to perform a reset operation on the memory cell operating in the reforming mode according to the magnitude relationship between the second cell current and the second reference current includes: determining whether the second cell current is less than the second reference current; The second unit cell current is less than the second reference current, does not perform a reset operation on the memory cell operating in the reforming mode, and ends the operation method; and if the second unit cell current is greater than or equal to the second reference current, the operation is performed The memory cell of the re-formation mode performs a reset operation.

In an embodiment of the present invention, the resetting operation includes: setting a source line voltage of the memory cell, and applying a reset voltage to the gate of the memory cell and the source line to which the memory cell is coupled, and a source line voltage, and obtaining a first reset current of the memory cell; adjusting a source line voltage of the memory cell, respectively applying a reset to the gate of the memory cell and the source line to which the memory cell is coupled a voltage and an adjusted source line voltage, and obtaining a second reset current of the memory cell; and determining whether to re-adjust the source of the memory cell according to the magnitude relationship between the first reset current and the second reset current The line voltage or the current value of the second reset current. The step of determining whether to adjust the source line voltage of the memory cell or the current value of the second reset current according to the magnitude relationship between the first reset current and the second reset current includes: determining whether the second reset current is Less than the first reset current; if the second reset current is less than the first reset current, recording the current value of the second reset current; and if the second reset current is equal to the first reset current, adjusting the memory cell again Source line voltage.

In an embodiment of the invention, if the second reset current is equal to the first reset current, the source line voltage of the memory cell is adjusted again, and the gates of the memory cells and their couplings are repeatedly performed. The step of applying the reset voltage and the adjusted source line voltage to the source line until the second reset current is less than the first reset current.

In an embodiment of the present invention, the operating method of the resistive memory storage device further includes: after recording the current value of the second reset current, adjusting the source line voltage of the memory cell again, respectively, to the memory The gate of the body cell and the source line coupled thereto apply a reset voltage and an adjusted source line voltage, and obtain a third reset current of the memory cell; and according to the second reset current and the The magnitude relationship of the three reset currents determines whether to adjust the source line voltage of the memory cell again or end the reset operation. Determining whether to adjust the source line voltage of the memory cell or ending the reset operation according to the magnitude relationship between the second reset current and the third reset current includes: determining whether the third reset current is greater than or equal to the second The current is reset; if the third reset current is greater than or equal to the second reset current, the reset operation is ended; and if the third reset current is less than the second reset current, the source line voltage of the memory cell is adjusted again.

In an embodiment of the invention, if the third reset current is less than the second reset current, the source line voltage of the memory cell is adjusted again, and the gates of the memory cells and their couplings are repeatedly performed. The step of applying the reset voltage and the adjusted source line voltage to the source line until the third reset current is greater than or equal to the second reset current.

Based on the above, in an exemplary embodiment of the present invention, the memory cell after the voltage is applied is operated in the reforming mode, which is highly reliable and is suitable as a one-time programmable memory element.

The above described features and advantages of the invention will be apparent from the following description.

The invention is illustrated by the following examples, but the invention is not limited to the illustrated embodiments. Further combinations are also allowed between the embodiments. The term "coupled" as used throughout the specification (including the scope of the claims) may be used in any direct or indirect connection. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Connected to the second device indirectly. In addition, the term "signal" may refer to at least one current, voltage, charge, temperature, data, electromagnetic wave or any other one or more signals.

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention. 2 is a schematic diagram showing a normal formation procedure, a normal reset operation, and a normal setting operation of a filament in a memory cell of a related example of the present invention. Referring to FIG. 1 and FIG. 2, the memory storage device 100 of this related example includes a memory control circuit 110 and a memory cell array 120. The memory cell array 120 is coupled to the memory control circuit 110. The memory cell array 120 includes a plurality of memory cells 122 arranged in an array. In this related example, the resistive memory element 122 includes an upper electrode 210, a lower electrode 220, and a dielectric layer 230. The upper electrode 210 and the lower electrode 220 are good metal conductors, and the materials of the two may be the same or different. The dielectric layer 230 is disposed between the upper electrode 210 and the lower electrode 220. The dielectric layer 230 includes a dielectric material including, for example, Transition Metal Oxide (TMO). The memory cell 122 of such a structure has at least two resistance states, and the resistance state of the resistive memory device 122 is changed by applying different voltages across the electrodes to provide a function of storing data.

In the present embodiment, the memory cell 122 has, for example, a transistor-resistor (1T1R) structure or a two-diode two-resistor (2T2R) structure, and its implementation can be sufficiently obtained by the general knowledge in the art. Instructions, suggestions and implementation instructions. The present invention does not limit the structure of the memory cell 122.

In this related example, the memory control circuit 110 is used to perform a normal forming procedure on the memory cell 122. The normal formation procedure refers to the process of initializing the memory cell 122. During this process, a bias voltage V1 (forming voltage) is continuously applied across the electrodes of the memory cell 122 to generate an applied electric field to the dielectric layer 230. In this related example, a positive voltage of V1 volt is applied to the upper electrode 210, and a voltage of 0 volt is applied to the lower electrode 220. In addition, the addition of an electric field separates the oxygen atoms 222 into oxygen ions 212 and oxygen vacancies 232. The oxygen vacancy 232 forms a filament in the dielectric layer 230 as a current transfer path. When the applied electric field exceeds the critical value, the dielectric layer 230 will undergo a dielectric collapse phenomenon, thereby transitioning from a high resistance state to a low resistance state. This type of collapse is not permanent and its resistance can still change.

The memory cell 122 that has undergone the normal formation process has a low resistance state. At the normal reset operation, the upper electrode 210 of the memory cell 122 is applied with a voltage of 0 volts, and the lower electrode 220 is applied with a positive voltage having a value of V2 volts. This voltage difference is a normal reset voltage, such as -V2 volts. The memory cell 122 that has undergone a normal reset operation changes its state from a low resistance state to a high resistance state. Next, at the normal setting operation, the upper electrode 210 of the memory cell 122 is applied with a positive voltage of V3 volts, and the lower electrode 220 is applied with a voltage of 0 volts. This voltage difference is a normal set voltage, such as +V3 volts. The memory cell 122 operated by the normal setting changes its state from a high resistance state to a low resistance state. In this related example, the magnitude and polarity of the normal reset voltage and the normal set voltage are for illustrative purposes only, and are not intended to limit the present invention. In the present embodiment, the forming procedure, the resetting operation, and the setting operation illustrated in FIG. 2 are for illustrative purposes only, and are not intended to limit the present invention.

On the other hand, for reliability testing and commercialization, the high temperature data retention capability and durability of the memory storage device 100 have a decisive influence. One of the reasons why the high temperature data retention capability of the memory storage device 100 is lost is that the oxygen ions 212 drift from the electrode layer (for example, the upper electrode 210) to the dielectric layer 230, and recombine with the oxygen vacancy 232 therein, thereby possibly blocking The current transfer path in the dielectric layer 230 is broken, that is, the filament is broken therein.

3 is a diagram showing a Cumulative Distribution Function (CDF) diagram of a unit cell current before and after heat treatment of a memory cell according to an embodiment of the invention. Referring to FIG. 1 to FIG. 3, in the correlation example of FIG. 2, after the memory cell 122 is subjected to a normal formation process, a normal setting operation or a normal reset operation may be performed to change the memory cell. The resistance state of 122, so that the recorded data is logical 1 or logic 0. The normal formation process is, for example, applying a voltage of 1.5 to 2.5 volts (ie, gate voltage Vg=1.5V to 2.5V) to the gate of the memory cell 122 when the formation process is performed, and the bit coupled thereto The line applies a voltage greater than 0 volts and less than 4 volts (ie, bit line voltage Vbl=0V~4V).

In the correlation example of FIG. 2, the cell current of the normal formation process memory cell 122 is substantially distributed in the region I of FIG. The region I is a region where the cell current is between 0 and the first critical current Ith1, and the first critical current Ith1 is about 22 microampere (μA). The memory cell 122 operating in the region I has a significant difference in the cell current distribution curves A and B before and after the heat treatment process, that is, the high temperature data retention capability of the memory cell 122 is significantly attenuated.

In an exemplary embodiment of the present invention, the memory control circuit 110 applies a larger forming voltage to the memory cell 122 in the reforming process than the normal forming process, such as a gate voltage Vg > 6.0V and a bit. The line voltage Vbl>5.0V. In the present embodiment, the voltage values of the gate voltage Vg and the bit line voltage Vb1 are determined, for example, depending on the material of the dielectric layer 230 of the memory cell 122. Thus, in an exemplary embodiment of the invention, the memory cell 122 of the reformatted program has a unit cell current that is substantially distributed in region II of FIG. Region II is the region where the unit cell current is between the second critical current Ith2 and 40 microamperes, and the second critical current Ith2 is about 27 microamperes. The memory cell 122 operating in the region II has substantially the same cell current distribution curves C and D before and after the heat treatment process, that is, the high temperature data retention capability of the memory cell 122 is substantially constant, and the reliability is high. . Therefore, in the exemplary embodiment of the present invention, the memory cell 122 after the voltage is applied is operated in the reforming mode (ie, in the region II), the high temperature data retention capability is constant, and the reliability is high, which is suitable as a one-time Programmable memory component.

In an exemplary embodiment of the present invention, the reforming mode is, for example, compared to a normal forming process, and the memory control circuit 110 applies a large forming voltage to the memory cell 122 in the reforming process to cause the memory cell 122 is operable in region II where the unit cell current is greater than the second critical current. The memory cell 122 that can operate in the reforming mode has high reliability and is suitable as a one-time programmable memory element. In the exemplary embodiment of FIG. 3, the various parameters disclosed (including gate voltage, bit line voltage, distribution curve, and critical current value) are for illustrative purposes only and are not intended to limit the invention. A number of exemplary embodiments are exemplified below to illustrate a method of operation of a resistive memory storage device.

4 is a flow chart showing the steps of an operation method of a memory storage device according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 4, in the embodiment, in step S100, the memory control circuit 110 applies a forming voltage to the memory cell 122 and obtains a first cell current of the memory cell 122. In step S100, the formation voltage applied to the memory cell 122 is, for example, a larger formation voltage than the normal formation process. In step S110, the memory control circuit 110 determines whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell 122 according to the magnitude relationship between the first cell current and the first reference current. In this embodiment, the memory cell after the voltage is applied or the memory cell after the applied voltage is applied can be operated in the reforming mode, which has high reliability and is suitable as a one-time programmable memory. Body component.

FIG. 5 is a flow chart showing the steps of a method for operating a memory storage device according to another embodiment of the present invention. Referring to FIG. 1 and FIG. 5, in the embodiment, in step S200, the memory control circuit 110 sets a voltage value for forming a voltage. The magnitude of the voltage value at which the voltage is formed is determined, for example, depending on the gate voltage of the memory cell 122 or the bit line voltage, or depending on the pulse width at which the voltage is formed. In step S200, the formation voltage set by the memory control circuit 110 is, for example, a formation voltage that is larger than the formation voltage of the normal formation program. In one embodiment, the pulse width of the forming voltage set by the memory control circuit 110 may be the same as or larger than the pulse width of the forming voltage of the normal forming program. In step S210, the memory control circuit 110 applies a forming voltage to the memory cell 122. In step S210, the operation of applying a voltage to the memory cell 122 is, for example, applying a gate voltage Vg and a bit line voltage Vbl to the gate of the memory cell 122 and the bit line to which it is coupled. In the present embodiment, the voltage values of the gate voltage Vg and the bit line voltage Vb1 are determined, for example, depending on the material of the dielectric layer 230 of the memory cell 122. In step S220, the memory control circuit 110 acquires the first unit cell current I1 of the memory cell 122.

Next, in step S230, the memory control circuit 110 determines whether the first unit cell current I1 is smaller than the first reference current Iref1. In the present embodiment, the first reference current Iref1 is set, for example, to 35 microamperes, which is not intended to limit the invention. If the first cell current I1 is greater than or equal to the first reference current Iref1 (ie, I1≧Iref1), it means that the memory cell after the applied voltage is applied is operable in the reforming mode, and is suitable as a one-time programmable memory. element. Therefore, the memory control circuit 110 ends the operation method of the memory storage device 100.

If the first unit cell current I1 is smaller than the first reference current Iref1, the memory control circuit 110 performs step S240. In step S240, the memory control circuit 110 adjusts the formation voltage set in step S200, and returns to step S210 to apply the adjusted formation voltage to the memory cell 122. In the present embodiment, one of the ways in which the memory control circuit 110 adjusts the voltage formation is, for example, stepping to form a voltage, that is, a pulse width signal whose voltage is adjusted to a gradually increasing level.

Next, the memory control circuit 110 repeatedly performs steps S210 to S240 until the first unit cell current I1 is greater than or equal to the first reference current Iref1, and ends the operation method of the memory storage device 100. Therefore, the memory cell after the applied forming voltage is applied can operate in the reforming mode and is suitable as a one-time programmable memory element. In this embodiment, the memory control circuit 110 may also set the number of times the voltage is applied to the memory cell 122 to be one or more times (for example, five times or less) before performing the operation method. invention. Therefore, the number of times the memory control circuit 110 repeatedly performs steps S210 to S240 is not greater than the set number of times. In an embodiment, the memory control circuit 110 may not repeatedly perform steps S210 to S240, that is, after the first application of the forming voltage, the first unit current I1 is greater than or equal to the first reference current Iref1.

Therefore, in the present embodiment, the memory cell after the voltage is applied or the memory cell after the applied voltage is applied can be operated in the reforming mode, and the reliability is high, and is suitable as one-time programmable. Memory component. In an exemplary embodiment of the invention, the memory control circuit 110 may perform a reset operation on the memory cell 122 operating in the reforming mode such that the memory cell 122 can function as a plurality of programmable memory elements. At least one exemplary embodiment is exemplified below to illustrate a method of operation of a resistive memory storage device.

6 is a flow chart showing the steps of a method of operating a memory storage device according to another embodiment of the present invention. Referring to FIG. 1 and FIG. 6, in the present embodiment, the memory cell 122 is operable in a reforming mode, for example, and has high reliability, and is suitable as a one-time programmable memory device. The operation method of this embodiment can perform a reset operation on the memory cell 122 operating in the reforming mode, so that the memory cell 122 can function as a multi-programmable memory element.

In step S300, the memory control circuit 110 obtains the second unit cell current I2 of the memory cell 122. In step S310, the memory control circuit 110 determines whether the second unit cell current I2 is smaller than the second reference current Iref2. If the second unit cell current I2 is smaller than the second reference current Iref2 (i.e., I2 < Iref2), the memory control circuit 110 does not perform a reset operation on the memory cell 122 operating in the reforming mode, and ends the operation method. If the second unit cell current I2 is greater than or equal to the second reference current Iref2, the memory control circuit 110 performs step S322 to perform a reset operation on the memory unit cell 122 operating in the reforming mode. Therefore, in step S310, the memory control circuit 110 determines whether to perform a reset operation on the memory cell operating in the reforming mode according to the magnitude relationship between the second cell current I2 and the second reference current Iref2.

In step S322, the memory control circuit 110 sets the source line voltage of the memory cell 122. In step S324, the memory control circuit 110 applies a reset voltage and a source line voltage to the gate of the memory cell 122 and the source line to which it is coupled. In step S326, the memory control circuit 110 takes the first reset current Irst1 of the memory cell 122 and records the first reset current value. In step S332, the memory control circuit 110 adjusts the source line voltage of the memory cell 122. In step S334, the memory control circuit 110 applies a reset voltage and an adjusted source line voltage to the gate of the memory cell 122 and the source line to which it is coupled. In step S336, the memory control circuit 110 obtains the second reset current Irst2 of the memory cell 122.

In step S340, the memory control circuit 110 determines whether the second reset current Irst2 is smaller than the first reset current Irst1. If the second reset current Irst2 is smaller than the first reset current Irst1 (ie, Irst2 < Irst1), the memory control circuit 110 performs step S350 to record the current value of the second reset current Irst2. If the second reset current Irst2 is equal to the first reset current Irst1 (ie, Irst2=Irst1), the memory control circuit 110 repeatedly performs steps S332 to S340 until the second reset current Irst2 is smaller than the first reset current Irst1. Therefore, in step S340, the memory control circuit 110 determines whether to adjust the source line voltage of the memory cell 122 or record the second reset according to the magnitude relationship between the first reset current Irst1 and the second reset current Irst2. Current value of current Irst2.

In step S362, the memory control circuit 110 adjusts the source line voltage of the memory cell 122. In step S364, the memory control circuit 110 applies a reset voltage and an adjusted bit line voltage to the gate of the memory cell 122 and the source line to which it is coupled. In step S366, the memory control circuit 110 obtains the third reset current Irst3 of the memory cell 122. In step S370, the memory control circuit 110 determines whether the third reset current Irst3 is greater than or equal to the second reset current Irst2. If the third reset current Irst3 is greater than or equal to the second reset current Irst2 (ie, Irst3 ≧ Irst2), the memory control circuit 110 ends the reset. If the third reset current Irst3 is smaller than the second reset current Irst2 (ie, Irst3<Irst2), the memory control circuit 110 repeatedly performs steps S362 to S370 until the third reset current Irst3 is greater than or equal to the second reset current Irst2.

In the present embodiment, one of the ways of obtaining the cell current or the reset current of the memory cell 122 is, for example, applying a read voltage or a verify voltage to the memory cell 122 to detect the current of the memory cell 122. The size of the value. In this embodiment, in the embodiment, one of the ways in which the memory control circuit 110 adjusts the reset voltage is, for example, a stepped reset voltage, that is, the reset voltage is adjusted to a pulse width signal whose level is gradually increased. In this embodiment, by using the operation method illustrated in FIG. 6, the memory control circuit 110 can perform a reset operation on the memory cell 122 operating in the reforming mode, so that the memory cell 122 can be used as multiple times. Programmable memory component.

In summary, in the exemplary embodiment of the present invention, the memory cell after a larger forming voltage is applied in the reforming process or after the adjusted larger forming voltage is applied, compared to the normal forming process. The memory cell can operate in a reforming mode with high reliability and is suitable as a one-time programmable memory component. In addition, the memory control circuit can perform a reset operation on the memory cell operating in the reforming mode so that the memory cell can serve as a multi-programmable memory element. This mode of operation maintains the high temperature data retention capability of the memory storage device operating in the reforming mode and optimizes the durability of the memory storage device operating in the reforming mode to improve reliability.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ memory storage device

110‧‧‧Memory Control Circuit

120‧‧‧Memory cell array

122‧‧‧ memory cell

210‧‧‧Upper electrode

212‧‧‧Oxygen ions

220‧‧‧ lower electrode

222‧‧‧Oxygen atom

230‧‧‧ dielectric layer

232‧‧‧Oxygen vacancies

V1‧‧‧ forming voltage

V2‧‧‧Reset voltage

V3‧‧‧Set voltage

HRS‧‧‧high resistance state

LRS‧‧‧Low resistance state

A, B, C, D‧‧‧ distribution curves

S100, S110, S200, S210, S220, S230, S240, S300, S310, S322, S324, S326, S332, S334, S336, S340, S350, S362, S364, S366, S370‧‧‧ method steps

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention. 2 is a schematic diagram showing a filament formation process, a reset operation, and a setting operation in a memory cell of a related example of the present invention. 3 is a graph showing a cumulative distribution function of unit cell currents of a memory cell before and after heat treatment according to an embodiment of the invention. 4 is a flow chart showing the steps of an operation method of a memory storage device according to an embodiment of the present invention. FIG. 5 is a flow chart showing the steps of a method for operating a memory storage device according to another embodiment of the present invention. 6 is a flow chart showing the steps of a method of operating a memory storage device according to another embodiment of the present invention.

Claims (10)

A method of operating a resistive memory storage device, comprising: applying a forming voltage to a memory cell and obtaining a first cell current of the memory cell; and according to the first cell current and a first Determining whether to adjust the forming voltage and applying the adjusted forming voltage to the memory unit cell, wherein the memory cell after the forming voltage is applied is operated in a reforming mode, and Programmable memory components. The method of operating the resistive memory storage device of claim 1, further comprising: determining whether the first unit cell current is less than the first reference current; if the first unit cell current is less than the first reference Current, adjusting the forming voltage, and applying the adjusted forming voltage to the memory cell; and ending the method of operation if the first cell current is greater than or equal to the first reference current. The method of operating the resistive memory storage device of claim 1, further comprising: repeating the step of adjusting the forming voltage and applying the adjusted forming voltage to the memory cell until the first crystal The cell current is greater than or equal to the first reference current. The method of operating a resistive memory storage device according to claim 1, wherein the forming voltage comprises a gate voltage and a one-bit line voltage, and the step of applying the forming voltage to the memory unit cell comprises Applying the gate voltage and the bit line voltage to the gate of the memory cell and the bit line to which the memory cell is coupled, wherein the gate voltage and the voltage value of the bit line voltage are based on the memory The material of the dielectric layer of the bulk cell is determined. The method for operating a resistive memory storage device according to claim 1, further comprising: performing a reset operation on the memory cell operating in the reforming mode, wherein the reset operation is performed The memory cell operates in this reforming mode and acts as a multi-programmable memory element. The method for operating a resistive memory storage device according to claim 5, further comprising: obtaining a second unit cell current of the memory unit cell; and, according to the second unit cell current and a second reference Determining whether the operation is performed on the memory cell operating in the reforming mode according to the magnitude relationship of the current, wherein determining whether the operation is performed according to the magnitude relationship between the second cell current and the second reference current The step of performing the reset operation in the memory cell of the reforming mode includes: determining whether the second cell current is less than the second reference current; if the second cell current is less than the second reference current, the operation is not The memory cell of the reforming mode performs the reset operation and ends the operation method; and if the second cell current is greater than or equal to the second reference current, the memory operating in the reforming mode The cell performs this reset operation. The method of operating a resistive memory storage device according to claim 5, wherein the resetting operation comprises: setting a source line voltage of the memory unit cell, respectively, to a gate of the memory unit cell Applying a reset voltage and the source line voltage to the source line coupled thereto, and obtaining a first reset current of the memory cell; adjusting the source line voltage of the memory cell, respectively Applying the reset voltage and the adjusted source line voltage to the gate of the memory cell and the source line to which the memory cell is coupled, and obtaining a second reset current of the memory cell; Determining whether to adjust the source line voltage of the memory cell or to record the current value of the second reset current according to the magnitude relationship between the first reset current and the second reset current, wherein according to the first weight And determining a magnitude of the current and the second reset current, determining whether to adjust the source line voltage of the memory cell or recording the current value of the second reset current includes: determining the second reset current Is it smaller than the first? Setting a current; if the second reset current is less than the first reset current, recording a current value of the second reset current; and if the second reset current is equal to the first reset current, adjusting the memory again The source line voltage of the unit cell. The method of operating a resistive memory storage device according to claim 7, wherein if the second reset current is equal to the first reset current, adjusting the source line voltage of the memory cell again, And repeating the steps of respectively applying the reset voltage and the adjusted source line voltage to the gate of the memory cell and the coupled source line until the second reset current is less than the first Reset the current. The operating method of the resistive memory storage device of claim 7, further comprising: adjusting the source line voltage of the memory cell after recording the current value of the second reset current, Applying the reset voltage and the adjusted source line voltage to the gate of the memory cell and the coupled source line, respectively, and obtaining a third reset current of the memory cell; Determining whether to adjust the source line voltage of the memory cell again or ending the reset operation according to the magnitude relationship between the second reset current and the third reset current, wherein the second reset current and the The magnitude relationship of the third reset current, determining whether to adjust the source line voltage of the memory cell again or ending the reset operation comprises: determining whether the third reset current is greater than or equal to the second reset a current; if the third reset current is greater than or equal to the second reset current, ending the reset operation; and if the third reset current is less than the second reset current, adjusting the memory cell again Source Line voltage. The method of operating a resistive memory storage device according to claim 9, wherein if the third reset current is less than the second reset current, adjusting the source line voltage of the memory cell again, And repeating the steps of respectively applying the reset voltage and the adjusted source line voltage to the gate of the memory cell and the coupled source line until the third reset current is greater than or equal to the The second reset current.