TW201915736A - Methods of proactive ecc failure handling - Google Patents

Abstract

An embodiment of a method and apparatus of proactive ECC failure handling is introduced. The method comprises: fetching a completion element from a completion queue, determining whether there is a unsafe value stored in a execution result table in the completion element, if yes, reassigning a new physical address to a user data corresponding to the unsafe value, and issuing a data programming command to a submission queue in order to program the user data to the new physical address, wherein the submission and completion queues are both located in a host.

Description

 Active error correction failure handling method  

The present invention relates to a flash memory, and more particularly to a method for processing an active error correction failure of a flash memory and a device using the same.

Flash memory devices are generally classified into NOR flash devices and NAND flash devices. The NOR flash device is a random access device, and the host device (Host) can provide an address for accessing the NOR flash device at the address pin, and is instantly stored in the data pin of the NOR flash device. User profile on this address. Conversely, NAND flash devices are not random access, but sequential access. The NAND flash device cannot access any random address like the NOR flash device. Instead, the master device needs to write a sequence of bytes (Bytes) to the NAND flash device to define the request command (Command). Type (eg, read, write, erase, etc.) and the address on this command. The address can point to a page (the smallest data block of a write job in flash memory) or a block (the smallest data block of an erase job in flash memory). In fact, NAND flash devices typically read or write complete pages of data from memory cells. When a full page of data is read from the array to the buffer in the device, the main unit can be bitwise or word by sequentially using the Strobe Signal to knock out the content. Tuples access data.

The Open Channel Solid State Disk does not implement the Flash Translation Layer (FTL) on the device side, but instead transfers the physical solid state drive to the host device management. Unlike traditional solid-state drives, open-channel SSDs let the master know the parallel architecture inside the solid-state drive and allow the master to manage it. The open channel solid state hard disk has an encoder for generating an error correction code according to the data to be written by the main device, and writing the data and the error correction code to the storage unit. In addition, there is an error correction circuit in the open channel solid state hard disk, and the error correction code is used to correct the error existing in the read data without the participation of the master device. However, as the number of accesses to the storage unit increases, the number of error bits in the stored data increases. Since the master device does not know the error rate trend of reading data, it cannot instruct the open channel solid state hard disk to perform data transfer operations to move the data to a less-used location.

Therefore, there is a need for an active error correction failure processing method for flash memory and a device using the same to solve the above problems.

An embodiment of the present invention provides an active error correction failure processing method, including: obtaining a completion component from a completion queue; determining whether an execution reply table of the completion component includes an unsafe value, and if so, reallocating the physical address to an unsafe value Corresponding user data; and an output data write command to the delivery queue to write the user data to the reassigned physical address, wherein the completion queue and the delivery queue are all located in the primary device.

An embodiment of the present invention provides an active error correction failure processing method, including: receiving a parameter setting command; setting an error bit threshold according to a parameter setting command; receiving a data reading command; reading from a data reading command to a source address User data, if the number of error bits of the user data is greater than or equal to the error bit threshold, the bit corresponding to the user data in the reply table is set to an unsafe value; and the execution reply table is included The completion component is written to the completion queue, wherein the parameter setting command and the data reading command are all received by the open channel solid state hard disk.

110‧‧‧Main device

120‧‧‧Data buffer

130‧‧‧Open Channel Solid State Drive

133‧‧‧Processing unit

135‧‧‧flash controller

137‧‧‧Access interface

137_0~137_ j ‧‧‧Access subinterface

139‧‧‧ storage unit

139_0_0~139_ j _ i ‧‧‧Storage subunit

310_0‧‧‧Information line

320_0_0~320_0_ i ‧‧‧ Chip enable control signal

410, 430, 450, 470‧‧‧ input and output channels

410_0~410_ m , 430_0~430_ m , 450_0~450_ m , 470_0~470_ m ‧‧‧ data plane

490_0~490_ n ‧‧‧Super Page

P#0~P#( n )‧‧‧ entity page

Submitted to 510‧‧‧

530‧‧‧ completed queue

S611~S636‧‧‧ method steps

710‧‧‧Device identification stage

730‧‧‧Parameter setting phase

S711~S735‧‧‧ method steps

S811~S827‧‧‧ method steps

900‧‧‧Complete components

910‧‧‧Execution reply form

920‧‧‧Status field

930‧‧‧Command ID

1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

2 is a block diagram of an access interface and a storage unit in accordance with an embodiment of the present invention.

Figure 3 is a schematic diagram showing the connection of an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention.

Figure 4 is a schematic diagram of a storage unit.

Figure 5 is a schematic diagram of the command queue.

Figure 6 is a flow chart showing the execution steps of a management command or a data access command.

Figure 7 is a flow chart of a device parameter method of a flash memory according to an embodiment of the present invention.

Figure 8 is a flow chart of a method for processing an active error correction failure according to an embodiment of the present invention.

Figure 9 is a data format diagram of the completed component.

The following description is a preferred embodiment of the invention, which is intended to describe the basic spirit of the invention, but is not intended to limit the invention. The actual inventive content must be referenced to the scope of the following claims.

It must be understood that the terms "comprising", "comprising" and "the" are used in the <RTI ID=0.0> </RTI> <RTIgt; </ RTI> to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude Add more technical features, values, method steps, job processing, components, components, or any combination of the above.

The words "first", "second", and "third" are used in the claims to modify the elements in the claims, and are not used to indicate a priority order, an advance relationship, or a component. Prior to another component, or the chronological order in which the method steps are performed, it is only used to distinguish components with the same name.

1 is a schematic diagram of an architecture of an open channel solid state hard disk system 100 in accordance with an embodiment of the present invention. The Open Channel SSD system 100 architecture includes a main device 110, a Data Buffer 120, and an Open Channel Solid State Disk (SSD) 130. When the main device 111 is in operation, a Queue, a Storage Mapping Table (also referred to as an L2P Logical-to-Physical Table), and a usage record can be established according to the requirements thereof. This system architecture can be implemented in electronic products such as personal computers, laptops, tablets, mobile phones, digital cameras, digital cameras, and the like. The data buffer 120, the queue, the physical storage comparison table, and the usage record can be implemented in a specific area in a random access memory (RAM). The main device 110 communicates with the open channel solid state drive 130 through an open channel solid state hard disk non-volatile memory (NVM-Nola-Volatile Memory Express) interface. The master device 110 can be implemented in a variety of ways, such as using a general purpose hardware (eg, a single processor, a multiprocessor with parallel processing capabilities, a graphics processor, or other computing capable processor), and executing instructions (Instructions) For macro code (Macrocode) or microcode (Microcode), the functions described later are provided. The master device 110 may include an arithmetic logic unit (ALU, Arithmetic and Logic Unit) and a shifter (Bit Shifter). The arithmetic logic unit is responsible for performing Boolean operations (such as AND, OR, NOT, NAND, NOR, XOR, XNOR, etc.) or mathematical operations (such as addition, subtraction, multiplication, division, etc.), while the shifter is responsible for displacement operations and bit rotation. . The open channel SSD NVMe specification, for example, version 1.2, is published in April 2016 and supports several I/O Channels, each of which is connected to a Logical Unit Numbers (LUNs). Used to respectively correspond to a plurality of storage subunits in the storage unit 139. In the open channel SSD NVMe specification, the main device 110 integrates a Flash Translation Layer (FTL) originally implemented in the device end to optimize the load. The traditional flash memory translation layer maps the logical block addresses (LBAs) of the host device or file system to the physical addresses of the storage unit 139 (also referred to as logical to entity mapping). In the Open Channel SSD NVMe specification, the host device 110 can instruct the Open Channel SSD 130 to store user data to a physical address in the storage unit 139. Therefore, the maintenance of the physical storage lookup table is performed by the host device 110 and The physical address of the user data stored in each logical block address is actually stored in the storage unit 139.

The open channel solid state drive 130 includes a processing unit 133. The processing unit 133 can communicate with the host device 110 by using an open channel SSD NVMe communication protocol to receive a data access command including a physical address, and instruct the flash controller 135 to perform erasing, reading or writing according to the data access command. In. It should be noted here that the processing unit 133 can be implemented using a Lightweight General-Purpose Processor.

The open channel SSD 130 further includes a flash controller 135, an access interface 137 and a storage unit 139, and the flash controller 135 communicates with the storage unit 139 through the access interface 137. In detail, the double data rate can be used. (Double Data Rate, DDR) protocol, for example, Open NAND Flash Interface (ONFI), Double Data Rate Switch (DDR Toggle) or other interface. The flash controller 135 of the open channel solid state hard disk 130 writes the user data to the specified destination address (physical address) in the storage unit 139 through the access interface 137, and the source address specified from the storage unit 139 ( The physical address) reads the user data. The access interface 137 uses a plurality of electronic signals to coordinate data and command transmission between the flash controller 135 and the storage unit 139, including a data line, a clock signal, and a control signal. The data line can be used to transmit commands, addresses, read and write data; the control signal line can be used to transmit Chip Enable (CE), Address Latch Enable (ALE), and command extraction. Control signals such as Command Latch Enable (CLE) and Write Enable (WE). Processing unit 133 and flash controller 135 may be present separately or integrated into the same wafer.

The flash controller 135 includes an Error Correction Code Encoder (ECC) and an Error Correction Decoder (ECC Decoder). In the write operation, the error correction encoder generates an error correction code according to the data transmitted from the host device 110 using the encoding algorithm, and writes the data of the master device and the error correction code (collectively referred to as user data) to the storage unit 139. . In the read operation, the error correction decoder checks the correctness of the user profile read from the storage unit 139 using the corresponding decoding algorithm and attempts to correct the error bit therein. If the user profile is correct, the flash controller 135 directly discards the error correction code and replies to the data originally read by the host device 110 through the processing unit 133. If the user profile contains an error bit but has been corrected by the error correction decoder, the flash controller 135 discards the corrected error correction code and replies to the corrected data of the host device 110 via the processing unit 133. If the error bit is too large to be recovered, the flash controller 135 replies to the master device 110 via the processing unit 133 to reply to the data read error message. The error correction code may be a Low Density Parity Check Code (LDPC), a BCH (Bose-Chaudhuri-Hocquenghem Code), or the like. In general, low-density parity check codes can provide better error bit correction capabilities than BCH codes. For example, for every 1K byte user data, the BCH code can provide correction capability of up to 76 error bits. The low-density parity check code provides correction capability of up to 120 error bits.

At system boot, the master device 110 obtains operational parameters required to control the operation of the open channel solid state drive 130 from the open channel solid state drive 130, such as the number of blocks, the number of bad blocks, and delays. (Latency) time, the total number of input and output channels, whether or not the error correction function is enabled.

The storage unit 139 can include a plurality of storage subunits, each of which communicates with the flash controller 135 using an associated access sub-interface. One or more of the storage subunits may be packaged in one die (Die). 2 is a block diagram of an access interface and a storage unit in accordance with an embodiment of the present invention. The open channel solid state drive 130 may include j+1 access sub-interfaces 137_0 to 137_j, and each access sub-interface is connected to i+1 storage sub-units. The access sub-interface and the storage sub-units connected thereto can be collectively referred to as an input-in channel and can be identified by a logical unit number. In other words, i+1 storage subunits share an access subinterface. For example, when the open channel solid state drive 130 includes 4 inputs and outputs (j=3) and each of the input and output connections is connected to 4 storage units (i=3), the open channel solid state drive 130 has a total of 16 storage subunits 139_0_0. To 139_j_i. The flash controller 135 can drive one of the access sub-interfaces 137_0 to 137_j to read data from the designated storage sub-unit. Each storage subunit has an independent wafer enable (CE) control signal. In other words, when data reading is to be performed on a specified storage subunit, the associated access subinterface needs to be driven to enable the wafer enable control signal of the storage subunit. Figure 3 is a schematic diagram showing the connection of an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention. The flash controller 135 can select one of the connected storage sub-units 139_0_0 to 139_0_i through the access sub-interface 137_0 using the independent chip enable control signals 320_0_0 to 320_0_i, and then select from the shared data line 310_0. The source address of the storage subunit reads the user data.

FIG. 4 is a schematic diagram of the storage unit 139. The storage unit 139 includes a plurality of data planes 410_0 to 410_m, 430_0 to 430_m, 450_0 to 450_m, and 470_0 to 470_m, each data plane or a plurality of data planes being placed in one logical unit number. The data planes 410_0 to 410_m and the shared access sub-interface are referred to as the input-input channels 410, the data planes 430_0 to 430_m and the shared access sub-interfaces are referred to as the input-input channels 430, the data planes 450_0 to 450_m, and the shared access sub-interfaces. The input-input channel 450, and the data planes 470_0 to 470_m and the shared access sub-interface are referred to as the input-input channels 470, where m can be an integer of 2 (eg, 2, 4, 8, 16, 32, etc.) The input and output channels 410, 430, 450, and 470 can be identified using a logical unit number. Each of the data planes 410_0 to 470_m includes a plurality of physical blocks, each of which contains a plurality of pages (Pages) P#0 to P#(n), each of which contains more than one zone. Sector, for example, four, where n can be 767 or 1023, and the like. Each page contains multiple NAND memory cells, and the NAND memory cells can be single-level cells (SLCs), multi-level cells (MLCs), and three-layer cells. Triple-Level Cells (TLCs) or Quad-Level Cells (QLCs). In some embodiments, when each NAND memory cell is a single-level cell and two states can be recorded, the page P#0 in the data planes 410_0 to 470_0 can virtually form a Super Page 490_0, a data plane. The page P#1 in 410_0 to 470_0 can virtually form the super page 490_1, and so on. In other embodiments, when each NAND memory cell is a multi-level cell and four states can be recorded, one physical word line can include page P#0 (which can be called the lowest bit page, MSB, Most Significant). Bit Page), page P#1 (can be called the highest bit page, LSB, Least Significant Bit Page), and so on. In still other embodiments, when each NAND memory cell is a three-layer cell and 8 states can be recorded, one physical word line may include page P#0 (which may be referred to as the lowest bit page, MSB Page). ), page P#1 (can be called the intermediate bit page, CSB, Center Significant Bit Page) and page P#2 (can be called the highest bit page, LSB Page). When each NAND memory cell is a four-layer cell and 16 states can be recorded, in addition to the MSB, CSB, and LSB pages, a TSB (TSB, Top Significant Bit) page is further included.

When the storage unit 139 is in operation, the page is a minimum unit for data writing or programming, and the size is, for example, 4 KB, and the physical address can be represented as a page number; if the page contains multiple segments, the size is, for example, 16 KB, each segment When 4KB of data can be stored, the section can be the smallest unit of data management. In this case, the physical address can be expressed as the sector number of the page (Sector Number) or the offset of the section on the page (Offset). In addition, in general, a block is the smallest unit of data erasure.

The physical blocks can be divided into active blocks, data blocks, and idle blocks according to their usage status. The active block represents a physical block in which data is being written, that is, a physical block in which the end of block information has not been written. The active block can be selected based on some parameters, such as the minimum number of writes or the longest user data write time. When the active block is full of user data or no longer written to the user profile, the block end information will be written into the active block and the active block will be treated as a data block. The idle block can be selected to become the active block, and the idle block does not store any valid user data. Usually, after the idle block is selected, the erase operation is performed to become the active block.

In some embodiments, the physical address transmitted by the host device 110 to the open channel SSD 130 may include information such as an input channel number, a logical unit number, a data plane number, a physical block number, a physical page number, and a segment number. Used to indicate the user profile of a particular segment in a particular entity page in a particular physical block that is to be read or written in a particular data plane in a particular input-in channel. In some embodiments, the segment number is sometimes replaced with a column number. In other embodiments, the physical address transmitted by the host device 110 to the open channel SSD 130 may include information such as a logical unit number, a data plane number, and a physical block number to indicate that the specific input and output channels are to be erased. A specific data block in a specific data plane.

Figure 5 is a schematic diagram of the command queue. The queue 115 can include a Submission Queue 510 and a Completion Queue 530 for temporarily storing the main device instructions and the Completion Element. Each of the delivery queue 510 and the completion queue 530 contains a collection of multiple entries. Each item in the delivery queue 510 stores a main device command, such as an Administration Command, for example, Device Identification, Parameter Setting, and I/O Command. For example, erase, read, write commands, etc., may also be referred to as data access commands.

Each of the completed queues 530 stores a Completion Element associated with a management command or data access command that functions like a confirmation message. The items in the collection are stored in order. The basic principle of the operation of the collection is to add a new item (called an enqueue) from the end position (or called the tail column), and execute the item at the starting position (or called the head, Head). Dequeued), wherein the total number of items listed or listed once may be greater than or equal to one. The first command or message added to the delivery queue 510 or the completion queue 530 will be the first one to be replaced or updated. The master device 110 can write a management or data access command to the delivery queue 510, and the processing unit 133 reads (or refers to the Fetch) the earliest arriving management or data access command from the delivery queue 510 and executes it. After the execution of the management or data access command is completed, the processing unit 133 writes the completion component to the completion queue 530, and the host device 110 can read or extract the completion component to determine the execution result of the management or data access command.

Figure 6 is a flow chart showing the execution steps of a management command or a data access command. The main device 110 generates and writes a management command or a material access command to the delivery queue 510 (step S611). The data access command includes information of the physical address, the physical address includes a source address or a destination address, and the source address or the destination address points to a physical address of the storage unit 139 or the data buffer 120, for example: specific A block, page, or sector address, not a logical block address. Next, the main device 110 sends a Submission Doorbell to the processing unit 133 (step S612) to notify the processing unit 133 about the information that the management command or the data access command has been written in the delivery queue 510, and updates the submission. The value of the end of the array column of column 510. It should be noted that step S611 and step S612 may be referred to as the main device 110 issuing a management command or a data access command to the open channel solid state drive 130. After receiving the delivery of the doorbell (step S631), the processing unit 133 reads the management command or the material access command located at the queue header from the delivery queue 510 (step S632), and indicates the flash control according to the management command or the data access command. The device 135 is configured to complete a specified job (for example, device identification, parameter setting, erasing, data reading, writing, etc.) (step S633).

It should be noted here that step S631 and step S632 may be referred to as an open channel solid state drive 130 to receive a management command or a material access command issued from the host device 110. When the designated job is completed, the processing unit 133 generates and writes the completion component to the completion queue 530 (step S6340) for notifying the master device 110 of the execution status information of the job corresponding to the specific management command or the material access command, and issues The interruption is given to the master device (step S635). After receiving the interruption (step S613), the main apparatus 110 reads the completion element located at the queue head from the completion queue 530 (step S613), and then issues the completion doorbell to the processing unit 133 (step S614). After receiving the completion of the doorbell (S636), the processing unit 133 updates the value of the queue header of the completion queue 530. It should be noted that step S634 and step S635 may be referred to as an open channel solid state hard disk 130 to reply to the result of the host device 110 executing a management command or a data access command. It should be noted here that steps S613 and S614 may be referred to as the result of the master device 110 receiving an execution management command or a data access command from the open channel solid state drive 130.

In steps S612 and S614, the main device 110 can set corresponding registers (Registers) to issue the delivery doorbell and the end doorbell to the processing unit 133.

A data access command can process multiple user data, for example, 64 pens, and the completion component can include an execution reply table of 64 bit lengths. In this execution reply table, each bit represents a user. The execution result of the data, for example: "0" indicates success, and "1" indicates failure. The data access command contains an opcode field that indicates the type of data access command (eg, erase, read, write, etc.). The completion component contains a status field for storing the execution status of the corresponding data access command (eg, success, failure, etc.). In addition, the processing unit 133 can execute the data access command in an out-of-order or priority order. Therefore, the data access command and the completion component both include a command identifier (Command Identifier) for the main device 110 and the processing unit 133. Associate each completion element to a specific data access command.

For example, an idle block needs to be erased to become an active block before writing, and the main device 110 can write an erase command to the delivery queue 510 (step S611) to indicate the open channel solid state drive 130 ( In detail, the processing unit 133) performs an erase job for a particular idle block in a particular input-in channel. The processing unit 133 instructs the flash controller 135 to complete the erase job specified in the storage unit 139 by driving the access interface 137 in response to the erase command (step S633). When the erase job is completed, the processing unit 133 writes the completion component to the completion queue 530 (step S634) to notify the host device 110 of the information that the corresponding erase job has been completed.

For another example, the main device 110 can write a data read command to the delivery queue 510 (step S611) to indicate that the open channel solid state drive 130 is in a specific physical block in a specific data plane in a specific input/output channel. The user profile is read by a specific section of the specific entity page. The processing unit 133 instructs the flash controller 135 to read the user data from the source address specified in the storage unit 139 through the drive access interface 137 in response to the data read command, and save the user data to the data read command. The data buffer 120 (step S633). When the read job is completed, the processing unit 133 writes the completion component to the completion queue 530 (step S634) to notify the host device 110 of the information that the corresponding material reading job has been completed.

For another example, the main device 110 can store the user data to be written in the data buffer 120, and store the write command to the delivery queue 510 (step S611) for instructing the open channel solid state hard disk 130 to write the data buffer. User data of the device 120 to (a specific section of a specific entity page in a specific active block), wherein the write command includes a destination address (physical address) of the (specific section) of the specific entity page and the user Information about the source address (physical address) of the data. The processing unit 133 reads the user profile from the source address of the data buffer 120 in response to the write command, and instructs the flash controller 135 to program the user profile to the write command in the storage unit 139 by driving the access interface 137. The specified destination address (step S633). When the write job is completed, the processing unit 133 writes the completion element to the completion queue 530 (step S634) to notify the host device 110 of the information that the corresponding write job has been completed.

Although FIG. 5 shows only two queues 510 and 530, those skilled in the art can divide the delivery queue 510 into an Administration Submission Queue and an I/O Submission Queue. The management command and the data access command from the host device 110 are temporarily stored, and the completion queue 530 is divided into an Administration Completion Queue and an I/O Completion Queue. To store the completion elements associated with the management commands and data access commands, respectively.

As the number of erasures of the block increases, the data retention capability of the block will gradually weaken, which will cause the user data stored in the entity page to contain more error bits. Since the error correction decoder automatically checks and corrects the error bit in the user profile, the master device 110 cannot know the extent of the error bit rate of a physical page, and thus cannot take an appropriate error prevention mechanism. Finally, when the error correction decoder cannot correct the error bit in the user data, the open channel SSD 130 returns the data read error message to the host device 110, and the host device 110 can only initiate the advanced data correction mechanism, for example, Use Redundant Array of Independent Disks (RAID) to correct user data. However, the execution of the independent hard disk redundant array recovery consumes a large amount of computing resources and time of the main device 110 and the open channel solid state hard disk 130, and the data bandwidth between the main device 110 and the open channel solid state hard disk 130. In order to avoid this drawback, embodiments of the present invention propose an error prevention mechanism to reduce the likelihood or frequency of data reading errors.

In general, the error prevention mechanism of the present invention first obtains the operating parameters of the open channel solid state hard disk 130, and then sets the operating parameters of the open channel solid state hard disk 130, wherein the operating parameters include the error bit threshold, and then cooperate with the active error. The Proactive ECC failure handling method is used to achieve the objectives of the present invention.

Figure 7 is a flow chart of a method for obtaining and setting device parameters of a flash memory according to the present invention. The entire process includes a Device Identification Phase 710 and a Parameter Setting Phase 730. The device identification phase 710 includes steps S711 to S715. The main device 110 writes a device identification command to the delivery queue 510 (step S711). The device identification command is used to request the open channel solid state drive 130 (in detail, the processing unit 133) to provide operational parameters, including: the number of blocks, the number of bad blocks, the delay time, the total number of input and output channels, whether the error correction function is enabled, The maximum capability value of the error correction function (in units of error bits/data length), etc., may include the error bit threshold (in units of error bits/data length). The open channel solid state hard disk 130 receives the device identification command from the delivery queue 510 (step S713). After receiving the device identification command, the open channel solid state hard disk 130 stores the operation parameter to the memory address specified by the device identification command, and then writes the completion element corresponding to the device identification command to the completion queue 530 (step S715).

The Parameter Setting Phase 730 includes steps S731 to S735. The main device 110 can set the operation parameters returned by the open channel solid state hard disk 130, for example, enable the error correction function, and set the value of the error bit threshold, for example: 100, wherein the error bit threshold is less than The maximum ability value of the enabled error correction function, for example: 120. Thereafter, the host device 110 stores the set value again to the parameter setting command, and then the host device 110 writes the parameter setting command to the delivery queue 510 (step S731). The open channel solid state hard disk 130 receives a parameter setting command from the delivery queue 510 (step S733). After the parameter setting command is obtained, the open channel solid state hard disk 130 performs setting of the operating parameter according to the set value of the parameter setting command, for example, enabling the error correction function and setting the error bit threshold to 100. When the set value of the parameter setting command is valid and the setting of the operation parameter is completed accordingly, the open channel solid state hard disk 130 writes the completion element corresponding to the parameter setting command to the completion queue 530 (step S735).

When the error bit threshold is set, the host device 110 can initiate the active error correction failure processing method of the present invention. Figure 8 is a flow diagram of an active error correction failure processing method performed by the host device 110 in accordance with an embodiment of the present invention. The main device 110 outputs a data read command to the open channel solid state drive 130 (step S811). The method for outputting the data read command may refer to steps S611 to S612.

Next, the open channel solid state hard disk 130 reads the user data from the specified source address (physical address) according to the data read command (step S813), and the details of step S813 can refer to steps S631 to S633. After obtaining the user data, the error correction decoder of the Open Channel SSD 130 automatically checks and corrects the error bits of the read user data and calculates the total number of error bits.

Next, the flash controller 135 of the open channel solid state hard disk 130 determines whether the total number of error bits of the read user profile is equal to or greater than the error bit threshold (step S815). If it is (the path of YES in step S815), the bit corresponding to the user data whose total number of error bits is equal to or larger than the error bit threshold is set to "1" in the execution reply table (step S817). Suppose a data read command requires reading 64 user data. Each bit in the execution reply table can respectively indicate whether the total number of error bits of a user data is equal to or greater than the error bit threshold. A value of "0", that is, a security value, indicates that the user data is still stored securely. If it is, the value is "1", that is, an unsafe value, indicating that there may be a risk in the storage of the user data.

Next, the open channel SSD 130 stores the user data to the destination address specified by the data read command (step S819), wherein the destination address is preferably the physical address of the data buffer 120. Next, the open channel solid state hard disk 130 writes the completion element to the completion queue 530 (step S821).

Next, the main device 110 acquires the execution reply table of the completion element from the completion queue 530 (step S823), and then, the main device 110 determines whether or not there is "1" in the execution reply table (step S825), and if otherwise, the execution of the present invention is ended.

Next, the master device 110 reassigns the physical address to the user profile corresponding to the "1" in the reply table (step S827), wherein the reallocated physical address is placed in the active block.

Next, the main device 110 outputs a data write command to the open channel solid state drive 130 to write the user data corresponding to the "1" in the execution reply table to the reallocated physical address (step S829), where the output For the method of writing data to the command, refer to steps S611 to S612.

Figure 9 is a data format diagram of the completed component. Completion component 900 can be a 16-bit tuple message. The 0th to 1st byte record command identification code 930 of the third double block of the completion component 900 is identical to the command identification code of the master device data read command for associating the completion component 900 to the master device. 110 data read command issued. The 0th to 1st double word storage execution reply table 910 of the completion component 900 has a total of 64 bits, and each bit can record the execution result of the user data in step S817, that is, the error bit of a user data. Whether the total is equal to or greater than the error bit threshold. The 17th to 31st bit record status field 920 of the third double word of the component 1100 is completed, and the status field 920 may indicate whether the data read command issued by the host device 110 has been successfully executed.

The value of the error bit threshold can be set using the following formula: Tr = MAX _i x α ; Tr represents the threshold, MAX _i represents the maximum capability value of the specific error correction capability (in units of error bits / data length), eg 120b /1KB, α represents a coefficient between 0 and 1, which can be 0.6≦ α ≦1. For example, if the initial value of α is set to 0.8, the initial setting value of the error bit threshold is 96. When the 64 user data is read, the status field of the completed component is displayed successfully, and all the execution reply forms of the completed component are “0”.

As the number of erasures increases and the storage unit 139 ages, the frequency of warning messages returned by the open channel SSD 130 will also increase. Therefore, the master device 110 can appropriately increase the value of α , for example, changing the value of α to 0.9, that is, changing the error bit threshold to 108 to avoid unnecessary data transfer operations. For example, when reading 64 user data, the status field of the completed component is displayed successfully, but there are 32 "1"s in the execution reply table of the completed component, that is, the value of the number of error bits of 32 user data exceeds 96. At this time, the main device 110 can change the error bit threshold to 108 and save to the parameter setting command, and then issue the parameter setting command to the open channel solid state hard disk 130, so that the open channel solid state hard disk 130 will change the error bit. The threshold is changed to 108, which effectively reduces the number of "1"s in the execution reply table. Thereafter, the master device 110 only needs to reallocate a physical address to the user data of "1". Since the reallocated physical address is located in the active block, and the active block usually has a lower number of erasures, that is, it has better data storage, it can effectively overcome the lack of prior art.

Although the present invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. On the contrary, this invention covers modifications and similar arrangements that are apparent to those skilled in the art. Therefore, the scope of the application claims must be interpreted in the broadest sense to include all obvious modifications and similar arrangements.

Claims (16)

 An active error correction failure processing method includes: obtaining a completion component from a completion queue; determining whether an execution reply table of the completion component includes an unsafe value, and if yes, reallocating a physical address to the unsafe value Corresponding user data; and outputting a data write command to a delivery queue to write the user data to the reallocated physical address.    The method for processing an active error correction failure as described in claim 1, wherein the completion queue and the delivery queue are all located in a master device.    The active error correction failure processing method of claim 2, wherein an open channel solid state hard disk obtains the data write command from the delivery queue, and the open channel solid state hard disk writes the completion component to The completion queue.    The method for processing an active error correction failure as described in claim 3, wherein the physical address is located in the open channel solid state drive.    The method for processing an active error correction failure as described in claim 1 further includes: outputting a data read command to an open channel solid state drive to read the user data.    The method for processing an active error correction failure according to claim 1, wherein the method further comprises: outputting a parameter setting command to an open channel solid state hard disk to set an error bit threshold.    The active error correction failure processing method according to claim 6, wherein the error bit threshold is smaller than a maximum capability value of the error correction function of the open channel solid state hard disk.    The method for processing an active error correction failure according to claim 1, wherein the method further comprises: outputting a device identification command to an open channel solid state hard disk to obtain at least one operating parameter of the open channel solid state hard disk.    An active error correction failure processing method includes: receiving a parameter setting command; setting an error bit threshold according to the parameter setting command; receiving a data reading command; reading the command to a source address according to the data reading command a user data, if an error bit number of the user data is greater than or equal to the error bit threshold, setting a bit corresponding to the user data in an execution reply table to an unsafe value; A completion component including the execution reply table is written to a completion queue.    The method for processing an active error correction failure as described in claim 9 further includes: when executing the data read command, if the number of error bits of the read user data is less than the error bit At the threshold, the bit corresponding to the user profile in the execution reply table is set to a safe value.    The method for processing an active error correction failure according to claim 9 of the patent application scope, the method further comprising: enabling an error correction function according to the parameter setting command.    The method for processing an active error correction failure according to claim 9, wherein the parameter setting command and the data reading command are all received by an open channel solid state hard disk.    The active error correction failure processing method according to claim 12, wherein the error bit threshold is smaller than a maximum capability value of an error correction function of the open channel solid state hard disk.    The method for processing an active error correction failure according to claim 12, wherein the completion queue and the delivery queue are all located in a main device.    The active error correction failure processing method described in claim 9 is wherein the parameter setting command is stored in a delivery queue.    The method for processing an active error correction failure as described in claim 9 further includes: storing the user data to a destination address specified by the data read command.