TW201913625A - Parallel busbar device for LED display screen unit board - Google Patents

Abstract

Disclosed a parallel bus device of LED display unit board, including a highest bit address bus and a lowest bit address bus, a synchronous controller, an address counter and an internal address bus; the lowest bit address bus and the highest bit address bus are connected to two input terminals of the synchronous controller respectively; a output terminal of the synchronous controller and a output terminal of the lowest bit address bus are connected to two input terminals of the address counter; the address counter is connected to a subsequent decoder output circuit through the internal address bus. Therefore, the traditional parallel bus is replaced with the two address buses such that a higher phase difference caused by the excessive number of the address buses and the serial unit boards is decreased, thereby ensuring the accuracy of the output signals and enhancing the controlling effect, while reducing costs.

Description

   Parallel bus bar device for LED display screen unit board   

The invention relates to a bus bar device, and in particular to a parallel bus bar device of an LED display screen unit board.

The beginning of LED display screens everywhere in life is composed of multiple unit boards connected in series. In the specific implementation of parallel bus transmission inside the LED display screen, the output signal is often inaccurate due to the connection of multi-level unit boards. And affect normal work. This is because the unit board requires multiple (for example, five) row address buses, and each row address bus is connected to a relay amplifier circuit. The signal flow between the two adjacent unit boards is amplified by the input signal of the previous unit board through the row address bus and then amplified by the relay amplifier circuit and transmitted to the input end of the next unit board. The unit boards will be connected by 5 relay amplifier circuits. Because the relay amplification will cause a slight phase difference for each input signal, a phase difference will occur between the five line address buses that should be synchronized. When there are more LED unit boards connected in series, the phase difference is accumulated. , The phase difference between the buses of the five rows is bound to be obvious.

As shown in FIG. 1, FIG. 1 is a schematic diagram of a parallel bus architecture of an LED display screen unit board. A [0] ~ A [N-1] are the input signals of the first-level unit board, Y1 [J-1: 0] are the output signals of the first-level unit board display and decoding, B [0] ~ B [N- 1] is the input signal of the second-level unit board, and Y2 [J-1,0] is the output signal of the second-level unit board. The input signals A [0] ~ A [N-1] of the first-level unit board are amplified by the relay amplifier circuit and transmitted to the second-level unit board as input signals of the second-level unit board.

In the prior art, parallel bus transmission between unit boards requires more than three address buses, as shown in Figure 1. Therefore, the obvious phase difference between multiple row address buses will cause a phase difference between the line voltage outputs, thereby The poor control effect of the unit board may even affect the normal operation of the display screen; in addition, multiple row address buses require multiple relay amplifier circuits, resulting in higher overall costs.

How to reduce and reduce the phase difference between the unit boards, thereby improving the control effect and reducing the production cost is a technical problem that needs to be solved in the field.

The object of the present invention is to provide a parallel bus device for an LED display screen unit board, which adopts a structure of two input buses, which enhances the accuracy of the bus output and reduces the overall cost.

In order to solve the above technical problems, the present invention provides a parallel bus device for an LED display screen unit board, which includes a highest bit address bus and a lowest bit address bus, a synchronization controller, an address counter, and an internal address bus. Row; the lowest bit address bus and the highest bit address bus are respectively connected to two inputs of the synchronization controller; the output of the synchronization controller and the lowest bit The output ends of the address bus are respectively connected to two input ends of the address counter; the address counter is connected to a subsequent decoding output circuit through an internal address bus; and the synchronization controller is configured to capture the The edge of the cycle critical point of the output signal of the highest bit address bus and performing a logic zeroing operation on the entire unit board; the address counter is used to determine the cycle according to the output signal of the synchronization controller And calculate the signal of the remaining bit address bus according to the output signal of the lowest bit address bus to obtain a standard parallel bus timing signal.

Preferably, the highest bit address bus and the lowest bit address bus are row input address buses.

Preferably, the decoding output circuit includes an address decoder and a line output bus connected to an output terminal of the address decoder; an input terminal of the address decoder is used as an input terminal of the decoding output circuit; The line output bus is used as an output terminal of the decoding output circuit.

Preferably, the changing edge of the cycle critical point of the signal of the highest bit address bus is a falling edge; the output signal of the lowest bit address bus is also a falling edge at the beginning of each cycle. The address counter performs a counting operation at each change edge of the output signal of the lowest bit address bus.

The invention provides an LED display screen unit board parallel bus device, which simplifies multiple address buses into two address buses of the highest bit and the lowest bit, and captures the signal of the highest bit address bus. Change the edge of the cycle critical point, perform logic clear operation on the entire unit board, and control the start position of the cycle based on the output signal of the synchronous controller, and calculate the remaining address bus based on the input signal of the lowest bit address bus. Signal to get the standard parallel bus timing signal. Since the two parallel buses are replaced with two address buses, the large phase difference caused by the excessive number of address buses and the number of serially connected unit boards is reduced, thereby ensuring the accuracy of the output signal and increasing the control effect. At the same time, the cost is reduced; and the present invention restores the standard parallel bus timing signals, and uses only two address buses to realize the function of the traditional multiple address buses.

1‧‧‧Synchronous controller

2‧‧‧ address counter

3‧‧‧ Internal Address Bus

4‧‧‧ address decoder

5‧‧‧ line output bus

6, 8‧‧‧ falling edge

7‧‧‧ rising edge

A [0] ~ A [N-1] ‧‧‧ Input signal of the first-level unit board

B [0] ~ B [N-1] ‧‧‧ Input signal of second-level unit board

Y1 [J-1: 0] ‧‧‧The first level unit board displays the decoded output signal

Y2 [J-1，0] ‧‧‧The second level unit board displays the decoded output signal

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required in the prior art and the embodiments are briefly introduced below. Obviously, the drawings described in the following are only some of the present invention. For those with ordinary knowledge in the technical field, the embodiment can also obtain other drawings according to these drawings without paying labor.

FIG. 1 is a schematic diagram of a parallel bus structure of an LED display screen unit board; FIG. 2 is a schematic structural diagram of a parallel bus device of the LED display screen unit board provided in the present invention; and FIG. 3 is a parallel bus of the LED display screen unit board provided in the present invention FIG. 4 is a schematic structural diagram of a synchronization controller provided by the present invention; and FIG. 5 is a timing diagram of waveform changes of each node in the synchronization controller provided by the present invention.

Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown. However, the inventive concepts may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, similar numbers always indicate similar elements.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements or signals, etc., these elements or signals should not be limited by these terms. These terms are used to distinguish one element from another, or a signal from another signal. In addition, as used herein, the term "or" may include, as appropriate, all combinations of any one or more of the associated listed items.

The core of the present invention is to provide a parallel bus device for an LED display screen unit board, which adopts a structure of two input buses, enhances the accuracy of the bus output, improves the control effect and reduces the overall cost.

In order to enable those with ordinary knowledge in the technical field to better understand the solution of the present invention, the present invention is further described in detail below with reference to the drawings and specific embodiments.

The invention provides a parallel bus bar device for an LED display screen unit board. Referring to FIG. 2, FIG. 2 is a schematic structural diagram of a parallel bus device for an LED display unit board provided by the present invention. The parallel bus device includes a highest bit address bus A [N-1] and a lowest bit address bus. A [0], synchronization controller 1, address counter 2, and internal address bus 3; among them, the highest bit address bus A [N-1] and the lowest bit address bus A [0] are Row address buses, of course, can also be column address buses.

Among them, N is the standard bus number required for traditional parallel bus transmission.

The lowest bit address bus A [0] and the highest bit address bus A [N-1] are connected to the two inputs of the synchronization controller 1, respectively; the output of the synchronization controller 1 and the least significant bit The output of the address bus A [0] is connected to the two inputs of the address counter 2 respectively; the address counter 2 is connected to the subsequent decoding output circuit through the internal address bus 3; the synchronization controller 1 is used to capture The edge of the highest bit address bus A [N-1] changes the periodic critical point of the output signal, and performs a logic zero operation on the entire unit board. The address counter 2 is used to determine the output signal of the synchronous controller 1. The starting position of the cycle, and the signal of the remaining bit address bus is calculated based on the output signal of the lowest bit address bus A [0] to obtain the standard parallel bus timing signal; the output of the synchronization controller 1 is controlled by synchronization The output of the device 1 is connected to the address counter 2, and the output of the address counter 2 is connected to the decoding output circuit through the internal address bus 3.

Among them, the LED display screen generally uses a sequential display, which is controlled by A [N-1: 0] and outputs Y [0] → Y [1] → Y [2] → ... Y [K-1] → Y [0] → ..., loop output in order. When the highest display line of Y [K-1] is reached, it turns to the first line Y [0], where K is not necessarily 2 ^ N, such as N = 5, as long as K is less than or equal to 32, such as K = 30, that is, 30 lines of output.

It can be understood that N represents the bus width, such as a 5bit bus, the expression method is A [4: 0], where the highest bit is A [4], and the lowest bit is A [0]; corresponding to the maximum controlled The output Y is 32, and Y is represented as Y [31: 0]; that is, Y [0] = “00000”, Y [1] = “00001” ... Y [31] = “11111” . Of course, the above is only a specific implementation manner, and the specific value of N is not limited by the present invention.

At the same time, Y [J-1: 0] is commonly used in LED parallel bus transmission to indicate that there are J lines of bus output; line output bus 5 is generally a voltage source output; where J = 2 ^ N; for example, A [ 4: 0] can control 2 ^ 5 = 32 lines of voltage source output; the number of standard buses required in traditional parallel buses is more than two, including 5 represented by A [4: 0], of course, in the present invention In China, there is no limit on the number of buses that need output control, nor is there a limit on the number of traditional parallel buses.

It should be noted here that the present invention only uses the two address buses of the highest bit address bus A [N-1] and the lowest bit address bus A [0] in the address bus, and The remaining address buses A [1] → A [N-2] in the conventional parallel bus are omitted.

The decoding output circuit includes an address decoder 4 and a line output bus 5 connected to the output of the address decoder 4. The input of the address decoder 4 is used as the input of the decoding output circuit. The line output bus 5 is used as the input. The output of the decode output circuit.

In order to further understand the working principle of the device, reference is made to FIG. 3, which is a timing diagram of input signals of the address bus of the parallel bus device.

As shown in Figure 3, the output of Y [n] is controlled by the bus of A [N-1: 0] and strictly follows n = A [N-1: 0], that is, the value of n in each output line is equal to A [ The binary value of N-1: 0]. When all inputs of A [N-1: 0] are logic "0", it means Y [0] output. When A [N-1: 0] = (K-1) When Y [K-1] is output at the highest value line; after Y [K-1] is output, the next line is output at Y [0]. At this moment A [N-1: 0] = ”00..00”, Therefore, when Y [K-1] → Y [0], A [N-1] will generate a synchronous change edge, as shown in the falling edge 6 shown in Figure 3.

To further explain, the change of the periodic critical point of the signal of the highest bit address bus A [N-1] is generally a falling edge; however, it is not excluded that the change of the periodic critical point is a rising edge. It can be understood that in sequential counting: the counting order from the smallest to the largest, the binary is: 00000 → 00001 → 00010 → ... → 11110 → 11111 → 00000 → ..., this case is the highest bit In order to change on the falling edge, complete a cycle; in the reverse counting: the countdown from the largest to the smallest, the binary is: 11111 → 11110 → 11101 → ... → 00001 → 00000 → 11111 → From low to high, it is the rising edge.

Synchronization controller 1 will capture the falling edge 6 of the highest bit address bus A [N-1] in Figure 3. All bits in the control unit board of the synchronization controller 1 are logic "0", including the synchronization controller. The output of 1 clears address counter 2 and resets internal address bus 3. Please refer to FIG. 4, which is a schematic structural diagram of a synchronization controller provided by the present invention. FIG. 5 is a timing chart of waveform changes of various nodes in a synchronization controller provided by the present invention. These nodes include A [N-1], A [0], ANB, AB0, AX, SYNC_CLR, and ADX.

The address counter 2 determines the starting position of the cycle of the lowest bit address bus A [0] according to the output signal of the synchronization controller 1, and calculates the remaining bits according to the output signal of the lowest bit address bus A [0]. The signal of the address bus.

Among them, due to the parallel bus transmission of the traditional LED display screen unit board, the signals of A [0] to A [N-1] are square waves with a fixed period and a duty cycle of 50%, and every two phases There is a certain regularity between the periods of adjacent signals. The address counter 2 calculates the signals of the remaining bit addresses according to the corresponding rules.

In the first specific embodiment of the present invention, the output signal of the lowest bit address bus A [0] is also a falling edge at the beginning of each cycle, and the address counter 2 converges at the lowest bit address. A count operation is performed for each change edge of the output signal of row A [0]. See falling edge 8 in Figure 3.

It should be noted here that the present invention does not limit the initial change edge of the output signal of the lowest bit address bus A [0], so the change edge may also be a rising edge.

The device for parallel bus of LED display screen unit board provided by the present invention simplifies multiple address buses into two address buses of the highest bit and the lowest bit. By capturing the signals of the highest bit address bus, The edge of the cycle critical point performs logic clear operation on the entire unit board, and controls the starting position of the cycle based on the output signal of the synchronization controller, and calculates the remaining address bus based on the input signal of the lowest bit address bus. Signal to get the standard parallel bus timing signal. Since the two parallel buses are replaced with two address buses, the large phase difference caused by the excessive number of address buses and the number of serially connected unit boards is reduced, thereby ensuring the accuracy of the output signal and increasing the control effect. At the same time, the cost is reduced; and the present invention restores the standard parallel bus timing signals, and uses only two address buses to realize the function of the traditional multiple address buses.

The parallel bus device of the LED display screen unit board provided by the present invention has been described in detail above. Specific embodiments are used herein to explain the principles and implementations of the present invention. The descriptions of the above embodiments are only used to help understand the method of the present invention and its core ideas. It should be noted that for those with ordinary knowledge in the technical field, various improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall into the protection scope of the patent scope of the present application Inside.

Claims (4)

    A parallel bus device for an LED display screen unit board includes a highest bit address bus and a lowest bit address bus, a synchronous controller, a bit counter, and an internal address bus. The bit address bus and the highest bit address bus are connected to two inputs of the synchronous controller; the output of the synchronous controller and the output of the lowest bit address bus are connected to the two The two inputs of the address counter are connected; the address counter is connected to a subsequent decoding output circuit through the internal address bus; the synchronization controller is used to capture the output signal of the highest bit address bus The edge of the cycle critical point changes the logic clear operation of the entire LED display screen unit board; the address counter is used to determine the start position of the cycle according to the output signal of the synchronization controller, and according to the lowest bit The address bus output signal calculates the signals of the remaining bit address buses to obtain a standard parallel bus timing signal.         The device according to claim 1, wherein the highest bit address bus and the lowest bit address bus are row input address buses.         The device according to claim 2, wherein the decoding output circuit includes a bit decoder and a line of output buses connected to the output of the address decoder; the input of the address decoder is used as the decoding output. The input of the circuit; this row of output buses is used as the output of the decoded output circuit.         The device according to claim 3, wherein the edge of the cycle critical point of the signal of the highest bit address bus is a falling edge; the output signal of the lowest bit address bus is at the beginning of each cycle The changing edge is a falling edge, and the address counter performs a counting operation on each changing edge of the output signal of the lowest bit address bus.