TW201909347A - Electronic package and substrate structure and the manufacture thereof - Google Patents

Abstract

The invention provides a substrate structure of an electronic package and a method for fabricating the same, the method comprising forming an opening on a grounding sheet or a power source sheet of a circuit portion to reduce the surface and proportion of the occupied circuit portion, thereby reducing stress concentration to prevent substrate warpage while forming a filling material in the opening to increase coupling capacity.

Description

 Electronic package and substrate structure and preparation method thereof  

The present invention relates to a substrate structure, and more particularly to a substrate structure applied to an electronic package and a method of fabricating the same.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements of semiconductor package miniaturization, Wafer Level Packaging (WLP) technology has been developed.

1A to 1D are schematic cross-sectional views showing the fabrication of a conventional wafer level semiconductor package 1.

As shown in FIG. 1A, a carrier 10 having a thermal release tape 11 is provided. Next, the plurality of semiconductor elements 12 are placed on the thermal release layer 11, and the semiconductor elements 12 have opposite active and uninitiated faces 12a, 12b, wherein the active face 12a has a plurality of electrode pads 120, and The active surface 12a is adhered to the thermal release adhesive layer 11.

As shown in Fig. 1B, an encapsulant 13 is formed on the thermal release layer 11 by lamination to coat the semiconductor element 12.

As shown in FIG. 1C, a baking process is performed to harden the encapsulant 13, and the thermal release adhesive layer 11 loses viscosity after being heated, and the thermal release adhesive layer 11 is removed together. The carrier 10 exposes the active surface 12a of the semiconductor component 12.

As shown in FIG. 1D, a redistribution layer (RDL) process is performed to form a line portion 14 on the encapsulant 13 and the active surface 12a of the semiconductor device 12, so that the line portion 14 is electrically The electrode pad 120 of the semiconductor device 12 is connected to the ground pad 140 and the power supply chip 141 (as shown in FIG. 1D'). Next, an insulating protective layer 15 is formed on the wiring portion 14, and the insulating protective layer 15 exposes a portion of the surface of the wiring portion 14 for bonding the conductive members 16 such as solder bumps.

However, in the manufacturing method of the conventional semiconductor package 1, the grounding piece 140 and the power supply piece 141 are made of a metal material, and the ratio of the area occupied by the semiconductor chip 140 is too large, so that the semiconductor package 1 is easily warped in a subsequent process. The grounding strip 140 (or the power strip 141) cannot be electrically connected to the electrode pads 120 of the semiconductor elements 12, resulting in poor electrical performance, which causes problems such as low yield and poor product reliability.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a substrate structure including: a wiring portion including at least one dielectric layer and at least one wiring layer, wherein the wiring layer includes a grounding strip and/or a power supply sheet And the grounding piece or the power supply sheet is formed with an opening; and a filler is formed in the opening.

The invention also provides a method for fabricating a substrate structure, comprising: providing a circuit portion including at least one dielectric layer and at least one circuit layer, wherein the circuit layer comprises a grounding piece and/or a power supply piece, and the grounding piece or The power sheet is formed with an opening; and a filler is formed in the opening.

In the above substrate structure and method of manufacturing the same, the ground strip has a gap with the power strip.

In the above substrate structure and method of manufacturing the same, the filler is a metal material.

In the foregoing substrate structure and method of manufacturing the same, the filler material is combined with the grounding piece or the power supply sheet.

The present invention further provides an electronic package comprising: a substrate structure as described above; and an electronic component disposed on the circuit portion and electrically connected to the ground plate and the power chip.

The invention further provides a method for manufacturing an electronic package, comprising: providing a substrate structure as described above; and disposing an electronic component on the circuit portion, and electrically connecting the electronic component to the grounding piece and/or the power supply piece.

In the foregoing electronic package and method of manufacturing the same, the package layer for forming the electronic component is formed.

It can be seen from the above that the electronic package and the substrate structure of the present invention and the manufacturing method thereof are designed to reduce the area ratio of the circuit layer occupied by the grounding piece or the power supply piece, thereby reducing stress concentration. Therefore, compared with the prior art, the present invention can avoid the warpage of the electronic package or the substrate structure, so that the grounding piece and the power supply piece can effectively electrically connect the electronic component, thereby improving yield and product reliability.

Moreover, by forming a filler material in the opening to increase the coupling capacitance, it can provide better noise filtering and reduce the output voltage surge of the electronic component, thereby improving yield and product reliability.

1‧‧‧Semiconductor package

10,20‧‧‧Carrier

11‧‧‧heating release layer

12‧‧‧Semiconductor components

12a‧‧‧ active face

12b‧‧‧Inactive surface

120‧‧‧electrode pads

13‧‧‧Package colloid

14,2a‧‧‧Line Department

140,220‧‧‧ Grounding piece

141,221‧‧‧Power film

15,25‧‧‧Insulation protective layer

16,33‧‧‧ conductive elements

2‧‧‧Substrate structure

21‧‧‧Dielectric layer

22‧‧‧Line layer

22a‧‧‧ Conductive layer

222‧‧‧ openings

23‧‧‧ Conductive blind holes

24‧‧‧Filling materials

250‧‧‧ openings

3‧‧‧Electronic package

31‧‧‧Electronic components

310‧‧‧Electrical bumps

32‧‧‧Encapsulation layer

T‧‧‧ gap

1A to 1D are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; FIG. 1D' is a partial top view corresponding to FIG. 1D; and FIGS. 2A to 2E are schematic cross-sectional views showing a method of fabricating the substrate structure of the present invention; 2A' is a partial top view corresponding to FIG. 2A; and 3A to 3B is a schematic cross-sectional view of a subsequent process of FIG. 2D.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention.

2A to 2D are schematic cross-sectional views showing the manufacturing method of the substrate structure 2 of the present invention.

As shown in FIGS. 2A and 2A', a carrier 20 is provided, and an RDL process is performed on the carrier 20 to form a line portion 2a, and the line portion 2a includes at least one dielectric layer 21 and at least A circuit layer 22, wherein the circuit layer 22 includes at least one grounding strip 220 and at least one power strip 221 .

In the present embodiment, the material forming the dielectric layer 21 is, for example, Polyimide (PI), Prepreg (PP), and Benezocy-clobutene (BCB). Or polybenzoxazole (PBO).

Furthermore, the circuit layer 22 can be a single-layer or multi-layer fan out type configuration, and the circuit layer 22 is formed by electroplating (such as by the conductive layer 22a), and the material can be selected to have high ductility. A metal with better conductivity, such as copper. For example, when the circuit layer 22 is a plurality of layers, the wiring layers 22 of the upper and lower layers can be electrically connected by the conductive blind holes 23.

Moreover, the grounding strip 220 and the power strip 221 are separated from each other to form a gap t, and the grounding strip 220 or the power strip 221 has at least one opening 222.

As shown in FIGS. 2B and 2C, a filler 24 is formed on the grounding piece 220 and the power supply sheet 221.

In the present embodiment, the filler 24 is a metal material. For example, a metal material is first formed on the dielectric layer 21 and the circuit layer 22, and the grounding piece 220 and the metal material around the power supply piece 221 are removed, and only the grounding piece 220 is retained (including the opening 222). And a metal material on the power supply sheet 221 (including the opening 222).

In addition, since the filler 24 is made of a metal material, the filler 24 in the gap t is only bonded to the side surface of the grounding strip 220 and the side surface of the power strip 221, and is not formed on the bottom surface of the gap t. The grounding strip 220 is prevented from being short-circuited with the power strip 221 .

As shown in FIG. 2D, the line portion 2a can continue to add at least one dielectric layer 21 and the circuit layer 22 to the filling material 24 as needed; or an insulating protective layer 25 is formed on the line portion 2a.

In the present embodiment, the insulating protective layer 25 is a solder resist layer having a plurality of openings 250 such that portions of the surface of the wiring layer 22 are exposed to the openings 250.

Furthermore, in a subsequent process, as shown in FIG. 2E, the carrier 20 can be removed to form the substrate structure 2. Alternatively, as shown in FIG. 3A, at least one electronic component 31 is disposed on the insulating protective layer 25, and an encapsulation layer 32 is formed on the insulating protective layer 25 to encapsulate the electronic component 31, and then, as in FIG. 3B. As shown, the carrier 20 is removed to form an electronic package 3 and a plurality of conductive elements 33, such as solder materials, can be formed on the circuit layer 22.

Further, the electronic component 31 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 31 is provided on the circuit layer 22 of the openings 250 by a plurality of conductive bumps 310, such as solder materials, and electrically connected to the circuit layer 22; or, the electronic component 31 can be electrically connected to the circuit layer 22; The circuit layer 22 is electrically connected by wire bonding by a plurality of bonding wires (not shown); or the electronic component 31 can directly contact the circuit layer 22. However, the manner in which the electronic component 31 is electrically connected to the wiring layer 22 is not limited to the above.

In addition, the encapsulation layer 32 may be a film for a press-bonding process, an encapsulant for a molding process, or a paste for a printing process, and the material of the encapsulation layer 32 is polyimine (PI), dry film. (dry film), epoxy (epoxy) or packaging material. For example, prior to the molding process, a dispensing operation may be performed to apply the encapsulation layer 32 to the electronic component 31, and the encapsulation layer 32 is pressed to a desired appearance by a mold. Therefore, the material or formation of the encapsulating layer 32 is not particularly limited.

The substrate structure 2 of the present invention is mainly formed by the grounding strip 220 or the power strip 221 having an opening 222 to reduce the proportion of the area occupied thereby, thereby reducing stress concentration, so the substrate is avoided compared to the prior art. The structure 2 is warped in the subsequent process, that is, the electronic package 3 is prevented from being warped, so that the grounding strip 220 and the power strip 221 can be electrically connected to the electronic component 31, thereby improving yield and product reliability.

Moreover, considering that the design of the opening 222 may affect electrical properties, the coupling capacitor is formed in the opening 222 to increase the coupling capacitance, so that the higher coupling capacitance and the lower inductance provide better noise. Filtering and reducing the output voltage surge of the electronic component 31, such as a Power Management IC, can improve yield and product reliability. For example, the coupling capacitance to ground can be increased by 15% and the parasitic inductance can be reduced by 16%.

The present invention provides a substrate structure 2 comprising a line portion 2a and a filler material 24. The circuit portion 2a includes at least one dielectric layer 21 and at least one circuit layer 22, wherein the circuit layer 22 includes at least one grounding strip 220 and/or at least one power strip 221, and the grounding strip 220 or the The power strip 221 has at least one opening 222. The filler 24 is formed in the opening 222.

In an embodiment, the grounding strip 220 and the power strip 221 have a gap t therebetween.

In one embodiment, the filler material 24 is a metal material.

In one embodiment, the filler 24 is combined with the grounding strip 220 or the power strip 221 .

The present invention also provides an electronic package 3, comprising: any one of the foregoing substrate structures 2, and the electronic component 31 disposed on the circuit portion 2a, and the electronic component 31 is electrically connected to the grounding plate 220. And/or the power strip 221 .

In one embodiment, the electronic package 3 further includes an encapsulation layer 32 covering the electronic component 31.

In summary, the electronic package and the substrate structure and the manufacturing method of the present invention are designed such that the grounding piece or the power supply sheet has an opening to reduce the proportion of the area occupied thereby, thereby reducing stress concentration and avoiding the electron. The package or the substrate structure is warped, so that the grounding piece and the power supply piece can be electrically connected to the electronic component, thereby improving yield and product reliability.

Moreover, by forming the filling material in the opening to improve the coupling capacitance, it can provide better noise filtering and reduce the output voltage surge of the electronic component, thereby improving yield and product reliability.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

Claims (14)

 A substrate structure includes: a circuit portion including at least one dielectric layer and at least one circuit layer, wherein the circuit layer includes at least one grounding piece and/or at least one power supply piece, and the grounding piece or the power supply The sheet is formed with at least one opening; and a filler is formed in the opening.    The substrate structure of claim 1, wherein the grounding strip has a gap with the power strip.    The substrate structure according to claim 2, further comprising an insulating protective layer formed on the wiring portion.    The substrate structure according to claim 1, wherein the material forming the filler is a metal.    The substrate structure of claim 1, wherein the filler material is bonded to the grounding piece or the power supply sheet.    An electronic package comprising: a substrate structure according to any one of claims 1 to 5; and an electronic component disposed on the circuit portion and electrically connected to the grounding piece and/or the power supply sheet.    The electronic package as claimed in claim 6 further comprising an encapsulation layer covering the electronic component.    A substrate structure is provided, comprising: providing a circuit portion including at least one dielectric layer and at least one circuit layer, wherein the circuit layer comprises at least one grounding piece and/or at least one power supply piece, and the grounding piece or The power strip is formed with at least one opening; and a filler is formed in the opening.    The method of fabricating a substrate structure according to claim 8, wherein the grounding strip has a gap with the power strip.    The method for fabricating a substrate structure according to claim 9 further comprises forming an insulating protective layer on the line portion.    The method for fabricating a substrate structure according to claim 8, wherein the material for forming the filler is metal.    The method of fabricating a substrate structure according to claim 8, wherein the filler material is combined with the grounding piece or the power supply sheet.    An electronic package manufacturing method comprising: providing a substrate structure according to any one of claims 8 to 12; and disposing an electronic component on the circuit portion, and electrically connecting the electronic component to the ground Tablet and / or the power chip.    The method of manufacturing an electronic package according to claim 13 further comprising forming an encapsulation layer for coating the electronic component.