TW201907497A - Method for fabricating bump structures on chips with panel type process - Google Patents

Abstract

A method for fabricating bump structures on chips with a panel type process is provided. First, a panel type substrate is provided. Semiconductor chips are fixed on the panel type substrate. Each semiconductor chip includes metal pads and a passivation layer exposing the metal pads. At least an electroless plating process is performed to form under bump metallurgy structures on the metal pads. The method simplifies the processes of forming electrical connections for semiconductor chips. The panel type process can effectively increase the yield, and reduce the manufacturing cost.

Description

 Method for fabricating grain bump structure by large plate surface process  

The invention relates to a method for fabricating a semiconductor grain bump structure, in particular to a method for fabricating a ball bottom metal layer by a large plate surface process.

The die package mainly provides functions such as integrated circuit (IC) protection, heat dissipation, and circuit conduction. One of the wafer bump processes is often used in flip chip technology, which is based on the wafer stage, and the under bump metallurgy structure (UBM structure) is formed on the outer metal pad of the wafer. Or a sub-metallurgical layer), and growing bumps on the bottom metal layer, and then dicing the wafer to form a plurality of independent semiconductor dies, after which the semiconductor dies 104 are connected to the package substrate through the bumps. Then, it is encapsulated in a gel.

Please refer to FIG. 1 to FIG. 6 . FIG. 1 is a schematic diagram of a conventional wafer bump manufacturing process, and FIG. 2 to FIG. 6 are schematic cross-sectional views showing a conventional wafer bump manufacturing process. As shown in FIG. 1, the conventional ball-metal layer process is performed at the wafer stage, and the wafer 10 is first provided. As shown in FIG. 2, the wafer 10 has a protective layer 12 and an electrode pad 14.

Next, as shown in FIG. 3, a liquid polyimide layer (PI layer) 15 is uniformly coated on the wafer by spin coating using a coater, and soft baked by a hot plate ( Soft bake) is shaped into a film. Thereafter, a UV exposure process is performed, and the position of the predetermined via hole of the PI layer 15 is masked by the photomask without being exposed to light (the via hole is positioned above the electrode pad 14). Thereafter, a development process is carried out, and the unexposed area is removed by spraying with a developing solution, and titanium (Ti) is deposited by sputtering to serve as the ball bottom metal layer 16.

Then, through a photoresist coating, exposure, and development process, a patterned photoresist 18 is formed (Fig. 4). Thereafter, a thick copper plating layer 20 is deposited by plating in the via holes of the patterned photoresist 18 (Fig. 5). Then, the patterned photoresist 18 is stripped and the unwanted portion of the underlying metal layer 16 is etched away. Then, through photoresist coating, exposure, development, metal plating and photoresist stripping process (not shown), the desired metal bumps 22 are obtained (Fig. 6).

However, the conventional technique for forming the ball-bottom metal layer 16 and the metal bumps 22 on the wafer 10 is wafer size processing, the throughput is limited by the wafer size, and the process is complicated, so that the mass production is poor. Slow output and high processing costs. Therefore, how to develop a process that solves the above various shortcomings of the prior art, in order to improve the yield of the product and reduce the manufacturing cost, is currently a problem to be solved.

In view of the above, the main object of the present invention is to provide a method for fabricating an electroless plating ball-bottom metal layer by a large-plate process, which simplifies the process and reduces the manufacturing cost.

To achieve the above and other objects, the present invention provides a method of fabricating a grain bump structure in a large-plate process. First, a collector carrier and a plurality of semiconductor dies are provided. The semiconductor die has an active face and a back surface opposite the active face. The active surface of the semiconductor die has a plurality of metal electrode pads and an insulating protective layer, and the insulating protective layer exposes the metal electrode pads. Thereafter, the back side of the semiconductor die is fixed to the collective carrier. Next, an electroless plating process is performed to form a ball-bottom metal layer on the metal electrode pad of the semiconductor die. Thereafter, a dielectric layer is formed overlying the collector carrier, the semiconductor die and the ball-bottom metal layer. Thereafter, a plurality of via holes are formed in the dielectric layer, and the via holes expose the bottom metal layer. Next, a plurality of metal bumps are formed in the via holes of the dielectric layer.

Therefore, the method for fabricating a grain bump structure by a large-plate process of the present invention directly forms an electrolessly plated bottom metal layer on a metal electrode pad of a semiconductor die through a convenient and high-efficiency electroless plating process, thereby simplifying the semiconductor The electrical connection processing of the die is easy to implement, and the high cost process such as plating and patterning is reduced, and the manufacturing cost is reduced.

10‧‧‧ wafer

12‧‧‧Protective layer

14‧‧‧electrode pads

15‧‧‧ Polyimine layer

16‧‧‧Bottom metal layer

18‧‧‧ patterned resist

20‧‧‧copper plating

22‧‧‧Metal bumps

30-44‧‧‧Steps

100,200‧‧‧ semiconductor package structure

102‧‧‧Collection carrier

103‧‧‧ film

104‧‧‧Semiconductor grains

104a‧‧‧ active face

104b‧‧‧Back

106‧‧‧Metal electrode pads

106a‧‧‧Bronze metal electrode pads

106b‧‧‧Aluminum metal electrode pad

108‧‧‧Insulation protection layer

108c‧‧‧ openings

110‧‧‧Bottom metal layer

110a‧‧‧ copper metal layer

110c‧‧‧ Nickel metal layer

110d‧‧‧First gold metal layer

110e‧‧‧palladium metal layer

110f‧‧‧second gold metal layer

120‧‧‧ dielectric layer

120c‧‧‧through hole

130‧‧‧ patterned dry film

130c‧‧‧Dry film opening

150‧‧‧Metal bumps

160‧‧‧Line redistribution

170‧‧‧The line is redistributed

180‧‧‧External solder balls

202‧‧‧Metal plates

1 is a schematic view of a conventional wafer bump manufacturing process; FIGS. 2 to 6 are schematic cross-sectional views of a conventional wafer bump manufacturing process; and FIG. 7 is a schematic view of the present invention for making a ball bottom by a large-plate process Schematic diagram of a method for forming a metal layer and a metal bump; FIG. 8A to FIG. 12 are schematic views showing a method for fabricating a ball metal layer and a metal bump in a large-plate process according to the first embodiment of the present invention, wherein FIG. 8B is a schematic view The schematic view of the top view of FIG. 8A, the rest is a schematic cross-sectional view; and FIGS. 13 to 16 are schematic cross-sectional views of the bottom metal layer of the second to fifth embodiments of the present invention; and FIGS. 17 to 18 The figure shows a schematic cross-sectional view of a semiconductor electrical connection structure fabricated in the sixth to seventh embodiments of the present invention.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention. The manufacture and use of the preferred embodiments of the invention are described in detail below. It must be understood that the present invention provides a number of applicable innovative concepts that can be widely implemented under specific background art. This particular embodiment is shown by way of example only, and is not intended to limit the scope of the invention.

Please refer to FIG. 7 to FIG. 12 . FIG. 7 is a schematic flow chart of a method for fabricating a ball metal layer and a metal bump in a large-plate process according to the present invention, and FIG. 8A to FIG. 12 illustrate the present invention. In the first embodiment of the invention, a cross-sectional view of the electroless plating ball metal layer and the metal bump is produced by a large-plate process, and FIG. 8B is a top plan view of FIG. 8A. As shown in step 30, FIG. 8A and FIG. 8B of FIG. 7, first, the carrier substrate 102 and the plurality of semiconductor dies 104 are provided.

The collective carrier 102 can be a metal plate or an insulating plate. The metal plate may be made of metal copper; the insulating plate may be epoxy resin, polyimide, cyanate ester, carbon fiber or mixed glass fiber and epoxy resin. Composition. The semiconductor die 104 can be an active or passive semiconductor die, which is a separate die that is formed by dividing various passive components, active components, and bonded structures on the entire wafer. The semiconductor die 104 is, for example, a capacitor die, a memory die, or a central processing unit (CPU) die. The semiconductor die 104 has an active face 104a and a back face 104b opposite the active face 104a. The active face 104a of the semiconductor die 104 has a plurality of metal electrode pads 106, such as aluminum metal electrode pads or copper metal electrode pads. An insulating protective layer 108 is previously formed on the active surface 104a of the semiconductor die 104 to cover the metal electrode pad 106. The material of the insulating protective layer 108 may be selected from benzo-cyclo-butene (BCB), poly-liminamide or other dielectric materials.

The insulating protective layer 108 is subjected to opening processing by means of plasma etching, reactive ion etching (RIE) or laser. Thereby, the opening 108c is formed in the insulating protective layer 108. The opening 108c corresponds to the position of the metal electrode pad 106 to expose the metal electrode pad 106.

Thereafter, as shown in step 32, FIG. 8A and FIG. 8B of FIG. 7, the back surface 104b of the semiconductor die 104 is fixed to the collective carrier 102. For example, the adhesive film 103 is attached to the upper surface of the collective carrier 102, and the semiconductor die 104 is placed thereon.

Thereafter, as shown in steps 34 and 9 of FIG. 7, an electroless plating process is performed to form a self-aligned ball-metal layer 110 on the metal electrode pad 106 of the semiconductor die 104, whereby the semiconductor die 104 is formed. The electrical connection processing process is completed.

Electroless plating is an auto-catalytic chemical treatment technique that forms a deposited metal layer on a metallized surface of an object to be plated. Electroless plating exposes or impregnates the object to be plated in a chemical solution. The chemical solution includes a reducing agent and a deposited metal material, and the reducing agent can react with the deposited metal material and the metal ion-coated metal ions to form a deposited metal layer on the exposed portion of the metal plating. Accordingly, electroless plating can form the ball-bottom metal layer 110 by self-alignment.

The ball bottom metal layer 110 serves as an interface between the metal electrode pad 106 and the subsequent bumps, and has characteristics such as low stress, good adhesion, strong corrosion resistance, and good copper-tin soldering properties. In the present embodiment, the bottom metal layer 110 is deposited by electroless plating on copper, nickel, palladium, gold or a combination thereof on the metal electrode pad 106. Since the metal electrode pad 106 is also made of the same or similar metal material, The electroplated bottom metal layer 110 can be directly formed and strongly bonded to the metal electrode pad 106, and the underlying metal electrode pad 106 can be protected by the ball bottom metal layer 110 to prevent the metal electrode pad 106 from being contaminated. In other embodiments of the invention, the bottom metal layer 110 may be made of copper, aluminum, nickel, titanium, tin, palladium, palladium, combinations thereof, or other similar elements.

Then, as shown in step 36, step 38 and FIG. 10 of FIG. 7, step 36 forms a dielectric layer 120 on the active surface 104a of the semiconductor die 104 and on the carrier substrate 102, covering the collector carrier 102 and the semiconductor crystal. The particles 104 are on the bottom metal layer 110. The dielectric layer 120 can be filled on the surface of the collective carrier 102 between the semiconductor dies 104 to increase the protection of the semiconductor die 104 to further fix the semiconductor die 104 to the collective carrier 102.

Step 38 forms a plurality of via holes 120c in the dielectric layer 120. The via hole 120c exposes the ball bottom metal layer 110. A via hole 120c is formed on the surface of the dielectric layer 120 by a process such as laser drilling or exposure development to expose the ball-bottom metal layer 110 on the semiconductor die 104.

In this embodiment, the dielectric layer 120 may be a sealing material layer, such as an epoxy molding compound (EMC, also referred to as a solid packaging material), and the step of forming the via hole 120c includes sealing the sealing material. The material layer is subjected to a laser drilling process. The step of forming the layer of the sealing material may include placing the encapsulant into the mold, heating, and then filling the cavity where the semiconductor die 104 and the assembly carrier 102 have been placed through the runner and the gate to complete the compression molding process, and then proceeding. The baking process is to cure the layer of the sealing material.

In other embodiments, the dielectric layer 120 can be a photoresist layer, and the step of forming the via holes 120c includes performing an exposure process and a development process on the photoresist layer.

As shown in step 40 and FIG. 11 of FIG. 7, a patterned dry film 130 is formed on the dielectric layer 120. The patterned dry film 130 includes a plurality of dry film openings 130c to expose the via holes 120c, the ball bottom metal layer 110, and a portion of the dielectric layer 120.

As shown in step 42, step 44 and FIG. 12 of FIG. 7, step 42 forms a metal bump 150 in the via hole 120c of the dielectric layer 120 and the dry film opening 130c. Specifically, the step of forming the metal bumps 150 may include performing a copper metal plating process to form a metal copper layer (not shown) on the dielectric layer 120 and the patterned dry film 130. Next, the patterned dry film 130 is removed, and excess metal copper is etched away, thereby forming metal bumps 150.

Step 44 forms a redistribution layer (RDL) 160 on the metal bump 150, wherein the circuit redistribution layer 160 is electrically connected to the metal electrode of the semiconductor die 104 through the metal bump 150 and the ball bottom metal layer 110. The pad 106 allows the semiconductor die 104 to be electrically extended outward therefrom.

Since the prior art is limited by the size of the wafer, the mass production is not good. In contrast, since the present invention employs a large-plate process, a large number of semiconductor dies 104 can be fixed to the collective carrier 102 for batch processing, so that the batch yield of the present invention can be a multiple of the prior art and greatly improved. Process efficiency.

Moreover, the present invention uses an electroless plating process to form the ball-bottom metal layer 110 as compared to conventional techniques to reduce the overall manufacturing cost and lead time required to form the metal bumps 150. The present invention directly forms the self-aligned bottom metal layer 110 by an electroless plating process, thereby eliminating the need to pattern the photoresist layer to provide pattern alignment for this step. Since the self-aligned ball-metal layer 110 is directly formed on the metal electrode pad 106 of the semiconductor die 104 by the electroless plating method, the electrical connection processing process of the semiconductor die 104 can be simplified and the implementation is easy and reduced. High-cost processes such as electroplating and patterning have the effect of reducing manufacturing costs.

The structure of the bottom metal layer 110 is described in detail. The bottom metal layer 110 of the present invention may be composed of a single layer of metal or a plurality of layers of metal, for example, an adhesion layer that can increase the bonding of the metal to the metal electrode pad 106, and avoids metal. An oxidized barrier layer, and a wetting layer that increases the adhesion of the copper-tin bump. The electroless plating process can utilize an electroless plating process combination such as electroless nickel-electroless palladium-immersion gold (ENEPIG) or electroless nickel-immersion gold (ENIG). Please refer to FIG. 13 to FIG. 16. FIG. 13 to FIG. 16 are schematic cross-sectional views showing the bottom metal layer of the second to fifth embodiments of the present invention.

As shown in FIG. 13, the electroless plating process of the second embodiment includes a copper electroless plating process, the metal electrode pad is a copper metal electrode pad 106a, and the ball bottom metal layer is a copper metal layer 110a, and the bottom-up order is arranged. They are a copper metal electrode pad 106a, a copper metal layer 110a, and a metal bump 150, respectively.

As shown in FIG. 14, the electroless plating process of the third embodiment includes a copper electroless plating process, the metal electrode pad is an aluminum metal electrode pad 106b, and the ball bottom metal layer 110 is a copper metal layer 110a, which is arranged from bottom to top. The order is an aluminum metal electrode pad 106b, a copper metal layer 110a, and a metal bump 150, respectively.

As shown in FIG. 15, the electroless plating process of the fourth embodiment includes a nickel electroless plating process and a copper electroless plating process, the metal electrode pad is an aluminum metal electrode pad 106b, and the ball bottom metal layer 110 includes a nickel metal layer 110c and a copper metal. The bottom layer up order of the layers 110a is an aluminum metal electrode pad 106b, a nickel metal layer 110c, a copper metal layer 110a, and a metal bump 150, respectively.

As shown in FIG. 16, the electroless plating process of the fifth embodiment includes a first gold electroless plating process, a palladium electroless plating process, and a second gold electroless plating process, and the metal electrode pad is an aluminum metal electrode pad 106b, and a ball bottom metal layer. 110 includes a first gold metal layer 110d, a palladium metal layer 110e, and a second gold metal layer 110f. The bottom-up arrangement order is an aluminum metal electrode pad 106b, a first gold metal layer 110d, a palladium metal layer 110e, and a second A gold metal layer 110f and a metal bump 150.

Subsequently, the present invention can also perform a line build-up process on the dielectric layer 120 and the line redistribution layer 160 according to actual electrical design requirements, and form an external solder ball to form a semiconductor package structure having a multilayer line. 17 to 18 are schematic cross-sectional views showing a semiconductor electrical connection structure fabricated in the sixth to seventh embodiments of the present invention. As shown in FIGS. 17 and 18, the present invention further performs a line build-up process on the dielectric layer 120 and the line redistribution layer 160 to form a line redistribution layer 170 and form an outer solder ball 180 to form a fan. A semiconductor package structure 100, 200 of a fan-out. The sixth embodiment removes the collective carrier 102 and is an independent semiconductor package structure 100. The semiconductor package structure 200 of the seventh embodiment includes the semiconductor die 104 carried by the metal plate 202.

In summary, the present invention directly forms a self-aligned ball-bottom metal layer on the metal electrode pad of the semiconductor die by electroless plating, thereby simplifying the electrical connection process of the semiconductor die and being easy to implement, reducing plating and patterning. The high cost process has the effect of reducing manufacturing costs. In addition, since the present invention employs a large-plate process, the process throughput and efficiency can be greatly improved.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

Claims (10)

 A method for fabricating a die bump structure by a large-plate process includes: providing a collective carrier and a plurality of semiconductor dies, each of the semiconductor dies having an active surface and a back surface opposite to the active surface The active surface of the semiconductor die has a plurality of metal electrode pads and an insulating protective layer, and the insulating protective layer exposes the metal electrode pads; and the back surfaces of the semiconductor dies are fixed on the collective carrier Performing an electroless plating process to form a ball-bottom metal layer on the metal electrode pads of the semiconductor dies; forming a dielectric layer covering the slab, the semiconductor dies and the spheroidal metal a plurality of via holes are formed in the dielectric layer, the via holes exposing the bottom metal layer; and a plurality of metal bumps are formed in the via holes of the dielectric layer.    The method of claim 1, wherein the electroless plating process comprises a copper electroless plating process, wherein each of the metal electrode pads is a copper metal electrode pad, and the ball bottom metal layer is a copper metal layer, The upper arrangement order is the copper metal electrode pad, the copper metal layer and each of the metal bumps.    The method of claim 1, wherein the electroless plating process comprises a copper electroless plating process, wherein each of the metal electrode pads is an aluminum metal electrode pad, and the ball bottom metal layer is a copper metal layer, The upper arrangement order is the aluminum metal electrode pad, the copper metal layer and each of the metal bumps.    The method of claim 1, wherein the electroless plating process comprises a nickel electroless plating process and a copper electroless plating process, wherein each of the metal electrode pads is an aluminum metal electrode pad, and the ball bottom metal layer comprises a nickel metal. The layer and the copper metal layer are arranged in order from bottom to top for each of the aluminum metal electrode pads, the nickel metal layer, the copper metal layer and each of the metal bumps.    The method of claim 1, wherein the electroless plating process comprises a first gold electroless plating process, a palladium electroless plating process and a second gold electroless plating process, wherein each of the metal electrode pads is an aluminum metal electrode pad. The bottom metal layer includes a first gold metal layer, a palladium metal layer and a second gold metal layer, and the bottom-up order is respectively the aluminum metal electrode pads, the first gold metal layer, and the a palladium metal layer, the second gold metal layer and each of the metal bumps.    The method of claim 1, wherein the dielectric layer is a layer of a glue material, and the step of forming the via holes comprises performing a laser drilling process on the layer of the sealant material.    The method of claim 1, wherein the dielectric layer is a photoresist layer, and the step of forming the via holes comprises performing an exposure process and a development process on the photoresist layer.    The method of claim 1, further comprising forming a patterned dry film on the dielectric layer, the patterned dry film comprising a plurality of dry film openings to expose the via holes, the bottom metal layer And a portion of the dielectric layer.    The method of claim 8, wherein the step of forming the metal bumps comprises forming the metal bumps in the via holes and the dry film openings.    The method of claim 1, further comprising forming a line redistribution layer on the metal bumps, wherein the circuit redistribution layer is electrically connected to the ball metal layer through the metal bumps Such metal electrode pads of semiconductor dies.