TW201907383A - Display device and driving method - Google Patents

Abstract

A display device includes a first shift register circuit and a second pull down circuit. The first shift register circuit is disposed on a first side of the display device and includes a first pull up circuit, a first pull down circuit, a first pull down control circuit and a first main pull down circuit. The first pull up circuit is configured to receive a first clock signal and to output a first transmitting scan signal according to a first control signal. The second pull down circuit is disposed on a second side of the display device and coupled to the first pull up circuit through a first scan line. The second side is a counter side of the first side. The first pull up circuit outputs the first transmitting scan signal to the second pull down circuit through the first scan line. The second pull down circuit is configured to receive the first clock signal and to adjust a falling edge of a first receiving signal on the second side according to the second control signal.

Description

   Display device and driving method   

The present disclosure is a display technology, and more particularly, to a display device and a driving method.

Generally speaking, the scanning signal is generated by a circuit disposed on one side of the display device and then transmitted to the other side to drive the pixel array. However, during the transmission through the scanning line, the waveform of the scanning signal may be distorted, that is, the scanning signal waveform transmitted to the other side may be different from the scanning signal waveform of the local side, so it is difficult to improve the display quality.

One aspect of the present disclosure is to provide a display device including a first shift register circuit and a second pull-down circuit. The first shift register circuit is disposed on the first side of the display device and includes a first pull-up circuit, a first pull-down circuit, a first pull-down control circuit, and a first main pull-down circuit. The first main pull-down circuit is electrically connected to the first pull-up circuit. The first pull-up circuit is used to receive a first clock signal and output a first transmission scan signal according to the first control signal. The first pull-down control circuit is used to control the first pull-down circuit to output the first transmission scanning signal to the first working voltage. The first main pull-down circuit is used to output a first control signal to a first operating voltage. The display device further includes a second pull-down circuit, which is disposed on the second side of the display device and is coupled to the first pull-up circuit via the first scan line. The second side is the opposite side of the first side. The first shift register circuit and the second pull-down circuit are disposed on both sides of the display area. The first pull-up circuit outputs the first transmission scan signal to the second pull-down circuit via the first scan line. The second pull-down circuit is further configured to receive the first clock signal and adjust the falling edge of the first receive scan signal on the second side according to the second control signal.

Another aspect of the present disclosure is to provide a driving method for a display device. The display device includes a first shift register circuit and a first pull-down circuit. The first shift register circuit is disposed on the first side of the display device, and the first pull-down circuit is disposed on the second side of the display device. The driving method includes the following steps. The first shift register circuit receives a first clock signal and outputs a first transmission scan signal according to the first control signal. The first pull-down circuit receives the first clock signal and adjusts the falling edge of the first receive scan signal on the second side according to the second control signal.

In summary, the pull-down circuit of the present disclosure can effectively improve the distortion phenomenon of the falling edge of the received scanning signal generated by transmitting to the other side of the display device through the scanning line. Therefore, the falling edges of the adjusted received scanning signals overlap and are consistent, and thus the display quality of the display device is improved.

The above description will be described in detail in the following embodiments, and the technical solution of the present disclosure will be further explained.

100‧‧‧ display device

110, 120‧‧‧Shift register unit

111, 113‧‧‧ shift register circuit

112, 114‧‧‧ pull-down circuit

115‧‧‧display area

1111, 1131, 1211‧‧‧‧Gate driving array circuit

11, 21, 31, 41‧‧‧ first end

12, 22, 32, 42‧‧‧ second end

13, 23, 33, 43‧‧‧ Control terminal

T1, T2, T3, T4, T11, T12, T32, T33, T35, T36, T41, T42, T43, T44, T51, T52, T53, T54, T55, T56‧‧‧Transistors

Ln, Ln + 1‧‧‧‧scan line

HC (n), HC (n + 1) ‧‧‧clock signal

Gn_1, Gn + 1_2‧‧‧Transmit scanning signal

Gn_2, Gn + 1_1, Gn_2’‧‧‧ receive scan signal

Qn_1, Qn + 1_2, Qn + 2_1‧‧‧Control signal

E1‧‧‧First side

E2‧‧‧Second side

1112‧‧‧ Pull-up circuit

211‧‧‧ pull-down circuit

212‧‧‧pull-down control circuit

213‧‧‧Main pull-down circuit

214‧‧‧Pull-up control circuit

VSS, VSSQ, VSSG, VGH‧‧‧ working voltage

Pn, Qn‧‧‧node

LC1, Qn-2, Qn + 4, Kn + 1, STn + 4, ST, STn‧‧‧

t1, t2‧‧‧‧time

V1‧‧‧ first place

V2‧‧‧ second place

In order to make the above and other objects, features, advantages, and embodiments of the present disclosure more comprehensible, the accompanying drawings are described as follows: FIG. 1 is a schematic diagram illustrating a display device according to an embodiment of the present disclosure; Figures 2 and 2B are schematic diagrams illustrating shift register circuits of some embodiments of the present disclosure; Figure 3 is a schematic diagram illustrating signal timing of an embodiment of the present disclosure; and Figures 4A and 4B are illustrative of the first aspect of the present disclosure. Schematic diagram of transmitting scanning signals and receiving scanning signals in the embodiment.

The following disclosure provides many different embodiments or illustrations to implement the features of the invention. Numerous symbols and / or letters may be repeatedly referenced in the present disclosure in different instances, and these repetitions are for simplification and explanation, and do not themselves specify the relationship between different embodiments and / or configurations in the following discussion.

In the embodiments and the scope of patent application, unless the article has a special limitation on the article, "a" and "the" may refer to a single or plural. It will be further understood that the terms "including", "including", "having" and similar terms used in this document indicate the features, regions, integers, steps, operations, elements and / or components recorded therein, but do not exclude It describes or additionally one or more of its other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

As used herein, "coupled" or "connected" can mean that two or more components make direct physical or electrical contact with each other, or indirectly make physical or electrical contact with each other, and "coupled" or "connected" "Connected" may also mean that two or more elements operate or act on each other. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no additional elements present.

About "about", "approximately" or "approximately about" as used herein is generally an error or range of the index value within about 20%, preferably within about 10%, and more preferably It is within about five percent. Unless explicitly stated in the text, the numerical values mentioned are regarded as approximate values, that is, errors or ranges indicated by "about", "about" or "approximately about".

Please refer to Figure 1. FIG. 1 is a schematic diagram illustrating a display device 100 according to an embodiment of the present disclosure. The display device 100 includes a plurality of identical shift register units 110 and 120. The following description uses the shift register unit 110 as an example. The shift register unit 110 includes shift register circuits 111 and 113 and pull-down circuits 112 and 114. The shift register circuit 111 and the pull-down circuit 114 are disposed on the first side E1 of the display device 100, the shift register circuit 113 and the pull-down circuit 112 are disposed on the second side E2 of the display device 100, and the second side E2 is the first Opposite side of one side E1. The shift register circuit 111 and the pull-down circuit 112 are disposed on both sides of the display area 115. The shift register circuit 111 on the first side E1 is connected to the pull-down circuit 112 on the second side E2 through the scan line Ln. Similarly, the shift register circuit 113 and the pull-down circuit 114 are disposed on both sides of the display area 115. The shift register circuit 113 on the second side E2 is connected to the first register E1 through the scan line Ln + 1. Pull-down circuit 114.

Please refer to Figure 2A. FIG. 2A is a schematic diagram illustrating a shift register circuit 111 according to an embodiment of the present disclosure. The shift register circuit 111 includes a pull-up circuit 1112 and a gate drive array circuit 1111. The gate drive array circuit 1111 includes a pull-down circuit 211, a pull-down control circuit 212, a main pull-down circuit 213, and a pull-up control circuit 214. The pull-up control circuit 214 is electrically connected to the pull-up circuit 1112, the pull-down control circuit 212 is electrically connected to the pull-down circuit 211, and the main pull-down circuit 213 is electrically connected to the pull-up circuit 1112.

Specifically, in an embodiment, the shift register circuit 111 in FIG. 2A can be implemented in the manner shown in FIG. 2B, but the disclosure is not limited thereto. The pull-down circuit 211 includes transistors T32, T33, T35, T36, T42, and T43. The transistors T32 and T33 are coupled to the operating voltage VSSG. The transistors T35, T36, T42, and T43 are coupled to the operating voltage VSSQ. The voltages VSSQ can be the same or different. The pull-down control circuit 212 includes transistors T51, T52, T53, T54, T55, and T56. The transistor T53 and the transistor T54 are coupled to the node Pn. The main pull-down circuit 213 includes transistors T41 and T44. The pull-up control circuit 214 includes transistors T11 and T12, and the transistor T12 is coupled to the node Qn.

In the pull-down control circuit 212, the transistor T51 operates according to the signal LC1, the transistors T55 and T56 operate according to the signal Qn-2, and the transistors T52 and T54 operate according to the control signal Qn_1. In the pull-down circuit 211, the transistors T42, T32, and T35 operate according to the potential of the node Pn, and the transistors T43, T33, and T36 operate according to the signal Kn + 1. In the main pull-down circuit 213, the transistor T41 operates according to the signal STn + 4, and the transistor T44 operates according to the signal ST. In the pull-up control circuit 214, the transistor T12 receives the clock signal HC (n) and outputs a signal STn according to the potential operation of the node Qn. The transistor T11 receives the operating voltage VGH and outputs Qn + 4 according to the signal STn operation.

In operation, the pull-up control circuit 214 is used to generate the control signal Qn_1, and the pull-up circuit 1112 is used to receive the clock signal HC (n) and output the transmission scan signal Gn_1 to the scan line Ln according to the control signal Qn_1. The pull-down control circuit 212 is used to control the pull-down circuit 211 to output the transmission scan signal Gn_1 to the operating voltage VSS. The main pull-down circuit 213 is used to output the control signal Qn_1 to the operating voltage VSS. The transmission scan signal Gn_1 is transmitted from the first side E1 through the scan line Ln to the second side E2, and a waveform distortion phenomenon may occur, resulting in a waveform of the reception scan signal Gn_2 different from the waveform of the transmission scan signal Gn_1 generated by the shift register circuit 111. The pull-down circuit 112 is used to receive the clock signal HC (n) and adjust the falling edge of the receiving scanning signal Gn_2 on the second side E2 according to the control signal Qn + 1_2.

In one embodiment, the pull-up circuit 1112 includes a transistor T1. The transistor T1 has a first terminal 11, a second terminal 12 and a control terminal 13. The first terminal 11 of the transistor T1 is used to receive the clock signal HC (n), the control terminal 13 of the transistor T1 is used to receive the control signal Qn_1 generated by the pull-up control circuit 214, and the second terminal 12 of the transistor T1 is used to receive Output transmission scan signal Gn_1.

In one embodiment, the pull-down circuit 112 includes a transistor T2. The transistor T2 has a first terminal 21, a second terminal 22 and a control terminal 23. The first terminal 21 of the transistor T2 is used to receive the clock signal HC (n), the control terminal 23 of the transistor T2 is used to receive the control signal Qn + 1_2, and the second terminal 22 of the transistor T2 is coupled to the electricity via the scanning line Ln. The second end 12 of the crystal T1 is used to adjust the falling edge of the receiving scanning signal Gn_2 on the second side E2.

It should be noted that the gate driving array circuit 1131 of the shift register circuit 113 generates a control signal Qn + 1_2 to control the turn-on time of the transistor T2 of the pull-down circuit 112. In one embodiment, when the transistor T1 finishes transmitting the transmission scanning signal Gn_1 on the first side E1 and is turned off according to the control signal Qn_1, the transistor T2 is kept on according to the control signal Qn + 1_2 to adjust the receiving scanning signal on the second side E2. The falling edge of Gn_2. For example, the transistor T2 adjusts the falling edge of the receiving scanning signal Gn_2 on the second side E2 to overlap the falling edge of the transmitting scanning signal Gn_1 on the first side E1. Specifically, through the size design of the transistor T2 and the optimization of the bus line, the falling edge of the transmission scanning signal Gn_1 and the falling edge of the receiving scanning signal Gn_2 can be adjusted to be consistent.

In an embodiment, as shown in FIG. 3, the control signal Qn + 1_2 is behind the control signal Qn_1. Within time t1, the control signal Qn_1 rises from the first level V1 to the second level V2 (the second level V2 is higher than the first level V1). At this time, the transistor T1 outputs a transmission scanning signal Gn_1, that is, The rising edge of the transmission scan signal Gn_1 is within the time t1. The control signal Qn_2 is still at the first level V1 within time t1. Therefore, the small potential difference Vgs between the gate and the source of the transistor T2 causes the receiving scanning signal Gn_2 of the second terminal 22 to rise slowly.

On the other hand, within time t2, the control signal Qn_1 drops from the second level V2 to the first level V1. At this time, the transistor T1 finishes outputting the transmission scanning signal Gn_1, that is, the falling edge of the transmission scanning signal Gn_1 is at time. Within t2. The control signal Qn_2 is still at the second level V2 within time t2. Therefore, the large potential difference Vgs between the gate and the source of the transistor T2 keeps the transistor T2 on, causing the receiving scanning signal Gn_2 of the second terminal 22 to be quickly pulled down. . In this way, within time t2, the falling edge of the receiving scanning signal Gn_2 on the second side E2 overlaps the falling edge of the transmitting scanning signal Gn_1 on the first side E1. Specifically, compared to the received scanning signal Gn_2 'adjusted without using the pull-down circuit 112 (as shown in FIG. 4A), the adjusted received scanning signal Gn_2 of the transistor T2 of the pull-down circuit 112 in this disclosure (as shown in FIG. 4B) (Shown in the figure) the falling edge of the transmission scanning signal Gn_1 clearly overlaps and is consistent.

In this way, within time t2, the pull-down circuit 112 maintained on according to the control signal Qn + 1_2 can effectively improve the distortion of the falling edge of the receive scanning signal Gn_2 on the second side E2.

The internal registers and connection methods of the shift register circuit 113 and the shift register circuit 111 of FIG. 2A are similar, and will not be repeated here. In the operation of the shift register circuit 113 and the pull-down circuit 114, the pull-up control circuit is used to generate the control signal Qn + 1_2, and the pull-up circuit is used to receive the clock signal HC (n + 1) and according to the control signal Qn + The 1_2 output transmits the scan signal Gn + 1_2 to the scan line Ln + 1. The pull-down control circuit is used to control the pull-down circuit to output the transmission scan signal Gn + 1_2 to the operating voltage VSS. The main pull-down circuit is used to output the control signal Qn + 1_2 to the operating voltage VSS. The transmission scan signal Gn + 1_2 is transmitted from the second side E2 to the first side E1 via the scan line Ln + 1. Waveform distortion may occur, resulting in the waveform of the reception scan signal Gn + 1_1 being different from the transmission generated by the shift register circuit 113. Scan signal Gn + 1_2 waveform. The pull-down circuit 114 is used to receive the clock signal HC (n + 1) and adjust the falling edge of the reception scan signal Gn + 1_1 of the first side E1 according to the control signal Qn + 2_1.

Similarly, in an embodiment, the pull-up circuit of the shift register circuit 113 includes the transistor T3. The transistor T3 has a first terminal 31, a second terminal 32 and a control terminal 33. The first terminal 31 of the transistor T3 is used to receive the clock signal HC (n + 1), and the control terminal 33 of the transistor T3 is used to receive the control signal Qn + 1_2 generated by the pull-up control circuit of the shift register circuit 113. The second terminal 32 of the transistor T3 is used to output a transmission scanning signal Gn + 1_2.

In one embodiment, the pull-down circuit 114 includes a transistor T4. The transistor T4 has a first terminal 41, a second terminal 42 and a control terminal 43. The first terminal 41 of the transistor T4 is used to receive the clock signal HC (n + 1), the control terminal 43 of the transistor T4 is used to receive the control signal Qn + 2_1, and the second terminal 42 of the transistor T4 is passed through the scan line Ln + 1 is coupled to the second terminal 32 of the transistor T3 and is used to adjust the falling edge of the receiving scanning signal Gn + 1_1 on the first side E1.

It should be noted that the gate driving array circuit 1211 of the shift register unit 120 generates a control signal Qn + 2_1 to control the turn-on time of the transistor T4 of the pull-down circuit 114. In one embodiment, when the transistor T3 finishes outputting the transmission scanning signal Gn + 1_2 on the second side E2 and is turned off according to the control signal Qn + 1_2, the transistor T4 is kept on according to the control signal Qn + 2_1 to adjust the first side E1. The falling edge of the received scan signal Gn + 1_1. For example, the transistor T4 adjusts the falling edge of the receiving scanning signal Gn + 1_1 on the first side E1 to overlap the falling edge of the transmitting scanning signal Gn + 1_2 on the second side E2.

Similarly, in one embodiment, the control signal Qn + 2_1 is behind the control signal Qn + 1_2. The timing of the control signal Qn + 1_2, the control signal Qn + 2_1, the transmission scan signal Gn + 1_2, and the reception scan signal Gn + 1_1 are similar to the control signal Qn_1, control signal Qn + 1_2, and transmission scan signal Gn_1 and The timing of receiving the scanning signal Gn_2 is not repeated here.

In this way, when the transistor T3 finishes outputting the transmission scanning signal Gn + 1_2 and is turned off, the transistor T4 that is kept on according to the control signal Qn + 2_1 can effectively improve the distortion of the falling edge of the receiving scanning signal Gn + 1_1 on the first side E1 situation.

In summary, the pull-down circuits 112 and 114 of the present disclosure can effectively improve the distortion of the falling edge waveforms of the received scanning signals Gn_2 and Gn + 1_1 generated by passing through the scanning lines Ln, Ln + 1 to the other side of the display device 100. phenomenon. Therefore, the falling edges of the adjusted receiving scanning signals Gn_2 and Gn + 1_1 overlap and are consistent, and thus the display quality of the display device 100 is improved.

Although this case has been disclosed as above in implementation, it is not intended to limit the case. Any person skilled in this art can make various modifications and retouches without departing from the spirit and scope of the case. Therefore, the scope of protection of this case should be considered after The attached application patent shall prevail.

Claims (15)

    A display device includes: a first shift register circuit disposed on a first side of the display device and including: a first pull-up circuit for receiving a first clock signal and according to a first The control signal outputs a first transmission scan signal; a first pull-down circuit; a first pull-down control circuit for controlling the first pull-down circuit to output the first transmission scan signal to a first operating voltage; and A first main pull-down circuit electrically connected to the first pull-up circuit and used to output the first control signal to the first operating voltage; and a second pull-down circuit provided on a second side of the display device And coupled to the first pull-up circuit via a first scan line, wherein the second side is an opposite side of the first side, and the first shift register circuit and the second pull-down circuit are arranged on a display On both sides of the area, the first pull-up circuit outputs the first transmission scan signal to the second pull-down circuit through the first scan line, and the second pull-down circuit is further used to receive the first clock signal and according to a first Two control signals adjust the second side Receiving a first scan signal drop of the edge.         The display device according to claim 1, wherein the first pull-up circuit includes a first transistor, and the second pull-down circuit includes a second transistor.         The display device according to claim 2, wherein the first transistor has a first terminal, a second terminal, and a control terminal, and the first terminal of the first transistor is used to receive the first clock signal. The control terminal of the first transistor is used to receive the first control signal, the second terminal of the first transistor is used to output the first transmission scanning signal, and the second transistor has a first terminal, A second end and a control end, the first end of the second transistor is used to receive the first clock signal, the control end of the second transistor is used to receive the second control signal, and the second The second end of the transistor is coupled to the second end of the first transistor through the first scanning line and is used to adjust the falling edge of the first receiving scanning signal on the second side.         The display device according to claim 1, further comprising: a second shift register circuit disposed on the second side and including: a second pull-up circuit for receiving a second clock signal and according to A second control signal outputs a second transmission scan signal; a third pull-down circuit; a second pull-down control circuit for controlling the third pull-down circuit to output the second transmission scan signal to the first operating voltage; and A second main pull-down circuit electrically connected to the second pull-up circuit and used to output the second control signal to the first operating voltage; and a fourth pull-down circuit disposed on the first side and via a first Two scan lines are coupled to the second pull-up circuit, wherein the second pull-up circuit outputs the second transmission scan signal to the fourth pull-down circuit via the second scan line, and the fourth pull-down circuit is further configured to receive the first pull-up circuit. The second clock signal and the falling edge of one of the second receiving scanning signals on the first side are adjusted according to a third control signal.         The display device according to claim 4, wherein the second pull-up circuit includes a third transistor, and the fourth pull-down circuit includes a fourth transistor.         The display device according to claim 5, wherein the third transistor has a first terminal, a second terminal, and a control terminal, and the first terminal of the third transistor is used to receive the second clock signal The control terminal of the third transistor is used to receive the second control signal, the second terminal of the third transistor is used to output the second transmission scanning signal, and the fourth transistor has a first terminal, A second terminal and a control terminal, wherein the first terminal of the fourth transistor is used to receive the second clock signal, and the control terminal of the fourth transistor is used to receive the third control signal; The second terminal of the four transistors is coupled to the second terminal of the third transistor through the second scanning line and is used to adjust the falling edge of the second receiving scanning signal on the first side.         The display device according to claim 1, wherein when the first transistor completes outputting the first transmission scan signal on the first side and is turned off according to the first control signal, the second transistor is controlled according to the second control The signal remains on to adjust the falling edge of the first received scan signal on the second side.         The display device according to claim 7, wherein the falling edge of the first transmission scan signal on the first side and the falling edge of the first reception scan signal on the second side overlap.         The display device according to claim 6, wherein when the third transistor finishes outputting the second transmission scan signal on the second side and is turned off according to the second control signal, the fourth transistor is controlled according to the third control The signal remains on to adjust the falling edge of the second received scan signal on the first side.         The display device according to claim 9, wherein a falling edge of the second transmission scanning signal on the second side and a falling edge of the second receiving scanning signal on the first side overlap.         The display device according to claim 1, wherein the second control signal lags behind the first control signal.         A driving method for a display device, wherein the display device includes a first shift register circuit and a first pull-down circuit, and the first shift register circuit is disposed on one of the display devices. Side, the first pull-down circuit is disposed on a second side of the display device, and the driving method includes: receiving a first clock signal through the first shift register circuit and according to a first control signal Outputting a first transmission scanning signal; and receiving the first clock signal through the first pull-down circuit and adjusting a falling edge of a first reception scanning signal on the second side according to a second control signal.         The driving method according to claim 12, wherein the first shift register circuit includes a first transistor, the first pull-down circuit includes a second transistor, and the driving method further includes: when the first When the transistor completes outputting the first transmission scanning signal on the first side and is turned off according to the first control signal, the second transistor is kept on according to the second control signal to adjust the second side. The falling edge of the first received scan signal.         The driving method according to claim 12, wherein the display device further includes a second shift register circuit and a second pull-down circuit, the second shift register circuit is disposed on the second side, and the first Two pull-down circuits are disposed on the first side, and the driving method further includes: receiving a second clock signal through the second shift register circuit and outputting a second transmission scan signal according to the second control signal; And by the second pull-down circuit, receiving the second clock signal and adjusting a falling edge of a second receiving scanning signal on the first side according to a third control signal.         The driving method according to claim 14, wherein the second shift register circuit includes a third transistor, the second pull-down circuit includes a fourth transistor, and the driving method further includes: when the third transistor When the crystal finishes outputting the second transmission scanning signal on the second side and is turned off according to the second control signal, the fourth transistor is kept on according to the third control signal to adjust the first side of the first side. Second, receive the falling edge of the scanning signal.