TW201906098A - Semiconductor device package - Google Patents
Semiconductor device package Download PDFInfo
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- TW201906098A TW201906098A TW106143712A TW106143712A TW201906098A TW 201906098 A TW201906098 A TW 201906098A TW 106143712 A TW106143712 A TW 106143712A TW 106143712 A TW106143712 A TW 106143712A TW 201906098 A TW201906098 A TW 201906098A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3733—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Control And Other Processes For Unpacking Of Materials (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
本發明係關於一種半導體裝置封裝,且更具體而言係關於一種具有在豎直方向上之熱導率高於在側向方向上之熱導率之導熱結構的半導體裝置封裝。The present invention relates to a semiconductor device package, and more particularly to a semiconductor device package having a thermally conductive structure having a thermal conductivity in a vertical direction that is higher than a thermal conductivity in a lateral direction.
半導體領域已見證一些半導體裝置封裝中之多種電子組件之整合密度之增長。此增加之整合密度常常對應於半導體裝置封裝中之所增加的功率密度。由於半導體裝置封裝之功率密度增長,因此在一些實施中熱耗散可能變得合乎需要。因此,在一些實施中提供具有經改良熱導率之半導體裝置封裝可為適用的。The semiconductor industry has witnessed an increase in the integration density of various electronic components in some semiconductor device packages. This increased integration density often corresponds to increased power density in semiconductor device packages. As the power density of semiconductor device packages increases, heat dissipation may become desirable in some implementations. Therefore, it may be applicable to provide a semiconductor device package with improved thermal conductivity in some implementations.
在一些實施例中,一種半導體裝置封裝包含封裝基板、半導體組件、熱散播器及導熱結構。該封裝基板具有表面。該半導體組件安置於該封裝基板之該表面上方。該熱散播器安置於該封裝基板之該表面及該半導體組件上方。該導熱結構安置於該半導體組件與該熱散播器之間。該導熱結構包含第一聚合層及複數個第一填充物。該第一填充物中之每一者具有兩端部且由該第一聚合層側向地環繞。該第一填充物中之每一者的該兩個端部自該第一聚合層之相對表面曝露且分別與該半導體組件及該熱散播器接觸。 在一些實施例中,一種半導體裝置封裝包含封裝基板、半導體組件、熱散播器及導熱結構。該封裝基板具有表面。該半導體組件安置於該封裝基板之該表面上方。該熱散播器安置於該封裝基板之該表面及該半導體組件上方。該導熱結構安置於該半導體組件與該熱散播器之間。該導熱結構之在基本上垂直於該封裝基板之該表面之豎直方向上的熱導率大於該導熱結構之在基本上平行於該封裝基板之該表面之側向方向上的熱導率。 在一些實施例中,一種半導體裝置封裝包含封裝基板、半導體組件、熱散播器及導熱結構。該封裝基板具有表面。該半導體組件安置於該封裝基板之該表面上方。該熱散播器安置於該封裝基板之該表面及該半導體組件上方。該導熱結構在中心區中具有第一厚度,且在邊緣區中具有第二厚度,且該第一厚度小於該第二厚度。In some embodiments, a semiconductor device package includes a package substrate, a semiconductor component, a heat spreader, and a thermally conductive structure. The package substrate has a surface. The semiconductor component is disposed above the surface of the package substrate. The heat spreader is disposed on the surface of the package substrate and the semiconductor component. The thermally conductive structure is disposed between the semiconductor component and the heat spreader. The thermally conductive structure includes a first polymer layer and a plurality of first fillers. Each of the first fillers has two ends and is laterally surrounded by the first polymer layer. The two ends of each of the first fillers are exposed from opposite surfaces of the first polymer layer and are in contact with the semiconductor component and the heat spreader, respectively. In some embodiments, a semiconductor device package includes a package substrate, a semiconductor component, a heat spreader, and a thermally conductive structure. The package substrate has a surface. The semiconductor component is disposed above the surface of the package substrate. The heat spreader is disposed on the surface of the package substrate and the semiconductor component. The thermally conductive structure is disposed between the semiconductor component and the heat spreader. The thermal conductivity of the thermally conductive structure in a vertical direction substantially perpendicular to the surface of the package substrate is greater than the thermal conductivity of the thermally conductive structure in a lateral direction substantially parallel to the surface of the package substrate. In some embodiments, a semiconductor device package includes a package substrate, a semiconductor component, a heat spreader, and a thermally conductive structure. The package substrate has a surface. The semiconductor component is disposed above the surface of the package substrate. The heat spreader is disposed on the surface of the package substrate and the semiconductor component. The thermally conductive structure has a first thickness in a central region and a second thickness in an edge region, and the first thickness is smaller than the second thickness.
以下揭示提供用於實施所提供之主題的不同特徵之許多不同實施例或實例。下文描述組件及配置的具體實例來闡釋本發明之某些態樣。當然,此等僅為實例且並不意欲為限制性。舉例而言,在以下描述中,第一特徵在第二特上方或上之形成可包含第一特徵與第二特徵直接接觸地形成或安置的實施例,並且亦可包含額外特徵可形成或安置於第一特徵與第二特徵之間以使得第一特徵及第二特徵可不直接接觸之實施例。另外,本發明可在各種實例中重複參考標號及/或字母。此重複係出於簡單性及清晰性之目的,且其本身並不指示所論述之各種實施例及/或組態之間的關係。 除非另外說明,否則諸如「上方」、「下方」、「上」、「左」、「右」、「下」、「頂部」、「底部」、「豎直」、「水平」、「側面」、「高於」、「低於」、「上部」、「在……上」、「在……下」等之空間描述係相對於圖中所示之定向來指示的。應理解,本文中所使用之空間描述僅係出於說明之目的,且本文中所描述之結構的實際實施可以任何定向或方式在空間上配置,其限制條件為本發明之實施例的優點係不因此配置而有偏差。 以下描述包含對一些半導體裝置封裝及其製造方法之描述。在一些實施例中,半導體裝置封裝包含具有聚合層及經豎直對準之填充物的導熱結構。經豎直對準之填充物有助於使導熱結構之在豎直方向上的熱導率大於在側向方向上的熱導率。此可實現在作業期間由半導體組件產生之熱經由短熱路徑而經快速及/或有效地傳遞至熱散播器,如下文所論述。該聚合層可有助於改良導熱結構與半導體組件之間的接觸。在一些實施例中,導熱結構在中心區中具有第一厚度,且在邊緣區中具有第二厚度,該第一厚度小於該第二厚度。 圖1為根據本發明之第一態樣的半導體裝置封裝1的一些實施例之橫截面視圖。如圖1中所展示,半導體裝置封裝1包含封裝基板10、一或多個半導體組件20、晶粒附接層24、熱散播器30及導熱結構40。封裝基板10具有表面101 (例如,上部表面)。在一些實施例中,封裝基板10可包含半導體基板、內插器或其他合適基板(例如,包含整合於其中之電路、一或多個導電層及/或導電結構之基板)。在一或多個實施例中,表面101經組態以收納半導體組件20。封裝基板10具有與表面101相對之另一表面102 (例如,下部表面),且表面102可經組態以提供在半導體組件20外部之電氣連接。舉例而言,表面102可曝露其上可形成或安置焊球或其他連接器的導電襯墊。半導體組件20安置於封裝基板10之表面101上方。在一些實施例中,半導體組件20可藉由嵌入於封裝基板10中之電路、導電層或導電結構電連接至表面102,從而可實現將半導體裝置封裝1電連接至諸如電路板之另一電子裝置。在一些實施例中,半導體組件20包含一或多個半導體晶粒或其類似者。半導體組件20可經由諸如晶粒附接層24 (例如晶粒附接膜及/或黏著劑,例如導電黏著劑)安置於封裝基板10上。熱散播器30安置於封裝基板10之表面101及半導體組件20上方。在一些實施例中,熱散播器30之材料可包含但不限於金屬、金屬合金或具有高熱導率之另一材料。在一些實施例中,導熱結構40插入於半導體組件20與熱散播器30之間且與半導體組件20及熱散播器30接觸,且可將在作業期間由半導體組件20產生之熱傳遞至熱散播器30。在一些實施例中,導熱結構40之區域(例如,導熱結構40之頂部表面的區域或導熱結構40之覆蓋區之區域)等於或大於半導體組件20之區域(例如,半導體組件20之頂部表面的區域或半導體組件20之覆蓋區的區域)的約90%,例如,半導體組件20之區域的至少約92%、半導體組件20之區域的至少約94%、半導體組件20之區域的至少約96%、半導體組件之區域的至少約98%、半導體組件20之區域的約100%或在半導體組件20之區域的約90%至半導體組件20之區域的約100%的範圍內的任何值。此可有助於改良熱耗散效率。 在一些實施例中,半導體組件20具有主動表面20A,該主動表面20A具有輸入/輸出(I/O)端子,例如接合襯墊或其他導電結構,其經組態成將半導體組件20電連接至封裝基板10。在一些實施例中,半導體組件20之主動表面20A可面對熱散播器30。在一些實施例中,半導體裝置封裝1可進一步包含將主動表面20A電連接至封裝基板10之電線22,諸如接合線。 熱散播器30可基本上環繞或覆蓋半導體組件20、電線22及導熱結構40。在一些實施例中,熱散播器30可包含彼此連接之第一部分301及第二部分302。第一部分301可基本上安置在導熱結構40之上部表面401上且與該上部表面401接觸。在一些實施例中,第一部分301可橫越導熱結構40之上部表面401側向地延伸,且在側向方向上可寬於導熱結構40。第二部分302連接至第一部分301,且可自第一部分301朝向封裝基板10延伸。在一些實施例中,第二部分302相對於封裝基板10之表面101在傾斜方向上延伸且可連接至封裝基板10 (例如,可在將第一部分301與封裝基板10的表面101連接的基本上筆直的傾斜線上延伸)。在一些實施例中,熱散播器30之第二部分302可黏著於表面101且與表面101接觸(例如,直接接觸)。在一些替代性實施例中,熱散播器30之第二部分302可藉由黏著層(圖中未繪示)連接至表面101。 在一些實施例中,半導體裝置封裝1可進一步包含囊封物32,該囊封物32至少部分地囊封半導體組件20、導熱結構40、熱散播器30及電線22。在一些實施例中,囊封物32可曝露熱散播器30的上部表面30A。在一些實施例中,囊封物32之材料可包含模製原料,諸如環氧樹脂或其類似者。囊封物32之熱導率係數低於導熱結構40之熱導率係數。在一些實施例中,囊封物32之熱導率係數在約0.7瓦每米每開爾文(W/mK)至約6 W/mK的範圍內。 導熱結構40在基本上垂直於封裝基板10之表面101的豎直方向Z上之熱導率大於導熱結構40在一個或兩個側向方向X、Y上的熱導率,該側向方向X、Y基本上平行於封裝基板10的表面101 (例如封裝基板10的表面101可基本上在於X及Y方向上延伸的平面中)。因此,在作業期間由半導體組件20產生的熱可藉由導熱結構40在豎直方向上朝向熱散播器30快速地及/或有效地傳遞,因此改良熱耗散效率。導熱結構40可提供短熱路徑,如下文所論述。在一些實施例中,導熱結構40經組態以具有高熱導率係數且經組態以黏著於半導體組件20及熱散播器30。在一些實施例中,導熱結構40之厚度可基本上大於約200微米。作為實例,導熱結構40之厚度可在約200微米至約700微米之範圍內;在約200微米至約600微米之範圍內;在約300微米至約600微米之範圍內;在約300微米至約500微米之範圍內;或在其他適合之範圍內。在一些實施例中,導熱結構40之熱導率係數可在約40 W/mK至約90 W/mK之範圍內。在一些實施例中,導熱結構40在不使用諸如晶粒附接材料及模製原料之媒介材料的情況下與半導體組件20及熱散播器30直接接觸,該中介材料可具有比導熱結構40之熱導率係數低的熱導率係數。此可有助於使半導體組件20與熱散播器30之間的熱路徑中之平均熱導率係數高,且因此增強半導體封裝裝置1的熱導率效率。 圖2A為根據本發明之一些實施例之呈初始狀態之導熱結構40的一些實施例之橫截面視圖。如圖1A及圖2A中所展示,導熱結構40可包含第一聚合層42及在第一聚合層42中以基本上豎直的方式對準之第一填充物44。在一些實施例中,第一聚合層42之材料可包含但不限於矽酮樹脂或其類似者。在一些實施例中,第一聚合層42之材料可光學敏感及/或熱敏感,且可光學固化及/或熱固化。在一些實施例中,第一聚合層42可在形成熱散播器30之前固化。在一些實施例中,第一填充物44之材料可包含但不限於石墨、石墨烯、碳纖維、氮化硼或其類似者。在一些實施例中,第一填充物44中之每一者由第一聚合層42側向地環繞或覆蓋,使得第一填充物44由第一聚合層42基本上保持豎直對準。第一填充物44中之每一者的端部44A及端部44B (例如相對豎直端部)自第一聚合層42曝露。經豎直對準之第一填充物44可具有高熱導率係數,且可提供在豎直方向Z上的熱傳遞通道。與未豎直對準之填充物(例如隨機散佈的填充物)相比,經豎直對準之第一填充物44有助於使導熱結構40在豎直方向Z上的熱導率基本上大於在側向方向X、Y上的熱導率,且因此在作業期間由半導體組件20產生之熱可經由短熱路徑(例如,沿著經豎直對準的第一填充物44的直接路徑)快速地及/或有效地傳遞至熱散播器30。第一聚合層42可為軟且有彈性的材料,從而可有助於改良導熱結構40與半導體組件20之間的接觸且可有助於避免分層。導熱結構40之材料可化學地穩定,且因此可避免導熱結構40與半導體組件20之間的化學交叉污染。 圖2B為根據本發明之一些實施例之呈變形狀態的導熱結構40之一些實施例之橫截面視圖。在一些實施例中,導熱結構40適於其中施加外力(諸如由模套或其類似者)以將導熱結構40夾持至半導體組件20的實施。在一些此等實施例中,可忽略晶粒附接層(例如晶粒附接膜)。在一些實施中,壓縮導熱結構40且藉由外力將其連接至熱散播器30及半導體組件20。藉由忽略可具有低熱導率係數的晶粒附接膜,導熱結構40可增強半導體裝置封裝1之熱耗散效率。在一些實施例中,導熱結構40可在熱散播器30形成之前固化。如圖2B中所展示,在壓縮導熱結構40之後,導熱結構40的第一填充物44仍可基本上豎直地對準(例如,儘管與完美豎直對準有一定偏離)且可提供在基本上豎直方向Z上的熱傳遞通道。在一些實施例中,在此變形之後的導熱結構40之厚度可縮減在初始厚度之約10%至約40%之範圍內的量(例如,縮減約10%、約20%、約30%、或約40%)。作為實例,當導熱結構40的初始厚度約500微米時,在變形之後的導熱結構40的厚度可為約400微米。另外,在壓縮導熱結構40之後,導熱結構40與半導體組件20之間的接觸可改良。在一些實施例中,導熱結構40之壓縮可增加導熱結構40之厚度偏差的容差,且可改良導熱結構40之厚度均一性。作為實例,若變形比率(諸如拉伸比率或延伸比率)係20%且導熱結構40的初始厚度係120微米,則導熱結構40的厚度偏差容差係24微米(120微米的20%)。相似地,若變形比率為20%且導熱結構40的初始厚度係500微米,則導熱結構40的厚度偏差容差為100微米(500微米的20%)。 本發明提供之半導體裝置封裝不限於上文所描述之實施例,且可包含其他不同實施例,諸如下文所描述的實施例。為簡化描述且出於本發明之實施例中之每一者之間的合宜比較起見,以下實施例中之每一者中之相同或相似組件標記有同樣編號且不會過多地描述。 圖3A為根據本發明之第二態樣之半導體裝置封裝2之一些實施例的橫截面視圖,且圖3B為根據本發明之一些實施例之半導體裝置封裝2的部分俯視圖。如圖3A及圖3B中所展示,不同於圖1之半導體裝置封裝1,半導體組件20之主動表面20A面對封裝基板10。在一些實施例中,半導體裝置封裝2可進一步包含將主動表面20A電連接至封裝基板10的導電結構26。作為實例,導電結構26可包含但不限於導電凸塊、導電球或其類似者。在一些實施例中,半導體裝置封裝2可進一步包含環繞導電結構26且安置於半導體組件20與封裝基板10之間的底部填充層28。在一些實施例中,熱散播器30之第二部分302藉由黏著層12連接至表面101。在一些實施例中,導熱結構40可具有側向邊緣40E,且半導體裝置封裝2可進一步包含環繞導熱結構40之邊緣40E的至少一個黏著結構50。黏著結構50可進一步連接至半導體組件20及熱散播器30。在一些實施例中,黏著結構50可經組態以將熱散播器30的第一部分301接合至半導體組件20。在一些實施例中,黏著層12及黏著結構50可包含相同材料,且可同時形成。在一些實施例中,黏著結構50可經組態以幫助設置導熱結構40的位置(例如,導熱結構40可由黏著結構50環繞,如圖3A中所展示)。在一些實施例中,黏著結構50圍繞半導體組件20的周邊定位,且黏著結構50的寬度可縮減,從而可有助於避免對導熱結構40的熱耗散的不利影響。在一些實施例中,黏著結構50的寬度(例如,沿著X方向)等於或小於半導體組件20的寬度的約10% (例如,等於或小於半導體組件20的寬度的約8%,等於或小於半導體組件20的寬度的約6%,等於或小於半導體組件20的寬度的約4%,或等於或小於半導體組件20的寬度的約2%)。在一些實施例中,導熱結構40之區域(例如,導熱結構40的頂部表面的區域或導熱結構40的覆蓋區的區域)等於或大於半導體組件20的區域的約90% (例如,等於或大於半導體組件20的區域的約92%,等於或大於半導體組件20的區域的約94%,等於或大於半導體組件20的區域的約96%,或等於或大於半導體組件20的區域的約98%)。在一些實施例中,可忽略囊封物。 圖4為根據本發明之一些實施例之黏著結構50之橫截面視圖。如圖4中所展示,黏著結構50可包含第二聚合層52及安置於第二聚合層52中之第二填充物54。在一些實施例中,第二填充物54在第二聚合層52中隨機地分佈。在一些實施例中,黏著結構50之第二聚合層52及導熱結構40之第一聚合層42可包含相同材料及相同催化劑以幫助避免歸因於材料差異的不利影響。在一些實施例中,黏著結構50之第二填充物54及導熱結構40之第一填充物44可包含不同材料。舉例而言,第一填充物44之材料可包含但不限於石墨、石墨烯、碳纖維、氮化硼或其類似者,而第二填充物54之材料可包含但不限於氧化矽、氧化鋁、銀或其類似者。在一些實施例中,第二聚合層52之材料可為光學敏感及/或熱敏感的,且可被光學固化及/或熱固化。 圖5A為根據本發明之第三態樣之半導體裝置封裝3之一些實施例的橫截面視圖,且圖5B為根據本發明之一些實施例之半導體裝置封裝3的部分俯視圖。如圖5A及圖5B中所展示,不同於圖3A的半導體裝置封裝2,半導體裝置封裝3包含扇出裝置封裝。在一些實施例中,半導體組件20可包含兩個或多於兩個半導體晶粒201。在一些實施例中,每一半導體晶粒201可具有邊緣201E (例如,外部側向邊緣),且囊封物32安置於導熱結構40與封裝基板10之間且環繞或覆蓋半導體晶粒201中之每一者的每一邊緣201E。在一些實施例中,半導體裝置封裝3可進一步包含基板70,且半導體晶粒201安置於基板70上方。 圖6為根據本發明之第四態樣之半導體裝置封裝4之一些實施例的橫截面視圖。如圖6中所展示,不同於圖3A的半導體裝置封裝2,半導體裝置封裝4的熱散播器30安置於導熱結構40上方且基本上平行於封裝基板10延伸。在一些實施例中,熱散播器30具有基本上板形的結構。在一些實施例中,囊封物32安置於熱散播器30與封裝基板10之間,且側向地環繞半導體組件20、導熱結構40及底部填充層28。 圖7為根據本發明之第五態樣之半導體裝置封裝5的一些實施例的橫截面視圖。如圖7中所展示,不同於圖5A的半導體裝置封裝3,半導體裝置封裝5具有基本上彎折或彎曲(例如弓形)形狀。在一些實施例中,半導體裝置封裝5的中心部分可相對於本文中所描述的其他實施例向上彎折(例如可具有凹面形狀)。在一些實施例中,導熱結構40在中心區40A中具有第一厚度t1,且導熱結構40在邊緣區40B中具有第二厚度t2,且第一厚度t1小於第二厚度t2;例如t1可為t2的約98%或更小、約95%或更小,或約90%或更小。在一些實施例中,導熱結構40在夾持熱散播器30之前固化,而黏著結構50在夾持熱散播器30之後固化,從而可提供導熱結構40的凹面形狀。 在本發明之一些實施例中,半導體裝置封裝包含導熱結構,該導熱結構具有聚合層及經豎直對準之填充物。經豎直對準的填充物有助於使導熱結構在豎直方向上的熱導率大於導熱結構在側向方向上的熱導率,且因此在作業期間由半導體組件產生的熱可經由短熱路徑傳遞至熱散播器。該聚合層可有助於改良導熱結構與半導體組件之間的接觸。導熱結構的材料化學地穩定,且因此可有助於避免導熱結構與半導體組件之間的化學交叉污染,且降低分層風險。 如本文中所使用,除非上下文另外明確規定,否則單數術語「一(a/an)」及「該」可包含複數個指示物。 如本文中所使用,術語「導電(conductive/electrically conductive)」及「導電性」指代輸送電流之能力。導電材料通常指示展現對於電流流動的極少或零對抗之彼等材料。導電性之一個量度為西門子/米(S/m)。通常,導電材料為具有大於約104 S/m (例如至少105 S/m或至少106 S/m)之導電性的一種材料。材料之導電性有時可隨溫度而變化。除非另外規定,否則材料的導電性係在室溫下量測。 如本文中所使用,術語「大致」、「基本上」、「實質」及「約」用以描述及說明小的變化。當與事件或情形結合使用時,該術語可指代其中事件或情形精確發生的例子以及其中事件或情形極近似地發生的例子。舉例而言,當結合數值使用時,術語可指小於或等於該數值的±10%的變化範圍,諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%。舉例而言,若兩個數值之間的差小於或等於該值的平均值的±10%,諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%,則可認為該兩個數值「基本上」相同或相等。舉例而言,「基本上」平行可指相對於0°的小於或等於±10°的角度變化範圍,諸如小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°、或小於或等於±0.05°。舉例而言,「基本上」垂直可指相對於90°的小於或等於±10°的角度變化範圍,諸如小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°,或小於或等於±0.05°。 另外,有時在本文中按範圍格式呈現量、比率及其他數值。應理解,此等範圍格式係為便利及簡潔而使用,且應靈活地理解為不僅包含明確地指定為範圍限制的數值,申請專利範圍且亦包含涵蓋於該範圍內的所有個別數值或子範圍,如同明確地指定每一數值及子範圍一般。 儘管已參考本發明之特定實施例描述並說明本發明,但這些描述及說明並不限制本發明。一般熟悉此項技術者應理解,在不脫離如由所附申請專利範疇界定的本發明之真實精神及範疇的情況下,可作出各種改變且可替代等效物。該說明可能未必按比例繪製。由於製造製程及容差,本發明中之藝術再現與實際設備之間可存在區別。可存在並未特定說明的本發明之其他實施例。應將本說明書及圖式視為說明性的而非限制性的。可進行修改,以使特定情形、材料、物質組成、方法或製程適應於本發明之目標、精神及範疇。所有此等修改皆既定在此所附權利要求書之範疇內。雖然本文中所揭示之方法已參考按特定次序執行之特定操作加以描述,但應理解,可在不脫離本發明之教示之情況下組合、細分或重新排序這些操作以形成等效方法。因此,除非本文中特別指示,否則作業的次序及分組不係對本發明之限制。The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to illustrate some aspects of the invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of the first feature above or above the second feature may include embodiments in which the first feature is formed or disposed in direct contact with the second feature, and may also include additional features that may be formed or disposed An embodiment between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the sake of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed. Unless otherwise stated, such as "above", "below", "up", "left", "right", "down", "top", "bottom", "vertical", "horizontal", "side" The spatial descriptions of "above", "below", "above", "above", "below", etc. are indicated relative to the orientation shown in the figure. It should be understood that the space description used herein is for illustration purposes only, and the actual implementation of the structure described in this article may be spatially configured in any orientation or manner, and its limitations are the advantages of the embodiments of the present invention. No deviation due to configuration. The following description contains descriptions of some semiconductor device packages and methods of manufacturing them. In some embodiments, the semiconductor device package includes a thermally conductive structure having a polymeric layer and a vertically aligned filler. The vertically aligned filler helps to make the thermal conductivity of the thermally conductive structure greater than the thermal conductivity in the lateral direction. This enables rapid and / or efficient transfer of heat generated by the semiconductor components during operation to the heat spreader via a short thermal path, as discussed below. The polymeric layer can help improve contact between the thermally conductive structure and the semiconductor component. In some embodiments, the thermally conductive structure has a first thickness in the central region and a second thickness in the edge region, the first thickness being smaller than the second thickness. FIG. 1 is a cross-sectional view of some embodiments of a semiconductor device package 1 according to a first aspect of the present invention. As shown in FIG. 1, the semiconductor device package 1 includes a package substrate 10, one or more semiconductor components 20, a die attach layer 24, a heat spreader 30, and a thermally conductive structure 40. The package substrate 10 has a surface 101 (for example, an upper surface). In some embodiments, the package substrate 10 may include a semiconductor substrate, an interposer, or other suitable substrate (eg, a substrate including a circuit integrated therein, one or more conductive layers, and / or a conductive structure). In one or more embodiments, the surface 101 is configured to receive the semiconductor component 20. The package substrate 10 has another surface 102 (eg, a lower surface) opposite the surface 101, and the surface 102 may be configured to provide an electrical connection outside the semiconductor component 20. For example, the surface 102 may expose conductive pads on which solder balls or other connectors may be formed or placed. The semiconductor device 20 is disposed above the surface 101 of the package substrate 10. In some embodiments, the semiconductor device 20 may be electrically connected to the surface 102 by a circuit, a conductive layer, or a conductive structure embedded in the package substrate 10, so that the semiconductor device package 1 may be electrically connected to another electronic device such as a circuit board. Device. In some embodiments, the semiconductor component 20 includes one or more semiconductor dies or the like. The semiconductor device 20 may be disposed on the package substrate 10 via, for example, a die attach layer 24 (eg, a die attach film and / or an adhesive such as a conductive adhesive). The heat spreader 30 is disposed above the surface 101 of the package substrate 10 and the semiconductor component 20. In some embodiments, the material of the heat spreader 30 may include, but is not limited to, a metal, a metal alloy, or another material having a high thermal conductivity. In some embodiments, the thermally conductive structure 40 is interposed between and in contact with the semiconductor device 20 and the heat spreader 30 and can transfer heat generated by the semiconductor device 20 to the heat spreader during operation器 30。 30. In some embodiments, the area of the thermally conductive structure 40 (eg, the area of the top surface of the thermally conductive structure 40 or the area of the coverage area of the thermally conductive structure 40) is equal to or greater than the area of the semiconductor component 20 (e.g., the area of the top surface of the semiconductor component 20) Area or the area covered by the semiconductor device 20), for example, at least about 92% of the area of the semiconductor device 20, at least about 94% of the area of the semiconductor device 20, and at least about 96% of the area of the semiconductor device 20 , At least about 98% of the area of the semiconductor device, about 100% of the area of the semiconductor device 20, or any value ranging from about 90% of the area of the semiconductor device 20 to about 100% of the area of the semiconductor device 20. This can help improve heat dissipation efficiency. In some embodiments, the semiconductor component 20 has an active surface 20A having input / output (I / O) terminals, such as a bonding pad or other conductive structure, configured to electrically connect the semiconductor component 20 to Package substrate 10. In some embodiments, the active surface 20A of the semiconductor component 20 may face the heat spreader 30. In some embodiments, the semiconductor device package 1 may further include a wire 22 such as a bonding wire that electrically connects the active surface 20A to the package substrate 10. The heat spreader 30 may substantially surround or cover the semiconductor component 20, the electrical wires 22, and the thermally conductive structure 40. In some embodiments, the heat spreader 30 may include a first portion 301 and a second portion 302 connected to each other. The first portion 301 may be substantially disposed on and in contact with the upper surface 401 of the thermally conductive structure 40. In some embodiments, the first portion 301 may extend laterally across the upper surface 401 of the thermally conductive structure 40 and may be wider than the thermally conductive structure 40 in a lateral direction. The second portion 302 is connected to the first portion 301 and may extend from the first portion 301 toward the package substrate 10. In some embodiments, the second portion 302 extends in an oblique direction relative to the surface 101 of the package substrate 10 and can be connected to the package substrate 10 (for example, the first portion 301 can be substantially connected to the surface 101 of the package substrate 10 (Straight, straight line). In some embodiments, the second portion 302 of the heat spreader 30 may be adhered to and in contact with the surface 101 (eg, in direct contact). In some alternative embodiments, the second portion 302 of the heat spreader 30 may be connected to the surface 101 by an adhesive layer (not shown). In some embodiments, the semiconductor device package 1 may further include an encapsulant 32 that at least partially encapsulates the semiconductor component 20, the thermally conductive structure 40, the heat spreader 30, and the electrical wires 22. In some embodiments, the encapsulant 32 may expose the upper surface 30A of the heat spreader 30. In some embodiments, the material of the encapsulant 32 may include a molding material, such as epoxy resin or the like. The thermal conductivity coefficient of the encapsulant 32 is lower than the thermal conductivity coefficient of the thermally conductive structure 40. In some embodiments, the thermal conductivity coefficient of the encapsulant 32 is in the range of about 0.7 Watts per meter per Kelvin (W / mK) to about 6 W / mK. The thermal conductivity of the thermally conductive structure 40 in a vertical direction Z substantially perpendicular to the surface 101 of the package substrate 10 is greater than the thermal conductivity of the thermally conductive structure 40 in one or two lateral directions X, Y, which lateral direction X And Y are substantially parallel to the surface 101 of the package substrate 10 (for example, the surface 101 of the package substrate 10 may be substantially in a plane extending in the X and Y directions). Therefore, the heat generated by the semiconductor component 20 during operation can be quickly and / or efficiently transferred toward the heat spreader 30 in the vertical direction by the heat conductive structure 40, thereby improving the heat dissipation efficiency. The thermally conductive structure 40 may provide a short thermal path, as discussed below. In some embodiments, the thermally conductive structure 40 is configured to have a high thermal conductivity coefficient and configured to adhere to the semiconductor component 20 and the heat spreader 30. In some embodiments, the thickness of the thermally conductive structure 40 may be substantially greater than about 200 microns. As an example, the thickness of the thermally conductive structure 40 may be in a range from about 200 microns to about 700 microns; within a range from about 200 microns to about 600 microns; within a range from about 300 microns to about 600 microns; between about 300 microns to Within a range of about 500 microns; or within other suitable ranges. In some embodiments, the thermal conductivity coefficient of the thermally conductive structure 40 may be in a range of about 40 W / mK to about 90 W / mK. In some embodiments, the thermally conductive structure 40 is in direct contact with the semiconductor component 20 and the thermal spreader 30 without using a media material such as die attach materials and molding materials. Low thermal conductivity coefficient. This may help to make the average thermal conductivity coefficient in the thermal path between the semiconductor component 20 and the heat spreader 30 high, and thus enhance the thermal conductivity efficiency of the semiconductor package device 1. FIG. 2A is a cross-sectional view of some embodiments of the thermally conductive structure 40 in an initial state according to some embodiments of the present invention. As shown in FIGS. 1A and 2A, the thermally conductive structure 40 may include a first polymeric layer 42 and a first filler 44 aligned in a substantially vertical manner in the first polymeric layer 42. In some embodiments, the material of the first polymer layer 42 may include, but is not limited to, a silicone resin or the like. In some embodiments, the material of the first polymeric layer 42 may be optically and / or thermally sensitive, and may be optically and / or thermally curable. In some embodiments, the first polymeric layer 42 may be cured before forming the heat spreader 30. In some embodiments, the material of the first filler 44 may include, but is not limited to, graphite, graphene, carbon fiber, boron nitride, or the like. In some embodiments, each of the first fillers 44 is laterally surrounded or covered by the first polymeric layer 42 such that the first filler 44 is maintained substantially vertically aligned by the first polymeric layer 42. An end portion 44A and an end portion 44B (for example, relatively vertical end portions) of each of the first fillers 44 are exposed from the first polymer layer 42. The vertically aligned first filler 44 may have a high thermal conductivity coefficient and may provide a heat transfer channel in the vertical direction Z. Compared to non-vertically aligned fillers (such as randomly dispersed fillers), the vertically aligned first fillers 44 help to substantially increase the thermal conductivity of the thermally conductive structure 40 in the vertical direction Z Greater thermal conductivity in the lateral directions X, Y, and therefore the heat generated by the semiconductor component 20 during operation may be via a short thermal path (e.g., a direct path along the vertically aligned first filler 44) ) Quickly and / or efficiently transferred to the heat spreader 30. The first polymer layer 42 may be a soft and elastic material, which may help improve contact between the thermally conductive structure 40 and the semiconductor component 20 and may help avoid delamination. The material of the thermally conductive structure 40 can be chemically stable, and thus chemical cross-contamination between the thermally conductive structure 40 and the semiconductor component 20 can be avoided. FIG. 2B is a cross-sectional view of some embodiments of the thermally conductive structure 40 in a deformed state according to some embodiments of the present invention. In some embodiments, the thermally conductive structure 40 is suitable for implementations in which an external force is applied (such as by a mold sleeve or the like) to clamp the thermally conductive structure 40 to the semiconductor component 20. In some of these embodiments, a die attach layer (eg, a die attach film) may be omitted. In some implementations, the thermally conductive structure 40 is compressed and connected to the heat spreader 30 and the semiconductor component 20 by an external force. By ignoring the die attach film, which may have a low thermal conductivity coefficient, the thermally conductive structure 40 may enhance the heat dissipation efficiency of the semiconductor device package 1. In some embodiments, the thermally conductive structure 40 may be cured before the heat spreader 30 is formed. As shown in FIG. 2B, after compressing the thermally conductive structure 40, the first filler 44 of the thermally conductive structure 40 may still be aligned substantially vertically (e.g., despite some deviation from perfect vertical alignment) and may be provided at Heat transfer channels in substantially vertical direction Z. In some embodiments, the thickness of the thermally conductive structure 40 after this deformation may be reduced by an amount in the range of about 10% to about 40% of the initial thickness (e.g., reduced by about 10%, about 20%, about 30%, Or about 40%). As an example, when the initial thickness of the thermally conductive structure 40 is about 500 microns, the thickness of the thermally conductive structure 40 after deformation may be about 400 microns. In addition, after the thermally conductive structure 40 is compressed, the contact between the thermally conductive structure 40 and the semiconductor component 20 can be improved. In some embodiments, the compression of the thermally conductive structure 40 can increase the tolerance of the thickness deviation of the thermally conductive structure 40 and improve the thickness uniformity of the thermally conductive structure 40. As an example, if the deformation ratio (such as the stretch ratio or elongation ratio) is 20% and the initial thickness of the thermally conductive structure 40 is 120 microns, the thickness deviation tolerance of the thermally conductive structure 40 is 24 microns (20% of 120 microns). Similarly, if the deformation ratio is 20% and the initial thickness of the thermally conductive structure 40 is 500 microns, the thickness deviation tolerance of the thermally conductive structure 40 is 100 microns (20% of 500 microns). The semiconductor device package provided by the present invention is not limited to the embodiments described above, and may include other different embodiments, such as the embodiments described below. To simplify the description and for a convenient comparison between each of the embodiments of the present invention, the same or similar components in each of the following embodiments are labeled with the same number and will not be described too much. 3A is a cross-sectional view of some embodiments of a semiconductor device package 2 according to a second aspect of the present invention, and FIG. 3B is a partial top view of the semiconductor device package 2 according to some embodiments of the present invention. As shown in FIGS. 3A and 3B, unlike the semiconductor device package 1 of FIG. 1, the active surface 20A of the semiconductor component 20 faces the package substrate 10. In some embodiments, the semiconductor device package 2 may further include a conductive structure 26 electrically connecting the active surface 20A to the package substrate 10. As an example, the conductive structure 26 may include, but is not limited to, a conductive bump, a conductive ball, or the like. In some embodiments, the semiconductor device package 2 may further include an underfill layer 28 surrounding the conductive structure 26 and disposed between the semiconductor component 20 and the package substrate 10. In some embodiments, the second portion 302 of the heat spreader 30 is connected to the surface 101 by an adhesive layer 12. In some embodiments, the thermally conductive structure 40 may have a lateral edge 40E, and the semiconductor device package 2 may further include at least one adhesive structure 50 surrounding the edge 40E of the thermally conductive structure 40. The adhesive structure 50 may be further connected to the semiconductor device 20 and the heat spreader 30. In some embodiments, the adhesive structure 50 may be configured to join the first portion 301 of the heat spreader 30 to the semiconductor component 20. In some embodiments, the adhesive layer 12 and the adhesive structure 50 may include the same material and may be formed at the same time. In some embodiments, the adhesive structure 50 may be configured to help position the thermally conductive structure 40 (eg, the thermally conductive structure 40 may be surrounded by the adhesive structure 50, as shown in FIG. 3A). In some embodiments, the adhesive structure 50 is positioned around the periphery of the semiconductor device 20, and the width of the adhesive structure 50 can be reduced, which can help to avoid the adverse effect on the heat dissipation of the thermally conductive structure 40. In some embodiments, the width (eg, along the X direction) of the adhesive structure 50 is equal to or less than about 10% of the width of the semiconductor device 20 (eg, equal to or less than about 8% of the width of the semiconductor device 20, equal to or less than (About 6% of the width of the semiconductor device 20 is equal to or less than about 4% of the width of the semiconductor device 20 or equal to or less than about 2% of the width of the semiconductor device 20). In some embodiments, the area of the thermally conductive structure 40 (eg, the area of the top surface of the thermally conductive structure 40 or the area of the footprint of the thermally conductive structure 40) is equal to or greater than about 90% of the area of the semiconductor component 20 (eg, equal to or greater than (About 92% of the area of the semiconductor device 20, equal to or greater than about 94% of the area of the semiconductor device 20, equal to or greater than about 96% of the area of the semiconductor device 20, or equal to or greater than about 98% of the area of the semiconductor device 20) . In some embodiments, the encapsulation may be ignored. FIG. 4 is a cross-sectional view of an adhesive structure 50 according to some embodiments of the present invention. As shown in FIG. 4, the adhesive structure 50 may include a second polymer layer 52 and a second filler 54 disposed in the second polymer layer 52. In some embodiments, the second fillers 54 are randomly distributed in the second polymeric layer 52. In some embodiments, the second polymeric layer 52 of the adhesive structure 50 and the first polymeric layer 42 of the thermally conductive structure 40 may include the same material and the same catalyst to help avoid adverse effects due to material differences. In some embodiments, the second filler 54 of the adhesive structure 50 and the first filler 44 of the thermally conductive structure 40 may include different materials. For example, the material of the first filler 44 may include, but is not limited to, graphite, graphene, carbon fiber, boron nitride, or the like, and the material of the second filler 54 may include, but is not limited to, silicon oxide, aluminum oxide, Silver or similar. In some embodiments, the material of the second polymeric layer 52 may be optically and / or thermally sensitive, and may be optically and / or thermally cured. 5A is a cross-sectional view of some embodiments of a semiconductor device package 3 according to a third aspect of the present invention, and FIG. 5B is a partial top view of the semiconductor device package 3 according to some embodiments of the present invention. As shown in FIGS. 5A and 5B, unlike the semiconductor device package 2 of FIG. 3A, the semiconductor device package 3 includes a fan-out device package. In some embodiments, the semiconductor component 20 may include two or more semiconductor dies 201. In some embodiments, each semiconductor die 201 may have an edge 201E (eg, an external lateral edge), and the encapsulant 32 is disposed between the thermally conductive structure 40 and the package substrate 10 and surrounds or covers the semiconductor die 201 Each edge 201E of each. In some embodiments, the semiconductor device package 3 may further include a substrate 70, and the semiconductor die 201 is disposed above the substrate 70. FIG. 6 is a cross-sectional view of some embodiments of a semiconductor device package 4 according to a fourth aspect of the present invention. As shown in FIG. 6, unlike the semiconductor device package 2 of FIG. 3A, the heat spreader 30 of the semiconductor device package 4 is disposed above the thermally conductive structure 40 and extends substantially parallel to the package substrate 10. In some embodiments, the heat spreader 30 has a substantially plate-shaped structure. In some embodiments, the encapsulant 32 is disposed between the heat spreader 30 and the package substrate 10 and laterally surrounds the semiconductor component 20, the thermally conductive structure 40 and the underfill layer 28. FIG. 7 is a cross-sectional view of some embodiments of a semiconductor device package 5 according to a fifth aspect of the present invention. As shown in FIG. 7, unlike the semiconductor device package 3 of FIG. 5A, the semiconductor device package 5 has a substantially bent or curved (eg, bowed) shape. In some embodiments, the central portion of the semiconductor device package 5 may be bent upwards (eg, may have a concave shape) relative to other embodiments described herein. In some embodiments, the thermally conductive structure 40 has a first thickness t1 in the central region 40A, and the thermally conductive structure 40 has a second thickness t2 in the edge region 40B, and the first thickness t1 is smaller than the second thickness t2; for example, t1 may be t2 is about 98% or less, about 95% or less, or about 90% or less. In some embodiments, the thermally conductive structure 40 is cured before the thermal spreader 30 is clamped, and the adhesive structure 50 is cured after the thermal spreader 30 is clamped, thereby providing a concave shape of the thermally conductive structure 40. In some embodiments of the present invention, the semiconductor device package includes a thermally conductive structure having a polymer layer and a vertically aligned filler. The vertically aligned filler helps to make the thermal conductivity of the thermally conductive structure in the vertical direction greater than the thermal conductivity of the thermally conductive structure in the lateral direction, and thus the heat generated by the semiconductor components during operation can be reduced by The heat path is transferred to the heat spreader. The polymeric layer can help improve contact between the thermally conductive structure and the semiconductor component. The material of the thermally conductive structure is chemically stable, and thus can help avoid chemical cross-contamination between the thermally conductive structure and the semiconductor component and reduce the risk of delamination. As used herein, the singular terms “a / an” and “the” may include plural referents unless the context clearly dictates otherwise. As used herein, the terms "conductive / electrically conductive" and "conductive" refer to the ability to carry a current. Conductive materials are generally indicative of materials that exhibit little or zero opposition to current flow. One measure of conductivity is Siemens / meter (S / m). Generally, a conductive material is a material having a conductivity of greater than about 10 4 S / m (eg, at least 10 5 S / m or at least 10 6 S / m). The conductivity of a material can sometimes change with temperature. Unless otherwise specified, the conductivity of materials is measured at room temperature. As used herein, the terms "substantially", "substantially", "substantially" and "about" are used to describe and illustrate small variations. When used in conjunction with an event or situation, the term may refer to both an example in which the event or situation occurs precisely and an example in which the event or situation occurs very closely. For example, when used in conjunction with a value, the term can refer to a range of variation that is less than or equal to ± 10% of the value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or Equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, if the difference between two values is less than or equal to ± 10% of the average value of the value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%, the two values can be considered to be "substantially" the same or equal. For example, "substantially" parallel may refer to a range of angular variation less than or equal to ± 10 ° with respect to 0 °, such as less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than Or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °. For example, "substantially" vertical may refer to a range of angles less than or equal to ± 10 ° with respect to 90 °, such as less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than Or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °. In addition, quantities, ratios, and other numerical values are sometimes presented in a range format herein. It should be understood that these range formats are used for convenience and brevity, and should be flexibly understood not only to include values explicitly designated as range limits, but also for patented ranges and all individual values or subranges covered by that range As if explicitly specifying each value and subrange. Although the invention has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the invention. Those skilled in the art will generally understand that various changes can be made and equivalents can be substituted without departing from the true spirit and scope of the invention as defined by the scope of the appended patent application. The description may not be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the artistic reproduction in the present invention and the actual equipment. There may be other embodiments of the present invention that are not specifically described. This specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, material composition, method, or process to the objectives, spirit, and scope of the present invention. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the present invention. Therefore, unless specifically indicated herein, the order and grouping of operations is not a limitation of the present invention.
1‧‧‧半導體裝置封裝1‧‧‧Semiconductor device package
2‧‧‧半導體裝置封裝2‧‧‧Semiconductor device package
3‧‧‧半導體裝置封裝3‧‧‧Semiconductor device package
4‧‧‧半導體裝置封裝4‧‧‧Semiconductor device package
5‧‧‧半導體裝置封裝5‧‧‧Semiconductor device package
10‧‧‧封裝基板10‧‧‧ package substrate
12‧‧‧黏著層12‧‧‧ Adhesive layer
20‧‧‧半導體組件20‧‧‧Semiconductor components
20A‧‧‧主動表面20A‧‧‧Active Surface
22‧‧‧電線22‧‧‧Wire
24‧‧‧晶粒附接層24‧‧‧ die attach layer
26‧‧‧導電結構26‧‧‧ conductive structure
28‧‧‧底部填充層28‧‧‧ underfill layer
30‧‧‧熱散播器30‧‧‧Heat spreader
30A‧‧‧上部表面30A30A‧‧‧Upper surface 30A
32‧‧‧囊封物32‧‧‧ Encapsulation
40‧‧‧導熱結構40‧‧‧Conductive structure
40A‧‧‧中心區40A‧‧‧Central Area
40B‧‧‧邊緣區40B‧‧‧Marginal zone
42‧‧‧第一聚合層42‧‧‧The first polymerization layer
44‧‧‧第一填充物44‧‧‧ the first filler
44A‧‧‧端部44A‧‧‧End
44B‧‧‧端部44B‧‧‧End
40E‧‧‧側向邊緣40E‧‧‧lateral edge
50‧‧‧黏著結構50‧‧‧ Adhesive structure
52‧‧‧第二聚合層52‧‧‧Second Polymerization Layer
54‧‧‧第二填充物54‧‧‧Second filler
70‧‧‧基板70‧‧‧ substrate
101‧‧‧表面101‧‧‧ surface
102‧‧‧表面102‧‧‧ surface
201‧‧‧半導體晶粒201‧‧‧Semiconductor die
201E‧‧‧邊緣201E‧‧‧Edge
301‧‧‧第一部分301‧‧‧Part I
302‧‧‧第二部分302‧‧‧Part Two
401‧‧‧上部表面401‧‧‧upper surface
當結合附圖閱讀時,自以下具體實施方式最好地理解本發明之一些實施例之態樣。應注意,各種結構可能未按比例繪製,且各種結構之尺寸可出於論述清楚起見任意增大或減小。 圖1為根據本發明之第一態樣之半導體裝置封裝之一些實施例之橫截面視圖; 圖2A為根據本發明之一些實施例之呈初始狀態之導熱結構的一些實施例之橫截面視圖; 圖2B為根據本發明之一些實施例之呈變形狀態之導熱結構的橫截面視圖; 圖3A為根據本發明之第二態樣的半導體裝置封裝之一些實施例的橫截面視圖; 圖3B為根據本發明之第二態樣之半導體裝置封裝之一些實施例的部分俯視圖; 圖4為根據本發明之一些實施例之黏著結構的橫截面視圖; 圖5A為根據本發明之第三態樣之半導體裝置封裝之一些實施例的橫截面視圖; 圖5B為根據本發明之第三態樣的半導體裝置封裝之一些實施例的部分俯視圖; 圖6為根據本發明之第四態樣之半導體裝置封裝之一些實施例的橫截面視圖;且 圖7為根據本發明之第五態樣之半導體裝置封裝之一些實施例的橫截面視圖。When read in conjunction with the accompanying drawings, aspects of some embodiments of the present invention are best understood from the following detailed description. It should be noted that various structures may not be drawn to scale, and the dimensions of various structures may be arbitrarily increased or decreased for clarity of discussion. 1 is a cross-sectional view of some embodiments of a semiconductor device package according to a first aspect of the present invention; FIG. 2A is a cross-sectional view of some embodiments of a thermally conductive structure in an initial state according to some embodiments of the present invention; 2B is a cross-sectional view of a thermally conductive structure in a deformed state according to some embodiments of the present invention; FIG. 3A is a cross-sectional view of some embodiments of a semiconductor device package according to a second aspect of the present invention; Partial top view of some embodiments of the semiconductor device package according to the second aspect of the present invention; FIG. 4 is a cross-sectional view of an adhesive structure according to some embodiments of the present invention; FIG. A cross-sectional view of some embodiments of a device package; FIG. 5B is a partial plan view of some embodiments of a semiconductor device package according to a third aspect of the present invention; Cross-sectional views of some embodiments; and FIG. 7 is a cross-sectional view of some embodiments of a semiconductor device package according to a fifth aspect of the present invention.
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US20020079572A1 (en) * | 2000-12-22 | 2002-06-27 | Khan Reza-Ur Rahman | Enhanced die-up ball grid array and method for making the same |
KR20050074961A (en) * | 2002-10-08 | 2005-07-19 | 치팩, 인코포레이티드 | Semiconductor stacked multi-package module having inverted second package |
KR100632459B1 (en) * | 2004-01-28 | 2006-10-09 | 삼성전자주식회사 | Heat-dissipating semiconductor package and manufacturing method |
CN100337981C (en) * | 2005-03-24 | 2007-09-19 | 清华大学 | Thermal interface material and its production method |
US7135769B2 (en) * | 2005-03-29 | 2006-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of manufacturing thereof |
WO2008129525A1 (en) * | 2007-04-23 | 2008-10-30 | University College Cork - National University Of Ireland, Cork | A thermal interface material |
US7553752B2 (en) * | 2007-06-20 | 2009-06-30 | Stats Chippac, Ltd. | Method of making a wafer level integration package |
US7602060B2 (en) * | 2007-06-25 | 2009-10-13 | Intel Corporation | Heat spreader in a flip chip package |
US9017808B2 (en) * | 2008-03-17 | 2015-04-28 | The Research Foundation For The State University Of New York | Composite thermal interface material system and method using nano-scale components |
US7629203B2 (en) * | 2008-03-31 | 2009-12-08 | Intel Corporation | Thermal interface material for combined reflow |
US7733655B2 (en) * | 2008-07-22 | 2010-06-08 | International Business Machines Corporation | Lid edge capping load |
US8344053B2 (en) * | 2009-09-10 | 2013-01-01 | Pixelligent Technologies, Llc | Highly conductive composites |
US9601406B2 (en) * | 2013-03-01 | 2017-03-21 | Intel Corporation | Copper nanorod-based thermal interface material (TIM) |
US9070660B2 (en) * | 2013-03-15 | 2015-06-30 | Intel Corporation | Polymer thermal interface material having enhanced thermal conductivity |
US9338927B2 (en) * | 2013-05-02 | 2016-05-10 | Western Digital Technologies, Inc. | Thermal interface material pad and method of forming the same |
US20150118514A1 (en) * | 2013-10-30 | 2015-04-30 | Teledyne Scientific & Imaging, Llc. | High Performance Thermal Interface System With Improved Heat Spreading and CTE Compliance |
US10163754B2 (en) * | 2013-12-26 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lid design for heat dissipation enhancement of die package |
US9746889B2 (en) * | 2015-05-11 | 2017-08-29 | Qualcomm Incorporated | Package-on-package (PoP) device comprising bi-directional thermal electric cooler |
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