TW201905922A - Resistive memory and recovery resistance window method of resistive memory cell thereof - Google Patents

Abstract

A resistive memory and a recovery resistance window method of a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in the reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase the compliance current of the resistive memory cell. During the third period, a reset operation is performed on the resistive memory cell.

Description

Resistive memory window method for resistive memory and resistive memory cell

The present invention relates to a memory, and more particularly to a method of restoring resistance window of a resistive memory and its resistive memory cell.

Resistive random access memory (RRAM) is a non-volatile memory. RRAM can use the change in resistance to remember or store values. Resistive memory and integrated circuit process compatibility is excellent. Resistive memory has a fast write speed and low write voltage, which meets the low power requirements of portable electronic products.

In resistive memory, three operations of forming, setting, and reset are three important steps to ensure the electrical characteristics of the resistive memory cell and the data retention. When performing a set/reset operation, it may be necessary to step up and multiple times to increase the input voltage to complete, which is called a ramping operation. For some problematic memory cells, when a high voltage is used to perform a resistive memory cell reset operation (or set operation), it may increase the resistive memory cell that should be in a low current state. The current (or the resistive memory cell that should be in a high current state reduces its current) is called a complementary switching (CS) phenomenon. The CS phenomenon is a unique phenomenon in the field of resistive memory.

Once the resistive memory cell has a CS phenomenon, the resistance window (or voltage window) of the reset operation of the memory cell will be narrowed (or even disappeared). "The narrowing of the resistance window" means that the high-resistance HRS and the low-resistance LRS will become indistinguishable, that is, the memory cell will lose its memory ability. Therefore, it is important to avoid the complementary switching phenomenon of the resistive memory cells during the setting operation and the reset operation. In any case, the endurance of resistive memory cells is limited. As the number of operations (resets and/or settings) advances, complementary switching of resistive memory cells is unavoidable. How to restore the resistance window is also an important issue when the complementary switching phenomenon occurs in the resistive memory cell.

The invention provides a resistive memory and a resistive memory cell recovery resistance window method thereof, which can restore the resistance window to prolong the durability of the resistive memory cell.

Embodiments of the present invention provide a method of recovering a resistance window of a resistive memory cell. The method for restoring the resistance window includes: applying a reset voltage difference between the upper electrode and the lower electrode of the resistive memory cell during the first period, wherein the over reset voltage difference falls on the reset complementary switching of the resistive memory cell (reset complementary switching, reset-CS) voltage range; applying a set voltage difference between the upper electrode and the lower electrode of the resistive memory cell during the second period to increase a compliance current of the resistive memory cell; The third period performs a first reset operation on the resistive memory cell.

Embodiments of the present invention provide a resistive memory. The resistive memory body includes a resistive memory cell, a word line signal providing circuit, a bit line signal providing circuit, and a source line signal providing circuit. The word line signal providing circuit is coupled to the word line of the resistive memory cell. The bit line signal providing circuit is coupled to the bit line of the resistive memory cell. The source line signal providing circuit is coupled to the source line of the resistive memory cell. When the recovery resistance window method is performed, the bit line signal supply circuit and the source line signal supply circuit apply a reset voltage difference between the upper electrode and the lower electrode of the resistive memory cell during the first period, wherein the reset is performed. The voltage difference falls within the reset complementary switching voltage range of the resistive memory cell. The bit line signal providing circuit and the source line signal providing circuit apply a set voltage difference between the upper electrode and the lower electrode of the resistive memory cell during the second period to increase the current limit of the resistive memory cell. The word line signal providing circuit, the bit line signal providing circuit and the source line signal providing circuit perform a first reset operation on the resistive memory cell during the third period.

Based on the above, the resistive memory of the embodiments of the present invention can perform a resistive memory cell recovery resistance window method. The reset voltage difference is applied to the resistive memory cell, and then the set voltage difference is applied to the resistive memory cell, thereby restoring the resistance window. The resistance window of the resistive memory cell is recovered, meaning that the durability of the resistive memory cell can be extended.

The above described features and advantages of the invention will be apparent from the following description.

The term "coupled (or connected)" as used throughout the specification (including the scope of the claims) may be used in any direct or indirect connection. For example, if the first device is described as being coupled (or connected) to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be A connection means is indirectly connected to the second device. In addition, wherever possible, the elements and/ Elements/components/steps that use the same reference numbers or use the same terms in different embodiments may refer to the related description.

FIG. 1 is a schematic diagram of a circuit block of a resistive memory 100 in accordance with an embodiment of the invention. The resistive memory 100 includes a resistive memory cell 110, a word line signal providing circuit 120, a bit line signal providing circuit 130, and a source line signal providing circuit 140. The word line signal providing circuit 120 is coupled to the word line WL of the resistive memory cell 110. The bit line signal supply circuit 130 is coupled to the bit line BL of the resistive memory cell 110. The source line signal providing circuit 140 is coupled to the source line SL of the resistive memory cell 110. In this embodiment, the resistive memory cell 110 includes a switching unit (eg, transistor T1) and a resistor R1.

The resistor R1 has a top electrode and a bottom electrode. The resistor R1 can be realized by an excessive metal oxide layer, and the embodiment of the invention is not limited thereto. The resistor R1 described above can be implemented in any manner depending on the design requirements of the embodiment. For example, but not limited to, the structure of the resistor R1 may be laminated in the order of "lower electrode, variable resistor, and upper electrode" in the vertical direction of the substrate. For example, the lower electrode material deposited on the single crystal substrate of lanthanum aluminum oxide LaAlO ₃ (LAO) may be a beryllium copper oxide YBa ₂ Cu ₃ O ₇ (YBCO) film, and the material of the variable resistor body may be calcium. A crystalline yttrium _- manganese oxide Pr _1-X Ca _X MnO ₃ (PCMO) film of a titanium oxide type oxide, and the upper electrode material may be an Ag film deposited by sputtering. Further, in addition to the above perovskite materials, it is known that a ZnSe-Ge heterostructure or an oxide of a metal such as Ti, Nb, Hf, Zr, Ta, Ni, V, Zn, Sn, In, Th, Al or the like may also be used. The material of the above variable resistor body. The resistance characteristics of the resistor R1 are also different depending on the material of the variable resistor body. The resistance value (resistance state) of the resistor R1 can be reversibly changed according to the direction of the voltage applied between the upper electrode and the lower electrode. By reading the resistance value (resistance state) of the variable resistor material, the resistor R1 can achieve the effect of the resistive memory.

The first end (upper or lower electrode) of the resistor R1 is coupled to the bit line signal supply circuit 130 via the bit line BL. The second end (lower or upper electrode) of the resistor R1 is coupled to the first end (eg, the drain) of the transistor T1. The second end (eg, the source) of the transistor T1 is coupled to the source line signal supply circuit 140 via the source line SL. The word line signal providing circuit 120 is coupled to the control terminal (e.g., the gate) of the transistor T1 in the resistive memory cell 110 via the word line WL. The resistive memory 100 also includes a control circuit 150. The control circuit 150 can detect the current of the resistive memory cell 110 to determine whether its write operation (eg, forming operation, setting operation, and/or reset operation) is completed.

FIG. 2 is a flow chart showing a method for restoring a resistance window of a resistive memory cell 110 according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, in step S210, the control circuit 150 can control the word line signal providing circuit 120, the bit line signal providing circuit 130 and the source line signal providing circuit 140 to perform the resistive memory cell 110. The reset operation, as well as measuring the current of the resistive memory cell 110 (ie, the current flowing through the resistor R1). The details of the reset operation performed in step S210 can be determined according to design requirements. In some embodiments, the word line signal providing circuit 120 can supply a voltage of 3-5 volts (pulse width of 100 nanoseconds) to the word line WL, and the bit line signal providing circuit 130 can supply the ground voltage to the bit line. BL, the source line signal supply circuit 140 can supply a voltage of 2-4 volts (pulse width of 100 nanoseconds) to the source line SL. In other embodiments, the source line signal providing circuit 140 may perform a ramping operation, for example, sequentially raising the voltage of the source line SL by using a step voltage between 2 and 5 volts. In other embodiments, the reset operation performed in step S210 may be a conventional reset operation, and thus will not be described again.

During the reset operation performed in step S210, the control circuit 150 can measure the current of the resistive memory cell 110 (i.e., the current flowing through the resistor R1). In step S220, the control circuit 150 determines whether or not to proceed to step S230 (recovery resistance window method) in accordance with the relationship between the current of the resistive memory cell 110 and the first specification spec1. The first specification spec1 can be determined according to design requirements. For example, in some embodiments, the first specification spec1 may include "the current of the resistive memory cell 110 does not exceed 1 microamperes after the reset operation." When it is determined in step S220 that the current of the resistive memory cell 110 conforms to the first specification spec1, it indicates that the reset operation of the resistive memory cell 110 is successful, so the reset operation is completed (end). When it is determined in step S220 that the current of the resistive memory cell 110 does not conform to the first specification spec1, it indicates that the reset operation of the resistive memory cell 110 is unsuccessful, and therefore step S230 (recovery resistance window method) needs to be performed.

FIG. 3 is a schematic diagram showing current changes of the resistive memory cell 110 of FIG. 1 according to an embodiment of the invention. The vertical axis shown in Fig. 3 indicates the current (in micro amps) of the resistive memory cell 110, and the horizontal axis indicates the step shown in Fig. 2. Please refer to FIG. 1 to FIG. 3. In step S220, the control circuit 150 can determine whether the current of the resistive memory cell 110 conforms to the first specification spec1 (for example, 1 microamperes). In the embodiment shown in FIG. 3, the current of the resistive memory cell 110 measured in step S210 is approximately 3.5 microamperes (beyond the first specification spec1), so step S230 (recovery resistance window method) needs to be performed.

In the embodiment shown in FIG. 2, step S230 includes step S231, step S232, and step S233. The control circuit 150 can control the word line signal supply circuit 120, the bit line signal supply circuit 130, and the source line signal supply circuit 140 to perform steps S231, S232, and S233.

In step S231, the bit line signal supply circuit 130 and the source line signal supply circuit 140 apply a reset voltage difference between the upper electrode and the lower electrode of the resistive memory cell 110 during the first period. The over-reset voltage difference falls on the “reset complementary switching voltage range” of the resistive memory cell 110. The over-reset voltage difference can be determined according to design requirements. For example, but not limited to, in some embodiments, the word line signal providing circuit 120 can supply a first high voltage (eg, a voltage of 6 volts or other voltage with a pulse width of 100 nanoseconds) to the word line. WL, the bit line signal providing circuit 130 may supply a reference voltage (for example, a ground voltage or other fixed voltage) to the bit line BL, and the source line signal providing circuit 140 may supply a second high voltage (for example, a voltage of 5 volts or other voltage) , the pulse width is 100 nanoseconds) to the source line SL.

FIG. 4 is a schematic diagram showing the characteristic curve of the resistive memory cell 110 (resistor R1) of FIG. 1 according to an embodiment. The horizontal axis of Fig. 4 represents the voltage difference between the upper electrode and the lower electrode of the resistive memory cell 110 (i.e., the upper electrode voltage minus the electrode voltage), and the vertical axis represents the current value flowing through the resistive memory cell 110. Curves 411 and 412 represent the current versus voltage characteristic of resistive memory cell 110 in a low resistance state LRS, while curve 413 and curve 414 represent the current versus voltage characteristic of resistive memory cell 110 in a high resistance state HRS. Depending on the material, in the case of a normal memory cell, the resistance value of the low resistance state LRS may be tens of ohms or hundreds of ohms (for example, several KΩ), and the resistance value of the high resistance state HRS may be greater than The resistance LSR resistance value is more than tens of times (for example, 10K~100MΩ). Assuming that the resistor R1 is in the high-resistance state HRS (refer to curve 414), when the voltage difference between the upper electrode and the lower electrode of the resistor R1 is greater than the set voltage VSET, the resistor R1 will undergo a "set" operation, so that the resistor R1 The resistive state changes from a high-resistance HRS to a low-resistance LRS. Referring to curve 412, when the voltage difference between the upper electrode and the lower electrode of the resistor R1 of the low-resistance LRS is less than the reset voltage VRESET, the resistor R1 will undergo a "reset" operation, so that the resistance state of the resistor R1 It will change from low-resistance LRS to high-resistance HRS.

Fig. 4 shows the characteristic curve of the problematic memory cell by a broken line curve, and the characteristic curve of the normal memory cell is shown by a solid line curve. For some problematic memory cells, a complementary switching (CS) phenomenon RST-CS may occur when performing a reset operation. In the case of a normal memory cell, in the case where the voltage difference falls in the "reset complementary switching voltage range" 401, the current value of the resistive memory cell 110 becomes smaller as the voltage difference (absolute value) increases. For a memory cell having a problem (for example, a complementary switching phenomenon RST-CS), in the case where the voltage difference falls in the "reset complementary switching voltage range" 401, as the voltage difference (absolute value) increases, The current value of the resistive memory cell 110 does not decrease.

The over-reset voltage difference applied in step S231 falls in the "reset complementary switching voltage range" 401 of the resistive memory cell 110. FIG. 3 illustrates that after the bit line signal providing circuit 130 and the source line signal providing circuit 140 apply a reset voltage difference to the resistive memory cell 110 (step S231), the current of the resistive memory cell 110 is approximately 7 micro. ampere.

Please refer to FIG. 1 to FIG. 2 . The bit line signal providing circuit 130 and the source line signal providing circuit 140 apply a set voltage difference between the upper electrode and the lower electrode of the resistive memory cell 110 during the second period (step S232) to increase the resistance of the resistive memory cell 110. Limit current. The set voltage difference can be determined according to design requirements. For example, but not limited to, in some embodiments, the bit line signal providing circuit 130 can supply a first voltage (eg, a voltage of 2-4 volts or other voltage with a pulse width of 100 nanoseconds) to the bit element. The line BL, the word line signal providing circuit 120 can supply a second voltage (for example, a voltage of 3.2 volts or other voltage, a pulse width of 100 nanoseconds) to the word line WL, and the source line signal providing circuit 140 can supply a reference voltage ( For example, a ground voltage or other fixed voltage) to the source line SL. The general word line voltage in a typical set operation is approximately 2-4 volts. The second voltage may be greater than a general word line voltage in a general set operation to increase a compliance current of the resistive memory cell 110. In other embodiments, the word line signal providing circuit 120 can supply a voltage of 2-4 volts to the word line WL, and the bit line signal providing circuit 130 can supply a voltage of 2-4 volts to the bit line BL, but The voltage pulse width of the word line WL and the bit line BL is greater than 100 nanoseconds (eg, hundreds of nanoseconds or microseconds). FIG. 3 illustrates that after the bit line signal providing circuit 130 and the source line signal providing circuit 140 apply a set voltage difference to the resistive memory cell 110 (step S232), the current of the resistive memory cell 110 is approximately 23 microamperes.

The word line signal supply circuit 120, the bit line signal supply circuit 130, and the source line signal supply circuit 140 perform a reset operation on the resistive memory cell 110 during the third period (step S233). The details of the reset operation performed in step S233 can be determined according to design requirements. In some embodiments, the reset operation performed in step S233 may be the same (or similar) to the reset operation performed in step S210. In other embodiments, the source line signal providing circuit 140 may perform a ramping operation in step S233, for example, sequentially stepping up the voltage of the source line SL with a step voltage between 2 and 5 volts. In other embodiments, the reset operation performed in step S233 may be a conventional reset operation, and thus will not be described again.

The control circuit 150 can measure the current of the resistive memory cell 110 in the reset operation of step S233. FIG. 3 illustrates that the current of the resistive memory cell 110 is approximately 1 microamperes after the reset operation is performed in step S233. Step S240 can compare the relationship between the current measured in step S233 and the second specification spec2. The second specification spec2 can be determined according to design requirements. For example, in some embodiments, the second specification spec2 may include "the current of the resistive memory cell 110 does not exceed 3 microamps after the reset operation." The second specification spec2 may be larger than the first specification spec1. In other embodiments, the second specification spec2 may be identical to the first specification spec1. In accordance with the relationship between the current of the resistive memory cell 110 and the second specification spec2, the control circuit 150 can decide whether or not to perform step S230 again (recovery resistance window method).

When it is determined in step S240 that the current of the resistive memory cell 110 conforms to the second specification spec2, it indicates that the reset operation of the resistive memory cell 110 is successful, so the reset operation is completed (end). When it is determined in step S240 that the current of the resistive memory cell 110 does not meet the second specification spec2, it indicates that the reset operation of the resistive memory cell 110 is unsuccessful. Therefore, step S250 needs to be performed to determine whether to perform step S230 again. (Restore the resistance window method).

In some embodiments, step S250 may compare the total time (time length of execution) of step S230 to the threshold value. In other embodiments, step S250 may compare the total number of times (the number of times) performed in step S230 with the threshold value. The control circuit can count the length of time (or number of times of execution) of the method of restoring the resistance window. In step S250, the control circuit 150 may decide whether to stop performing step S230 again (recovering the resistance window method) in accordance with the length of time (or the number of times of execution). When it is determined in step S250 that the length of time (or the number of times of execution) has not reached the threshold value, step S230 (recovery resistance window method) is performed again. When it is determined in step S250 that the time length (or the number of times of execution) has reached the threshold value, the reset operation of the resistive memory cell 110 can be determined to be a failure, that is, the lifetime of the resistive memory cell 110 is exhausted.

It should be noted that in different application scenarios, the related functions of the control circuit 150 shown in FIG. 1 and/or the related functions of the flowchart shown in FIG. 1 may utilize a general programming language (for example, C or C++). ), hardware description languages (such as Verilog HDL or VHDL) or other suitable programming language to implement as software, firmware or hardware. The programming language that can perform the related functions can be arranged as any known computer-accessible media, such as magnetic tapes, semiconductors, magnetic disks, or optical disks. (compact disks, such as CD-ROM or DVD-ROM), or the programming language can be transmitted over the Internet, wired communication, wireless communication, or other communication medium. The programming language can be stored in an accessible medium of the computer such that the software (or firmware) programming codes are accessed/executed by the processor of the computer. For the hardware implementation, combined with the aspects disclosed in the embodiments, one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processing Various exemplary logic, logic blocks, modules, and circuits in a digital signal processor (DSP), Field Programmable Gate Array (FPGA), and/or other processing unit can be used Implement or perform the functions described in this article. Additionally, the apparatus and method of the present invention can be implemented by a combination of hardware and software.

In summary, the resistive memory 100 of the embodiments of the present invention can perform a recovery resistance window method of the resistive memory cell 110. The over-voltage difference is applied to the resistive memory cell 110, and then the set voltage difference is applied to the resistive memory cell 110, thereby restoring the resistive window. The resistance window of the resistive memory cell 110 is recovered, meaning that the durability of the resistive memory cell 110 can be extended.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Resistive memory

110‧‧‧Resistive memory cells

120‧‧‧Word line signal providing circuit

130‧‧‧ bit line signal supply circuit

140‧‧‧Source line signal supply circuit

150‧‧‧Control circuit

401‧‧‧Reset complementary switching voltage range

411～414‧‧‧ Curve

BL‧‧‧ bit line

HRS‧‧‧high resistance state

LRS‧‧‧Low resistance state

R1‧‧‧ resistance

RST-CS‧‧‧Complementary switching phenomenon

S210～S250‧‧‧Steps

SL‧‧‧ source line

T1‧‧‧O crystal

VSET‧‧‧Set voltage

VRESET‧‧‧Reset voltage

WL‧‧‧ character line

1 is a schematic diagram of a circuit block of a resistive memory according to an embodiment of the invention. 2 is a flow chart showing a method of recovering a resistance window of a resistive memory cell according to an embodiment of the invention. FIG. 3 is a schematic diagram showing current changes of the resistive memory cell of FIG. 1 according to an embodiment of the invention. FIG. 4 is a schematic diagram showing the characteristic curve of the resistive memory cell shown in FIG. 1 according to an embodiment.

Claims (16)

A method for recovering a resistance window of a resistive memory cell, comprising: applying a reset voltage difference between an upper electrode and a lower electrode of a resistive memory cell during a first period, wherein the over reset voltage difference falls a reset complementary switching voltage range of the resistive memory cell; applying a set voltage difference between the upper electrode and the lower electrode of the resistive memory cell during a second period to increase one of the resistive memory cells Limiting the current; and performing a first reset operation on the resistive memory cell during a third period. The method for restoring a resistance window according to claim 1, further comprising: performing a second reset operation on the resistive memory cell to measure at least a first current of the resistive memory cell; Determining whether to perform the recovery resistance window method by describing at least one relationship between the first current and a first specification. The method for restoring a resistance window according to claim 1, further comprising: measuring at least a second current of the resistive memory cell in the first reset operation; and according to the at least one second current A second specification relationship determines whether to resume the recovery resistor window method again. The method for restoring a resistance window according to claim 3, further comprising: counting a length of time or a number of times of performing the method of recovering the resistance window; and determining whether to stop the recovery according to the length of the performed time or the number of times of performing Resistance window method. The method for restoring a resistance window according to claim 1, wherein the step of applying the over-reset voltage difference comprises: providing a reference voltage to a one-dimensional line of the resistive memory cell; providing a first high a voltage to a word line of the resistive memory cell; and a second high voltage to a source line of the resistive memory cell. The method for restoring a resistance window according to claim 5, wherein the reference voltage comprises a ground voltage, the first high voltage is 5-7V, and the second high voltage is 4-6V. The method for recovering a resistance window according to claim 1, wherein the step of applying the set voltage difference comprises: providing a first voltage to a one-dimensional line of the resistive memory cell; providing a second voltage to a word line of the resistive memory cell; and a reference voltage to a source line of the resistive memory cell. The method for restoring a resistance window according to claim 7, wherein the reference voltage comprises a ground voltage, the first voltage is 2-4V, and the second voltage is 3-5V, and the second voltage is greater than Set the general word line voltage in operation. A resistive memory comprising: a resistive memory cell; a word line signal providing circuit coupled to a word line of the resistive memory cell; and a bit line signal providing circuit coupled to the resistive a source line of the memory cell; and a source line signal providing circuit coupled to a source line of the resistive memory cell, wherein the bit line signal providing circuit and the gate line when performing a recovery resistor window method The source line signal providing circuit applies a reset voltage difference between an upper electrode and a lower electrode of the resistive memory cell during a first period, and the over reset voltage difference falls on a weight of the resistive memory cell Setting a complementary switching voltage range, the bit line signal providing circuit and the source line signal providing circuit apply a set voltage difference between the upper electrode and the lower electrode of the resistive memory cell during a second period to increase the a limit current of the resistive memory cell, the word line signal providing circuit, the bit line signal providing circuit and the source line signal providing circuit perform a first reset operation on the resistive memory cell in a third period . The resistive memory of claim 9, further comprising: a control circuit for controlling the word line signal providing circuit, the bit line signal providing circuit and the source line signal providing circuit, Performing a second reset operation on the resistive memory cell and measuring at least one first current of the resistive memory cell, wherein the control circuit determines whether the relationship between the at least one first current and a first specification is Perform the recovery resistor window method. The resistive memory of claim 9, further comprising: a control circuit for measuring at least a second current of the resistive memory cell in the first reset operation, wherein the control circuit Determining whether to perform the recovery resistance window method again according to the relationship between the at least one second current and a second specification. The resistive memory of claim 11, wherein the control circuit counts a length of time or a number of times of the method of recovering the resistance window, and the control circuit determines the length of the progress or the number of times of the operation. Whether to stop the recovery resistor window method. The resistive memory according to claim 9, wherein the application of the reset voltage difference is that the bit line signal providing circuit provides a reference voltage to the bit line, and the word line signal providing circuit A first high voltage is supplied to the word line, and the source line signal providing circuit provides a second high voltage to the source line. The resistive memory of claim 13, wherein the reference voltage comprises a ground voltage, the first high voltage is 5-7V, and the second high voltage is 4-6V. The resistive memory according to claim 9, wherein the setting of the set voltage difference is that the bit line signal providing circuit provides a first voltage to the bit line, and the word line signal providing circuit provides a second voltage to the word line, and the source line signal providing circuit provides a reference voltage to the source line. The resistive memory of claim 15, wherein the reference voltage comprises a ground voltage, the first voltage is 2-4V, and the second voltage is 3-5V, and the second voltage is greater than Set the general word line voltage in operation.