TW201904012A - Semiconductor device - Google Patents

Abstract

An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.

Description

   Semiconductor device   

The present invention relates to a semiconductor device.

As a transistor constituting a high-frequency amplifier module of a mobile terminal in recent years, a heterojunction bipolar transistor (HBT) is mainly used. A semiconductor device in which an electrostatic destruction prevention circuit (protection circuit) is connected between a collector and an emitter of HBT is known (Patent Document 1). The protection circuit is composed of a plurality of diodes connected in series with each other.

[Advanced technical literature]

[Patent Literature]

Patent Document 1: Japanese Patent No. 4977313

The diode constituting the protection circuit is designed to satisfy the following conditions: it does not conduct during normal function operation, but conducts when a voltage exceeding the upper limit of the allowable voltage is generated between the collector and the emitter. In order to satisfy this condition, a circuit in which eight or more diodes are connected in series can be used as a protection circuit. Since it is necessary to ensure that more than eight diode regions are arranged, the wafer area will increase.

An object of the present invention is to provide a semiconductor device capable of suppressing an increase in wafer area even if a protection circuit is incorporated in an amplifier circuit.

The semiconductor device according to the first aspect of the present invention includes: an amplifier circuit including a semiconductor element formed on a substrate; a protection circuit including a plurality of protection diodes formed on the substrate and connected in series with each other, the protection circuit being connected To the output terminal of the amplifying circuit; and a pad conductor layer, at least a part of the pad conductor layer includes a pad for connection to an external circuit of the substrate. In a plan view, the pad conductor layer and the pad The protection circuits overlap at least partially.

By arranging the pad conductor layer and the protection circuit to partially overlap, it is possible to suppress an increase in the chip area.

The semiconductor device according to the second aspect of the present invention, in addition to the structure of the semiconductor device according to the first aspect, has the following feature: it also has a ground conductor formed on the substrate, and can pass a high voltage generated by the output terminal Protect the circuit from ground conductors.

The semiconductor device according to the third aspect of the present invention, in addition to the configuration of the semiconductor device according to the first and second aspects, is characterized by further having an insulating protective film covering the pad conductor layer An opening is provided to expose a part of the surface of the pad conductor layer and cover the other area. In a plan view, the opening at least partially overlaps the protection circuit.

The pad conductor layer exposed in the opening provided in the protective film functions as a pad for wire bonding or bumps. The pads and the protective circuit at least partially overlap, thereby suppressing an increase in the wafer area.

The semiconductor device according to the fourth aspect of the present invention, in addition to the configuration of the semiconductor device according to the third aspect, further includes bumps formed on the pad conductor layer on the bottom surface of the opening.

The bump can be installed face-down on the module substrate.

The semiconductor device according to the fifth aspect of the present invention, in addition to the configuration of the semiconductor device according to the fourth aspect, has the following feature: the planar shape of the bump is a rounded rectangle.

By making the planar shape of the bump into a rounded rectangle, the bump can be processed stably in almost the same shape as the mask shape of the bump.

The semiconductor device according to the sixth aspect of the present invention, in addition to the structure of the semiconductor device according to the first to fifth aspects, has the following feature: a plurality of the above-mentioned protective diode structures are folded back halfway in a plan view In the diode array, a part of the protection circuit is arranged outside the pad conductor layer.

Even when the entire area of the diode row cannot be converged inside the pad conductor layer and a part of it protrudes from the pad conductor layer, by folding back the diode row, the secondary conductor layer can be reduced Outstanding area.

The semiconductor device according to the seventh aspect of the present invention, in addition to the structure of the semiconductor device based on the first to fifth aspects, has the following feature: a plurality of the above-mentioned protective diode structures are folded back halfway in a plan view A diode row, each of the plurality of protective diodes includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the upper surface of the first semiconductor layer A part of the region, and the second conductivity type is opposite to the first conductivity type; and the first electrode ohmically connected to the upper surface of the first semiconductor layer, in a plan view, the first electrode has a A U-shaped planar shape sandwiching the second semiconductor layer in the width direction of the diode row.

By adopting such a configuration, when a high voltage is applied to the diode array, it becomes less likely to cause electrostatic discharge. Thereby, it is possible to suppress the destruction of the protective diode caused by electrostatic discharge.

The semiconductor device according to the eighth aspect of the present invention, in addition to the structure of the semiconductor device according to the first to seventh aspects, has the following feature: the semiconductor element is formed of a compound semiconductor.

Compared with silicon-based semiconductor devices, the operating frequency can be increased.

By arranging the pad conductor layer and the protection circuit to partially overlap, it is possible to suppress an increase in the chip area.

31‧‧‧Input stage amplifier circuit

32‧‧‧Output stage amplifier circuit

33, 34‧‧‧ matching circuit

35、36‧‧‧bias circuit

40‧‧‧Protection circuit

41‧‧‧ Heterojunction Bipolar Transistor (HBT)

42‧‧‧Input capacitor

43‧‧‧ Ballast resistance

44‧‧‧ collector terminal

45‧‧‧ circuit unit

47‧‧‧ diode series circuit

48‧‧‧Protection diode

49A‧‧‧1HBT unit block

49B‧‧‧2HBT unit block

50‧‧‧ substrate

51‧‧‧Subset polar layer

52‧‧‧ Collector

53‧‧‧ Base layer

54‧‧‧Emitter layer

55‧‧‧n-type semiconductor layer

57‧‧‧ Collector electrode

58‧‧‧Base electrode

59‧‧‧Emitter electrode

60‧‧‧Back electrode

61‧‧‧Cathode electrode

62‧‧‧Anode electrode

63‧‧‧ Base control wiring

64‧‧‧High frequency input wiring

65‧‧‧solder pad

66‧‧‧Through hole

67‧‧‧Contact hole

68‧‧‧Protection film

69‧‧‧Contact hole

70‧‧‧bond wire

71‧‧‧Through hole

72‧‧‧Inorganic insulating film

73‧‧‧Insulating resin film

74, 75, 76 ‧‧‧ contact hole

77‧‧‧Bump for grounding

77A‧‧‧Au layer

77B‧‧‧Solder layer

78‧‧‧High frequency output bump

78A‧‧‧Au layer

78B‧‧‧Solder layer

79‧‧‧Contact hole

81‧‧‧Bump for grounding

82‧‧‧Bump for high frequency output

B1‧‧‧ Base wiring

C1‧‧‧ Collector wiring of layer 1

C2‧‧‧Layer 2 collector wiring

D1‧‧‧Diode wiring

E1‧‧‧Emitter wiring of layer 1

E2‧‧‧Layer 2 wiring

J2‧‧‧ connection wiring

P1‧‧‧The first layer of pad conductor layer

P2‧‧‧Layer 2 conductor layer

Q2‧‧‧ connection wiring

1A is a block diagram of a power amplifier module incorporating a semiconductor device according to the first embodiment, and FIG. 1B is an equivalent circuit diagram of an output stage amplifier circuit and a protection circuit.

Fig. 2 is a plan view of an output stage amplifier circuit.

FIG. 3A is a plan view of an HBT that can be used in the semiconductor device of the first embodiment, and FIG. 3B is a cross-sectional view at the one-dot chain line 3B-3B of FIG. 3A.

4A is a plan view of a protective diode that can be used in the semiconductor device of the first embodiment. FIG. 4B is a cross-sectional view at the one-dot chain line 4B-4B of FIG. 4A.

FIG. 5 is a cross-sectional view at the one-dot chain line 5-5 of FIG. 2.

6 is an equivalent circuit diagram of an output stage amplifier circuit and a protection circuit of the semiconductor device according to the second embodiment.

7 is a plan view of the semiconductor device according to the second embodiment.

8 is a plan view of a semiconductor device according to a third embodiment.

9 is a plan view of a protection diode constituting a protection circuit of a semiconductor device according to a modification.

10 is a cross-sectional view of a pad portion of a semiconductor device according to a modification.

11 is a plan view of a semiconductor device according to a fourth embodiment.

12 is a schematic cross-sectional view of a portion corresponding to one HBT of the semiconductor device according to the fourth embodiment.

13 is a cross-sectional view of a portion of a semiconductor device according to a fourth embodiment where bumps for high-frequency output are formed.

14 is a plan view of a semiconductor device according to a first modification of the fourth embodiment.

15 is a plan view of a semiconductor device according to a second modification of the fourth embodiment.

16 is a plan view of a semiconductor device according to a third modification of the fourth embodiment.

17 is a cross-sectional view of a semiconductor device according to a fifth embodiment.

18 is a plan view of a semiconductor device according to a modification of the fifth embodiment.

FIG. 19A is an equivalent circuit diagram of an output stage amplifier circuit used as an analog object for simulating the influence of parasitic inductance, and FIG. 19B is a graph showing an analog result of a waveform of an output voltage.

20A is a graph showing the normalized maximum peak voltage when the parasitic inductance Le is set to 0 and the parasitic inductance Lc is changed, and FIG. 20B is a normalized when the parasitic inductance Lc is set to 0 and the parasitic inductance Le is changed. The graph of the maximum peak voltage.

FIG. 21A is an equivalent circuit diagram of an amplifying circuit for an analog object for simulating the influence of parasitic resistance, and FIG. 21B is a graph showing an analog result.

22 is a plan view of a semiconductor device based on a comparative example.

23 is a plan view of a semiconductor device according to another comparative example.

24 is a plan view of a semiconductor device according to still another comparative example.

25 is a plan view of a semiconductor device according to still another comparative example.

26A is a schematic plan view of a protection circuit that can be used in the semiconductor device according to the first embodiment, and FIG. 26B is a schematic plan view of the protection circuit that can be used in the semiconductor device according to a comparative example.

[First embodiment]

The semiconductor device according to the first embodiment will be described with reference to the drawings of FIGS. 1A to 5.

FIG. 1A is a block diagram of a power amplifier module incorporating a semiconductor device according to this embodiment. The input signal input from the high-frequency input terminal RFi is input to the input stage amplifier circuit 31 via the matching circuit 33. The signal amplified by the input stage amplifier circuit 31 is input to the output stage amplifier circuit 32 via the matching circuit 34. The output signal amplified by the output stage amplifier circuit 32 is output from the high-frequency output terminal RFo.

A bias voltage is applied to the bias circuits 35 and 36 from the bias voltage terminal Vbat. Based on the signal input from the bias control terminal Vb1, the bias circuit 35 supplies a bias current to the input stage amplifier circuit 31. Based on the signal input from the bias control terminal Vb2, the bias circuit 36 supplies the bias current to the output stage amplifier circuit 32. The power supply voltage is applied to the input stage amplifier circuit 31 from the power supply terminal Vcc1, and the power supply voltage is applied to the output stage amplifier circuit 32 from the power supply terminal Vcc2.

A protection circuit 40 is connected between the output terminal of the output stage amplifier circuit 32 and the ground GND. The protection circuit 40 has a function of suppressing a further increase in voltage when a voltage exceeding the allowable upper limit value is generated at the output terminal of the output stage amplifier circuit 32 due to a load fluctuation of the power amplifier module.

FIG. 1B is an equivalent circuit diagram of the output stage amplifier circuit 32 (FIG. 1A) and the protection circuit 40. The high-frequency input signal is input to the base of the heterojunction bipolar transistor (HBT) 41 through the input capacitor 42. A bias current is supplied to the HBT 41 via the ballast resistor 43. The emitter of HBT41 is grounded. The collector terminal (corresponding to the high-frequency output terminal RFo of FIG. 1A) 44 of the HBT 41 is dropped to the ground GND via the protection circuit 40.

Although the equivalent circuit diagram shown in FIG. 1B shows one circuit unit 45 composed of the HBT 41, the input capacitor 42, and the ballast resistor 43, in practice, a plurality of circuit units 45 of the same configuration are connected in parallel.

The protection circuit 40 includes a plurality of, for example, two diode series circuits 47 connected in parallel. Each of the diode series circuits 47 includes a plurality of, for example, ten protection diodes 48 connected in series. Each protective diode 48 is connected in a clockwise direction from the collector terminal 44 toward the ground GND. The protection circuit 40 does not conduct during normal operation, but conducts when the collector terminal 44 generates a voltage exceeding the allowable upper limit. As a result, a further increase in the voltage generated by the collector terminal 44 is suppressed.

FIG. 2 is a plan view of the output stage amplifier circuit 32 (FIG. 1A). The 16 HBT41s are arranged in a matrix of 4 rows and 4 columns. The eight HBT41s located in the first and second columns constitute the first HBT unit block 49A, and the eight HBT41s located in the third and fourth columns constitute the second HBT unit block 49B. An input capacitor 42 and a ballast resistor 43 are arranged corresponding to each HBT 41. One diode series circuit 47 is arranged with respect to the first HBT cell block 49A, and another diode series circuit 47 is arranged with respect to the second HBT cell block 49B. Each of the diode series circuits 47 includes a protective diode 48.

Next, the configuration of each HBT41 (FIG. 2) will be described with reference to FIGS. 3A and 3B.

FIG. 3A is a top view of HBT41, and FIG. 3B is a cross-sectional view at the one-dot chain line 3B-3B of FIG. 3A. The sub-collector layer 51 is formed on a part of the upper surface of the semi-insulating substrate 50 composed of GaAs. A collector layer 52 is formed on a part of the upper surface of the sub-collector layer 51, and a base layer 53 is formed thereon. An emitter layer 54 is formed on a part of the upper surface of the base layer 53, and an n-type semiconductor layer 55 is formed thereon. A pair of collector electrodes 57 is formed on the upper surface of the sub-collector layer 51, a base electrode 58 is formed on the upper surface of the base layer 53, and an emitter electrode 59 is formed on the n-type semiconductor layer 55. The collector electrode 57 is ohmically connected to the sub-collector layer 51, and the base electrode 58 is ohmically connected to the base layer 53. The emitter electrode 59 is ohmically connected to the emitter layer 54 via the n-type semiconductor layer 55.

As shown in FIG. 3A, the base electrode 58 has a U-shaped shape that surrounds the emitter electrode 59 from three directions in a plan view and opens in one direction (the right direction in FIG. 3A). Font). A pair of collector electrodes 57 are arranged on both sides of the base layer 53 (in FIG. 3A, upper side and lower side).

A collector wiring C1 is formed on each of the pair of collector electrodes 57. The base wiring B1 is formed on the base electrode 58. The base wiring B1 is arranged on the base of the two arms connecting the U-shaped base electrode 58. The base wiring B1 is shown with a broken line in FIG. 3B, which means that the base wiring B1 does not appear in the cross section of FIG. 3B. The base wiring B1 extends in a direction away from the emitter electrode 59 (left direction in FIG. 3A). The emitter wiring E1 is formed on the emitter electrode 59. The emitter wiring E1 extends in a direction away from the base wiring B1 (right direction in FIG. 3A). The collector wiring C1, the base wiring B1, and the emitter wiring E1 are formed of a metal wiring layer of the first layer.

A collector wiring C2 of the second layer is arranged on the collector wiring C1. The collector wiring C2 of the second layer passes through the contact hole provided in the interlayer insulating film and is connected to the collector wiring C1 of the first layer. The collector wiring C2 extends from the portion where the pair of collector wirings C1 are arranged, and extends in the same direction (the right direction in FIG. 3A) as the emitter wiring E1 to be integrated. In FIG. 3B, the broken line shown between the left and right collector wiring C2 means that the collector wiring C2 is integrated at a portion other than the cross section of FIG. 3B.

The back electrode 60 is formed on the back of the substrate 50. The back electrode 60 passes through the through hole penetrating the substrate 50 in a region other than the cross section shown in FIG. 3B and is connected to the emitter wiring E1. In this specification, the “through hole” refers to a hole for connecting the back electrode 60 of the substrate 50 and the conductor layer or wiring on the front side of the substrate 50. In contrast, the “contact hole” refers to a hole for connecting the wiring layer of the first layer and the wiring layer of the second layer.

Next, the configuration of the protective diode 48 (FIG. 2) will be described with reference to FIGS. 4A and 4B.

FIG. 4A is a top view of the protective diode 48, and FIG. 4B is a cross-sectional view at the one-dot chain line 4B-4B of FIG. 4A.

The protective diode 48 is composed of a sub-collector layer 51 formed on the substrate 50, a collector layer 52 formed on a part of the upper surface thereof, and a base layer 53. The pn junction between the collector layer 52 and the base layer 53 functions as a diode.

A cathode electrode 61 is formed on the sub-collector layer 51, and an anode electrode 62 is formed on the base layer 53. The cathode electrode 61 has the same laminated structure as the collector electrode 57 (FIG. 3B). The anode electrode 62 has the same laminated structure as the base electrode 58 (FIG. 3B). Diode wiring D1 is connected to cathode electrode 61 and anode electrode 62, respectively.

In a plan view, the cathode electrode 61 (FIG. 4A) has a U-shaped planar shape sandwiching the base layer 53 in the width direction of the diode row and opening to the right in FIG. 4A. The diode wiring D1 connected to the anode electrode 62 extends in the direction (right direction) in which the cathode electrode 61 opens, and is connected to the cathode electrode 61 of the protection diode 48 adjacent to the right. The diode wiring D1 connected to the cathode electrode 61 extends in a direction (left direction) opposite to the direction in which the cathode electrode 61 opens, and is connected to the anode electrode 62 of the protection diode 48 adjacent to the left.

As shown in FIG. 2, the collector wiring C2 connected to the HBT41 of the first HBT cell block 49A is continuous with the conductor plane in the region disposed between the HBT41 in the first column and the HBT41 in the second column. This conductor plane constitutes a part of collector wiring C2. Below the conductor plane constituting the collector wiring C2, a conductor plane constituting the emitter wiring E1 of the first layer is arranged. This conductor plane is connected to the emitter electrodes 59 (FIG. 3A and FIG. 3B) of eight HBTs 41 included in the first HBT cell block 49A. The conductor plane constituting the emitter wiring E1 passes through the through hole 66 penetrating the substrate 50 and is connected to the back electrode 60 (FIG. 3B).

In the second HBT cell block 49B, the conductor plane constituting the collector wiring C2 and the conductor plane constituting the emitter wiring E1 are similarly arranged.

The high-frequency input wiring 64 is arranged along each column of the HBT 41 and is continuous with the common conductor plane at the end. The high-frequency input wiring 64 is formed of the same wiring layer as the collector wiring C2 of the second layer.

The base wiring B1 of each HBT 41 is connected to the base control wiring 63 via the ballast resistor 43 after crossing the high-frequency input wiring 64. The intersection of the base wiring B1 and the high-frequency input wiring 64 operates as an input capacitor 42 (FIG. 1B). The base control wiring 63 is formed of the same wiring layer as the emitter wiring E1 of the first layer.

The pad conductor layer P2 is arranged adjacent to both the first HBT cell block 49A and the second HBT cell block 49B (in FIG. 2, the lower side). The pad conductor layer P2 is formed by the wiring layer of the second layer and is continuous with the collector wiring C2 of the second layer. A part of the pad conductor layer P2 is used as the pad 65. Specifically, an opening is formed in a part of the protective film covering the pad conductor layer P2, and the portion exposed in the opening corresponds to the pad 65. Here, the "pad conductor layer" means a conductor layer arranged to form a pad, and a wiring conductor for transmitting electrical signals to the pad is not included in the pad conductor layer. For example, the pad conductor layer P2 is composed of a two-dimensionally expanded region where pads can be arranged.

A pair of diode series circuits 47 constituting the protection circuit 40 (FIG. 1B) are arranged below the pad conductor layer P2. One diode series circuit 47 is arranged corresponding to the first HBT cell block 49A, and the other diode series circuit 47 is arranged corresponding to the second HBT cell block 49B. The diode series circuit 47 has a planar shape that is folded back at an intermediate point.

The upstream end of the current flowing in the diode series circuit 47 in the clockwise direction is referred to as an upstream end, and the downstream end is referred to as a downstream end. The diode wiring D1 connected to the cathode electrode 61 (FIGS. 4A and 4B) at the downstream end of the diode series circuit 47 is continuous with the emitter wiring E1. The diode wiring D1 connected to the anode electrode 62 (FIGS. 4A and 4B) at the upstream end of the diode series circuit 47 passes through the contact hole 67 and is connected to the second-layer pad conductor layer P2.

In the first embodiment, the pad conductor layer P2 and the protective diode 48 constituting the protection circuit 40 overlap at least partially in a plan view, and a pad-on-element (POE) structure is adopted.

FIG. 5 is a cross-sectional view at the one-dot chain line 5-5 of FIG. 2. A protective diode 48 is formed on the substrate 50. A pad conductor layer P2 is formed on the interlayer insulating film covering the protective diode 48. The protective film 68 is formed so as to cover the pad conductor layer P2 and other areas on the substrate 50. A part of the upper surface of the pad conductor layer P2 is exposed on the bottom surface of the opening formed in the protective film 68. This exposed portion corresponds to the pad 65. The bonding wire 70 is bonded to the pad 65.

The interlayer insulating film between the wiring layer of the first layer such as the emitter wiring E1 and the substrate 50, and the interlayer insulating film between the wiring layer of the second layer such as the pad conductor layer P2 and the wiring layer of the first layer can be, for example, Using silicon nitride (SiN). For the protective film 68, an insulating resin such as polyimide can be used, for example. In addition, a SiN layer may be disposed on the base of the protective film 68 made of insulating resin.

[Effects of the first embodiment]

Next, the superior effects of the semiconductor device according to the first embodiment will be described in comparison with the semiconductor device based on the comparative example shown in the drawings of FIGS. 22 to 25.

22 to 25 are plan views of semiconductor devices based on comparative examples. In the description of the comparative example, the description of the configuration common to the semiconductor device according to the first embodiment is omitted.

In the comparative example shown in FIG. 22, a pad conductor layer P1 composed of a wiring layer of the first layer is arranged below the pad conductor layer P2. The pad conductor layer P1 of the first layer and the pad conductor layer P2 of the second layer are connected to each other through the contact hole 69 provided in the interlayer insulating film disposed therebetween. The pad conductor layer P1 of the first layer and the pad conductor layer P2 of the second layer have almost the same planar shape, and the contact hole 69 has a slightly smaller planar shape than the pad conductor layers P1 and P2.

Since the pad conductor layer P1 of the first layer is disposed under the pad conductor layer P2 of the second layer, the protection circuit 40 and the pad including the diode wiring D1 composed of the conductor layer of the first layer cannot be connected The conductor layers P2 are arranged to overlap. Therefore, the protection circuit 40 is arranged between the first HBT cell block 49A and the pad conductor layer P2 and between the second HBT cell block 49B and the pad conductor layer P2. As in the case of the first embodiment, the protection circuit 40 is composed of two diode series circuits 47, and each of the diode series circuits 47 has a planar shape folded back at an intermediate point. The collector wiring C2 and the pad conductor layer P2 are connected via a connection wiring Q2 constituted by a wiring layer of the second layer. The connection wiring Q2 and the protection circuit 40 partially overlap.

The connection structure of the diode wiring D1 and the emitter wiring E1 connected to the cathode electrode 61 (FIGS. 4A and 4B) at the downstream end of the protection circuit 40 is the same as the connection structure of the semiconductor device according to the first embodiment (FIG. 2) . The diode wiring D1 connected to the anode electrode 62 (FIGS. 4A and 4B) at the upstream end of the protection circuit 40 is continuous with the pad conductor layer P1 of the first layer.

In the comparative example shown in FIG. 23, the protection circuit 40 is composed of one diode series circuit. The other configuration is the same as the configuration of the comparative example shown in FIG. 22. The diode series circuit is not folded back but extends along a straight line. The direction in which the diode series circuit extends is parallel to the row direction of the HBT 41 arranged in a matrix of 4 rows and 4 columns.

The diode wiring D1 connected to the cathode electrode 61 at the downstream end of the protection circuit 40 is continuous with the emitter wiring E1 of the second HBT cell block 49B. The protection circuit 40 is not directly connected to the emitter wiring E1 of the first HBT cell block 49A, but is connected via the back electrode 60 (FIGS. 3B, 4B, and 5). The diode wiring D1 connected to the anode electrode 62 at the upstream end of the protection circuit 40 is continuous with the pad conductor layer P1 of the first layer.

In any of the comparative examples of FIGS. 22 and 23, the protection circuit 40 is disposed between the first HBT cell block 49A and the pad conductor layer P2 and between the second HBT cell block 49B and the pad conductor layer P2.

In the comparative example shown in FIG. 24, the protection circuit 40 is arranged adjacent to the first HBT cell block 49A in the row direction (left direction in FIG. 24).

The diode wiring D1 connected to the anode electrode 62 at the upstream end of the protection circuit 40 is continuous with the pad conductor layer P1 of the first layer. The protection circuit 40 extends in the column direction (upward direction in FIG. 24) from the connection position with the pad conductor layer P1 and reaches a position exceeding the upper end of the first HBT cell block 49A. The diode wiring D1 connected to the cathode electrode 61 at the downstream end of the protection circuit 40 passes through the contact hole 74 and is connected to the second-layer connection wiring J2 and is connected to the emitter wiring E1 of the first HBT cell block 49A via the connection wiring J2 connection. The emitter wiring E1 of the second HBT cell block 49B is connected to the protection circuit 40 via the back electrode 60 (FIGS. 3B, 4B, and 5).

Between the protection circuit 40 and the emitter wiring E1 of the first HBT cell block 49A, the base control wiring 63 of the first layer and the high-frequency input wiring 64 of the second layer are arranged. Therefore, it is impossible to connect the cathode electrode 61 on the downstream end of the protection circuit 40 and the emitter wiring E1 with a short wiring length using the wiring layer of the first layer or the second layer. In the comparative example shown in FIG. 24, the connection wiring J2 extends from the position of the contact hole 74 along the diode row of the protection circuit 40 to the area between the first HBT cell block 49A and the pad conductor layer P2. Then, the connection wiring J2 is connected to the emitter wiring E1 between the first HBT cell block 49A and the pad conductor layer P2. Since the emitter wiring E1 and the protection circuit 40 are connected via a long connection wiring J2, the influence of parasitic inductance increases.

In the comparative example shown in FIG. 25, the cathode electrode 61 at the downstream end of the protection circuit 40 passes through the through hole 71 and is connected to the back electrode 60 (FIG. 3B, FIG. 4B, and FIG. 5) to be grounded.

In any of the comparative examples shown in FIGS. 22 to 25, the pad conductor layer P2 and the protection circuit 40 are not overlapped, but the surfaces of the respective substrates 50 (FIGS. 3B, 4B, and 5) are proprietary. On the other hand, in the first embodiment (FIG. 2), the pad conductor layer P2 and the protection circuit 40 are arranged at least partially overlapping. Therefore, compared to these comparative examples, the wafer area can be reduced.

In the comparative examples of FIGS. 22 and 23, the protection circuit 40 is disposed between the first HBT cell block 49A and the pad conductor layer P2 and between the second HBT cell block 49B and the pad conductor layer P2. Therefore, the connection wiring Q2 connecting the pad conductor layer P2 and the collector wiring C2 increases. The parasitic resistance caused by the connection wiring Q2 is inserted in series into the collector circuit of the HBT41 (FIG. 1B). In the first embodiment (FIG. 2), since the pad conductor layer P2 is arranged adjacent to the first HBT cell block 49A and the second HBT cell block 49B, the wiring connecting the pad conductor layer P2 and the collector wiring C2 can be shortened. Therefore, it is possible to suppress the performance degradation of the amplifier circuit caused by the increase in the parasitic resistance of the collector circuit inserted into the HBT41 (FIG. 1B).

In the comparative example of FIG. 24, the parasitic inductance caused by the connection wiring J2 is inserted into the protection circuit 40 in series. If the parasitic inductance increases, especially in the high-frequency band, the responsiveness becomes poor, so the protection function will decrease. In the first embodiment, long wiring with a large parasitic inductance is not used for the connection of the protection circuit 40. Therefore, it is possible to suppress a decrease in the protection function of the protection circuit 40.

In the comparative example of FIG. 25, it is necessary to newly secure a region for arranging the through hole 71 for connecting the protection circuit 40 and the back electrode 60 (FIG. 3B, FIG. 4B, and FIG. 5). Therefore, the wafer size is further increased relative to the comparative example of FIG. 24. In the first embodiment, since there is no need to provide such a through hole 71, it is possible to avoid the increase in the size of the wafer.

Furthermore, in the first embodiment, one diode series circuit 47 is connected to the emitter wiring E1 of the first HBT cell block 49A, and the other diode series circuit 47 is connected to the emitter wiring E1 of the second HBT cell block 49B . Therefore, in the first HBT cell block 49A and the second HBT cell block 49B, the protection circuit 40 is well-balanced.

Also, by folding back each of the two diode series circuits 47 at the intermediate point, it is possible to eliminate the protrusion of the diode series circuit 47 from the pad conductor layer P2 or reduce the area of the protrusion. Therefore, even if two diode series circuits 47 are arranged, it does not hinder the miniaturization of the wafer size.

Next, with reference to FIGS. 26A and 26B, the effect of using the planar diode shown in FIG. 4A as the protective diode 48 (FIG. 2) will be described.

FIG. 26A is a schematic diagram of the protection circuit 40 viewed from above. Ten protection diodes 48 are connected in series. Each of the protective diodes 48 includes an n-type sub-collector layer 51 (FIGS. 4A and 4B), and a p-type base layer 53 disposed inside the sub-collector layer 51 in a plan view. FIG. 26A shows the conductivity type of the uppermost surface of the stacked semiconductor layers. When focusing on the uppermost surface of the semiconductor layer, the n-type region of the sub-collector layer 51 surrounds the p-type region of the base layer 53 from three directions. Therefore, in the width direction of the diode column, n-type regions are arranged on both sides of the p-type region.

The base layer 53 of the protection diode 48 at the upstream end of the clockwise current flowing in the diode column is connected to the collector terminal 44, and the sub-collector layer 51 of the protection diode 48 at the downstream end is connected to the ground GND (Figure 1B) connection.

26B is a schematic diagram of a plan view of a protection circuit based on a comparative example. In the comparative example, the p-type base layer 53 is arranged to be biased toward one side in the width direction of the diode column. The diode array is folded back halfway, and the two protective diodes 48 approach in the width direction. In the comparative example shown in FIG. 26B, the p-type region of the protection diode 48 at the upstream end and the n-type region of the protection diode 48 at the downstream end face each other and are close to each other. With this configuration, when a high voltage is applied to the collector terminal 44 from the outside, it is known that electrostatic discharge is likely to occur between the protection diode 48 at the upstream end and the protection diode 48 at the downstream end (refer to International Publication No. 2016/047217). If an electrostatic discharge occurs, the protective diode 48 will be destroyed.

In the first embodiment, between the p-type region of the protection diode 48 at the upstream end and the n-type region of the protection diode 48 at the downstream end, there is an n-type region of the protection diode 48 at the upstream end. Thus, the p-type region of the protection diode 48 at the upstream end and the n-type region of the protection diode 48 at the downstream end do not face each other. Therefore, it becomes difficult to generate electrostatic discharge when a high voltage is applied, and it is possible to suppress the destruction of the protective diode 48.

In the first embodiment, although the U-shaped cathode electrode 61 configured to protect the diode 48 surrounds the p-type region from three directions, the reverse may be configured such that the anode electrode 62 is U-shaped and the anode electrode 62 is separated from Three directions surround the n-type region.

As another effect, since the semiconductor device based on the first embodiment is composed of a compound semiconductor, the operating frequency can be increased compared to a silicon-based semiconductor device.

[Second Embodiment]

Next, the semiconductor device according to the second embodiment will be described with reference to FIGS. 6 and 7. Hereinafter, a description of the configuration common to the configuration of the semiconductor device according to the first embodiment will be omitted.

6 is an equivalent circuit diagram of the output stage amplifier circuit 32 (FIG. 1A) and the protection circuit 40 of the semiconductor device according to the second embodiment. In the first embodiment, the protection circuit 40 is composed of two diode series circuits 47, but in the second embodiment, the protection circuit 40 is composed of one diode series circuit.

7 is a plan view of the semiconductor device according to the second embodiment. In the first embodiment, as shown in FIG. 2, a diode series circuit 47 is connected to the emitter wiring E1 of the first HBT cell block 49A and the emitter wiring E1 of the second HBT cell block 49B, respectively. In contrast, in the second embodiment, the protection circuit 40 is connected only to the emitter wiring E1 of the second HBT cell block 49B, and the protection circuit 40 is not directly connected to the emitter wiring E1 of the first HBT cell block 49A. The emitter wiring E1 of the first HBT cell block 49A is connected to the protection circuit 40 via the back electrode 60 (FIGS. 3B, 4B, and 5) and the emitter wiring E1 of the second HBT cell block 49B.

In the second embodiment, a plurality of protection diodes 48 constituting the protection circuit 40 are arranged along one straight line. The arrangement direction is parallel to the direction from the second HBT unit block 49B toward the first HBT unit block 49A.

In the second embodiment, the protection circuit 40 and the pad conductor layer P2 also overlap, and the POE structure is also adopted. Therefore, the same effect as the first embodiment can be obtained in the second embodiment.

In the second embodiment, since only the emitter wiring E1 of the second HBT cell block 49B is directly connected to the protection circuit 40, the protection effect cannot be balanced between the HBT41 of the first HBT cell block 49A and the HBT41 of the second HBT cell block 49B. In order to protect the HBT41 of the first HBT cell block 49A and the HBT41 of the second HBT cell block 49B in a balanced manner, the configuration of the first embodiment is preferably adopted as compared with the configuration of the second embodiment.

However, in the first embodiment, the number of protection diodes 48 constituting the protection circuit 40 is twice the number of protection diodes 48 constituting the protection circuit 40 in the second embodiment. Therefore, it is sometimes difficult to converge the entire area of the protection circuit 40 inside the pad conductor layer P2 (FIG. 2). In the second embodiment, it is easy to converge the entire area of the protection circuit 40 inside the pad conductor layer P2. In this way, the second embodiment is more advantageous than the first embodiment from the viewpoint of shrinking the wafer.

[Third Embodiment]

Next, the semiconductor device according to the third embodiment will be described with reference to FIG. 8. Hereinafter, a description of the configuration common to the configuration of the semiconductor device according to the second embodiment will be omitted.

8 is a plan view of a semiconductor device according to a third embodiment. In the second embodiment, a plurality of protection diodes 48 constituting the protection circuit 40 (FIG. 7) are arranged along one straight line. In the third embodiment, the diode array composed of the plurality of protection diodes 48 constituting the protection circuit 40 is folded back halfway. The turn-back point need not be the middle point of the diode array.

In the third embodiment, the protection circuit 40 also overlaps the pad conductor layer P2. Therefore, the same effect as the second embodiment can be obtained. Furthermore, since the diode row can be folded back at an arbitrary position, the degree of freedom of the position for connecting the anode electrode 62 at the upstream end of the protection circuit 40 to the contact hole 67 of the pad conductor layer P2 is improved.

Since the opening of the pad 65 serves as an intrusion path for moisture, it is preferable that the contact hole 67 avoid the pad 65. In the third embodiment, the degree of freedom of the position of the contact hole 67 is improved, thereby making it easier for the contact hole 67 to avoid the pad 65.

In the case where a film insulating resin film is used as the interlayer insulation in order to flatten the base surface of the pad conductor layer P21, the flatness of the upper surface of the pad conductor layer P2 deteriorates at the location where the contact hole 67 is arranged . In order to ensure the flatness of the surface of the pad conductor layer P2 in the pad 65, it is preferable to arrange the contact hole 67 so as not to overlap the pad 65. In the third embodiment, since the degree of freedom of the position of the contact hole 67 is improved, it is easy to arrange the contact hole 67 so as not to overlap the pad 65.

[Modifications of the first, second, and third embodiments]

Next, modifications of the first, second, and third embodiments will be described.

9 is a plan view of a protection diode 48 constituting a protection circuit 40 of a semiconductor device according to a modification. Hereinafter, the top view of the protective diode 48 shown in FIG. 4A will be described after comparison. In the protective diode 48 shown in FIG. 4A, the cathode electrode 61 surrounds the base layer 53 from three directions. On the other hand, in the modification shown in FIG. 9, the cathode electrode 61 is arranged adjacent to the base layer 53 in the direction in which the diode row extends in a plan view.

An anode electrode 62 is formed on the upper surface of the base layer 53. The diode wiring D1 connected to the anode electrode 62 and the diode wiring D1 connected to the cathode electrode 61 extend in mutually opposite directions.

In the modification shown in FIG. 9, compared with the embodiment shown in FIG. 4A, the width of the diode wiring D1 can be widened. Therefore, an increase in the parasitic inductance caused by the diode wiring D1 can be suppressed.

In addition, in the modification shown in FIG. 9, there may be a p-type region of the protection diode 48 located at the upstream end of the clockwise current and a protection diode 48 located at the downstream end shown in the comparative example of FIG. 26B. The n-type area is arranged face to face. In the case of a configuration in which the diode array is folded back, in order to suppress the situation in which the protection diode 48 is destroyed when a high voltage is applied, attention needs to be paid to the arrangement of the protection diode 48.

10 is a cross-sectional view of a pad portion of a semiconductor device according to a modification. Hereinafter, it will be described in comparison with the cross-sectional view of the pad portion shown in FIG. 5. In the first embodiment shown in FIG. 5, the interlayer insulating film between the first-layer wiring layer such as the emitter wiring E1 and the second-layer wiring layer such as the pad conductor layer P2 uses an inorganic insulating film such as SiN. In the modification shown in FIG. 10, the interlayer insulating film between the wiring layer of the first layer and the wiring layer of the second layer has a two-layer structure of an inorganic insulating film 72 and an insulating resin film 73. For the insulating resin film 73, for example, polyimide or the like can be used.

In the modification shown in FIG. 10, the upper surface of the insulating resin film 73, that is, the base surface of the pad conductor layer P2 can be made flat. Furthermore, the impact when the bonding wire 70 is bonded to the pad 65 becomes difficult to be transmitted to the semiconductor element directly below, so that the destruction of the element due to the impact at the time of bonding can be suppressed.

[Fourth embodiment]

Next, the semiconductor device according to the fourth embodiment will be described with reference to the drawings of FIGS. 11 to 13. Hereinafter, a description of the configuration common to the configuration of the semiconductor device according to the first embodiment will be omitted. Although the semiconductor device according to the first embodiment is for upward mounting, the semiconductor device according to the fourth embodiment is for downward mounting.

11 is a plan view of a semiconductor device according to a fourth embodiment. The emitter wiring E1 of the first layer is arranged for each emitter electrode 59 (FIG. 3B) of the plurality of HBTs 41. The emitter wiring E2 of the second layer is arranged for each column of the HBT 41 arranged in a matrix of 4 rows and 4 columns. The emitter wiring E2 is connected to the emitter electrode 59 of the HBT 41 via the emitter wiring E1 directly below.

One collector wiring C1 of the first layer is arranged with respect to the eight HBTs 41 of the first HBT cell block 49A. A second layer of collector wiring C2 is arranged between the emitter wiring E2 corresponding to the first column and the emitter wiring E2 corresponding to the second column. The collector wiring C2 passes through the contact hole 75 and is connected to the collector wiring C1 directly below. The collector wiring C2 is continuous with the pad conductor layer P2. The emitter wiring E2 corresponding to the second column is drawn out to an area that does not overlap the collector wiring C1 of the first layer, passes through the contact hole 74, and is connected to the diode wiring D1 of the first layer.

The configurations of the emitter wirings E1 and E2 and the collector wirings C1 and C2 corresponding to the second HBT cell block 49B are also the same as the configurations of the emitter wirings E1 and E2 and the collector wirings C1 and C2 corresponding to the first HBT cell block 49A.

A bump 77 for grounding is disposed on the emitter wiring E2, and a bump 78 for high-frequency output is disposed on the pad conductor layer P2. FIG. 11 shows an example in which two bumps 78 are arranged on the pad conductor layer P2, but the number of bumps 78 is not limited to two. The number of bumps 78 may be one or three or more.

FIG. 12 is a schematic cross-sectional view of a portion corresponding to one HBT48. In the first embodiment, the collector wiring C2 of the second layer is arranged directly above the collector wiring C1 (FIG. 3B) of the first layer. However, in the fourth embodiment, the collector wiring C1 of the first layer The collector wiring C2 of the second layer is not arranged directly above. Instead, the emitter wiring E2 of the second layer is arranged directly above the emitter wiring E1 of the first layer.

A bump 77 for grounding is arranged on the emitter wiring E2. The bump 77 has, for example, a laminated structure in which an Au layer 77A and a solder layer 77B are laminated.

13 is a cross-sectional view of a portion where bumps 78 for high-frequency output are formed. The protective diode 48 constituting the protective circuit 40 (FIG. 1B) is covered with an interlayer insulating film composed of an inorganic insulating film 72 and an insulating resin film 73. Above the protective diode 48, a pad 65 composed of a part of the pad conductor layer P2 is arranged. A bump 78 for high-frequency output is arranged on the pad 65. The bump 78 has a two-layer structure in which an Au layer 78A and a solder layer 78B are laminated.

[Effects of the fourth embodiment]

Next, the excellent effects of the fourth embodiment will be described. In the fourth embodiment, the POE structure in which the protection circuit 40 overlaps the pad conductor layer P2 as shown in FIG. 9 is also adopted. Therefore, the same effect as in the case of the first embodiment can be obtained. For example, the wafer size can be reduced. In addition, since the increase in the parasitic inductance inserted into the protection circuit 40 in series can be suppressed, it is possible to suppress the decrease in the protection function in the high-frequency band. Furthermore, since the increase in the parasitic resistance of the collector circuit inserted in series in the HBT 41 can be suppressed, it is possible to suppress the decrease in the performance of the output stage amplifier circuit.

[Modification of Fourth Embodiment] Next, referring to the drawings of FIGS. 14 to 16, a semiconductor device according to various modifications of the fourth embodiment will be described. 14 is a plan view of a semiconductor device according to a first modification of the fourth embodiment. In the fourth embodiment, as shown in FIG. 9, protection circuits 40 are arranged for the first HBT cell block 49A and the second HBT cell block 49B, respectively. On the other hand, in the modification of the fourth embodiment shown in FIG. 14, the protection circuit 40 is arranged only for the second HBT cell block 49B, and the protection circuit 40 is not arranged for the first HBT cell block 49A.

The emitter wiring E2 of the first HBT cell block 49A is connected to the protection circuit 40 via the ground conductor in the module substrate and the emitter wiring E2 of the second HBT cell block 49B in a state of being mounted downward on the module substrate. In addition, in a modification of the fourth embodiment, the diode rows of the protection circuit 40 are arranged along one straight line. However, the diode array of the protection circuit 40 may be folded like the protection circuit 40 of the third embodiment (FIG. 8).

15 is a plan view of a semiconductor device according to a second modification of the fourth embodiment. In the fourth embodiment, as shown in FIG. 11, the planar shapes of the bump 77 for grounding and the bump 78 for high-frequency output are rectangular. On the other hand, in the second modification, as shown in FIG. 15, the planar shapes of the bump 77 and the bump 78 are rounded rectangles having four corners of the rectangle with rounded corners. For example, the planar shapes of the bump 77 and the bump 78 have a racetrack-shaped outer peripheral line composed of two parallel lines of equal length and two half circles connecting the two parallel lines.

In the fourth embodiment, as shown in FIGS. 12 and 13, the bump 77 is composed of the Au layer 77A and the solder layer 77B, and the bump 78 is composed of the Au layer 78A and the solder layer 78B. In contrast, in the second modification, a Cu layer (Cu pillar) can be used instead of the Au layer 77A and the Au layer 78A. The bumps including the Cu pillar and the solder layer disposed on the upper surface are called Cu pillar bumps. In FIGS. 12 and 13, the cross-sectional shapes of the solder layers 77B and 78B are represented by rectangles. However, after the solder reflow process, the side surfaces and upper surfaces of the solder layers 77B and 78B are smoothly continuous and bulge upward. Surface.

16 is a plan view of a semiconductor device according to a third modification of the fourth embodiment. In the third modification, the planar shapes of the bump 77 for grounding and the bump 78 for high-frequency output according to the semiconductor device (FIG. 14) of the first modification are rounded rectangles. In addition, the bumps 77 and 78 can use Cu stud bumps in the same manner as the second modification (FIG. 15).

In the first modification, the second modification, and the third modification of the fourth embodiment, the same excellent effects as the fourth embodiment can be obtained. In addition, if the planar shapes of the bumps 77 and 78 are rounded rectangles as in the semiconductor devices based on the second modification and the third modification, the bumps can be processed stably to form projections almost the same as the mask shape of the bumps Piece.

[Fifth Embodiment]

Next, the semiconductor device according to the fifth embodiment will be described with reference to FIG. 17. Hereinafter, the configuration common to the configuration of the semiconductor device according to the fourth embodiment shown in FIGS. 11, 12, and 13 will not be described.

17 is a cross-sectional view of a semiconductor device according to a fifth embodiment. In the fourth embodiment, the emitter wiring E2 of the second layer is arranged right above the HBT 41 for each column of the HBT 41 (FIG. 11). On the other hand, in the fifth embodiment, as shown in FIG. 17, the collector wiring C2 of the second layer is arranged right above the HBT 41 for each column of the HBT 41. The collector wiring C2 is connected to the collector electrode 57 (FIG. 3B) of the HBT 41 via the collector wiring C1 of the first layer.

One emitter wiring E1 of the first layer is arranged for the eight HBTs 41 of the first HBT cell block 49A. The emitter wiring E2 of the second layer is arranged between the collector wiring C2 corresponding to the first column and the collector wiring C2 corresponding to the second column. The emitter wiring E2 passes through the contact hole 76 of the interlayer insulating film provided thereunder and is connected to the emitter wiring E1 of the first layer.

The configurations of the emitter wirings E1 and E2 and the collector wirings C1 and C2 corresponding to the second HBT cell block 49B are the same as the configurations of the emitter wirings E1 and E2 and the collector wirings C1 and C2 corresponding to the first HBT cell block 49A .

The emitter wiring E2 of the first HBT cell block 49A and the second HBT cell block 49B is continuous with the pad conductor layer P2. Among the collector wiring C1 of the first layer of the HBT41 in the second column, the collector wiring C1 disposed closest to the pad conductor layer P2 is connected to the anode electrode 62 at the upstream end of the protection circuit 40. The polar body wiring D1 is continuous. The diode wiring D1 connected to the cathode electrode 61 at the downstream end of the protection circuit 40 passes through the contact hole 79 and is connected to the pad conductor layer P2.

A bump 81 for grounding is disposed on the pad conductor layer P2, and a bump 82 for high-frequency output is disposed on the collector wiring C2 of the second layer. In the fourth embodiment, although the bumps 78 (FIG. 11) for high-frequency output are superimposed on the protection circuit 40, the bumps 81 for grounding may be superimposed on the protection circuit 40 as in the fifth embodiment.

[Modification of the fifth embodiment]

Next, a semiconductor device according to a modification of the fifth embodiment will be described with reference to FIG. 18.

18 is a plan view of a semiconductor device according to a modification of the fifth embodiment. In the semiconductor device according to the fifth embodiment, the planar shapes of the bump 81 for grounding and the bump 82 for high-frequency output (FIG. 17) are rectangular. On the other hand, in this modification, the planar shapes of the bumps 81 and 82 are rectangular with rounded corners. In addition, Cu bumps 81 and 82 can use Cu stud bumps. Even in the case where the bump 81 for ground is superposed on the protection circuit 40 as in the fifth embodiment, as the bumps 81 and 82, Cu pillar bumps having a planar shape with rounded rectangles can be used.

[Influence of parasitic inductance]

Next, the influence of the parasitic inductance inserted into the protection circuit 40 (FIG. 1B) in series will be described with reference to the drawings of FIGS. 19A to 20B. The influence of the parasitic inductance inserted into the protection circuit 40 (FIG. 1B) in series is determined by analogy.

FIG. 19A is an equivalent circuit diagram of an output stage amplifier circuit that becomes an analog object. A protection circuit 40 is connected between the collector terminal 44 and the ground GND. The protection circuit 40 is composed of ten protection diodes 48 connected in series so that the current flowing from the collector terminal 44 to the ground GND is clockwise. It is assumed that the parasitic inductance Lc is inserted between the protection circuit 40 and the collector terminal 44 and the parasitic inductance Le is inserted between the protection circuit 40 and the ground GND.

An analogy of the output voltage was made by setting the input power to the output stage amplifier circuit to 3 dBm, the power supply voltage to 3.4 V, and the frequency of the high-frequency signal to 2.5 GHz to vary the load of the output stage amplifier circuit.

FIG. 19B is a graph showing the analog result of the waveform of the output voltage. The horizontal axis represents the elapsed time in units of "ps", and the vertical axis represents the output voltage. One waveform can be obtained relative to a certain load, and a plurality of waveforms can be obtained corresponding to various loads. It can be seen that when the load changes, the peak value of the output voltage also changes. The voltage value when the peak value of the output voltage reaches the maximum when the load changes is referred to as the maximum peak voltage. By changing the parasitic inductances Lc and Le, the maximum peak voltage is calculated. The maximum peak voltage when the parasitic inductances Lc and Le are both 0 is used as a reference, and the calculated maximum peak voltage is standardized.

20A is a graph showing the normalized maximum peak voltage when the parasitic inductance Le is set to 0 and the parasitic inductance Lc is changed. 20B is a graph showing the normalized maximum peak voltage when the parasitic inductance Lc is set to 0 and the parasitic inductance Le is changed. It can be seen that in any case, the normalized maximum peak voltage increases as the parasitic inductances Lc and Le increase. The increase in the standardized maximum peak voltage means that the protection function of the protection circuit 40 decreases. This is because the parasitic inductances Lc and Le degrade the response characteristics of the protection circuit 40. In order to maintain a sufficient protection function of the protection circuit 40, it is preferable to reduce the parasitic inductances Lc and Le.

In the above-described first to fifth embodiments, the distance from the protection circuit 40 to the collector electrode 57 (FIG. 3B) of the HBT 41 and the emitter electrode 59 (FIG. 3B) from the protection circuit 40 to the HBT 41 can be avoided The protection circuit 40 is arranged to increase the distance up to. Therefore, it is possible to suppress an increase in the parasitic inductances Lc and Le and maintain a sufficient protection function.

[Influence of parasitic resistance]

Next, referring to FIGS. 21A and 21B, the simulation results of the input power and output power when the parasitic resistance Rc of the collector wiring of the HBT 41 changes will be described.

21A is an equivalent circuit diagram of an amplification circuit of an analog object. It is assumed that the parasitic resistance Rc is inserted between the collector and collector terminal 44 of the HBT 41. The parasitic resistance Rc is increased in units of 20 mΩ, and the relationship between input power and output power is solved by analogy. Set the frequency of the input signal to 2.5GHz and the power supply voltage to 3.4V.

21B is a graph showing the results of the analogy. The horizontal axis represents the input power in units of "dBm", and the vertical axis represents the output power in units of "dBm". It can be seen that the output power decreases as the parasitic resistance Rc increases. The reason for the decrease in output power is based on the following reasons. When the power is large, the collector current flows, and a voltage drop occurs in the parasitic resistance Rc. Due to this voltage drop, the collector voltage Vce of the effective HBT41 will drop. As a result, the output power drops. In order to suppress the decrease in output power, it is preferable to reduce the parasitic resistance Rc.

In the first to fifth embodiments described above, the HBT 41 and the pad 65 for the collector terminal can be arranged close to each other. Therefore, an increase in parasitic resistance Rc can be suppressed. As a result, it is possible to suppress the performance degradation of the output stage amplifier circuit.

The above embodiments are examples, and there is no doubt that partial replacement or combination of the configurations shown in the different embodiments can be realized. The same operation and effect based on the same configuration of a plurality of embodiments are not described individually for each embodiment. Furthermore, the present invention is not limited to the above-mentioned embodiments. For example, various changes, improvements, combinations, etc. can be realized, which are obvious to those having ordinary knowledge in the technical field.

Claims (8)

    A semiconductor device includes: an amplifier circuit including a semiconductor element formed on a substrate; a protection circuit including a plurality of protection diodes formed on the substrate and connected in series with each other, and connected to an output terminal of the amplifier circuit; At least a portion of the pad conductor layer includes a pad for connection to an external circuit of the substrate, and the pad conductor layer and the protection circuit at least partially overlap in a plan view.         The semiconductor device according to claim 1, wherein the semiconductor device further has a ground conductor formed on the substrate, and the protection circuit is connected between the output terminal of the amplifier circuit and the ground conductor.         The semiconductor device according to claim 1 or 2, wherein the semiconductor device further has an insulating protective film that covers the pad conductor layer and is provided such that part of the surface of the pad conductor layer The area is exposed and covers other areas. In a plan view, the opening and the protection circuit at least partially overlap.         The semiconductor device according to claim 3, wherein the semiconductor device further has bumps formed on the pad conductor layer on the bottom surface of the opening.         The semiconductor device according to claim 4, wherein the planar shape of the bump is a rectangle with rounded corners.         The semiconductor device according to claim 1 or 2, wherein a plurality of the protection diodes constitute a diode row folded back halfway in a plan view, and a part of the protection circuit is arranged on the pad The outer side of the conductor layer.         The semiconductor device according to claim 1 or 2, wherein the plurality of protection diodes constitute a diode row that is folded back halfway in a plan view, and each of the plurality of protection diodes includes: A first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on a part of the upper surface of the first semiconductor layer, and the second conductivity type and the first conductivity type Conversely; and the first electrode ohmically connected to the upper surface of the first semiconductor layer, in a plan view, the first electrode has a U sandwiching the second semiconductor layer in the width direction of the diode row The flat shape of the glyph.         The semiconductor device according to claim 1 or 2, wherein the semiconductor element is formed of a compound semiconductor.