TW201901457A - Method of controlling on-die termination and system performing the same - Google Patents

Abstract

A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

Description

Method for controlling intra-grain termination and system for performing the same

The exemplary embodiments are generally related to semiconductor integrated circuits, and more particularly to a method of controlling on-die termination (ODT) and a system for performing the method. [Cross-Reference to Related Applications] This non-provisional application in the United States is based on 35 USC § 119, which is filed on May 29, 2017, and is filed on July 14, 2017. The priority of the Korean Patent Application No. 10-2017-0089692, the entire disclosure of which is incorporated herein by reference.

The intra-die termination (ODT) is introduced to enhance signal integrity by reducing signal reflection between the transmitter and the receiver. The intra-die termination circuit can reduce signal reflection by providing a termination resistance that matches the impedance of the transmission line. However, if a die within the die is implemented to enhance signal integrity, power consumption may increase.

At least one embodiment of the inventive concept provides a method of controlling a intra-die terminal capable of reducing power consumption and enhancing signal integrity.

At least one embodiment of the inventive concept provides a system for performing a method of controlling an intra-die terminal capable of reducing power consumption and enhancing signal integrity.

In accordance with an exemplary embodiment of the inventive concept, a method of controlling an intra-die termination (ODT) in a multi-row system including a plurality of memory banks, the method comprising: when the multi-row memory system is When energized, the in-die termination circuit of the plurality of memory banks is enabled to an initial state; during the writing operation, the plurality of memory banks are written into the die of the target memory bank The in-die termination circuit of the termination circuit and the non-target memory bank is enabled; and the intra-die termination circuit of the read target memory bank of the plurality of memory banks during a read operation The enabling, while enabling the intra-die termination circuit of the non-target memory banks of the plurality of memory banks.

In accordance with an exemplary embodiment of the inventive concept, a method of controlling an intra-die termination (ODT) in a memory device includes: in-grain termination circuitry of the memory device when the memory device is powered Having an initial state to have a first resistance value; energizing the intra-die termination circuit during a write operation to the memory device; and during a read operation on the memory device The termination circuit in the die is de-energized.

According to an exemplary embodiment of the inventive concept, a system includes: a plurality of memory banks including a plurality of memory devices; and a memory controller configured to control the plurality of memory banks. An intra-die termination (ODT) circuit of the plurality of memory banks is enabled to be in an initial state when the system is powered, and the intra-gate termination circuit of the plurality of memory banks is in the plurality of The write target memory bank and the non-target memory bank in the memory bank are enabled during a write operation, and during the read operation, the read target memory banks in the plurality of memory banks are read The intra-die termination circuitry is disabled, and the intra-die termination circuitry of the non-target memory banks of the plurality of memory banks is enabled.

According to an exemplary embodiment of the inventive concept, a system includes a first memory bank and a second memory bank. The first memory bank includes a plurality of first memory devices coupled to a first intra-die termination (ODT) circuit. The second memory bank includes a plurality of second memory devices connected to the termination circuitry in the second die. The first intra-gate termination circuit and the second intra-die termination circuit are enabled during a write operation of the first memory bank and during a read operation of the first memory bank The first intra-gate termination circuit is disabled and the second intra-die termination circuit is enabled.

A method of controlling a terminal within a die according to an exemplary embodiment and a system for performing the same can reduce power consumption and enhance signal integrity by performing static intra-die terminal control so as to be during a read operation The intra-gate termination circuit of the target memory bank and the intra-die termination circuit of the non-target memory bank are generally maintained in an enabled state, and the intra-die termination circuit of the read target memory bank is disabled.

The above described features and advantages of the invention will be apparent from the following description.

In the following, the inventive concept will be more fully explained with reference to the accompanying drawings in which FIG. The same reference numbers in all figures refer to the same elements.

1 is a flowchart illustrating a method of controlling an intra-die terminal (ODT) according to an exemplary embodiment of the inventive concept, and FIG. 2 is a flowchart illustrating a method of controlling a terminal within a die according to an exemplary embodiment of the inventive concept. Timing diagram.

1 and 2 illustrate a method of controlling a terminal within a die in a multi-row system including a plurality of memory ranks. A multi-row system will be explained below with reference to FIG. In an embodiment, the memory bank is a set of memory chips connected to the same wafer select signal. Thus, when there are multiple banks of memory, each bank of memory receives a different wafer select signal. In yet another embodiment, the set of memory chips for a given bank of memory share the same command and control signals.

Referring to FIG. 1, when the multi-row system is energized, the intra-die termination circuits of the plurality of memory banks are energized to an initial state (S100). For example, the enabling of the intra-die termination circuit to an initial state can be performed by applying power to the intra-die termination circuit and setting the resistance of each of the intra-die termination circuits to be the same. The resistance value. The intra-die termination circuits of the plurality of memory banks are enabled during a write operation to the write target memory banks in the plurality of memory banks (S200). For example, if an intra-gate termination circuit currently in the intra-die termination circuit of the memory bank is currently de-energized due to a previous read operation of the memory bank, then the write is performed. The termination circuit in this die is energized during the entry. In addition, the intra-die termination circuit that is currently the write target of the memory bank can be enabled for a period of time prior to actual writing. The intra-grain termination circuit of the read target memory bank in the plurality of memory banks is disabled during a read operation on the read target memory bank (S300).

The memory access operations may include write operations and read operations and the memory access operations may be distinguished from other operations such as mode register write operations, mode register read operations, refresh operations, and the like. In the case of a write operation, the plurality of memory banks can be divided into a write target memory bank that is an object of a write operation and a non-target memory bank that is excluded from the write target memory. For example, during a write operation, data is written to one of a plurality of memory banks (ie, written to a target memory bank) and the material is not written to the remaining memory banks. In the case of a read operation, the plurality of memory banks can be divided into a read target memory bank that is the object of the read operation and a non-target memory bank that is excluded from the read target memory row. . For example, during a read operation, data is read from one of a plurality of memory banks (ie, a read target memory bank) and data is not read from the remaining memory banks. The write target memory bank or the read target memory bank can be simply referred to as the target memory bank.

Referring to FIG. 2, at time point T1, when the multi-row system is energized, the intra-die termination circuits of the plurality of memory banks are energized to an initial state. In an exemplary embodiment, each of the intra-grain termination circuits of the plurality of memory banks is set to have a first resistance value in an initial state. Although FIG. 2 shows that the energization time point of the intra-die termination circuit coincides with the energization time, the power-on sequence may be completed first and then the intra-die termination may be performed after a certain time interval has elapsed. The circuit is energized into an initial state.

During the time interval T2 to T3 and T4 to T5, all of the intra-die terminal circuits including the memory banks of the write target memory bank and the non-target memory bank are maintained in an energized state while the write operation is being performed. In an exemplary embodiment, the intra-die termination circuitry of the plurality of memory banks is maintained in an initial state to have a first resistance value during a write operation. In another exemplary embodiment, during the write operation, the resistance value of the intra-die termination circuit of the write target memory bank is changed from the first resistance value to a second resistance different from the first resistance value. value.

During the time interval T6 to T7 while the read operation is being performed, the intra-die termination circuit of the read target memory bank is disabled and the intra-die termination circuit of the non-target memory bank is enabled. In an exemplary embodiment, during a read operation, the intra-die termination circuitry of the non-target memory bank is maintained in an initial state to have a first resistance value. Although FIG. 2 shows that the time interval at which the read target memory bank is de-energized coincides with the time interval of the read operation, the time interval at which the read target memory bank is disabled can be less than the time interval of the read operation. In other words, it is sufficient to read the intra-die terminal circuit of the target memory bank only when the data is read through the data input-output pin output. For example, the intra-die termination circuit of the read target memory bank can be disabled only when the pin of the target memory bank outputs data read from the target memory bank.

At time point T8, when the multi-row system is powered down, the power supply is blocked and the in-die termination circuitry of all memory banks is disabled. For example, there may be a switch between the power supplied to the termination circuitry within the die, and the blocking may be performed by opening the switch. For example, when the switch is a transistor, the switch can be turned off based on a control signal applied to the gate of the transistor.

As long as the intra-gate termination circuit of the target memory bank is enabled and the intra-gate termination circuit of the non-target memory bank is disabled, signal integrity may be due to signal waves incident on the non-target memory bank It is not terminated and thus may cause jitter to deteriorate. In contrast, in accordance with at least one embodiment of the inventive concept, signal integrity can be enhanced by almost always enabling intra-die termination circuitry in addition to reading the target memory bank. Although the intra-die termination circuitry of the non-target memory bank is always enabled, as will be explained below, in the case of a pseudo-open drain terminal, no standby power consumption is caused.

If the intra-die termination circuit of the non-target memory bank is enabled in the write operation and is disabled during the read operation, all memory banks are in a standby state to receive the memory access command (eg, write Entering a command or reading a command) and decoding the memory access command. In this case, the intra-die termination circuit does not enter the power down mode and thus the standby power consumption is increased. In contrast, according to an exemplary embodiment, in the write operation and the read operation, the intra-die terminal circuits of the non-target memory banks are maintained in an energized state. In this case, the intra-die termination circuit can enter the power-down mode more easily and thus the power consumption to be used can be reduced.

In an embodiment, regardless of a memory access command (eg, a write command or a read command) output by the memory controller, the intra-die terminal of the non-target memory bank in the plurality of memory banks The circuit has a constant resistance value. This constant resistance value can be based on the value stored in the mode register.

In an exemplary embodiment, a memory bank corresponding to a target memory bank for a write operation or a read operation is notified based on a plurality of row selection signals respectively supplied to the plurality of memory banks The plurality of memory banks. In this case, all of the memory banks in the inactive state enter the power down mode and the target memory bank corresponding to the activated row select signal is awakened from the power down mode to the normal mode of operation. The non-target memory bank does not need to change the enabling state of the termination circuitry within the die and thus the non-target memory bank can maintain the power down mode.

In this way, the method for controlling the intra-die terminal according to at least one embodiment and the system for performing the method can reduce power consumption and enhance signal integrity by static intra-die terminal control, so that during the read operation The intra-gate termination circuit of the target memory bank and the intra-die termination circuit of the non-target memory bank are generally maintained in an enabled state, and the intra-die termination circuit of the read target memory bank is disabled.

Although the method of controlling the intra-die termination has been described with respect to the multi-row system with reference to FIGS. 1 and 2, the exemplary embodiment is applicable to a system including a memory device of a single memory bank.

In the case of a single row system, a single memory device corresponds to a write target memory bank during a write operation and to a read target memory bank during a read operation. According to an exemplary embodiment, when the memory device is powered on, the intra-die termination circuit of the memory device is energized to an initial state to have a first resistance value. The intra-die termination circuitry can be enabled during a write operation to the memory device and the intra-die termination circuitry can be disabled during a read operation on the memory device.

FIG. 3 is a block diagram showing a multi-row system according to an exemplary embodiment of the inventive concept.

Referring to FIG. 3, the multi-row system 10 includes a memory controller 20 and a memory subsystem 30. The memory subsystem 30 includes a plurality of memory banks RNK1 through RNKM and each of the memory banks RNK1 through RNKM includes one or more memory devices MEM, M being a natural number greater than one. The memory controller 20 and the memory subsystem 30 may each include an interface circuit to communicate with each other. The interface circuit can be connected by a control bus for transmitting commands CMD, an address ADDR, and a control signal CTRL, and a data bus for transmitting data. In an embodiment, the command CMD includes the address ADDR. The memory controller 20 can issue the command CMD and the address ADDR to access the memory subsystem 30, and the data can be written into the memory subsystem 30 or the data can be self-memory under the control of the memory controller 20. Subsystem 30 reads out. In an embodiment, memory controller 20 includes separate pins for outputting control signals CTRL, command CMD, address ADDR, and exchanging data DATA with memory subsystem 30. When the command CMD includes the address ADDR, the memory controller 20 can omit the pin for outputting the address ADDR. According to an exemplary embodiment, when the multi-row system 10 is powered on, the intra-die termination circuits of the plurality of memory banks RNK1 to RNKM are energized into an initial state in which the RNK1 to RNKM are arranged for the plurality of memories The intra-die termination circuit of the plurality of memory banks RNK1 to RNKM during the write operation of the write target memory bank is enabled, and during the read operation on the read target memory bank The intra-grain termination circuits of the read target memory banks in the memory banks RNK1 to RNKM are disabled.

4 is a block diagram showing an exemplary embodiment of a memory device included in the multi-row system of FIG.

Referring to Figure 4, memory device 400 includes control logic 410 (e.g., control logic circuitry), address register 420, bank control logic 430 (e.g., repository control logic), row address A row address multiplexer 440, a refresh counter 445, a row decoder 460, a column decoder 470, a memory cell array 480, and a sense amplifier unit 485 ( For example, a sense amplifier circuit), an input-output (I/O) gating circuit 490, and a data input-output (I/O) circuit 500.

The memory cell array 480 includes a plurality of bank arrays 480a through 480h. Row decoder 460 includes a plurality of bank row decoders 460a through 460h coupled to bank arrays 480a through 480h, respectively. Column decoder 470 includes a plurality of bank column decoders 470a through 470h coupled to bank arrays 480a through 480h, respectively. The sense amplifier unit 485 includes a plurality of bank sense amplifiers 485a through 485h coupled to the bank arrays 480a through 480h, respectively.

The address register 420 receives from the memory controller 20 an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR. The address register 420 provides the received bank address BANK_ADDR to the repository control logic 430, the received row address ROW_ADDR to the row address multiplexer 440, and the received column address COL_ADDR to the column Decoder 470.

The repository control logic 430 can generate a repository control signal based on the repository address BANK_ADDR. One of the repository row decoders 460a through 460h corresponding to the repository address BANK_ADDR can be activated based on the repository control signal. One of the repository column decoders 470a through 470h corresponding to the repository address BANK_ADDR can be activated based on the repository control signal.

Row address multiplexer 440 can receive row address ROW_ADDR from address register 420 and can receive refresh row address REF_ADDR from self-refresh counter 445. The row address multiplexer 440 can selectively output one of the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output by the self address multiplexer 440 can be applied to the bank row decoders 460a through 460h.

A bank row decoder activated in the bank row decoders 460a through 460h can decode the row address RA output by the self address multiplexer 440 and can activate the word line corresponding to the row address RA ( Word-line). For example, the activated bank row decoder can apply a word line drive voltage to a word line corresponding to the row address RA.

Column decoder 470 can include a column address latch. The column address latch can receive the column address COL_ADDR from the address register 420 and temporarily store the received column address COL_ADDR. In an exemplary embodiment, in a burst mode, the column address latch generates a column address that is incremented from the received column address COL_ADDR. The column address latch can apply the temporarily stored or generated column address to the bank column decoders 470a through 470h.

A bank column decoder activated in the bank column decoders 470a through 470h can decode the column address COL_ADDR output from the column address latch and can control the input-output gate circuit 490 to output and column The data corresponding to the address COL_ADDR.

Input/output gate control circuit 490 can include circuitry for gating the input-output data. The input/output gating circuit 490 can further include read data latches for storing data output from the bank arrays 480a through 480h and write drivers for writing data to the bank arrays 480a through 480h.

The data to be read from one of the repository arrays 480a through 480h can be sensed by a sense amplifier 485 coupled to the one of the arrays of data to be read, and can be stored for reading. In the data latch. The data stored in the read data latch can be provided to the memory controller 20 via the data input/output circuit 500. The material DQ in a bank array to be written to the bank arrays 480a through 480h can be provided from the memory controller 20 to the data input/output circuit 500. The write driver can write the material DQ into one of the repository arrays 480a through 480h.

Control logic 410 can control the operation of memory device 400. For example, control logic 410 can generate a control signal for memory device 400 for a write operation or a read operation. The control logic 410 can include a command decoder 411 and a mode register set 412 that decodes the command CMD received from the memory controller 20, the mode register set 412. Set the operating mode of the memory device. For example, the value of the scratchpad in the pattern register set 412 can indicate the mode of operation of the memory device.

FIG. 5 is a block diagram showing an embodiment of a data input-output circuit included in the memory device shown in FIG. 4, according to an exemplary embodiment of the inventive concept.

Referring to FIG. 5, the data input-output circuit 500 includes an intra-die terminal circuit 300, a data input-output pin 600, a transmission driver DR 710, and a reception buffer BF 720. The transfer driver 710 drives the data input-output pin 600 based on the read data and the receive buffer 720 receives the write data provided via the data input-output pin 600. For example, the read data is output from the memory of the memory bank to the transfer driver 710 and the memory controller outputs the write data to the receive buffer 720. In an embodiment, the transfer driver DR 710 and the receive buffer BF 720 are implemented by an operational amplifier.

The intra-die termination circuit 300 includes a terminal control unit 310 (e.g., a terminal control circuit) and a termination resistor unit 350.

The terminating resistor unit 350 is coupled to the data input-output pin 600 and provides a termination impedance to the transmission line coupled to the data input-output pin 600. The method of controlling the intra-die terminal according to an exemplary embodiment can be applied to a terminal that controls an input-output pin for achieving bidirectional communication between the memory controller 20 and the memory device 30. Therefore, the method according to the exemplary embodiment can be applied to a data strobe pin, a data mask pin, or a terminal device in addition to the data input-output pin 600. Termination data strobe pin. The method according to an exemplary embodiment does not include an intra-die terminal for an address pin, a command pin for achieving one-way communication from the memory controller 20 to the memory device 30. The term "pin" broadly refers to an electrical interconnection for an integrated circuit, such as a pad or other electrical contact on the integrated circuit.

In an embodiment, the termination resistor unit 350 performs a pull-up terminal operation to provide termination resistance and/or pull-down terminal operation between the supply voltage node and the data input-output pin 600. A termination resistor is provided between the ground node and the data input-output pin 600. A center tap terminal (CTT) for both pull-up terminal operation and pull-down terminal operation will be explained below with reference to FIGS. 14A and 14B, and a first pseudo open only for pull-down terminal operation will be described below with reference to FIGS. 15A and 15B. A bungee (POD) terminal, and a second pseudo open gate terminal for operation of only the pull-up terminal will be described below with reference to FIGS. 16A and 16B.

Although FIG. 5 illustrates an exemplary embodiment in which a separate termination resistor unit 350 is provided, the signal driver (not shown) in the transmission driver 710 itself can function as a termination resistor. For example, in a write operation, transfer driver 710 does not transfer read data, and transfer driver 710 acts as termination resistor unit 350 while receive buffer 720 is enabled to receive write data.

When the termination resistor unit 350 performs the pull-up terminal operation, the voltage of the transmission line connected to the data input-output pin 600 can be substantially maintained at the level of the power supply voltage. As a result, current flows through the terminating resistor unit 350 and the transmission line only when the data is transferred to the logic low level. In contrast, when the termination resistor unit 350 performs a pull-down terminal operation, the voltage of the transmission line connected to the data input-output pin 600 can be substantially maintained at the ground voltage. As a result, current flows through the terminating resistor unit 350 and the transmission line only when the data is transferred to the logic high level.

The terminal control unit 310 (for example, the terminal control circuit) receives the strength code SCD and the output enable signal OEN. The terminal control unit 310 generates a terminal control signal TCS for controlling the terminal resistor unit 350 to adjust the terminal impedance based on the intensity code SCD and the output enable signal OEN.

In an exemplary embodiment, the strength code SCD is a plurality of bits associated with a data rate. The data rate refers to the operating frequency of the memory device or the toggle rate of the data transmitted via the data input-output pin 600. For example, the termination impedance may change to a first impedance when the operating frequency is the first frequency and to the second terminal when the operating frequency is the second other frequency. As will be described below with reference to FIGS. 19A and 19B, an intensity code SCD having a plurality of bits may be provided based on values stored in the mode register 412 in FIG.

In an embodiment, the output enable signal OEN is actived during a read operation. Although the output enable signal OEN is in use, the terminal control unit 310 provides the terminal control signal TCS at a predetermined logic level to control the termination resistor unit 350 not to provide the termination impedance. In this case, the terminating resistor unit 350 can be electrically decoupled from the data input-output pin 600 in response to the terminal control signal TCS having a predetermined logic level. When the terminating resistor unit 350 is electrically decoupled from the data input-output pin 600, the in-die terminal circuit 300 or the terminating resistor unit 350 may be referred to as "disabled".

Although the output enable signal OEN is deactivated during the write operation, the terminal control unit 310 generates the terminal control signal TCS to control the termination resistor unit 350 to provide the termination impedance. The terminal control unit 310 can change the logic level of the terminal control signal TCS in response to the strength code SCD to change the terminal impedance. For example, the value of the intensity code SCD may indicate a particular termination impedance or resistance. If the terminating resistor unit 350 was previously electrically decoupled from the data input-output pin 600, the terminating resistor unit 350 is recoupled to the data input-output unit 600 in response to the application of the terminal control signal TCS.

FIG. 6 is a circuit diagram showing an intra-die terminal circuit included in the data input-output circuit shown in FIG. 5, according to an exemplary embodiment of the inventive concept.

Referring to FIG. 6, the intra-die termination circuit 300 includes a pull-up terminal control unit 330, a pull-down terminal control unit 340, a pull-up driver 360, and a pull-down driver 370.

The pull-up terminal control unit 330 includes a first selector 334 to a third selector 336 (eg, a multiplexer), and the pull-down terminal control unit 340 includes a fourth selector 344 to a sixth selector 346 (eg, a multiplexer) ). The pull-up driver 360 includes a first p-channel metal oxide semiconductor (PMOS) transistor 361 to a third PMOS transistor 363 and first to third resistors R1 to R3. The first PMOS transistor 361 to the third PMOS transistor 363 are connected to the power supply voltage VDDQ, and each of the first to third resistors R1 to R3 is connected to the first to third PMOS transistors 361 to 361 A corresponding one of 363 is between the data input-output pin 600. The pull-down driver 370 includes a first n-channel metal oxide semiconductor (NMOS) transistor 371 to a third NMOS transistor 373 and fourth to sixth resistors R4 to R6. The first NMOS transistor 371 to the third NMOS transistor 373 are connected to the ground voltage VSSQ, and each of the fourth to sixth resistors R4 to R6 is connected to the first NMOS transistor 371 to the third NMOS transistor. A corresponding one of 373 is between the data input-output pin 600.

Each of the first selector 334 to the third selector 336 may receive the power supply voltage VDDQ as each of the first inputs, and receive the first intensity code bits to the third intensity code bits SCD1, SCD2, and SCD3 As each of the second inputs, the output enable signal OEN is received as each of the control signals. Each of the fourth selector 644 to the sixth selector 346 may receive the ground voltage VDDQ as each of the first inputs, and receive the fourth intensity code bits to the sixth intensity code bits SCD4, SCD5, and SCD6. As each of the second inputs, the output enable signal OEN is received as each of the control signals. The intensity code SCD may include intensity code bits SCD1 to SDC6.

Although the output enable signal OEN is activated at the logic high level during the read operation, the first selector 334 to the third selector 336 may output the first terminal control signal to the third terminal control signal of the logic high level. TCS1, TCS2, and TCS3, and the fourth selector 344 to the sixth selector 346 can output the fourth terminal control signals to the sixth terminal control signals TCS4, TCS5, and TCS6 which are logic low levels. The first PMOS transistor 361 to the third PMOS transistor 363 are turned off in response to the first terminal control signal to the logic high level to the third terminal control signals TCS1, TCS2, and TCS3, and the fourth PMOS transistor 371 is The sixth PMOS transistor 373 is turned off in response to the fourth terminal control signal to the sixth terminal control signals TCS4, TCS5, and TCS6 that are logic low. Therefore, during the read operation, the data input-output pin 600 is electrically disconnected from the power supply voltage VDDQ and the ground voltage VSSQ and the intra-die termination circuit 300 is disabled.

Although the output enable signal OEN is activated at the logic low level during the write operation, the first to third selectors 334 to 336 output the first intensity code bits to the third intensity code bits SCD1, SCD2. And SCD3 as the first terminal control signal to the third terminal control signals TCS1, TCS2, TCS3, and the fourth selector 344 to the sixth selector 346 output the fourth intensity code bit to the sixth intensity code bits SCD4, SCD5, And SCD6 serves as a fourth terminal control signal to sixth terminal control signals TCS4, TCS5, and TCS6.

As described above, the intensity code SCD (i.e., the intensity code bits SCD1 through SCD6) can be associated with a data rate or operating frequency. Therefore, when the data rate is relatively high, the channel is quickly charged/discharged by reducing the terminal impedance. When the data rate is relatively low, the current consumption can be reduced by increasing the termination impedance to reduce the direct current (DC) current flowing through the channel.

Although each of the first to sixth resistors R1 to R6 is illustrated as a single resistor in FIG. 6, in the exemplary embodiment, each of the first to sixth resistors R1 to R6 One may be implemented as a plurality of resistors having parallel connections and/or series connections and a plurality of transistors for controlling the connection of the plurality of resistors.

FIG. 6 illustrates an exemplary embodiment of the center tap terminal scheme illustrated in FIGS. 14A and 14B, and the pseudo open gate terminal scheme can be understood therefrom. The configuration of the pull-up terminal control unit 330 and the pull-up driver 360 is omitted from FIG. 6 corresponding to the first pseudo-opening terminal shown in FIGS. 15A and 15B, and the configuration of the pull-down terminal control unit 340 and the pull-down driver 370 is omitted from FIG. Corresponding to the second pseudo open dipole terminal shown in FIGS. 16A and 16B.

7, FIG. 8A, and FIG. 8B are diagrams illustrating a method of controlling a terminal within a die in a write operation, according to an exemplary embodiment of the inventive concept.

As shown in FIG. 7, the memory controller MC is connected in parallel to the plurality of memory banks RNK1 to RNKM by the data input-output pins PADC and PAD1 to PADM and the transmission line TL. The transmission line TL branches at the shared node NC of the data input-output pins PAD1 to PADM of the memory banks RNK1 to RNKM.

FIG. 7 shows an exemplary case in which the first memory bank RNK1 corresponds to the write target memory bank and the other memory banks RNK2 to RNKM correspond to the non-target memory bank. In Figure 7, the energizing elements are marked with hatching. In the write operation, the transfer driver DR0 is enabled and the receive buffer BF0 is disabled in the memory controller MC corresponding to the data transmitter device. Further, the reception buffer BF1 is enabled in the write target memory bank RNK1 corresponding to the data sink device, but is written in the transfer driver DR1 in the target memory bank RNK1, and in the non-target memory banks RNK2 to RNKM. The receive buffers BF2 to BFM and the transfer drivers DR2 to DRM are disabled.

According to an exemplary embodiment, during the write operation, the intra-die terminal circuits TER1 in the write target memory bank RNK1 and the intra-die terminal circuits TER2 to TERM in the non-target memory banks RNK2 to RNKM are enabled. . The intra-die termination circuit TER0 in the memory controller MC is disabled. The current path from the transfer driver DR0 in the memory controller MC to the intra-die termination circuits TER1 to TERM in the memory banks RNK1 to RNKM can form a current path and thus signal reflection can be reduced and signal integrity can be enhanced.

In FIGS. 8A and 8B, time points Ta0 to Tf1 correspond to edges of the operation clock signal pair CK_T and CK_C. The first row selection signal CS_RNK1 and the first command signal CMD_RNK1 are dedicated to the first memory bank RNK1, and the second row selection signal CS_RNK2 and the second command signal CMD_RNK2 are dedicated to the second memory bank RNK2. The data selection communication number pair WCK_T and WCK_C and the data signal DQ_[15:0] are supplied from the memory controller MC to the write target memory bank RNK1. ODT_RNK1 represents the intra-die terminal state of the first memory bank RNK1, and ODT_RNK2 represents the intra-die terminal state of the second memory bank RNK2. DES stands for "deselect" and TRANSITION indicates the transition interval when the state of the terminal in the die changes.

8A and 8B illustrate an exemplary case of a write operation performed when the first memory bank RNK1 corresponds to the write target memory bank and the second memory bank RNK2 corresponds to the non-target memory bank. While the first row of selection signals CS_RNK1 is activated, the command bit signal command and the write command WR are transmitted by the first command signal CMD_RNK1, and the second row selection signal CS_RNK2 and the second command signal CMD_RNK2 are maintained in a deactivated state.

According to an exemplary embodiment, during the write operation, the intra-die termination circuitry in the write target memory bank RNK1 and the intra-die termination circuitry in the non-target memory bank RNK2 are enabled. In an exemplary embodiment, as shown in FIG. 8A, the intra-die termination in the target memory bank RNK1 is written while the data signal DQ_[15:0] for the write operation is toggled. The intra-die termination circuitry in the circuit and non-target memory bank RNK2 maintains the initial state NT-ODT. In an exemplary embodiment, while the data signal DQ_[15:0] for the write operation is in a two-state thixotropic, the intra-die termination circuit in the non-target memory bank RNK2 maintains the initial state NT-ODT and The intra-die terminal circuit written in the target memory bank RNK1 is changed to the state TG-ODT, and the state TG-ODT has a resistance value different from that of the initial state NT-ODT. Although the data signal having 16-bit data is set forth above, the inventive concept is not limited thereto, as the size of the material may be less than 16 bits or greater than 16 bits in alternative embodiments.

9 and 10 are diagrams illustrating a method of controlling a terminal within a die in a read operation, according to an exemplary embodiment of the inventive concept.

As shown in FIG. 9, the memory controller MC is connected in parallel to the plurality of memory banks RNK1 to RNKM by the data input-output pins PADC and PAD1 to PADM and the transmission line TL. The transmission line TL branches at the shared node NC of the data input-output pins PAD1 to PADM of the memory banks RNK1 to RNKM.

FIG. 9 shows an exemplary case in which the first memory bank RNK1 corresponds to the read target memory bank and the other memory banks RNK2 to RNKM correspond to the non-target memory bank. In Figure 9, the energizing elements are marked with hatching. In the read operation, the receive buffer BF0 is enabled and the transfer driver DR0 is disabled in the memory controller MC corresponding to the data sink device. In addition, the transfer driver DR1 is enabled in the read target memory bank RNK1 corresponding to the data transmitter device, and the read buffer BF1 in the target memory bank RNK1 is read, and the non-target memory banks RNK2 to RNKM are read. The receive buffers BF2 to BFM and the transfer drivers DR2 to DRM are disabled.

According to an exemplary embodiment, during the read operation, the intra-die terminal circuits TER1 in the write target memory bank RNK1 are disabled and the intra-die terminal circuits TER2 to TERM in the non-target memory banks RNK2 to RNKM are Empowerment. The intra-die termination circuit TER0 in the memory controller MC is energized. The self-reading intra-die terminal circuit TER0 in the target memory bank RNK1 to the intra-die terminal circuit TER0 in the transfer driver DR0 and the non-target memory banks RNK2 to RNKM can form a current path and thus Signal reflection can be reduced and signal integrity can be enhanced.

In FIG. 10, the time point Ta0Tf1 corresponds to the edge of the operation clock signal pair CK_T and CK_C. The first row selection signal CS_RNK1 and the first command signal CMD_RNK1 are dedicated to the first memory bank RNK1, and the second row selection signal CS_RNK2 and the second command signal CMD_RNK2 are dedicated to the second memory bank RNK2. The data selection communication number is supplied to the memory controller MC from the read target memory bank RNK1 to the WCK_T and WCK_C and the data signal DQ_[15:0]. ODT_RNK1 represents the intra-die terminal state of the first memory bank RNK1, and ODT_RNK2 represents the intra-die terminal state of the second memory bank RNK2. DES means "deselection" and TRANSITION indicates the transition interval when the state of the terminal in the die changes.

FIG. 10 shows an exemplary case of a read operation performed when the first memory bank RNK1 corresponds to the read target memory bank and the second memory bank RNK2 corresponds to the non-target memory bank. While the first row of selection signals CS_RNK1 is activated, the command bit signal command and the read command RD are transmitted by the first command signal CMD_RNK1, and the second row selection signal CS_RNK2 and the second command signal CMD_RNK2 are maintained in a deactivated state.

According to an exemplary embodiment, during the read operation, the intra-die termination circuitry in the read target memory bank RNK1 is disabled and the intra-die termination circuitry in the non-target memory bank RNK2 is enabled. In an exemplary embodiment, as shown in FIG. 10, the intra-die termination circuit in the non-target memory bank RNK2 while the data signal DQ_[15:0] for the read operation is performing the two-state thixotropic The initial state NT-ODT is maintained and the intra-die termination circuit in the read target memory bank RNK1 is changed to the disable state NT-ODT OFF.

11 is a diagram showing an embodiment of resistance setting applied to a control method of a terminal in a die according to an exemplary embodiment of the inventive concept.

Referring to FIG. 11, during the read operation, the intra-die termination circuit in the target memory bank RNK_TG is disabled and the intra-die termination circuit in the non-target memory bank RNK_NT and the memory controller MC has the first resistance value. M*Rtt. During the write operation, the intra-die termination circuitry in the target memory bank RNK_TG and the non-target memory bank RNK_NT has a first resistance value M*Rtt and the intra-die termination circuitry in the memory controller MC is disabled. The first resistance value M*Rtt may correspond to the resistance value of the initial state described above. Therefore, as described with reference to FIG. 8A, during the write operation, the intra-die termination circuit in the target memory bank RNK_TG and the intra-die termination circuit in the non-target memory bank RNK_NT can maintain the initial state to have the first resistance. The value is M*Rtt.

Figure 12 is a diagram for explaining the equivalent resistance of the intra-die termination circuit in the write operation corresponding to the resistance setting shown in Figure 11.

Referring to FIG. 12, all intra-die terminal circuits in the target memory bank RNK1 and the non-target memory banks RNK2 to RNKM during the write operation while transferring data from the memory controller MC to the target memory bank RNK1 There is a first resistance value M*Rtt. When the number of the plurality of memory banks RNK1 to RNKM is M, M resistors having a first resistance value M*Rtt are connected in parallel between the common node NC and the power supply voltage VDDQ, and the common node NC and the power source are connected. The equivalent resistance value between the voltages VDDQ corresponds to Rtt. In the same manner, the equivalent resistance value between the common node NC and the ground voltage VSSQ corresponds to Rtt. Various terminal schemes corresponding to the equivalent resistance value Rtt will be explained below with reference to FIGS. 14A to 16B.

Figure 13 is a diagram for explaining the equivalent resistance of the intra-die termination circuit in the read operation corresponding to the resistance setting shown in Figure 11.

Referring to FIG. 13, during the read operation while transferring data from the target memory bank RNK1 to the memory controller MC, the intra-die terminal circuit in the target memory bank RNK1 is disabled and the non-target memory bank RNK2 The intra-die termination circuit in the RNKM and the memory controller MC has a first resistance value M*Rtt. When the number of the plurality of memory banks RNK1 to RNKM is M, M resistors having a first resistance value M*Rtt are connected in parallel between the common node NC and the power supply voltage VDDQ, and the common node NC and the power source are connected. The equivalent resistance value between the voltages VDDQ corresponds to Rtt. In the same manner, the equivalent resistance value between the common node NC and the ground voltage VSSQ corresponds to Rtt. Various terminal schemes corresponding to the equivalent resistance value Rtt will be explained below with reference to FIGS. 14A to 16B. The configuration shown in FIGS. 14A to 16B is an exemplary embodiment for explaining several possible terminal schemes, but the configuration of the transmission driver and the intra-die termination circuit is not limited thereto. For example, an N-type transistor can be interchanged with a P-type transistor and/or a transistor for power gating can be added to the transmission driver.

14A and 14B are diagrams for explaining a center tap terminal (CTT).

Referring to Figure 14A, the transmission driver 70 in the transmitter device drives the input-output pad PADH based on the transmission signal ST from the internal signal of the transmitter device. The input-output pad PADH of the transmitter device is connected to the input-output pad PADS of the receiver device via a transmission line TL. The termination circuit 80 of the central tap terminal scheme is connected to the input-output pad PADS of the receiver device for impedance matching. The receive buffer BF in the receiver device can compare the input signal SI with the reference voltage VREF by the input-output pad PADS to provide the buffer signal SB to the internal circuit of the receiver device.

The transfer driver 70 may include a pull-up unit connected between the first power supply voltage VDDQ and the input-output pad PADH and a second power supply voltage VSSQ connected to the input-output pad PADH and lower than the first power supply voltage VDDQ. Drop-down unit. The pull-up unit may include a turn-on resistor RON and a p-channel metal oxide semiconductor (PMOS) transistor TP1 that switch in response to the transmission signal ST. The pull-down unit may include a turn-on resistor RON and an n-channel metal oxide semiconductor (NMOS) transistor TN1 that are switched in response to the transmission signal ST. The turn-on resistor RON may be omitted and each turn-on resistor RON may represent a resistance between the voltage node and the input-output pad PADH when each of the transistors TP1 and TN1 is turned on.

The terminal circuit 80 of the central tap terminal scheme may include a first sub-terminal circuit connected between the first power supply voltage VDDQ and the input-output pad PADS and connected between the input-output pad PADS and the second power supply voltage VSSQ The second sub-terminal circuit. The first sub-terminal circuit may include a termination resistor Rtt and a PMOS transistor TP2 that are turned on in response to a low voltage. The second sub-terminal circuit may include a terminating resistor Rtt and an NMOS transistor TN2 that are turned on in response to a high voltage. The terminating resistor Rtt may be omitted and each terminating resistor Rtt may represent the resistance between the voltage node and the input-output pad PADS when each of the transistors TP2 and TN2 is turned "on".

In the case of the terminal circuit 80 of the center tap terminal scheme in FIG. 14A, the high voltage level VIH and the low voltage level VIL of the input signal SI can be represented as FIG. 14B. It can be assumed that the second power supply voltage VSSQ is the ground voltage (ie, VSSQ = 0), and the voltage drop along the transmission line TL can be ignored. Therefore, the high voltage level VIH, the low voltage level VIL, and the optimum reference voltage VREF can be calculated according to Expression 1. Expression 1: VIH=VDDQ*(RON+Rtt)/(2RON+Rtt), VIL=VDDQ*RON/(2RON+Rtt), VREF=(VIH+VIL)/2=VDDQ/2

15A and 15B are diagrams for explaining a first pseudo open bungee (POD) terminal.

Referring to Figure 15A, the transmission driver 70 in the transmitter device drives the input-output pad PADH based on the transmission signal ST from the internal signal of the transmitter device. The input-output pad PADH of the transmitter device is connected to the input-output pad PADS of the receiver device via a transmission line TL. The terminal circuit 81 of the first pseudo open end terminal scheme can be connected to the input-output pad PADS of the receiver device for impedance matching. The receive buffer BF in the receiver device can compare the input signal SI with the reference voltage VREF by the input-output pad PADS to provide the buffer signal SB to the internal circuit of the receiver device.

The transfer driver 70 may include a pull-up unit connected between the first power supply voltage VDDQ and the input-output pad PADH and a second power supply voltage VSSQ connected to the input-output pad PADH and lower than the first power supply voltage VDDQ. Drop-down unit. The pull-up unit may include a turn-on resistor RON and a PMOS transistor TP1 that perform switching in response to the transmission signal ST. The pull-down unit may include a turn-on resistor RON and an NMOS transistor TN1 that perform switching in response to the transmission signal ST. The turn-on resistor RON may be omitted and each turn-on resistor RON may represent a resistance between the voltage node and the input-output pad PADH when each of the transistors TP1 and TN1 is turned on.

The terminal circuit 81 of the first pseudo open gate terminal scheme may include a terminating resistor Rtt and an NMOS transistor TN2 that are turned on in response to a high voltage. The terminating resistor Rtt may be omitted and the terminating resistor Rtt may represent the resistance between the voltage node and the input-output pad PADS when the NMOS transistor TN2 is turned on.

In the case of the terminal circuit 81 of the first pseudo open dipole termination scheme of FIG. 15A, the high voltage level VIH and the low voltage level VIL of the input signal SI can be represented as FIG. 15B. It can be assumed that the second power supply voltage VSSQ is the ground voltage (ie, VSSQ = 0), and the voltage drop along the transmission line TL can be ignored. Therefore, the high voltage level VIH, the low voltage level VIL, and the optimum reference voltage VREF can be calculated according to Expression 2. Expression 2: VIH=VDDQ*RTT/(RON+RTT), VIL=VSSQ=0, VREF=(VIH+VIL)/2=VDDQ*RTT/2(RON+RTT)

16A and 16B are diagrams for explaining a second pseudo open dipole terminal.

Referring to Figure 16A, the transmission driver 70 in the transmitter device drives the input-output pad PADH based on the transmission signal ST from the internal signal of the transmitter device. The input-output pad PADH of the transmitter device is connected to the input-output pad PADS of the receiver device via a transmission line TL. The terminal circuit 82 of the second pseudo open terminal scheme is connected to the input-output pad PADS of the receiver device for impedance matching. The receive buffer BF in the receiver device can compare the input signal SI with the reference voltage VREF by the input-output pad PADS to provide the buffer signal SB to the internal circuit of the receiver device.

The transfer driver 70 may include a pull-up unit connected between the first power supply voltage VDDQ and the input-output pad PADH and a second power supply voltage VSSQ connected to the input-output pad PADH and lower than the first power supply voltage VDDQ. Drop-down unit. The pull-up unit may include a turn-on resistor RON and a PMOS transistor TP1 that perform switching in response to the transmission signal ST. The pull-down unit may include a turn-on resistor RON and an NMOS transistor TN1 that perform switching in response to the transmission signal ST. The turn-on resistor RON may be omitted and each turn-on resistor RON may represent a resistance between the voltage node and the input-output pad PADH when each of the transistors TP1 and TN1 is turned on.

The termination circuit 82 of the second pseudo open termination terminal scheme may include a termination resistor Rtt and a PMOS transistor TP2 that are turned on in response to a low voltage. The terminating resistor Rtt may be omitted and the terminating resistor Rtt may represent the resistance between the voltage node and the input-output pad PADS when the NMOS transistor TN2 is turned on.

In the case of the terminal circuit 82 of the first pseudo open dipole termination scheme of FIG. 16A, the high voltage level VIH and the low voltage level VIL of the input signal SI can be represented as FIG. 16B. It can be assumed that the second power supply voltage VSSQ is the ground voltage (ie, VSSQ = 0), and the voltage drop along the transmission line TL can be ignored. Therefore, the high voltage level VIH, the low voltage level VIL, and the optimum reference voltage VREF can be calculated according to Expression 3. Expression 3: VIH=VDDQ, VIL=VDDQ*RON/(RON+Rtt), VREF=(VIH+VIL)/2=VDDQ*(2RON+Rtt)/2(RON+Rtt)

As such, the intra-die termination circuitry in accordance with at least one example embodiment may employ various termination schemes. In an exemplary embodiment, a training process is performed according to Expression 1, Expression 2, and Expression 3 to obtain an optimum reference voltage VREF. In an exemplary embodiment, the memory controller takes into account the intra-die termination resistors of the continuously enabled non-target memory banks to adjust the resistance values or locations of the intra-die termination circuits in the memory controller. The on-resistance value of the transfer driver in the memory controller.

17 is a diagram showing an embodiment of resistance setting applied to a control method of a terminal in a die according to an exemplary embodiment of the inventive concept.

Referring to FIG. 17, during the read operation, the intra-die termination circuit in the target memory bank RNK_TG is disabled and the intra-die termination circuit in the non-target memory bank RNK_NT and the memory controller MC has the first resistance value. M*Rtt. During the write operation, the intra-die termination circuit in the target memory bank RNK_TG has a second resistance value M*Rtt+Rtg different from the first resistance value M*Rtt, and the intra-grain in the non-target memory bank RNK_NT The termination circuit has a first resistance value M*Rtt and the intra-die termination circuitry in the memory controller MC is disabled. The first resistance value M*Rtt may correspond to the resistance value of the initial state mentioned above. For example, the first resistance value M*Rtt can be about 70 ohms (Ω) and the second resistance value M*Rtt+Rtg can be about 150 ohms. Therefore, as described with reference to FIG. 8B, during the write operation, the resistance value of the intra-die termination circuit in the target memory bank RNK_TG can be changed from the first resistance value M*Rtt to the second resistance value M*Rtt+Rtg. And the intra-die termination circuit in the non-target memory bank RNK_NT can maintain the initial state to have the first resistance value M*Rtt. In an embodiment, the second resistance value is greater than the first resistance value, the intra-die termination circuit of the target memory bank RNK_TG is disabled during the read operation and the intra-die termination circuit of the non-target memory bank RNK_NT is enabled And being set to the first resistance value, and the intra-die termination circuit of the target memory bank is enabled and set to the second resistance value during the write operation.

FIG. 18 is a diagram showing a command address signal command, according to an exemplary embodiment.

Figure 18 illustrates an exemplary command address signal command conforming to the low power double data rate 5 (LPDDR5) standard. Referring to Figure 18, the command address signal command can be represented as a combination of command address signals CA0 through CA5. "L" indicates a logic low level, "H" indicates a logic high level, and EDC_EN, WS_RD, WS_FAST, DC0 to DC3, NT0, NT1, and BL indicate a field value that forms a command address signal command. Specifically, NT0 and NTI represent field values controlled by the terminal.

As shown in FIG. 18, when static intra-die terminal control according to an exemplary embodiment is employed, NT0 and NT1 may be omitted and the corresponding portion may be reserved for future use (RFU).

19A and 19B are diagrams for explaining a mode register for an intra-die terminal, according to an exemplary embodiment.

Information on intra-die terminal control can be stored in mode register 412 in FIG. For example, a corresponding portion of mode register 412 can have a mode register setting MRSET as shown in Figures 19A and 19B. Some values of operands OP0 through OP7 may represent information about the resistance value of the termination circuitry within the die.

FIG. 19A shows the value ODT of the resistance value for collectively controlling the intra-die termination circuit in the target memory bank and the intra-die termination circuit in the non-target memory bank as described with reference to FIG. 8A. 19B shows a first value TG-ODT for controlling the first resistance value of the intra-die termination circuit in the target memory bank as described with reference to FIG. 8B and for controlling the intra-grain in the non-target memory bank A second value NT-ODT of the second resistance value of the termination circuit. The values ODT, TG-ODT, and NT-ODT stored in the mode register 412 can be provided from the memory controller to the memory bank by a mode register write operation. The intensity code SCD mentioned above can be provided based on the values ODT, TG-ODT, and NT-ODT.

FIG. 20 is a block diagram showing a semiconductor memory device according to an exemplary embodiment of the inventive concept.

Referring to Fig. 20, the semiconductor memory device 900 includes first semiconductor integrated circuit layers LA1 to kth semiconductor integrated circuit layers LAk, among the first semiconductor integrated circuit layers LA1 to kth semiconductor integrated circuit layers LAk, the lowest The first semiconductor integrated circuit layer LA1 is assumed to be an interface or a control chip, and the other semiconductor integrated circuit layers LA2 to LAk are assumed to be a slave chip including a core memory wafer. A plurality of memory banks as described above can be formed from the wafer.

The first semiconductor integrated circuit layer LA1 to the kth semiconductor integrated circuit layer LAk can transmit and receive signals between the layers via the substrate via TSV (for example, germanium via). The lowest first semiconductor integrated circuit layer LA1 as an interface or control wafer can communicate with an external memory controller via a conductive structure formed on the external surface.

Each of the first semiconductor integrated circuit layer 910 to the kth semiconductor integrated circuit layer 920 may include a memory region 921 and a peripheral circuit 922 for driving the memory region 921. For example, the peripheral circuit 922 can include a row-driver, a column-driver, a data input-output circuit, a command buffer, and an address buffer, and the row driver is used to drive the word of the memory. a line line, a column driver for driving the bit line of the memory, a data input-output circuit for controlling input/output of the data, and a command buffer for receiving a command from an external source and buffering the command, the address The buffer is used to receive the address from an external source and buffer the address.

The first semiconductor integrated circuit layer 910 may further include a control circuit. The control circuit can control access to the memory area 921 based on commands and address signals from the memory controller and can generate control signals for accessing the memory area 921.

FIG. 21 is a block diagram showing a mobile system according to an exemplary embodiment of the inventive concept.

Referring to FIG. 21, the mobile system 1200 includes an application processor (AP) 1210, a connectivity circuit 1220, a volatile memory (VM) device 1230, and a nonvolatile memory (nonvolatile memory). NVM) device 1240, user interface 1250, and power supply 1260.

The application processor 1210 can execute computer instructions stored in a computer readable medium (eg, a memory device) including applications such as a web browser, a gaming application, a video player, and the like. The connectivity circuit 1220 can perform wired or wireless communication with an external device. The volatile memory device 1230 can store data processed by the application processor 1210 or can operate as a working memory. For example, the volatile memory device 1230 can be a dynamic random access memory, such as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double Low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphics double data rate synchronous dynamic random access memory (graphics double data rate synchronous dynamic random access memory) GDDR SDRAM), Rambus dynamic random-access memory (RDRAM), etc. The non-volatile memory device 1240 can store a boot image for launching the mobile system 1200. The user interface 1250 can include at least one input device (eg, a keypad, a touch screen, etc.) and at least one output device (eg, a speaker, display device, etc.). A power supply 1260 can supply a supply voltage to the mobile system 1200. In an exemplary embodiment, the mobile system 1200 further includes a camera image processor (CIS) and/or, for example, a memory card, a solid state drive (SSD), a hard disk drive (hard disk drive). , HDD), storage device such as compact disc read only memory (CD-ROM).

The volatile memory device 1230 and/or the non-volatile memory device 1240 may have a configuration for performing a control method according to the intra-die terminal of the exemplary embodiment as described with reference to FIGS. 1 through 19B.

As described above, the method of controlling an intra-die terminal according to an exemplary embodiment and the system for performing the method can reduce power consumption and enhance signal integrity by static intra-die terminal control, so that during a read operation The intra-gate termination circuit of the target memory bank and the intra-die termination circuit of the non-target memory bank are generally maintained in an enabled state, and the intra-die termination circuit of the read target memory bank is disabled.

Embodiments of the inventive concept are applicable to various devices and systems including memory devices. For example, the inventive concept can be applied to, for example, a memory card, a mobile phone, a smart phone, a personal data assistant (PDA), a portable multimedia player (PMP), a digital camera, and a camera. Camcorder, personal computer (PC), server computer, workstation, laptop, digital TV, set-top box , portable game console (portable game console), navigation system and other systems.

The above is a description of the exemplary embodiments of the inventive concept and should not be construed as limiting. While a few exemplary embodiments have been described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the inventive concept.

10‧‧‧Multiple-row system

20, MC‧‧‧ memory controller

30‧‧‧Memory Subsystem/Memory Device

70‧‧‧Transfer driver

80, 81, 82‧‧‧ terminal circuits

300‧‧‧In-die terminal circuit

310‧‧‧Terminal Control Unit

330‧‧‧Upper Terminal Control Unit

334‧‧‧First selector

335‧‧‧Second selector

336‧‧‧ third selector

340‧‧‧Terminal Resistor Unit / Pull-down Terminal Control Unit

344‧‧‧fourth selector

345‧‧‧ fifth selector

346‧‧‧ sixth selector

350‧‧‧Terminal resistor unit

360‧‧‧ Pull-up drive

361‧‧‧First PMOS transistor

362‧‧‧Second PMOS transistor

363‧‧‧ Third PMOS transistor

370‧‧‧ Pulldown drive

371‧‧‧First NMOS transistor

372‧‧‧Second NMOS transistor

373‧‧‧ Third NMOS transistor

400, MEM‧‧‧ memory device

410‧‧‧Control logic

411‧‧‧Command decoder

412‧‧‧Mode Register/Mode Register

420‧‧‧ address register

430‧‧‧Repository Control Logic

440‧‧‧ address multiplexer

445‧‧‧Refresh counter

460‧‧‧ line decoder

460a, 460h‧‧‧Repository Row Decoder

470‧‧‧ column decoder

470a, 470h‧‧‧Repository Column Decoder

480‧‧‧ memory cell array

480a, 480h‧‧‧repository array

485‧‧‧Sense Amplifier/Sensor Amplifier Unit

485a, 485h‧‧‧Repository sense amplifier

490‧‧‧Input-output gate control circuit

500‧‧‧Data input/output circuit

600‧‧‧Data input-output pin

710, DR0, DR1, DR2, DRM‧‧‧ transmission drive

720, BF, BF0, BF1, BF2, BFM‧‧‧ receive buffer

900‧‧‧Semiconductor memory device

910‧‧‧First semiconductor integrated circuit layer

920‧‧‧kth semiconductor integrated circuit layer

921‧‧‧ memory area

922‧‧‧ peripheral circuits

1200‧‧‧Mobile System

1210‧‧‧Application Processor

1220‧‧‧Connected circuit

1230‧‧‧Volatile memory device

1240‧‧‧Non-volatile memory device

1250‧‧‧User interface

1260‧‧‧Power supply

ADDR‧‧‧ address

AP‧‧‧Application Processor

BANK_ADDR‧‧‧ repository address

BL, DC0, DC1, DC2, DC3, EDC_EN, NT0, NT1, WS_FAST, WS_RD, WS_WR‧‧‧ field values

CA0, CA1, CA2, CA3, CA4, CA5, CA6, CAS‧‧‧ command address signals

CK_C, CK_T‧‧‧ operation clock signal pair

CMD‧‧‧ Order

CMD_RNK1‧‧‧ first command signal

CMD_RNK2‧‧‧second command signal

COL_ADDR‧‧‧ column address

CS_RNK1‧‧‧first row selection signal

CS_RNK2‧‧‧Second row of selection signals

CTRL‧‧‧ control signal

DATA, DQ‧‧‧ data

DES‧‧‧Deselection

DQ_[15:0]‧‧‧Information Signal

H‧‧‧Logic high standard

L‧‧‧Logic low level

LA1‧‧‧First semiconductor integrated circuit layer

LA(K-1)‧‧‧Semiconductor integrated circuit layer/k-1 semiconductor integrated circuit layer

LAk‧‧‧Semiconductor integrated circuit layer / kth semiconductor integrated circuit layer

M*Rtt‧‧‧first resistance value

M*Rtt+Rtg‧‧‧second resistance value

MRSET‧‧‧ mode register setting

NC‧‧‧ shared node

NT-ODT‧‧‧ value / initial state / second value

NT-ODT OFF‧‧‧Enable status

OEN‧‧‧ output enable signal

ODT‧‧ value

ODT_RNK1‧‧‧In-die terminal state of the first memory bank

ODT_RNK2‧‧‧In-die terminal state of the second memory bank

OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7‧‧‧ operands

PAD1, PAD2, PADC, PADM‧‧‧ data input-output pins

PADH, PADS input-output pad

R1‧‧‧ first resistor

R2‧‧‧second resistor

R3‧‧‧ third resistor

R4‧‧‧ fourth resistor

R5‧‧‧ fifth resistor

R6‧‧‧ sixth resistor

RA, ROW_ADDR‧‧‧ address

RD‧‧‧ read command

REF_ADDR‧‧‧ Refresh row address

RNK_NT‧‧‧ non-target memory row

RNK_TG‧‧‧target memory row

RNK1‧‧‧ memory row/first memory bank/target memory bank/write target memory bank/read target memory bank

RNK2, RNKM‧‧‧ memory row / second memory row / non-target memory row

RON‧‧‧Connected resistor

Rtt‧‧‧ equivalent resistance value / terminating resistor

S100, S200, S300‧‧‧ steps

SB‧‧‧buffer signal

SCD‧‧‧ intensity code

SCD1‧‧‧ intensity code bit/first intensity code bit

SCD2‧‧‧ intensity code bit/second intensity code bit

SCD3‧‧‧ intensity code bit/third intensity code bit

SCD4‧‧‧ intensity code bit/fourth intensity code bit

SCD5‧‧‧ intensity code bit/fifth intensity code bit

SCD6‧‧‧ intensity code bit/sixth intensity code bit

SI‧‧‧ input signal

ST‧‧‧ transmission signal

T1, T2, T3, T4, T5, T6, T7, T8, Ta0, Ta1, Ta2, Ta3, Tb0, Tb1, Tb2, Tc0, Tc1, Tc2, Tc3, Td0, Td1, Te0, Te1, Tf0, Tf1‧ ‧ ‧ time point

TCS‧‧‧ terminal control signal

TCS1‧‧‧ first terminal control signal

TCS2‧‧‧second terminal control signal

TCS3‧‧‧ third terminal control signal

TCS4‧‧‧ fourth terminal control signal

TCS5‧‧‧ fifth terminal control signal

TCS6‧‧‧ sixth terminal control signal

TER0, TER1, TER2, TERM‧‧‧ die terminal circuit

TG-ODT‧‧‧Status/Value/First Value

TL‧‧‧ transmission line

TN1, TN2‧‧‧ transistor/NMOS transistor

TP1, TP2‧‧‧Opto/PMOS transistor

TSV‧‧‧ substrate perforation

VDDQ‧‧‧Power supply voltage / first supply voltage

VIH‧‧‧High voltage level

VIL‧‧‧low voltage level

VREF‧‧‧reference voltage / optimal reference voltage

VSSQ‧‧‧ Ground Voltage / Second Supply Voltage

WCK_C, WCK_T‧‧‧ data selection communication number pair

WR‧‧‧Write command

FIG. 1 is a flowchart illustrating a method of controlling an intra-die terminal (ODT) according to an exemplary embodiment of the inventive concept. FIG. 2 is a timing diagram illustrating a method of controlling a terminal within a die according to an exemplary embodiment of the inventive concept. FIG. 3 is a block diagram showing a multi-rank system according to an exemplary embodiment of the inventive concept. 4 is a block diagram showing an exemplary embodiment of a memory device included in the multi-row system of FIG. FIG. 5 is a block diagram showing an embodiment of a data input-output circuit included in the memory device shown in FIG. 4, according to an exemplary embodiment of the inventive concept. FIG. 6 is a circuit diagram showing an intra-die terminal circuit included in the data input-output circuit shown in FIG. 5, according to an exemplary embodiment of the inventive concept. 7, FIG. 8A and FIG. 8B are diagrams illustrating a method of controlling a terminal within a die in a write operation, according to an exemplary embodiment of the inventive concept. 9 and 10 are diagrams illustrating a method of controlling a terminal within a die in a read operation, according to an exemplary embodiment of the inventive concept. 11 is a diagram showing an embodiment of resistance setting applied to a control method of a terminal in a die according to an exemplary embodiment of the inventive concept. Figure 12 is a diagram for explaining the equivalent resistance of the intra-die termination circuit in the write operation corresponding to the resistance setting shown in Figure 11. Figure 13 is a diagram for explaining the equivalent resistance of the intra-die termination circuit in the read operation corresponding to the resistance setting shown in Figure 11. 14A and 14B are diagrams for explaining a center-tapped termination (CTT). 15A and 15B are diagrams for explaining a first pseudo-open drain (POD) terminal. 16A and 16B are diagrams for explaining a second pseudo open dipole terminal. 17 is a diagram showing an embodiment of resistance setting applied to a control method of a terminal in a die according to an exemplary embodiment of the inventive concept. FIG. 18 is a diagram showing a command-address signal (CAS) command according to an exemplary embodiment of the inventive concept. 19A and 19B are diagrams for explaining a mode register for an intra-die terminal according to an exemplary embodiment of the inventive concept. FIG. 20 is a block diagram showing a semiconductor memory device according to an exemplary embodiment of the inventive concept. FIG. 21 is a block diagram showing a mobile system according to an exemplary embodiment of the inventive concept.

Claims (20)

A method of controlling an intra-die termination (ODT) in a multi-row memory system including a plurality of memory banks, the method comprising: when the multi-row memory system is powered on, The intra-gate termination circuit of the memory bank is enabled to be in an initial state; during the writing operation, the intra-gate termination circuit and the non-target memory row of the plurality of memory banks written into the target memory bank The intra-die termination circuit is enabled; and during the read operation, the intra-die termination circuit of the read target memory bank of the plurality of memory banks is disabled, and the plurality of The intra-die termination circuit of the non-target memory banks in the memory bank is enabled. The method of claim 1, wherein each of the intra-grain termination circuits of the plurality of memory banks has a first resistance value in the initial state. The method of claim 2, wherein the enabling the intra-gate termination circuit during the writing operation comprises: arranging the plurality of memory banks during the writing operation The intra-die terminal circuit is maintained in the initial state to have the first resistance value. The method of claim 2, wherein the enabling the intra-gate termination circuit during the writing operation further comprises: writing the write target memory during the writing operation The resistance value of the intra-die termination circuit is changed from the first resistance value to a second resistance value different from the first resistance value. The method of claim 2, wherein the enabling the intra-gate termination circuit of the non-target memory bank during the read operation comprises: during the read operation, The intra-die termination circuit of the non-target memory bank is maintained in the initial state to have the first resistance value. The method of claim 1, wherein the intra-die termination circuitry of the plurality of memory banks is configured to terminate data input-output pins of the plurality of memory banks. The method of claim 6, wherein the intra-gate termination circuit of the plurality of memory banks is even when data input-output operation through the data input-output pin is not performed The initial state is maintained. The method of claim 1, wherein the plurality of memory banks are divided by the write target memory bank or the read target regardless of a memory access command from the memory controller. The intra-grain termination circuits of the non-target memory banks excluding the memory have constant resistance values. The method of claim 8, wherein the constant resistance value of the non-target memory bank is determined based on a value stored in a mode register of the multi-row memory system. . The method of claim 1, wherein the resistance value of the intra-die termination circuit of the write target memory bank is set equal to the write target of the plurality of memory banks a resistance value of the intra-die termination circuit of the non-target memory bank outside the memory. The method of claim 1, wherein the resistance value of the intra-die termination circuit of the write target memory bank is set to be different from the plurality of memory banks except the write A resistance value of the intra-die termination circuit of the non-target memory bank outside the target memory. The method of claim 11, wherein the resistance value of the intra-grain termination circuit of the write target memory bank is set to be larger than the grain of the non-target memory bank The resistance value of the internal termination circuit. The method of claim 1, wherein the write target memory bank or the read target memory bank is switched from a power-off mode in order to perform the write operation or the read operation Up to a normal operation mode, and the non-target memory of the plurality of memory banks except the write target memory bank or the read target memory bank is discharged during the writing operation or The power down mode is maintained during a read operation. A system comprising: a plurality of memory banks including a plurality of memory devices; and a memory controller configured to control the plurality of memory banks, wherein the plurality of memory banks have intra-die terminations ( An ODT) circuit is enabled to be in an initial state when the system is powered on, and the intra-gate termination circuit of the plurality of memory banks is in a write target memory row and non-distribution to the plurality of memory banks The target memory bank is enabled during a write operation, and during the read operation, the intra-die termination circuitry of the read target memory bank of the plurality of memory banks is disabled, while The intra-die termination circuitry of the non-target memory banks in the plurality of memory banks is enabled. The system of claim 14, wherein the plurality of memory banks are divided by the write target memory bank or the read regardless of a memory access command from the memory controller. The intra-grain termination circuits of the non-target memory banks that are excluded from the target memory have constant resistance values. A system comprising: a first memory bank comprising a plurality of first memory devices coupled to a first intra-die termination (ODT) circuit; and a second memory bank including a termination to a second intra-die termination circuit a plurality of second memory devices, wherein the first intra-gate termination circuit and the second intra-die termination circuit are energized during a write operation of the first memory bank, and During the read operation of the first bank of memories, the first intra-gate termination circuitry is disabled and the second intra-die termination circuitry is enabled. The system of claim 16, wherein each of the enabled intra-die termination circuits provides a termination impedance to a transmission line coupled to a data input-output pin of the corresponding memory bank. The system of claim 17, wherein the first intra-gate terminal circuit is in use only when the data input-output pin outputs read data corresponding to the read operation. It is disabled during the read operation. The system of claim 16, wherein during the writing operation, the resistance value of the termination circuit in the first die is set equal to the resistance value of the termination circuit in the second die. The system of claim 16, wherein during the writing operation, a resistance value of the first intra-gate termination circuit is set to be different from a resistance value of the termination circuit in the second die .