SG10201804199UA - Method of controlling on-die termination and system performing the same - Google Patents

Method of controlling on-die termination and system performing the same

Info

Publication number
SG10201804199UA
SG10201804199UA SG10201804199UA SG10201804199UA SG10201804199UA SG 10201804199U A SG10201804199U A SG 10201804199UA SG 10201804199U A SG10201804199U A SG 10201804199UA SG 10201804199U A SG10201804199U A SG 10201804199UA SG 10201804199U A SG10201804199U A SG 10201804199UA
Authority
SG
Singapore
Prior art keywords
memory ranks
controlling
odt
die termination
rank
Prior art date
Application number
SG10201804199UA
Inventor
Son Young-Hoon
Kim Si-Hong
Lee Chang-Kyo
Choi Jung-Hwan
Ha Kyung-Soo
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201804199UA publication Critical patent/SG10201804199UA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation. FIG. 1
SG10201804199UA 2017-05-29 2018-05-18 Method of controlling on-die termination and system performing the same SG10201804199UA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20170066377 2017-05-29
KR1020170089692A KR20180130417A (en) 2017-05-29 2017-07-14 Method of controlling on-die termination and system performing the same

Publications (1)

Publication Number Publication Date
SG10201804199UA true SG10201804199UA (en) 2018-12-28

Family

ID=64669789

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201804199UA SG10201804199UA (en) 2017-05-29 2018-05-18 Method of controlling on-die termination and system performing the same

Country Status (3)

Country Link
KR (1) KR20180130417A (en)
SG (1) SG10201804199UA (en)
TW (1) TWI763803B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI705455B (en) * 2019-07-03 2020-09-21 友懋國際科技股份有限公司 Impedance transformation network and memory module including the same
CN112783824A (en) * 2019-11-07 2021-05-11 安徽寒武纪信息科技有限公司 Memory and device comprising same
CN114255801B (en) * 2020-09-24 2023-09-15 长鑫存储技术有限公司 Dual reference voltage generator, equalizing circuit and memory
KR20220106789A (en) 2020-09-24 2022-07-29 창신 메모리 테크놀로지즈 아이엔씨 Dual reference voltage generator, equalization circuit and memory
KR20220063581A (en) 2020-11-10 2022-05-17 삼성전자주식회사 Apparatus, memory device and method for storing multiple parameter codes for operation parameters

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7259585B2 (en) * 2005-09-28 2007-08-21 International Business Machines Corporation Selective on-die termination for improved power management and thermal distribution
US7342411B2 (en) * 2005-12-07 2008-03-11 Intel Corporation Dynamic on-die termination launch latency reduction
DE202010017690U1 (en) * 2009-06-09 2012-05-29 Google, Inc. Programming dimming terminating resistor values
US8966208B2 (en) * 2010-02-25 2015-02-24 Conversant Ip Management Inc. Semiconductor memory device with plural memory die and controller die
WO2013048493A1 (en) * 2011-09-30 2013-04-04 Intel Corporation Memory channel that supports near memory and far memory access

Also Published As

Publication number Publication date
KR20180130417A (en) 2018-12-07
TW201901457A (en) 2019-01-01
TWI763803B (en) 2022-05-11

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