TW201842725A - Slew control for high-side switch - Google Patents

Abstract

A circuit for slew rate control for a high-side switch is disclosed. The circuit comprises a sample and level-shift circuit. The sample and level-shift circuit is connected to the high-side switch. The circuit further comprises a sampling capacitor, and the sampling capacitor is configured to sample an input voltage corresponding to the sample and level-shift circuit. Additionally, the circuit includes a charge-limiting circuit. The sampling capacitor is configured to charge a gate capacitance of the high-side switch. The charge-limiting circuit is configured to limit a rate of charge transferred to the gate capacitance of the high-side switch per unit of time.

Description

Switching control for high-side switches

The present invention relates to a transistor-based switch, and more particularly to a switching control for a high-side switch.

High-side switches can be used to drive a variety of loads, and therefore can be used in many different applications. A typical system and method for driving a high-side switch utilizes a charge pump. A charge pump uses a capacitor as an energy storage element to create a DC to DC converter that is one of a higher voltage or a lower voltage power source. Regarding the high-side switch, in addition to supplying a DC current to drive the high-side switch, it also relies on a charge pump to supply other circuit components (such as amplifiers). This method requires the use of large capacitors in the charge pump to supply the DC load current. If an integrated solution on a chip is required, large capacitors can occupy precious surface area. To address this issue, some systems implement external capacitors to supply DC current. Although this reduces the required surface area of the wafer, it then includes additional pins to connect external capacitors. Using a charge pump design to drive a high-side switch is detrimental to situations that require a reduced chip size or situations that are cost sensitive and therefore require a reduced number of pins. In addition, the use of a charge pump design is not conducive to situations that require as few external components as possible, such as external capacitors, because external components also increase the overall bill of materials (BOM) and cost. Generally speaking, a high-side switch includes three main components: a channel component, a gate control block, and an input logic block. The channel element is usually a transistor, which is usually a metal oxide semiconductor field effect transistor (MOSFET) or a laterally diffused metal oxide semiconductor transistor (LDMOS). An LDMOS transistor is considered a type of MOSFET. Channel elements operate in a linear region to pass current from a power source to a load. The gate control block provides a voltage to the gate of the channel element to "turn on" or "off" it. The input logic block interprets the on / off signal and triggers the gate control block to "turn on" or "off" the channel element. In electronics, slew rate is defined as the change in voltage per unit time. Signal slew rates that exceed a circuit's slew rate can cause distortion. Furthermore, exceeding the slew rate can cause an increased amount of electromagnetic radiation (EME), thereby violating electromagnetic compatibility (EMC) standards, and may interfere with other electronic devices. Therefore, the slew rate can significantly limit the operation of a corresponding circuit. Adding a current limiter provides some control over the slew rate, but this solution still requires the use of a large charge pump. FIG. 1 is a circuit level diagram of a known system and method with additional current limiters for driving a high-side switch. As shown, a charge pump 2 is connected to a current controller 4. The current controller 4 includes an amplifier 6 and a transistor 10. Here, the transistor 10 used is a p-channel metal oxide semiconductor (pMOS). The current controller 4 is powered by the charge pump 2 and controls an output based on the voltage difference from the resistors 12, 24. The positive rail of the amplifier 6 is powered by the charge pump 2 and the negative rail of the amplifier 6 is powered by a supply voltage 8. A current sense resistor 12 is connected between the charge pump 2 and the amplifier 6. A current sensing FET 14 is connected between the amplifier 6 and an output pin 18. A high-side switching FET 16 has a drain side connected to the charge pump 2, a gate side connected to the output terminal of the amplifier 6 via a transistor 10, and a source side connected to the output pin 18. The output pin 18 is used to connect the system to a circuit load 20. In addition, a resistor 32 is connected between the gate side and the source side of the FET 16. The circuit further includes a clock generator 22. A resistor 24 is connected between the charge pump 2 and the amplifier 6. The circuit further includes a load reference 26. It is also shown that when the high-side switching FET 16 is "off", a FET 28 is connected in series with a resistor 30. A current limiter 34 is used to provide some control over the slew rate of the high-side switching FET 16. Still referring to FIG. 1, the charge pump 2 needs to deliver a large output current due to its connection to the amplifier 6 and the high-side switching FET 16. The current controller 4 is used to quickly charge the gate of the high-side switch to the desired voltage V _{GS to} draw a large amount of current from the charge pump 2. Therefore, the charge pump 2 contains a relatively large capacitor, which makes it difficult to integrate the circuit of FIG. 1 onto a single chip. Large integrated capacitors increase the size of the silicon grains and thus the cost of the product. If large capacitors are located externally, additional pins become necessary, and any external capacitors may increase BOM cost, thus increasing the cost of the overall system. Using the current limiter 34 to control the slew rate of the high-side switching FET 16 results in the need for a large charge pump 2. Therefore, there is a need for an improved system and method for controlling the slew rate of a high-side switch.

The foregoing needs are met by currently disclosed systems and methods including a sampling and level shifting circuit for controlling a high-side switching slew rate. An exemplary circuit for slew rate control of a high-side switch is disclosed. The circuit includes a sampling and level shifting circuit. The sampling and level shifting circuit is connected to the high-side switch. The circuit further includes a sampling capacitor, and the sampling capacitor is configured to sample an input voltage corresponding to the sampling and level shifting circuit. In addition, the circuit includes a charge limiting mechanism that can be implemented as a circuit. The sampling capacitor is configured to charge a gate capacitance of one of the high-side switches. The charge limiting mechanism is configured to limit a charge rate of the gate capacitance transferred to the high-side switch per unit time. The invention discloses an exemplary method for controlling a slew rate of a high-side switch. The method includes supplying an input current to a sampling and level shifting circuit. The method further includes sampling an input voltage. A sampling capacitor is configured for the sampling of the input voltage. In addition, the method includes level shifting the input voltage. The method includes using the sampling capacitor to charge a gate capacitance of one of the high-side switches. In addition, the method includes limiting a charge supplied to the sampling capacitor, and limiting the charge by at least one current sink.

Priority of Application This application claims the priority of Indian Application No. 201711012738 filed on April 10, 2017, the entire contents of which are hereby incorporated. Before explaining any embodiment of the invention in detail, it should be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the following drawings. The invention is capable of other embodiments and of being practiced or carried out in various ways. Furthermore, it should be understood that the words and terminology used herein are for the purpose of description and should not be regarded as limiting. The use of "including", "including" or "having" and variations thereof in this document means to cover the items listed thereafter and their equivalents and additional items. Unless otherwise specified or limited, the terms "installation,""connection,""support," and "coupling" and variations thereof are widely used and encompass direct and indirect installation, connection, support, and coupling. In addition, "connected" and "coupled" are not limited to physical or mechanical connections or couplings. The following discussion is presented to enable those skilled in the art to make and use embodiments of the invention. Those skilled in the art will readily understand various modifications to the illustrated embodiments, and the general principles herein may be applied to other embodiments and applications without departing from the embodiments of the present invention. Therefore, the embodiments of the present invention are not intended to be limited to the embodiments shown, but are given the broadest scope consistent with the principles and features disclosed herein. The following detailed description will be read with reference to the drawings, in which the same components in different drawings have the same component symbols. The selected embodiments are not necessarily drawn to scale and are not intended to limit the scope of the embodiments of the invention. Those skilled in the art will recognize that the examples provided herein have many useful alternatives that fall within the scope of embodiments of the invention. Embodiments of the present invention provide a system and method for controlling a slew rate of a high-side switch for selectively supplying power to an output load. FIG. 2 is a circuit level diagram of an embodiment of a system and method for controlling a slew rate of a high-side switch according to the present invention. In one embodiment, a sampling and level shifting circuit 40 may be provided. The sampling and level shifting circuit 40 can be connected to a voltage supply 42. The voltage supply 42 may be the output of an amplifier (eg, an operational amplifier). Alternatively, the voltage supply 42 may supply a fixed or variable supply voltage. In some embodiments, the voltage supply 42 may advantageously be 1.8 volts, 2.5 volts, 3.3 volts, or 5 volts. Alternatively, any other voltage level may be supplied by the voltage supply 42. The sampling and level shifting circuit 40 may include a plurality of switches 50, 52, 54, and 56. The sampling and level shifting circuit 40 may further include a sampling capacitor 58. In addition, the sampling and level shifting circuit 40 may include a field effect transistor (FET) 60. A conversion control member 80 may include current slots 82, 84, 86 that can be connected in parallel. The switching control 80 may be connected in parallel with the FET 60. In a non-limiting example, as shown in FIG. 2, a high-side switch 70 may be an n-channel metal oxide semiconductor field effect transistor (nMOS transistor) or an n-channel laterally diffused metal oxide semiconductor transistor ( nLDMOS transistor). An nLDMOS transistor is considered a type of nMOS transistor. In some scenarios, it may be advantageous to use a different type of transistor. One output terminal of the sampling and level shift circuit 40 can be connected to the gate side of the high-side switch 70. The drain side of the high-side switch 70 may be connected to a voltage supply 48. The output pin 72 can be connected to a circuit load. In some non-limiting embodiments, a low-side switch may be included and connected to the output pin 72 such that the high-side switch 70 and the low-side switch constitute a half-bridge configuration. Still referring to FIG. 2, the sample and level shift circuit 40 can eliminate one of the requirements for a charge pump when driving the high-side switch 70. The sampling capacitor 58 can sample the voltage of the voltage supply 42. The sampling capacitor 58 can then be used to charge the gate-side capacitance of the high-side switch 70. Charging the gate-side capacitor can “turn on” the high-side switch 70. In one non-limiting embodiment, when the high-side switch 70 is "on", an input voltage can be supplied to a circuit load. In another non-limiting embodiment, the gate capacitance of the high-side switch 70 can be used as a hold capacitor. Therefore, there may not be a DC load required to hold the capacitor. The sampling and level shifting circuit 40 may not provide any DC current. In another non-limiting embodiment, an explicit holding capacitor may be connected in parallel to the gate capacitance of the high-side switch 70. Again, there may not be a DC load required to hold the capacitor. In some non-limiting embodiments, as opposed to having a charge pump power amplifier, the voltage supplies 48, 42 may supply a fixed voltage. In the case where one amplifier is used as the voltage supply 42, the amplifier can be used as a short-circuit current controller. In some scenarios, it may be advantageous to use different amplifier configurations or a different type of amplifier. In some scenarios, it may be advantageous to include an amplifier configured to operate in a common mode voltage range from the voltage supply 48 to a few volts below the voltage supply 48. The amplifier can be specifically designed to handle a high input common-mode voltage and a low output common-mode voltage. In some scenarios, it may be advantageous to include a supply of one of 3.3 volts 48, 42. Alternatively, the voltage supplies 48, 42 can supply any other predetermined voltage levels, including 5 volts, 12 volts, 14 volts, 24 volts, and 48 volts. In some scenarios, it may be advantageous to use a vehicle battery for at least one of the voltage supplies 48,42. In some scenarios, it may be advantageous to have at least one of the voltage supplies 48, 42 have a supply voltage in the range of 4.5 volts to 60 volts. In one non-limiting embodiment, the voltage supplies 48, 42 may be configured to increase the respective supply voltage (ie, the ramp-up voltage) for a predetermined time. In a non-limiting embodiment, the disclosed system may be an integrated circuit on a single chip. The integrated circuit can use 1/3 of the surface area of the wafer used by the charge pump system as shown in FIG. 1. Alternatively, the disclosed system can use up to 99% of the surface area of the wafer used by the charge pump system as shown by FIG. 1. In some scenarios, it may be advantageous to specifically include the sampling capacitor 58 in the integrated circuit on a single chip. In one non-limiting embodiment, the sampling capacitor 58 may be smaller than the capacitor associated with the charge pump system shown by FIG. 1. In some non-limiting embodiments, the sampling capacitor may be in a capacitance range of 2 pF to 250 pF. In a non-limiting embodiment, the number of pins included in the present invention may be less than the number of pins included by the charge pump system as shown in FIG. 1. In one non-limiting example, the present invention may include one less pin for a charge pump system such as that shown in FIG. In another non-limiting example, the invention may include up to three pins, such as the charge pump system shown in FIG. 1. In a non-limiting embodiment, the current sinks 82, 84, 86 can each control the amount of charge stored in the sampling capacitor 58. By selecting the current slots 82, 84, 86 that are operating, the conversion rate for charging the high-side switch 70 can also be selected. Therefore, each of the current sinks 82, 84, 86 may correspond to the charging of a different slew rate of one of the high-side switches 70. When slew rate control is not desired, FET 60 may be used to short each of the current sinks 82, 84, 86. By controlling the amount of charge stored in the sampling capacitor 58, the charge rate of V _GS to the high-side switch 70 can be controlled. When the FET 60 is short-circuited to the current slots 82, 84, 86, the sampling capacitor 58 can reach a full charge, and the conversion rate for charging the high-side switch 70 can be relatively high. The slew rate of the high-side switch 70 may be programmable. FIG. 3 is a circuit level diagram of another embodiment of a system and method for controlling a slew rate of a high-side switch according to the present invention. In one embodiment, a sampling and level shifting circuit 40 may be provided. The sampling and level shifting circuit 40 can be connected to a voltage supply 42. The voltage supply 42 may be the output of an amplifier (eg, an operational amplifier). Alternatively, the voltage supply 42 may supply a fixed or variable supply voltage. In some embodiments, the voltage supply 42 may advantageously be 1.8 volts, 2.5 volts, 3.3 volts, or 5 volts. Alternatively, any other voltage level may be supplied by the voltage supply 42. The sampling and level shifting circuit 40 may include a plurality of switches 50, 52, 54, and 56. The sampling and level shifting circuit 40 may further include a sampling capacitor 58. In addition, the sampling and level shifting circuit 40 may include a field effect transistor (FET) 60. A conversion control 88 may include at least one current slot 82 that is tunable. The switching control 88 may be connected in parallel with the FET 60. In a non-limiting example, as shown in FIG. 3, a high-side switch 70 may be an n-channel metal oxide semiconductor field effect transistor (nMOS transistor) or an n-channel laterally diffused metal oxide semiconductor transistor ( nLDMOS transistor). An nLDMOS transistor is considered a type of nMOS transistor. In some scenarios, it may be advantageous to use a different type of transistor. One output terminal of the sampling and level shift circuit 40 can be connected to the gate side of the high-side switch 70. The drain side of the high-side switch 70 may be connected to a voltage supply 48. The output pin 72 can be connected to a circuit load. In some non-limiting embodiments, a low-side switch may be included and connected to the output pin 72 such that the high-side switch 70 and the low-side switch constitute a half-bridge configuration. Still referring to FIG. 3, the sample and level shift circuit 40 can eliminate one of the requirements for a charge pump when driving the high-side switch 70. The sampling capacitor 58 can sample the voltage of the voltage supply 42. The sampling capacitor 58 can then be used to charge the gate-side capacitance of the high-side switch 70. Charging the gate-side capacitor can “turn on” the high-side switch 70. In one non-limiting embodiment, when the high-side switch 70 is "on", an input voltage can be supplied to a circuit load. In one non-limiting embodiment, the current sink 82 controls the amount of charge stored in the sampling capacitor 58. By selecting the current slot 82, the conversion rate for charging the high-side switch 70 can also be selected. When slew rate control is not desired, the FET 60 may be used to short the current sink 82. By controlling the amount of charge stored in the sampling capacitor 58, the charge rate of V _GS to the high-side switch 70 can be controlled. When the FET 60 is shorted to the current slot 82, the sampling capacitor 58 can reach a full charge, and the conversion rate for charging the high-side switch 70 can be relatively high. The slew rate of the high-side switch 70 may be programmable. Referring to FIGS. 2 and 3, it is apparent that when at least one current slot 82 is implemented, any number of current slots may be implemented. Referring to FIG. 2, a non-limiting example embodiment includes three current slots 82, 84, 86 connected in parallel. Alternatively, any number of current sinks connected in parallel may be included. Any of the current slots 82, 84, 86 may be tunable and selectable. FIG. 4 is a circuit level diagram of another embodiment of a system and method for controlling a slew rate of a high-side switch according to the present invention. In one embodiment, a sampling and level shifting circuit 90 may be provided. The sampling and level shifting circuit 90 can be connected to a voltage supply 42. The voltage supply 42 may be the output of an amplifier (eg, an operational amplifier). Alternatively, the voltage supply 42 may supply a fixed or variable supply voltage. In some embodiments, the voltage supply 42 may advantageously be 1.8 volts, 2.5 volts, 3.3 volts, or 5 volts. Alternatively, any other voltage level may be supplied by the voltage supply 42. The sampling and level shifting circuit 90 may include a plurality of switches 50, 52, 54, and 56. The sampling and level shifting circuit 90 may further include a sampling capacitor 92. Conversion control can be performed via the sampling capacitor 92. In a non-limiting example, as shown in FIG. 4, a high-side switch 70 may be an n-channel metal oxide semiconductor field effect transistor (nMOS transistor) or an n-channel laterally diffused metal oxide semiconductor transistor ( nLDMOS transistor). An nLDMOS transistor is considered a type of nMOS transistor. In some scenarios, it may be advantageous to use a different type of transistor. One output terminal of the sampling and level shifting circuit 90 can be connected to the gate side of the high-side switch 70. The drain side of the high-side switch 70 may be connected to a voltage supply 48. The output pin 72 can be connected to a circuit load. In some non-limiting embodiments, a low-side switch may be included and connected to the output pin 72 such that the high-side switch 70 and the low-side switch constitute a half-bridge configuration. Still referring to FIG. 4, the sampling and level shifting circuit 90 can eliminate the need for a charge pump when driving the high-side switch 70. The sampling capacitor 92 can sample the voltage of the voltage supply 42. Then, the sampling capacitor 92 can be used to charge the gate-side capacitance of the high-side switch 70. Charging the gate-side capacitor can “turn on” the high-side switch 70. In one non-limiting embodiment, when the high-side switch 70 is "on", an input voltage can be supplied to a circuit load. In a non-limiting embodiment, the sampling capacitor 92 may be adjustable. In some situations, it may be advantageous to include an adjustable sampling capacitor 92 because the sampling capacitor 92 may then be used as a charge limiting mechanism. In this non-limiting embodiment, the sampling capacitor corresponds to a sampling and level shifting circuit. Therefore, adjusting the capacitance of the sampling capacitor 92 can realize the switching control of the high-side switch 70. 5 is a schematic diagram of a circuit level of another embodiment of a system and method for controlling a slew rate of a high-side switch according to the present invention. In one embodiment, a sampling and level shifting circuit 96 may be provided. The sampling and level shifting circuit 96 can be connected to a voltage supply 98. The sampling and level shifting circuit 96 may include a plurality of switches 50, 52, 54, and 56. The sampling and level shifting circuit 96 may further include a sampling capacitor 58. In a non-limiting example, as shown in FIG. 5, a high-side switch 70 may be an n-channel metal oxide semiconductor field effect transistor (nMOS transistor) or an n-channel laterally diffused metal oxide semiconductor transistor ( nLDMOS transistor). An nLDMOS transistor is considered a type of nMOS transistor. In some scenarios, it may be advantageous to use a different type of transistor. One output terminal of the sampling and level shifting circuit 96 can be connected to the gate side of the high-side switch 70. The drain side of the high-side switch 70 may be connected to a voltage supply 48. The output pin 72 can be connected to a circuit load. In some non-limiting embodiments, a low-side switch may be included and connected to the output pin 72 such that the high-side switch 70 and the low-side switch constitute a half-bridge configuration. Still referring to FIG. 5, the sampling and level shifting circuit 96 can eliminate one of the requirements for a charge pump when driving the high-side switch 70. The sampling capacitor 58 can sample the voltage of the voltage supply 98. The sampling capacitor 58 can then be used to charge the gate-side capacitance of the high-side switch 70. Charging the gate-side capacitor can “turn on” the high-side switch 70. In one non-limiting embodiment, when the high-side switch 70 is "on", an input voltage can be supplied to a circuit load. The voltage supply 98 can supply a fixed or variable supply voltage. In some embodiments, the voltage supply 42 may advantageously be 1.8 volts, 2.5 volts, 3.3 volts, or 5 volts. Alternatively, any other voltage level may be supplied by the voltage supply 42. In one non-limiting embodiment, the voltage supply 98 may be configured to increase the supply voltage (ie, the ramp-up voltage) for a predetermined time. In a non-limiting embodiment, a voltage supply 98 may be used as a charge limiting mechanism. An adjustable voltage supply 98 may limit a voltage corresponding to charging the sampling capacitor. Therefore, the slew rate of the high-side switch can be controlled. In one non-limiting embodiment, the switching control circuit may include other types of charge limiting mechanisms. The charge limiting mechanism can limit the sampling current of the sampling capacitor 58. In some non-limiting embodiments, the charge limiting mechanism may limit the sampling voltage of the sampling capacitor 58. The sampling current can be in the range of 5 mA to 5 mA. The sampling voltage can be in the range of 0% to 100% of the final target gate-source voltage. The charge limiting mechanism may be configured to limit a frequency corresponding to a sampling and level shifting circuit. Those skilled in the art will understand that although the present invention has been described above in connection with specific embodiments and examples, the present invention is not necessarily so limited, and many other embodiments, examples, uses, modifications, and those embodiments, examples, and Examples of deviations in use are intended to be covered by the scope of the patent application for inventions attached hereto. The entire disclosures of each patent and publication cited herein are incorporated by reference, as if each such patent or publication was individually incorporated herein by reference. Various features and advantages of the present invention are described in the scope of the following invention application patents.

2‧‧‧ charge pump

4‧‧‧Current Controller

6‧‧‧ amplifier

8‧‧‧ supply voltage

10‧‧‧ Transistor

12‧‧‧ current sense resistor

14‧‧‧Current sensing field effect transistor (FET)

16‧‧‧High-side switching field effect transistor (FET)

18‧‧‧ output pin

20‧‧‧Circuit Load

22‧‧‧ Clock Generator

24‧‧‧ Resistor

26‧‧‧Load reference

28‧‧‧Field Effect Transistor (FET)

30‧‧‧ Resistor

32‧‧‧ Resistor

34‧‧‧ current limiter

40‧‧‧Sampling and level shifting circuit

42‧‧‧Voltage supply

48‧‧‧ Voltage Supply

50‧‧‧ switch

52‧‧‧Switch

54‧‧‧Switch

56‧‧‧Switch

58‧‧‧Sampling capacitor

60‧‧‧Field Effect Transistor (FET)

70‧‧‧High-side switch

72‧‧‧ output pin

80‧‧‧ Conversion control

82‧‧‧Current Slot

84‧‧‧Current Slot

86‧‧‧Current Slot

88‧‧‧ Conversion control

90‧‧‧Sampling and level shifting circuit

92‧‧‧Sampling capacitor

96‧‧‧Sampling and level shifting circuit

98‧‧‧Voltage Supply

FIG. 1 is a circuit level diagram of a known system and method with current limiter for driving a high-side switch. FIG. 2 is a circuit level diagram of an embodiment of a system and method for controlling a slew rate of a high-side switch according to the present invention. FIG. 3 is a circuit level diagram of another embodiment of a system and method for controlling a slew rate of a high-side switch according to the present invention. FIG. 4 is a circuit level diagram of another embodiment of a system and method for controlling a slew rate of a high-side switch according to the present invention. 5 is a schematic diagram of a circuit level of another embodiment of a system and method for controlling a slew rate of a high-side switch according to the present invention.

Claims (18)

A circuit for slew rate control of a high-side switch includes: a sampling and level shift circuit, the sampling and level shift circuit is connected to the high-side switch; a charge limiting circuit; and a sampling A capacitor configured to: sample an input voltage corresponding to one of the sampling and level shifting circuits; and charge a gate capacitor of one of the high-side switches; and the charge limiting circuit configured to limit each A rate of charge transferred to the gate capacitance of the high-side switch per unit time. The circuit of claim 1, wherein the charge limiting circuit is further configured to limit a current corresponding to the sampling capacitor. The circuit of claim 1, wherein the charge limiting circuit is further configured to limit a voltage corresponding to the sampling capacitor. The circuit of claim 1, wherein the charge limiting circuit is further configured to limit a sampling capacitor corresponding to one of the sampling and level shifting circuits. The circuit of claim 1, wherein the charge limiting circuit is further configured to limit a frequency corresponding to the sampling and level shifting circuit. The circuit of claim 1, wherein the high-side switching relationship is an n-channel metal oxide semiconductor field effect transistor (nMOS transistor). The circuit of claim 1, wherein the slew rate control circuit for the high-side switch is an integrated circuit on a single chip. The circuit of claim 1, wherein the charge limiting circuit comprises an adjustable voltage supply. The circuit of claim 1, wherein the charge limiting circuit comprises the sampling capacitor. The circuit of claim 1, wherein: the sampling capacitor is an adjustable sampling capacitor; and the charge limiting circuit includes the sampling capacitor. A method for controlling a slew rate of a high-side switch, the method comprising: supplying an input current to a sampling and level shifting circuit; using a sampling capacitor to sample an input voltage, the sampling capacitor being configured Use for the sampling of the input voltage; level shift the input voltage; use the sampling capacitor to charge a gate capacitor of one of the high-side switches; and limit a charge supplied to the sampling capacitor by at least A current sink limits the charge. The method of claim 11, further comprising connecting a transistor in parallel with the at least one current slot, and turning on the transistor to remove any charge limitation corresponding to the at least one current slot. The method of claim 11, further comprising selecting one of the at least one current slot, each of the at least one current slot corresponding to a different high-side switching slew rate. The method of claim 11, further comprising limiting a current corresponding to the sampling capacitor. The method of claim 11, further comprising limiting a voltage corresponding to one of the sampling capacitors. The method of claim 11, further comprising limiting a sampling capacitor corresponding to one of the sampling and level shifting circuits. The method of claim 11, further comprising limiting a frequency corresponding to the sampling and level shifting circuit. A switching device includes: a high-side switch; and a control circuit for controlling the slew rate of a high-side switch, the control circuit includes: a sampling and level shift circuit, the sampling and level shift circuit A circuit connected to the high-side switch; a charge limiting circuit; and a sampling capacitor configured to: sample an input voltage corresponding to the sampling and level shifting circuit; and gate a high-side switch Charge the capacitor; and wherein the charge limiting circuit is configured to limit a charge rate of the gate capacitor transferred to the high-side switch per unit time.